ETC AT90SC6404R

Features
General
• High-performance, Low-power secureAVRä RISC Architecture
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– 133 Powerful Instructions (Most Executed in a Single Clock Cycle)
– Linear Addressing of up to 8M Bytes of Code and up to 16M Bytes of Data
Low-power Idle and Power-down Modes
Bond Pad Locations Conforming to ISO 7816-2
ESD Protection to ± 6000V
Operating Ranges: from 2.7V to 5.5V
Compliant with EMV 2000 Specifications; PC Industry Compatible
Available in Wafers, Modules and Industry-standard Packages
Memory
• 64K Bytes of ROM Program Memory
• 4K Bytes of EEPROM, Including 64-byte OTP Area and 192-byte Bit-addressable Area
– 1 to 64-byte Program/Erase
– 2 ms Program, 2 ms Erase
– Typically 1,000,000 Write/Erase Cycles
– 10 Years Data Retention
• 2K Bytes of RAM
Secure
Microcontroller
for Smart Cards
AT90SC6404R
Preliminary
Peripherals
• ISO 7816 Controller
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– Up to 625 kbs at 5 MHz
– Compliant with T = 0 and T = 1 Protocols
One I/O Port
Programmable Internal Oscillator (Up to 16 MHz on ROM)
Two 16-bit Timers
Random Number Generator (RNG)
2-level, 8-vector Interrupt Controller
Hardware DES and Triple DES DPA Resistant
Checksum Accelerator
CRC 16 Engine (Compliant with ISO/IEC 3309)
Security
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Dedicated Hardware for Protection Against SPA/DPA Attacks
Advanced Protection Against Physical Attack, Including Active Shield
Environmental Protection Systems
Voltage Monitor
Frequency Monitor
Temperature Monitor
Light Protection
Secure Memory Management/Access Protection (Supervisor Mode)
Development Tools
• Hardware/Software Development Support on Voyager Emulation Platform (ATV2)
• IAR Systems C-Spy® Debugger
• Software Libraries and Application Notes
Rev. 1574BS–SMIC–01/03
Note: This is a summary document. A complete document will be1
available under NDA. For more information, please contact your
local Atmel sales office.
Description
The AT90SC6404R is a low-power, high-performance, 8-/16-bit microcontroller, based
on the secureAVRä RISC architecture, with ROM program memory and EEPROM data
memory. By executing powerful instructions in a single clock cycle, the AT90SC6404R
achieves throughputs close to 1 MIPS per MHz. Its Harvard architecture includes 32
general-purpose working registers directly connected to the ALU, allowing two independent registers to be accessed in one single instruction executed in one clock cycle.
The AT90SC6404R uses secureAVR architecture that allows the linear addressing of up
to 8M bytes of code and up to 16M bytes of data, and also provides a number of new
functional and security features.
Additional security features include power, frequency and temperature protection logic,
logical scrambling on program data and addresses, power analysis countermeasures,
and memory accesses controlled by a supervisor mode.
A block diagram of the AT90SC6404R is shown in Figure 1.
2
AT90SC6404R
1574BS–SMIC–01/03
AT90SC6404R
Figure 1. AT90SC6404R secureAVR RISC Architecture
Data Bus
8-bit
OTP
Access
Control
RNG
EEPROM
User Memory
PC
X
16
8
RAM
Data Memory
8
Interrupt
Unit
ALU
8
16
Control
Lines
Access
Control
Y
Z
16
Instruction
Decoder
GND
VCC
General
Purpose
Registers
Program
Memory
Instruction
Register
CLK
Secure
Control
ISO 7816
Controller
ISO 7816
I/O Port 0
IN/OUT0
Status
Register
Timer
Reset
Circuit
RST
DES
DPA Counter
measures
CRC and
Checksum
Accelerator
3
1574BS–SMIC–01/03
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© Atmel Corporation 2003.
Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company’s standard warranty
which is detailed in Atmel’s Terms and Conditions located on the Company’s web site. The Company assumes no responsibility for any errors
which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does
not make any commitment to update the information contained herein. No licenses to patents or other intellectual property of Atmel are granted
by the Company in connection with the sale of Atmel products, expressly or by implication. Atmel’s products are not authorized for use as critical
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others.
Printed on recycled paper.
1574BS–SMIC–01/03
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