CY28353-2 Differential Clock Buffer/Driver Features Description • Phase-locked loop (PLL) clock distribution for double data rate synchronous DRAM applications • Distributes one differential clock input to six differential outputs • External feedback pins (FBINT, FBINC) are used to synchronize the outputs to the clock input • Conforms to the DDRI specification • Spread Aware for electromagnetic interference (EMI) reduction • 28-pin SSOP package This PLL clock buffer is designed for 2.5 VDD and 2.5 AVDD operation and differential data input and output levels. This device is a zero delay buffer that distributes a differential clock input pair (CLKINT, CLKINC) to six differential pairs of clock outputs (CLKT[0:5], CLKC[0:5]) and one differential pair feedback clock outputs (FBOUTT, FBOUTC). The clock outputs are controlled by the input clocks (CLKINT, CLKINC) and the feedback clocks (FBINT, FBINC). The two-line serial bus can set each output clock pair (CLKT[0:5], CLKC[0:5]) to the Hi-Z state. When AVDD is grounded, the PLL is turned off and bypassed for test purposes. The PLL in this device uses the input clocks (CLKINT, CLKINC) and the feedback clocks (FBINT, FBINC) to provide high-performance, low-skew, low–jitter output differential clocks. Block Diagram Pin Configuration 10 SCLK SDATA CLKC1 GND SCLK CLKT2 CLKC2 Serial Interface Logic CLKT3 CLKC3 CLKT4 CLKC4 CLKINT CLKINC FBINC FBINT CLKINT CLKINC PLL AVDD AGND VDD CLKT5 CLKC5 CLKT2 CLKC2 FBOUTT FBOUTC AVDD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 CY28353-2 CLKC0 CLKT0 VDD CLKT1 CLKT0 CLKC0 CLKT1 CLKC1 28 27 26 25 24 23 22 21 20 19 18 17 16 15 GND CLKC5 CLKT5 CLKC4 CLKT4 VDD SDATA FBINC FBINT FBOUTT FBOUTC CLKT3 CLKC3 GND 28 pin SSOP Cypress Semiconductor Corporation Document #: 38-07372 Rev. *A • 3901 North First Street • San Jose • CA 95134 • 408-943-2600 Revised December 27, 2002 CY28353-2 Pin Description [1] Pin Number Pin Name I/O Pin Description 8 CLKINT I Complementary Clock Input. 9 CLKINC I Complementary Clock Input. 21 FBINC I Feedback Clock Input. Connect to FBOUTC for accessing the PLL. 20 FBINT I Feedback Clock Input. Connect to FBOUTT for accessing the PLL. Electrical Characteristics LV Differential Input Differential Input 2,4,13,17,24,26 CLKT(0:5) O Clock Outputs. 1,5,14,16,25,27 CLKC(0:5) O Clock Outputs. 19 FBOUTT O Feedback Clock Output. Connect to Differential Output FBINT for normal operation. A bypass delay capacitor at this output will control Input Reference/ Output Clocks phase relationships. 18 FBOUTC O Feedback Clock Output. Connect to FBINC for normal operation. A bypass delay capacitor at this output will control Input Reference/Output Clocks phase relationships. 7 SCLK 22 SDATA I, PU Serial Clock Input. Clocks data at SDATA into the internal register. I/O, PU Differential Outputs Data Input for the two-line serial bus Serial Data Input. Input data is clocked Data Input and Output for the to the internal register to enable/disable two-line serial bus individual outputs. This provides flexibility in power management. 3,12,23 VDD 2.5V Power Supply for Logic. 2.5V Nominal 10 AVDD 2.5V Power Supply for PLL. 2.5V Nominal 6,15,28 GND Ground. 11 AGND Analog Ground for PLL. Note: 1. A bypass capacitor (0.1µF) should be placed as close as possible to each positive power pin (< 0.2”). If these bypass capacitors are not close to the pins their high-frequency filtering characteristic will be cancelled by the lead inductance of the traces. Document #: 38-07372 Rev. *A Page 2 of 8 CY28353-2 Maximum Ratings[2] Storage Temperature: .................................–65°C to +150°C This device contains circuitry to protect the inputs against damage due to high static voltages or electric field; however, precautions should be taken to avoid application of any voltage higher than the maximum rated voltages to this circuit. For proper operation, VIN and VOUT should be constrained to the range: Operating Temperature: .................................... 0°C to +85°C VSS < (VIN or VOUT) < VDD. Maximum Power Supply: ................................................3.5V Unused inputs must always be tied to an appropriate logic voltage level (either VSS or VDD). Input Voltage Relative to VSS:.............................. VSS – 0.3V Input Voltage Relative to VDDQ or AVDD: ............. VDD + 0.3V DC Parameters VDDA = VDDQ = 2.5V + 5%, TA = 0°C to +70°C[3] Parameter Description Condition Min. Typ. SDATA, SCLK Max. Unit 1.0 V VIL Input Low Voltage VIH Input High Voltage VID Differential Input Voltage[4] CLKINT, FBINT 0.35 VIX Differential Input Crossing Voltage[5] CLKINT, FBINT (VDDQ/2) – 0.2 IIN Input Current VIN = 0V or VIN = VDDQ, CLKINT, FBINT IOL Output Low Current VDDQ = 2.375V, VOUT = 1.2V 26 35 mA IOH Output High Current VDDQ = 2.375V, VOUT=1V –18 –32 mA 2.2 VOL Output Low Voltage VDDQ = 2.375V, IOL = 12 mA Output High Voltage VDDQ = 2.375V, IOH = –12 mA Output Voltage Swing IOZ High-impedance Output VO = GND or VO = VDDQ Current IDSTAT (VDDQ/2) – 0.2 V 10 µA VDDQ – 0.4 V (VDDQ/2) + 0.2 V 10 µA 300 mA 1 mA 9 12 mA 4 6 pF VDDQ/2 235 Static Supply Current IDD PLL Supply Current Cin Input Pin Capacitance VDDA only AC Parameters VDD = VDDQ = 2.5V ± 5%, TA = 0°C to +70°C Parameter fCLK Description Operating Clock Frequency tDC Input Clock Duty Cycle tlock Maximum PLL lock Time Tr / Tf Output Clocks Slew Rate tpZL, tpZH tpLZ, tpHZ Output Disable Time [11] [9,10] Condition Min. AVDD, VDD = 2.5V ± 0.2V 60 Typ. 40 Output Enable Time[11](all outputs) (all outputs) V V –10 All VDDQ and VDDI, FO = 170 MHz Dynamic Supply Current[8] (VDDQ/2) + 0.2 0.6 1.1 Output Crossing Voltage[7] V 1.7 [6] VOC IDDQ VDDQ/2 VDDQ + 0.6 –10 VOH VOUT V 20% to 80% of VOD 1 Max. Unit 170 MHz 60 % 100 µs 2.5 V/ns 3 ns 3 ns Notes: 2. Multiple Supplies: The voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply srquencing is NOT required. 3. Unused inputs must be held HIGH or LOW to prevent them from floating. 4. Differential input signal voltage specifies the differential voltage |VTR – VCP| required for switching, where VTR is the true input level and VCP is the complementary input level. 5. Differential cross-point input voltage is expected to track VDDQ and is the voltage at which the differential signals must be crossing. 6. For load conditions see Figure 7. 7. The value of VOC is expected to be |VTR + VCP|/2. In case of each clock directly terminated by a 120Ω resistor. See Figure 7. 8. All outputs switching loaded with 16 pF in 60Ω environment. See Figure 7. 9. Parameters are guaranteed by design and characterization. Not 100% tested in production 10. PLL is capable of meeting the specified parameters while supporting SSC synthesizers with modulation frequency between 30kHz and 33.3kHz with a down spread of –0.5% 11. Refers to transition of non-inverting output Document #: 38-07372 Rev. *A Page 3 of 8 CY28353-2 AC Parameters VDD = VDDQ = 2.5V ± 5%, TA = 0°C to +70°C[9,10] Parameter tCCJ Description Cycle to Cycle Jitter tjit(h-per) Half-period jitter[13] Condition Min. f > 66 MHz –100 f > 66 MHz –100 Typ. Max. Unit 100 ps 100 ps tPLH Low-to-High Propagation Delay, CLKINT to CLKT[0:5] 1.5 3.5 6 ns tPHL High-to-Low Propagation Delay, CLKINT to CLKT[0:5] 1.5 3.5 6 ns 100 ps –150 150 ps –50 50 ps tSKEW Any Output to Any Output Skew[12] [12] tPHASE Phase Error tPHASEJ Phase Error Jitter f > 66MHz Zero Delay Buffer Power Management When used as a zero delay buffer the CY28353-2 will likely be in a nested clock tree application. For these applications the CY28353-2 offers a differential clock input pair as a PLL reference. The CY28353-2 then can lock onto the reference and translate with near zero delay to low skew outputs. For normal operation, the external feedback input, FBINT, is connected to the feedback output, FBOUTT. By connecting the feedback output to the feedback input the propagation delay through the device is eliminated. The PLL works to align the output edge with the input reference edge thus producing a near zero delay. The reference frequency affects the static phase offset of the PLL and thus the relative delay between the inputs and outputs. The individual output enable/disable control of the CY28353-2 allows the user to implement unique power management schemes into the design. Outputs are tri-stated when disabled through the two-line interface as individual bits are set low in Byte0 and Byte1 registers. The feedback output pair (FBOUTT, FBOUTC) cannot be disabled via two line serial bus. The enabling and disabling of individual outputs is done in such a manner as to eliminate the possibility of partial “runt” clocks. Serial Control Registers Following the acknowledge of the Address Byte, two additional bytes must be sent: • Command Code byte • Byte Count byte. When VDDA is strapped low, the PLL is turned off and bypassed for test purposes. Function Table Inputs Outputs PLL VDDA CLKINT CLKINC CLKT(0:5)[14] CLKC(0:5)[14] FBOUTT FBOUTC GND L H L H L H BYPASSED/OFF GND H L H L H L BYPASSED/OFF 2.5V L H L H L H On 2.5V H L H L H L On 2.5V < 20 MHz < 20 MHz Hi-Z Hi-Z Hi-Z Hi-Z Off Byte0: Output Register (1 = Enable, 0 = Disable) Bit @Pup Pin# 7 1 2, 1 CLKT0, CLKC0 Description 6 1 4, 5 CLKT1, CLKC1 5 1 – Reserved 4 1 – 3 1 13, 14 CLKT2, CLKC2 Reserved 2 1 26, 27 CLKT5, CLKC5 1 1 – 0 1 24, 25 Reserved CLKT4, CLKC4 Notes: 12. All differential input and output terminals are terminated with 120Ω/16 pF, as shown in Figure 7. 13. Period Jitter and Half-period Jitter specifications are separate specifications that must be met independently of each other. 14. Each output pair can be three-stated via the two-line serial interface. Document #: 38-07372 Rev. *A Page 4 of 8 CY28353-2 Byte1: Output Register (1 = Enable, 0 = Disable) Bit @Pup Pin# 7 1 – 6 1 17, 16 5 0 – Description Reserved CLKT3, CLKC3 Reserved 4 0 – Reserved 3 0 – Reserved 2 0 – Reserved 1 0 – Reserved 0 0 – Reserved Byte2: Test Register 3 Bit @Pup Pin# 7 1 – 0 = PLL leakage test, 1 = disable test Description 6 1 – Reserved 5 1 – Reserved 4 1 – Reserved 3 1 – Reserved 2 1 – Reserved 1 1 – Reserved 0 1 – Reserved Differential Parameter Measurement Information CLKINT CLKINC FBINT FBINC t(∅)n+1 t(∅)n t(∅)n = Σ n1=N t(∅)n (N is large number of samples) Figure 1. Static Phase Offset CLKINT CLKINC FBINT FBINC td(∅) t(∅) td(∅) td(∅) t( ∅ ) td(∅) Figure 2. Dynamic Phase Offset Document #: 38-07372 Rev. *A Page 5 of 8 CY28353-2 CLKT[0:5], FBOUTT CLKC[0:5], FBOUTC CLKT[0:5], FBOUTT CLKC[0:5], FBOUTC tsk(o) Figure 3. Output Skew CLKT[0:5], FBOUTT CLKC[0:5], FBOUTC tc(n) CLKT[0:5], FBOUTT CLKC[0:5], FBOUTC 1 f(o) tjit(hper) = tc(n) - 1 fo Figure 4. Period Jitter CLKT[0:5], FBOUTT CLKC[0:5], FBOUTC t(hper_N+1) t(hper_n) 1 f(o) tjit(hper) = thper(n) - 1 2x fo Figure 5. Half-Period Jitter CLKT[0:5], FBOUTT CLKC[0:5], FBOUTC t c(n) t c(n) tjit(cc) = tc(n)-tc(n+1) Figure 6. Cycle-to-Cycle Jitter Document #: 38-07372 Rev. *A Page 6 of 8 CY28353-2 T PCB M easurem ent Point CLKT 16 pF CLKIN 110 Ω 110 Ω T PCB CLKC M easurem ent Point 16 pF 110 Ω FBINT FBO UTT FBO UTC FBINC Figure 7. Differential Signal Using Direct Termination Resistor Ordering Information Part Number Package Type Product Flow CY28353OC-2 28-pin SSOP Commercial, 0° to 70°C CY28353OC-2 28-pin SSOP–Tape and Reel Commercial, 0° to 70°C Package Diagram 28-lead (5.3 mm) Shrunk Small Outline Package O28 51-85079-*C Spread Aware is a trademark of Cypress Semiconductor. All products and company names mentioned in this document may be the trademarks of their respective holders. Document #: 38-07372 Rev. *A Page 7 of 8 © Cypress Semiconductor Corporation, 2002. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. CY28353-2 Document Title: CY28353-2 Differential Clock Buffer/Driver Document Number: 38-07372 ECN NO. Issue Date Orig. of Change ** 112788 05/07/02 DMG *A 122912 12/27/02 RBI REV. Document #: 38-07372 Rev. *A Description of Change New Data Sheet Add power up requirements to maximum ratings information. Page 8 of 8