ETC FST16861MTDX

Revised December 2000
FST16861
20-Bit Bus Switch
General Description
Features
The Fairchild Switch FST16861 provides 20-Bits of highspeed CMOS TTL-compatible bus switching. The low ON
resistance of the switch allows inputs to be connected to
outputs without adding propagation delay or generating
additional ground bounce noise.
■ 4Ω switch connection between two ports.
The device is organized as a 10-bit or 20-Bit bus switch.
When OE1 is LOW, the switch is ON and Port 1A is connected to Port 1B. When OE2 is LOW, Port 2A is connected
to Port 2B. When OEX is HIGH, a high impedance state
exists between the A and B Ports.
■ Control inputs compatible with TTL level.
■ Minimal propagation delay through the switch.
■ Low lCC.
■ Zero bounce in flow-through mode.
Ordering Code:
Order Number
Package Number
Package Description
MTD48
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
FST16861MTD
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Logic Diagram
Connection Diagram
Truth Table
Inputs
Inputs/Outputs
Pin Descriptions
OE1
OE2
1A, 1B
2A, 2B
Pin Name
Description
L
L
1A = 1B
2A = 2B
OE1, OE2
Bus Switch Enables
L
H
1A = 1B
Z
1A, 2A
Bus A
H
L
Z
2A = 2B
1B, 2B
Bus B
H
H
Z
Z
© 2000 Fairchild Semiconductor Corporation
DS500318
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FST16861 20-Bit Bus Switch
March 2000
FST16861
Absolute Maximum Ratings(Note 1)
Recommended Operating
Conditions (Note 4)
0.5V to +7.0V
Supply Voltage (VCC )
DC Switch Voltage (VS) (Note 2)
−0.5V to +7.0V
Power Supply Operating (VCC)
DC Input Voltage (VIN) (Note 3)
−0.5V to +7.0V
Input Voltage (VIN)
0V to 5.5V
0V to 5.5V
DC Input Diode Current (lIK) VIN < 0V
−50mA
Output Voltage (VOUT)
DC Output (IOUT ) Current
128mA
Input Rise and Fall Time (tr, tf)
±100mA
DC VCC/GND Current (ICC/IGND)
Storage Temperature Range (TSTG)
4.0V to 5.5V
Switch Control Input
−65°C to +150 °C
0nS/V to 5nS/V
Switch I/O
0nS/V to DC
-40 °C to +85 °C
Free Air Operating Temperature (TA)
Note 1: The “Absolute Maximum Ratings” are those values beyond which
the safety of the device cannot be guaranteed. The device should not be
operated at these limits. The parametric values defined in the Electrical
Characteristics tables are not guaranteed at the absolute maximum rating.
The “Recommended Operating Conditions” table will define the conditions
for actual device operation.
Note 2: VS is the voltage observed/applied at either the A or B Ports across
the switch.
Note 3: The input and output negative voltage ratings may be exceeded if
the input and output diode current ratings are observed.
Note 4: Unused control inputs must be held HIGH or LOW. They may not
float.
DC Electrical Characteristics
Symbol
Parameter
VCC
(V)
TA = −40 °C to +85 °C
Min
Typ
(Note 5)
Max
−1.2
Units
Conditions
IIN = −18mA
VIK
Clamp Diode Voltage
VIH
HIGH Level Input Voltage
4.0–5.5
VIL
LOW Level Input Voltage
4.0–5.5
0.8
V
II
Input Leakage Current
5.5
±1.0
µA
0 ≤ VIN ≤ 5.5V
0
±1.0
µA
VIN = 5.5V
±1.0
µA
0 ≤ A, B ≤ VCC
VIN = 0V, IIN = 64mA
4.5
2.0
V
V
IOZ
OFF-STATE Leakage Current
5.5
RON
Switch On Resistance
4.5
4
7
Ω
(Note 6)
4.5
4
7
Ω
VIN = 0V, IIN = 30mA
4.5
7
12
Ω
VIN = 2.4V, IIN = 15mA
4.0
11
VIN = 2.4V, IIN = 15mA
20
Ω
ICC
Quiescent Supply Current
5.5
3
µA
VIN = VCC or GND, IOUT = 0
∆ ICC
Increase in ICC per Input
5.5
2.5
mA
One input at 3.4V
Other inputs at VCC or GND
Note 5: Typical values are at VCC = 5.0V and T A = +25°C
Note 6: Measured by the voltage drop between A and B pins at the indicated current through the switch. On resistance is determined by the lower of the
voltages on the two (A or B) pins.
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TA = −40 °C to +85 °C,
CL = 50pF, RU = RD = 500Ω
Symbol
Parameter
VCC = 4.5 – 5.5V
Min
tPHL, tPLH
Prop Delay Bus-to-Bus (Note 7)
tPZH, tPZL
Output Enable Time
1.0
VCC = 4.0V
Max
Min
Units
Conditions
Max
0.25
0.25
ns
VI = OPEN
Figures
1, 2
5.0
5.3
ns
VI = 7V for tPZL
Figures
1, 2
VI = OPEN for tPZH
tPHZ, tPLZ
Output Disable Time
1.0
Figure
No.
6.0
6.3
ns
VI = 7V for tPLZ
VI = OPEN for tPHZ
Figures
1, 2
Note 7: This parameter is guaranteed by design but is not tested. The bus switch contributes no propagation delay other than the RC delay of the typical On
resistance of the switch and the 50pF load capacitance, when driven by an ideal voltage source (zero output impedance).
Capacitance
Symbol
(Note 8)
Parameter
Typ
Max
Units
Conditions
CIN
Control Pin Input Capacitance
3
pF
VCC = 5.0V, VIN = 0V
CI/O
Input/Output Capacitance “OFF State”
6
pF
VCC, OE = 5.0V, VIN = 0V
Note 8: TA = +25°C, f = 1 Mhz, Capacitance is characterized but not tested.
AC Loading and Waveforms
Note: Input driven by 50Ω source terminated in 50Ω
Note: C L includes load and stray capacitance
Note: Input PRR = 1.0 MHz, tW = 500 ns
FIGURE 1. AC Test Circuit
FIGURE 2. AC Waveforms
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FST16861
AC Electrical Characteristics
FST16861 20-Bit Bus Switch
Physical Dimensions inches (millimeters) unless otherwise noted
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Package Number MTD48
Technology Description
The Fairchild Switch family derives from and embodies Fairchild’s proven switch technology used for several years in its
74LVX3L384(FST3384) bus switch product.
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
2. A critical component in any component of a life support
device or system whose failure to perform can be reasonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the
user.
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