3.3V SDRAM Modules HYS64V32220GD(L)-8A 256MB PC100 144 pin SO-DIMM SDRAM Modules Preliminary information • 144 Pin Eight Byte Small Outline Dual-In-Line Synchronous DRAM Modules for PC 100 notebook applications • Two bank 32M x 64 non-parity module organisation • Performance: -8A fCK Clock frequency (max.) tAC Clock access time CAS latency = 3 PC100 Units 100 MHz 6 ns • Single +3.3V(± 0.3V ) power supply • Programmable CAS Latency, Burst Length and Wrap Sequence (Sequential & Interleave) • Auto Refresh (CBR) and Self Refresh • Decoupling capacitors mounted on substrate • All inputs, outputs are LVTTL compatible • Serial Presence Detect with E2PROM • Uses 256Mbit SDRAM components in 16M x 16 SDRAM organisation • 8192 refresh cycles every 64 ms • Gold contact pad • This module family is fully compliant with the latest INTEL SO-DIMM layout specification INFINEON Technologies 1 Powered by ICminer.com Electronic-Library Service CopyRight 2003 6.99 HYS64V32220GD(L)-8A PC100 144 pin SO-DIMM SDRAM Modules This INFINEON modules are industry standard 144 pin 8-byte Synchronous DRAM (SDRAM) Small Outline Dual In-line Memory Modules (SO-DIMM) which are organised as x64 high speed memory arrays designed for use in non-parity applications. These SO-DIMMs use 256Mbit SDRAMs in TSOPII packages. Decoupling capacitors are mounted on the board. The DIMMs use optional serial presence detects implemented via a serial E2PROM using the two pin I2C protocol. The first 128 bytes are utilized by the DIMM manufacturer and the second 128 bytes are available to the end user. All INFINEON 144-pin SO-DIMMs provide a high performance, flexible 8-byte interface in a 67,5 mm long footprint. Product Spectrum: 32M x 64 HYS64V32220GD(L)-8A SDRAMs RowAddr. Bank Column Refresh used Select Addr. 8 16Mx16 13 BA0, BA1 9 8k Period 7,8 µs Note: All partnumbers end with a place code (not shown), designating the die revision. Consult factory for current revision. Example: HYS64V32220GD-8A-A, indicating Rev.A dies are used for SDRAM components. Card Dimensions: Organisation 32M x 64 PCB-Board INTEL Rev. 1.0 L x H x T [mm] 67.60 x 31.75 x 3.80 Pin Names A0-A12 BA0,BA1 DQ0 - DQ63 RAS CAS WE CKE0 CLK0 DQMB0 - DQMB7 CS0 - CS3 Vcc Vss SCL SDA N.C. INFINEON Technologies Address Inputs for 32M x 64 modules Bank Selects Data Input/Output Row Address Strobe Column Address Strobe Read / Write Input Clock Enable Clock Input Data Mask Chip Select Power (+3.3 Volt) Ground Clock for Presence Detect Serial Data Out for Presence Detect No Connection 2 Powered by ICminer.com Electronic-Library Service CopyRight 2003 HYS64V32220GD(L)-8A PC100 144 pin SO-DIMM SDRAM Modules Pin Configuration PIN # 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 Front Side VSS DQ0 DQ1 DQ2 DQ3 VCC DQ4 DQ5 DQ6 DQ7 Vss DQMB0 DQMB1 Vcc A0 A1 A2 Vss DQ8 DQ9 DQ10 DQ11 Vcc DQ12 DQ13 DQ14 DQ15 Vss NC NC CLK0 Vcc RAS WE CS0 CS1 INFINEON Technologies PIN # 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 Back Side PIN # VSS DQ32 DQ33 DQ34 DQ35 Vcc DQ36 DQ37 DQ38 DQ39 Vss DQMB4 DQMB5 Vcc A3 A4 A5 Vss DQ40 DQ41 DQ42 DQ43 Vcc DQ44 DQ45 DQ46 DQ47 Vss NC NC CKE0 Vcc CAS CKE1 A12 NC 73 75 77 79 81 83 85 87 89 91 93 95 97 99 101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 135 137 139 141 143 3 Powered by ICminer.com Electronic-Library Service CopyRight 2003 Front Side NC Vss NC NC Vcc DQ16 DQ17 DQ18 DQ19 Vss DQ20 DQ21 DQ22 DQ23 Vcc A6 A8 Vss A9 A10 Vcc DQMB2 DQMB3 Vss DQ24 DQ25 DQ26 DQ27 Vcc DQ28 DQ29 DQ30 DQ31 Vss SDA Vcc PIN # 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 Back Side CLK1 Vss NC NC Vcc DQ48 DQ49 DQ50 DQ51 Vss DQ52 DQ53 DQ54 DQ55 Vcc A7 BA0 Vss BA1 A11 Vcc DQMB6 DQMB7 Vss DQ56 DQ57 DQ58 DQ59 Vcc DQ60 DQ61 DQ62 DQ63 Vss SCL Vcc HYS64V32220GD(L)-8A PC100 144 pin SO-DIMM SDRAM Modules WE CS0 CS1 CS WE CS WE CS WE CS WE DQMB0 LDQM LDQM DQMB4 LDQM LDQM DQ0-DQ7 DQ0-DQ7 DQ0-DQ7 DQ32-DQ39 DQ0-DQ7 DQ0-DQ7 DQMB1 UDQM UDQM DQMB5 UDQM UDQM DQ8-DQ15 DQ8-DQ15 DQ8-DQ15 DQ40-DQ47 DQ8-DQ15 DQ8-DQ15 D0 D4 D2 D6 CS WE CS WE CS WE CS WE DQMB2 LDQM LDQM DQMB6 LDQM LDQM DQ16-DQ23 DQ0-DQ7 DQ0-DQ7 DQ48-DQ55 DQ0-DQ7 DQ0-DQ7 DQMB3 UDQM UDQM DQMB7 UDQM UDQM DQ24-DQ31 DQ8-DQ15 DQ8-DQ15 DQ56-DQ63 DQ8-DQ15 DQ8-DQ15 D1 D5 D3 D7 A0-A12, BA0, BA1 E2PROM (256wordx8bit) D0 - D7 VCC SA0 SA1 SA2 D0 - D7 C1-C4 VSS D0 - D7 RAS D0 - D7 CAS D0 - D7 CKE0 D0 - D7 CLK0 CLK1 4 SDRAM 4 SDRAM note: all resistors are 10 Ohms Block Diagram for two bank 32M x 64 SDRAM DIMM - Module INFINEON Technologies SCL SDA 4 Powered by ICminer.com Electronic-Library Service CopyRight 2003 HYS64V32220GD(L)-8A PC100 144 pin SO-DIMM SDRAM Modules DC Characteristics TA = 0 to 70 °C; VSS = 0 V; VDD,VDDQ = 3.3 V ± 0.3 V Parameter Symbol Limit Values min. max. Unit Input high voltage VIH 2.0 Vcc+0.3 V Input low voltage VIL – 0.5 0.8 V Output high voltage (IOUT = – 4.0 mA) VOH 2.4 – V Output low voltage (IOUT = 4.0 mA) VOL – 0.4 V Input leakage current, any input (0 V < VIN < 3.6 V, all other inputs = 0 V) II(L) – 20 20 µA Output leakage current (DQ is disabled, 0 V < VOUT < VCC) IO(L) – 20 20 µA Capacitance TA = 0 to 70 °C; VDD = 3.3 V ± 0.3 V, f = 1 MHz Parameter Symbol Limit Values Unit 32M x 64 max. Input capacitance (A0 to A11, BA0, BA1) CI1 TBD pF Input capacitance (RAS, CAS, WE, CKE0) CI2 TBD pF Input Capacitance (CLK0, CLK1) CI3 TBD pF Input capacitance (CS0) CI4 TBD pF Input capacitance (DQMB0-DQMB7) CI5 TBD pF Input / Output capacitance (DQ0-DQ63) CIO TBD pF Input Capacitance (SCL,SA0-2) Csc 8 pF Input/Output Capacitance Csd 10 pF INFINEON Technologies 5 Powered by ICminer.com Electronic-Library Service CopyRight 2003 HYS64V32220GD(L)-8A PC100 144 pin SO-DIMM SDRAM Modules Operating Currents per memory bank (TA = 0 to 70oC, Vdd = 3.3V ± 0.3V (Recommended Operating Conditions unless otherwise noted) Parameter & Test Condition Symb. -8A ICC1 TBD mA mA mA 1 ICC2P TBD mA 1 ICC2PS TBD mA 1 ICC2N TBD mA 1 ICC2NS TBD mA 1 Note OPERATING CURRENT trc=trcmin., tck=tckmin. Ouputs open, Burst Length = 4, CL=3 All banks operated in random access, all banks operated in ping-pong manner to maximize gapless data access PRECHARGE STANDBY CURRENT in Power Down Mode CS =VIH (min.), CKE<=Vil(max) tck = min. tck = Infinity PRECHARGE STANDBY CURRENT in Non-Power Down Mode tck = min. CS = VIH (min.), CKE>=Vih(min) tck = Infinity NO OPERATING CURRENT CKE>=VIH(min.) ICC3N TBD mA 1 tck = min., CS = VIH(min), active state ( max. 4 banks) CKE<=VIL(max.) ICC3P TBD mA 1 BURST OPERATING CURRENT tck = min., Read command cycling ICC4 TBD mA 1,2 AUTO REFRESH CURRENT tck = min., Auto Refresh command cycling ICC5 TBD mA 1 ICC6 TBD mA 1 SELF REFRESH CURRENT Self Refresh Mode, CKE=0.2V L-version Notes: 1. These parameters depend on the cycle rate. These values are measured at 100 MHz for -8A modules. Input signals are changed once during tck, excepts for ICC6 and for standby currents when tck=infinity. 2. These parameters are measured with continuous data stream during read access and all DQ toggling. CL=3 and BL=4 is assumed and the VDDQ current is excluded. INFINEON Technologies 6 Powered by ICminer.com Electronic-Library Service CopyRight 2003 HYS64V32220GD(L)-8A PC100 144 pin SO-DIMM SDRAM Modules AC Characteristics 1)2) TA = 0 to 70 °C; VSS = 0 V; VCC = 3.3 V ± 0.3 V, tT = 1 ns Parameter Limit Values Symbol Unit -8A PC100-322 min. max. Clock and Access Time Clock Cycle Time CAS Latency = 3 tCK CAS Latency = 2 10 15 – – ns ns CAS Latency = 3 tCK CAS Latency = 2 – – 100 66 Access Time from Clock CAS Latency = 3 tAC CAS Latency = 2 – – 6 6 ns ns Clock High Pulse Width tCH 3 – ns Clock Low Pulse Width tCL 3 – ns Transition time tT 0.5 10 ns Input Setup Time tIS 2 – ns 4 Input Hold Time tIH 1 – ns 4 Power Down Mode Entry Time tSB 1 – CLK 4 Power Down Mode Exit Setup Time tPDE 1 – CLK 4 Mode Register Set-up time tRSC 2 – CLK Row to Column Delay Time tRCD 20 ns 5 Row Precharge Time tRP 20 ns 5 Row Active Time tRAS 50 100k ns 5 Row Cycle Time tRC 70 – ns 5 Activate(a) to Activate(b) Command period tRRD 20 ns 5 CAS(a) to CAS(b) Command period tCCD 1 Clock Frequency MHz MHz 2, 3 Setup and Hold Parameter Common Parameters INFINEON Technologies 7 Powered by ICminer.com Electronic-Library Service CopyRight 2003 – CLK HYS64V32220GD(L)-8A PC100 144 pin SO-DIMM SDRAM Modules Parameter Limit Values Symbol Unit -8A PC100-322 min. max. Refresh Cycle Refresh Period (8192 cycles) tREF – Self Refresh Exit Time tSREX 1 Data Out Hold Time tOH 3 – ns Data Out to Low Impedance Time tLZ 0 – ns Data Out to High Impedance Time tHZ 3 8 ns DQM Data Out Disable Latency tDQZ – 2 CLK Data Input to Precharge (write recovery) tWR 2 – CLK DQM Write Mask Latency tDQW 0 – CLK 64 ms CLK Read Cycle Write Cycle INFINEON Technologies 8 Powered by ICminer.com Electronic-Library Service CopyRight 2003 2 HYS64V32220GD(L)-8A PC100 144 pin SO-DIMM SDRAM Modules Notes: 1. An initial pause of 100µs is required after power-up, then a Precharge All Banks command must be given followed by 8 Auto Refresh (CBR) cycles before the Mode Register Set Operation can begin. 2. AC timing tests have Vil = 0.4 V and Vih = 2.4 V with the timing referenced to the 1.4 V crossover point. The transition time is measured between Vih and Vil. All AC measurements assume tT=1ns with the AC output load circuit shownSpecified tac and toh parameters are measured with a 50 pF only, without any resistive termination and with a input signal of 1V / ns edge rate between 0.8V and 2.0 V. . t CH 2.4 V 0.4 V CLOCK t CL t SETUP tT t HOLD INPUT 1.4 V t AC t LZ t AC t OH I/O OUTPUT 1.4 V t HZ 50 pF Measurement conditions for tac and toh SPT03404 3. If clock rising time is longer than 1ns, a time (tT -0.5) ns has to be added to this parameter. 4. If tT is longer than 1ns, a time (tT -1) ns has to be added to this parameter. 5. Any time that the refresh Period has been exceeded, a minimum of two Auto (CRB) Refresh commands must be given to “wake-up“ the device. 6. Self Refresh Exit is a synchronous operation and begins on the 2nd positive clock edge after CKE returns high. Self Refresh Exit is not complete until a time period equal to tRC is satisfied once the Self Refresh Exit command is registered. 7. Referenced to the time which the output achieves the open circuit condition, not to output voltage levels. INFINEON Technologies 9 Powered by ICminer.com Electronic-Library Service CopyRight 2003 HYS64V32220GD(L)-8A PC100 144 pin SO-DIMM SDRAM Modules Serial Presence Detects: A serial presence detect storage device - E2PROM - is assembled onto the module. Information about the module configuration, speed, etc. is written into the E2PROM device during module production using a serial presence detect protocol ( I2C synchronous 2-wire bus) SPD-Table: Byte# 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Description SPD Entry Value Number of SPD bytes Total bytes in Serial PD Memory Type Number of Row Addresses (without BS) Number of Column Addresses Number of DIMM Banks Module Data Width Module Data Width (cont’d) Module Interface Levels SDRAM Cycle Time at CL=3 SDRAM Access time from Clock at CL=3 Dimm Config (Error Det/Corr.) Refresh Rate/Type 16 17 18 19 20 SDRAM width, Primary Error Checking SDRAM data width Minimum clock delay for back-toback random column address Burst Length supported Number of SDRAM banks Supported CAS Latencies CS Latencies WE Latencies 21 SDRAM DIMM module attributes 22 SDRAM Device Attributes :General 23 24 SDRAM Cycle Time at CL = 2 SDRAM Access Time from Clock at CL=2 SDRAM Cycle Time at CL = 1 SDRAM Access Time from Clock at CL=1 Minimum Row Precharge Time 25 26 27 INFINEON Technologies 10 Powered by ICminer.com Electronic-Library Service CopyRight 2003 128 256 SDRAM 2 64 0 LVTTL 10.0 ns 6.0 ns none Self-Refresh, 7.8µs n/a / x8 tccd = 1 CLK 1, 2, 4 & 8 2 2, & 3 CS latency = 0 Write latency = 0 non buffered/ non reg. Vcc tol +/10% 12.0 ns 6.0 ns Hex 32Mx64 -8A 80 08 04 0D 09 02 40 00 01 A0 60 00 82 10 00 01 0F 04 06 01 01 00 0E F0 60 not supported not supported FF FF 20 ns 14 HYS64V32220GD(L)-8A PC100 144 pin SO-DIMM SDRAM Modules SPD-Table (cont’d): Byte# Description SPD Entry Value 28 Minimum Row Active to Row Active delay 29 Minimum RAS to CAS delay 30 Minimum Ras pulse width 31 Module Bank Density (per bank) 32 SDRAM input setup time 33 SDRAM input hold time 34 SDRAM data input setup time 35 SDRAM data input hold time 36-61 Superset information 62 SPD Revision 63 Checksum for bytes 0 - 62 64- Manufactures’s information (optional) 125 126 Frequency Specification 127 Details 128+ Unused storage locations INFINEON Technologies 11 Powered by ICminer.com Electronic-Library Service CopyRight 2003 20 ns 20 ns 60 ns 128MB 2 ns 1 ns 2 ns 1 ns Revision 1.2 PC100 Hex 32Mx64 -8A 14 14 32 20 20 10 20 10 FF 12 D5 FF 64 C7 FF HYS64V32220GD(L)-8A PC100 144 pin SO-DIMM SDRAM Modules 64 MByte SO-DIMM Module package (144 pin, dual read-out, single in-line memory module) 67,6 63,6 31.75 3.8 3.3 1 23.2 59 61 32.8 143 1 ± 0.1 2.6 1.5 ±0.1 3.7 2 60 1.8 62 144 4 20 6 4 ±0.1 4.6 2.54 min. 0.25 max. Detail of Contacts 0.6 ±0.05 0.8 INFINEON Technologies GLD09138 12 Powered by ICminer.com Electronic-Library Service CopyRight 2003