HYS 64/72V64220GU SDRAM-Modules 3.3 V 64M × 64/72-Bit SDRAM Modules 168-pin Unbuffered DIMM Modules • 168-pin unbuffered 8 Byte Dual-In-Line SDRAM Modules for PC main memory applications • Programmable CAS Latency, Burst Length, and Wrap Sequence (Sequential & Interleave) • PC100-222 and PC133-333 versions • Auto Refresh (CBR) and Self Refresh • Two bank 64M × 64 and 64M × 72 organization • Decoupling capacitors mounted on substrate • Optimized for byte-write non-parity or ECC applications • Serial Presence Detect with E2PROM • Fully PC board layout compatible to INTEL’s Rev. 1.0 module specification • Uses Infineon 256 Mbit SDRAM components in 32M × 8 organization and TSOPII-54 packages • All inputs and outputs are LVTTL compatible • JEDEC standard Synchronous DRAMs (SDRAM • Gold contact pad, card size: 133.35 mm × 31.75 mm × 4.00 mm (JEDEC MO-161-BA) • Programmed Latencies: Product Speed CL tRCD tRP -7.5 PC133 3 3 3 -8 PC100 2 2 2 • Single + 3.3 V (± 0.3 V) power supply • SDRAM Performance: -7.5 -8 PC133 PC100 Unit fCK Clock Frequency (max.) 133 100 MHz tAC Clock Access time 5.4 6 ns The HYS 64V64220GU and HYS 72V64220GU are industry standard 168-pin 8-byte Dual in-line Memory Modules (DIMMs) which are organized as 64M × 64 and 64M × 72 in two banks high speed memory arrays designed with 256M Synchronous DRAMs (SDRAMs) for non-parity and ECC applications. The DIMMs use 7-5 speed sorted 256 Mbit Synchronous DRAMs (SDRAMs) to meet the PC133-333 requirements and -8 components for the standard PC100 applications. Decoupling capacitors are mounted on the PC board. The PC board design is according to INTEL’s PC100 module specification. The DIMMs have a serial presence detect, implemented with a serial E2PROM using the 2-pin I2C protocol. The first 128 bytes are utilized by the DIMM manufacturer and the second 128 bytes are available to the end user. All Infineon 168-pin DIMMs provide a high performance, flexible 8-byte interface in a 133.35 mm long footprint, with 1.25“ (31.75 mm) height. INFINEON Technologies 1 3.01 HYS 64/72V64220GU SDRAM-Modules Ordering Information Type Code Package Descriptions Module Height HYS 64V64220GU-7.5-C2 PC133-333-520 L-DIM-168-30 PC133 64M × 64 2 bank SDRAM module 1.25“ HYS 72V64220GU-7.5-C2 PC133-333-520 L-DIM-168-30 PC133 64M × 72 2 bank SDRAM module 1.25“ HYS 64V64220GU-8-C2 PC100-222-620 L-DIM-168-30 PC100 64M × 64 2 bank SDRAM module 1.25“ HYS 72V64220GU-8-C2 PC100-222-620 L-DIM-168-30 PC100 64M × 72 2 bank SDRAM module 1.25“ Note: All part numbers end with a place code, designating the die revision. Consult factory for current revision. Example: HYS 64V64220GU-8-C2, indicating Rev.C2 dies are used for SDRAM components. INFINEON Technologies 2 3.01 HYS 64/72V64220GU SDRAM-Modules Pin Definitions and Functions A0 - A12 Address Inputs CLK0 - CLK3 BA0, BA1 Bank Selects DQMB0 - DQMB7 Data Mask DQ0 - DQ63 Data Input/Output CS0 - CS3 Clock Input Chip Select CB0 - CB7 Check Bits (x72 organization only) VDD RAS Row Address Strobe VSS Ground CAS Column Address Strobe SCL Clock for Presence Detect WE Read/Write Input SDA Serial Data Out for Presence Detect N.C./DU No Connection CKE0, CKE1 Clock Enable Power (+ 3.3 V) Address Format Part Number Rows Columns 64M × 64/72 HYS64/72V64220GU 13 10 Bank Select Refresh Period Interval 2 8k 64 ms 7.8 µs Pin Configuration PIN# Symbol PIN# Symbol PIN# Symbol PIN# Symbol 1 VSS 43 VSS 85 VSS 127 VSS 2 DQ0 44 DU 86 DQ32 128 CKE0 3 DQ1 45 CS2 87 DQ33 129 CS3 4 DQ2 46 DQMB2 88 DQ34 130 DQMB6 5 DQ3 47 DQMB3 89 DQ35 131 DQMB7 6 VDD 48 DU 90 VDD 132 N.C. 7 DQ4 49 VDD 91 DQ36 133 VDD 8 DQ5 50 N.C. 92 DQ37 134 N.C. 9 DQ6 51 N.C. 93 DQ38 135 N.C. 10 DQ7 52 N.C. (CB2) 94 DQ39 136 CB6 11 DQ8 53 N.C. (CB3) 95 DQ40 137 CB7 12 VSS 54 VSS 96 VSS 138 VSS 13 DQ9 55 DQ16 97 DQ41 139 DQ48 14 DQ10 56 DQ17 98 DQ42 140 DQ49 15 DQ11 57 DQ18 99 DQ43 141 DQ50 16 DQ12 58 DQ19 100 DQ44 142 DQ51 17 DQ13 59 VDD 101 DQ45 143 VDD 18 VDD 60 DQ20 102 VDD 144 DQ52 INFINEON Technologies 3 3.01 HYS 64/72V64220GU SDRAM-Modules Pin Configuration (cont’d) PIN# Symbol PIN# Symbol PIN# Symbol PIN# Symbol 19 DQ14 61 N.C. 103 DQ46 145 N.C. 20 DQ15 62 DU 104 DQ47 146 DU 21 N.C. (CB0) 63 CKE1 105 N.C. (CB4) 147 N.C. 22 N.C. (CB1) 64 VSS 106 N.C. (CB5) 148 VSS 23 VSS 65 DQ21 107 VSS 149 DQ53 24 N.C. 66 DQ22 108 N.C. 150 DQ54 25 N.C. 67 DQ23 109 N.C. 151 DQ55 26 VDD 68 VSS 110 VDD 152 VSS 27 WE 69 DQ24 111 CAS 153 DQ56 28 DQMB0 70 DQ25 112 DQMB4 154 DQ57 29 DQMB1 71 DQ26 113 DQMB5 155 DQ58 30 CS0 72 DQ27 114 CS1 156 DQ59 31 DU 73 VDD 115 RAS 157 VDD 32 VSS 74 DQ28 116 VSS 158 DQ60 33 A0 75 DQ29 117 A1 159 DQ61 34 A2 76 DQ30 118 A3 160 DQ62 35 A4 77 DQ31 119 A5 161 DQ63 36 A6 78 VSS 120 A7 162 VSS 37 A8 79 CLK2 121 A9 163 CLK3 38 A10 80 N.C. 122 BA0 164 N.C. 39 BA1 81 WP 123 A11 165 SA0 40 VDD 82 SDA 124 VDD 166 SA1 41 VDD 83 SCL 125 CLK1 167 SA2 42 CLK0 84 VDD 126 A12 168 VDD Note: Pin names in paranthese are for the x72 ECC versions; example: Pin 106 = (CB5) INFINEON Technologies 4 3.01 HYS 64/72V64220GU SDRAM-Modules CS1 CS0 CS DQM DQ0-DQ7 DQMB0 DQ(7:0) CS DQM DQ0-DQ7 D8 D0 CS DQM DQ0-DQ7 DQMB1 DQ(15:8) D1 CB(7:0) CS DQM DQ0-DQ7 D4 CS DQM DQ0-DQ7 CS DQM DQ0-DQ7 CS DQM DQ0-DQ7 DQMB4 DQ(39:32) CS DQM DQ0-DQ7 DQMB5 DQ(47:40) D9 D12 CS DQM DQ0-DQ7 D5 D13 CS D16 DQM DQ0-DQ7 D17 CS3 CS2 CS DQM DQ0-DQ7 DQMB2 DQ(23:16) CS DQM DQ0-DQ7 D2 CS DQM DQ0-DQ7 DQMB3 DQ(31:24) CS DQM DQ0-DQ7 A0-A12, BA0, BA1 D0-D15, (D16, D17) VDD D0-D15, (D16, D17) D0-D7, (D8) RAS, CAS, WE D0-D15, (D16, D17) CKE0 D0-D7, (D16) CS DQM DQ0-DQ7 DQMB7 DQ(63:56) D14 CS DQM DQ0-DQ7 D7 D11 D15 E 2 PROM (256 Word x 8 Bit) SA0 SA1 SA2 SCL C0-C31, (C32...C35) VSS CS DQM DQ0-DQ7 D6 D10 D3 SA0 SA1 SA2 SCL SDA WP 47 k Ω Clock Wiring VDD 10 k Ω CKE1 CS DQM DQ0-DQ7 DQMB6 DQ(55:48) CLK0 CLK1 CLK2 CLK3 D9-D15, (D17) 64 M x 64 64 M x 72 4 SDRAM + 3.3 pF 4 SDRAM + 3.3 pF 4 SDRAM + 3.3 pF 4 SDRAM + 3.3 pF 5 SDRAM 5 SDRAM 4 SDRAM + 3.3 pF 4 SDRAM + 3.3 pF Note: D16 & D17 is only used in the x72 ECC version and all resistor values are 10 Ω except otherwise noted. SPB03971 Block Diagram: 64M × 64/72 Two Bank SDRAM DIMM Modules INFINEON Technologies 5 3.01 HYS 64/72V64220GU SDRAM-Modules DC Characteristics TA = 0 to 70 °C; VSS = 0 V; VDD,VDDQ = 3.3 V ± 0.3 V Parameter Symbol Limit Values min. max. Unit Input High Voltage VIH 2.0 VDD + 0.3 V Input Low Voltage VIL – 0.5 0.8 V Output High Voltage (IOUT = – 4.0 mA) VOH 2.4 – V Output Low Voltage (IOUT = 4.0 mA) VOL – 0.4 V Input Leakage Current, any input (0 V < VIN < 3.6 V, all other inputs = 0 V) II(L) – 40 40 µA Output Leakage Current (DQ is disabled, 0 V < VOUT < VDD) IO(L) – 40 40 µA Capacitance TA = 0 to 70 °C; VDD = 3.3 V ± 0.3 V, f = 1 MHz Parameter Symbol Limit Values Unit max. 64M × 64 max. 64M × 72 CI1 105 144 pF Input Capacitance (CS0 - CS3) CI2 32 40 pF Input Capacitance (CLK0 - CLK3) CICL 40 43 pF Input Capacitance (CKE0, CKE1) CI3 65 72 pF Input Capacitance (DQMB0 - DQMB7) CI4 20 25 pF Input/Output Capacitance (DQ0 - DQ63, CB0 - CB7) CIO 17 17 pF Input Capacitance (SCL, SA0-2) CSC 8 8 pF Input/Output Capacitance CSD 8 8 pF INFINEON Technologies 6 Input Capacitance (A0 to A11, BA0, BA1, RAS, CAS, WE) 3.01 HYS 64/72V64220GU SDRAM-Modules Operating Currents per SDRAM Component 1) TA = 0 to 70 oC, VDD = 3.3 V ± 0.3 V (Recommended Operating Conditions unless otherwise noted) Parameter Operating current Test Condition Symbol -7.5 -8 Unit Note – ICC1 230 170 mA 1) tCK = min. ICC2P 2 2 mA 1) tCK = min. ICC2N 40 30 mA 1) CKE ≥ VIH(MIN.) ICC3N 50 45 mA 1) CKE ≤ VIL(MAX.) ICC3P 10 10 mA 1) max. tRC = tRC(MIN.), tCK = tCK(MIN.) Outputs open, Burst Length = 4, CL = 3 All banks operated in random access, all banks operated in ping-pong manner to maximize gapless data access Precharge stand-by current in Power Down Mode CS = VIH(MIN.), CKE ≤ VIL(MAX.) Precharge Stand-by Current in Non-Power Down Mode CS = VIH (MIN.), CKE ≥ VIH(MIN.) No operating current tCK = min., CS = VIH(MIN.), active state (max. 4 banks) Burst operating current tCK = min., Read command cycling – ICC4 150 100 mA 1), 2) Auto refresh current tCK = min., Auto Refresh command cycling – ICC5 240 220 mA 1) ICC6 3 3 mA 1) Self refresh current Self Refresh Mode, CKE = 0.2 V INFINEON Technologies 7 3.01 HYS 64/72V64220GU SDRAM-Modules AC Characteristics 3), 4) TA = 0 to 70 °C; VSS = 0 V; VDD = 3.3 V ± 0.3 V, tT = 1 ns Parameter Symbol Limit Values -7.5 PC133-333 Unit Note -8 PC100-222 min. max. min. max. 7.5 12 – – 10 10 – – ns ns – 133 – 100 MHz – 100 – 100 MHz Clock Clock Cycle Time CAS Latency = 3 CAS Latency = 2 tCK System Frequency CAS Latency = 3 CAS Latency = 2 for HYS64/72V64220GU-7.5-C2 fCK Clock Access Time CAS Latency = 3 CAS Latency = 2 tAC Clock High Pulse Width Clock Low Pulse Width – – *) 4), 5) – – 5.4 6 – – 6 6 ns ns tCH 2.5 – 3 – ns 6) tCL 2.5 – 3 – ns 6) Input Setup Time tCS 1.5 – 2 – ns 7) Input Hold Time tCH 0.8 – 1 – ns 7) Power Down Mode Entry Time tSB – 1 – 1 CLK 8) Power Down Mode Exit Setup Time tPDE 1 – 1 – CLK 9) Mode Register Setup Time tRSC 2 – 2 – CLK Transition Time (rise and fall) tT 1 – 1 – ns – RAS to CAS Delay tRCD 20 – 20 – ns – Precharge Time tRP 20 – 20 – ns – Active Command Period tRAS 45 100k 50 100k ns – Cycle Time tRC 67.5 – 70 – ns – Bank to Bank Delay Time tRRD 15 – 16 – ns – 1 – 1 – CLK – Setup and Hold Times Common Parameters CAS to CAS Delay Time (same bank) tCCD INFINEON Technologies 8 3.01 HYS 64/72V64220GU SDRAM-Modules AC Characteristics (cont’d) 3), 4) TA = 0 to 70 °C; VSS = 0 V; VDD = 3.3 V ± 0.3 V, tT = 1 ns Parameter Symbol Limit Values -7.5 PC133-333 Unit Note -8 PC100-222 min. max. min. max. Refresh Cycle Refresh Period (8192 cycles) tREF – 64 – 64 ms 8) Self Refresh Exit Time tSREX 1 – 1 – CLK 10) Data Out Hold Time tOH 3 – 3 – ns 4) Data Out to Low Impedance tLZ 0 – 0 – ns – Read Cycle Data Out to High Impedance tHZ 3 7 3 8 ns 11) DQM Data Out Disable Latency tDQZ – 2 – 2 CLK – Data Input to Precharge (write recovery) tWR 2 – 2 – CLK – DQM Write Mask Latency tDQW 0 – 0 – CLK – Write Cycle Notes 1. These parameters depend on the cycle rate. These values are measured at 133 MHz for -7.5 modules and at 100 Mhz for -8 modules. Input signals are changed once during tCK, except for ICC6 and for standby currents when tCK = infinity. All values are shown per memory component. 2. These parameters are measured with continuous data stream during read access and all DQ toggling. CL = 3 and BL = 4 assumed and the VDDQ current is excluded. 3. All AC characteristics are shown on SDRAM component level. An initial pause of 100 µs is required after power-up, then a Precharge All Banks command must be given followed by eight Auto-Refresh (CBR) cycles before the Mode Register Set Operation can begin. 4. AC timing tests have VIL = 0.4 V and VIH = 2.4 V with the timing referenced to the 1.4 V crossover point. The transition time is measured between VIH and VIL. All AC measurements assume tT = 1 ns with the AC output load circuit show. Specified tAC and tOH parameters are measured with a 50 pF only, without any resistive termination and with a input signal of 1 V/ns edge rate between 0.8 V and 2.0 V. 5. If clock rising time is longer than 1 ns, a time (tT/2 – 0.5) ns must be added to this parameter. INFINEON Technologies 9 3.01 HYS 64/72V64220GU SDRAM-Modules 6. Rated at 1.4 V 7. If tT is longer than 1 ns, a time (tT – 1) ns has to be added to this parameter. 8. Anytime the Refresh Period has been exceeded, a minimum of two Auto-Refresh (CBR) commands must be given to “wake-up” the device. 9. Timing is asynchronous. If setup time is not met by rising edge of the clock then the CKE signal is assumed latched on the next cycle. 10.Self-Refresh Exit is a synchronous operation and begins on the second positive clock edge after CKE returns high. Self-Refresh Exit is not complete until a time period equal to tRC is satisfied after the Self Refresh Exit command is registered. 11.This is referenced to the time at which the output achieves the open circuit condition, not to output voltage levels. t CH 2.4 V 0.4 V CLOCK t CL t SETUP tT t HOLD 1.4 V INPUT t AC t LZ t AC I/O t OH 50 pF OUTPUT 1.4 V Measurement conditions for tAC and tOH t HZ SPT03404 Note: *) 256MByte PC133 modules with place codes earlier than “-C2” (f.e. “A” and “B”) are only backward compatible to PC100 3-2-2 when operating on a 100 Mhz memory bus. A serial presence detect storage device - E2PROM - is assembled onto the module. Information about the module configuration, speed, etc. is written into the E2PROM device during module production using a serial presence detect protocol (I2C synchronous 2-wire bus). INFINEON Technologies 10 3.01 HYS 64/72V64220GU SDRAM-Modules SPD-Table for PC133 Modules Byte# Description SPD Entry Value 0 1 2 3 Number of SPD Bytes Total Bytes in Serial PD Memory Type Number of Row Addresses (without BS bits) Number of Column Addresses Number of DIMM Banks Module Data Width Module Data Width (cont’d) Module Interface Levels SDRAM Cycle Time at CL = 3 SDRAM Access Time from Clock at CL = 3 DIMM Config Refresh Rate/Type SDRAM Width, Primary Error Checking SDRAM Data Width Minimum Clock Delay for Back-to-Back Random Column Address Burst Length Supported Number of SDRAM Banks Supported CAS Latencies CS Latencies WE Latencies SDRAM DIMM Module Attributes SDRAM Device Attributes: General Min. Clock Cycle Time at CAS Latency = 2 for HYS64//72V64220GU-7.5-C2 Max. Data Access Time from Clock for CL = 2 Minimum Clock Cycle Time at CL = 1 Maximum Data Access Time from Clock at CL = 1 Minimum Row Precharge Time Minimum Row Active to Row Active Delay 128 256 SDRAM 13 Hex 64M × 64 64M × 72 -7.5 -7.5 80 80 08 08 04 04 0D 0D 10 2 64 /72 0 LVTTL 7.5 ns 5.4 ns none/ECC Self-Refresh, 7.8 µs x8 na / x8 tCCD = 1 CLK 0A 02 40 00 01 75 54 00 82 08 00 01 0A 02 48 00 01 75 54 02 82 08 08 01 1, 2, 4 & 8 4 CAS latency = 2 & 3 CS latency = 0 Write latency = 0 non buffered/non reg. VDD tol +/– 10% 10.0 ns 0F 04 06 01 01 00 0E A0 0F 04 06 01 01 00 0E A0 6.0 ns 60 60 not supported not supported FF FF FF FF 20 ns 15 14 0F 14 0F 20 ns 45 ns 256 MByte 1.5 ns 14 2D 40 15 14 2D 40 15 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 tRRD 29 30 31 32 Minimum RAS to CAS Delay tRCD Minimum RAS Pulse Width tRAS Module Bank Density (per bank) SDRAM Input Setup Time INFINEON Technologies 11 3.01 HYS 64/72V64220GU SDRAM-Modules SPD-Table for PC133 Modules (cont’d) Byte# Description SPD Entry Value 33 34 35 36-61 SDRAM Input Hold Time SDRAM Data Input Hold Time SDRAM Data Input Setup Time Superset Information (may be used in future) 62 SPD Revision 63 Checksum for Bytes 0 - 62 for HYS64/72V64220GU-7.5-C2 64-125 Manufacturers Information (FFH if not used) 126 Frequency Specification 127 100 MHz Support Details for HYS64/72V64220GU-7.5-C2 128+ Unused Storage Locations INFINEON Technologies 0.8 ns 1.5 ns 0.8 ns – Hex 64M × 64 64M × 72 -7.5 -7.5 08 08 15 15 08 08 FF FF Revision 1.2 – 12 37 12 49 – XX XX 64 64 FF FF FF FF – – 12 3.01 HYS 64/72V64220GU SDRAM-Modules SPD-Table for PC100 Modules Byte# Description SPD Entry Value 0 1 2 3 Number of SPD Bytes Total Bytes in Serial PD Memory Type Number of Row Addresses (without BS bits) Number of Column Addresses Number of DIMM Banks Module Data Width Module Data Width (cont’d) Module Interface Levels SDRAM Cycle Time at CL = 3 SDRAM Access Time from Clock at CL = 3 DIMM Config Refresh Rate/Type SDRAM Width, Primary Error Checking SDRAM Data Width Minimum Clock Delay for Back-to-Back Random Column Address Burst Length Supported Number of SDRAM Banks Supported CAS Latencies CS Latencies WE Latencies SDRAM DIMM Module Attributes SDRAM Device Attributes: General Min. Clock Cycle Time at CAS Latency = 2 Max. Data Access Time from Clock for CL = 2 Minimum Clock Cycle Time at CL = 1 Maximum Data Access Time from Clock at CL = 1 Minimum Row Precharge Time Minimum Row Active to Row Active Delay 128 256 SDRAM 13 Hex 64M × 64 64M × 72 -8 -8 80 80 08 08 04 04 0D 0D 10 2 64 / 72 0 LVTTL 10.0 ns 6.0 ns none/ECC Self-Refresh, 7.8 µs x8 na / x8 tCCD = 1 CLK 0A 02 40 00 01 A0 60 00 82 08 00 01 0A 02 48 00 01 A0 60 02 82 08 08 01 1, 2, 4 & 8 4 CAS latency = 2 & 3 CS latency = 0 Write latency = 0 non buffered/non reg. VDD tol +/– 10% 10.0ns 6.0 ns 0F 04 06 01 01 00 0E A0 60 0F 04 06 01 01 00 0E A0 60 not supported not supported FF FF FF FF 20 ns 16 ns 14 10 14 10 20 ns 50 ns 256 MByte 2 ns 1 ns 14 32 40 20 10 14 32 40 20 10 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 tRRD 29 30 31 32 33 Minimum RAS to CAS Delay tRCD Minimum RAS Pulse Width tRAS Module Bank Density (per bank) SDRAM Input Setup Time SDRAM Input Hold Time INFINEON Technologies 13 3.01 HYS 64/72V64220GU SDRAM-Modules SPD-Table for PC100 Modules Byte# Description SPD Entry Value 34 35 36-61 SDRAM Data Input Setup Time SDRAM Data Input Hold Time Superset Information (may be used in future) 62 SPD Revision 63 Checksum for Bytes 0 - 62 64-125 Manufacturers Information 126 Frequency Specification 127 100 MHz Support Details 128+ Unused Storage Locations INFINEON Technologies 14 2 ns 1 ns – Hex 64M × 64 64M × 72 -8 -8 20 20 10 10 FF FF Revision 1.2 – – 100 MHz – – 12 9A XX 64 FF FF 12 AC XX 64 FF FF 3.01 HYS 64/72V64220GU SDRAM-Modules Package Outlines L-DIM-168-30 (JEDEC MO-161-BA) SDRAM DIMM Module Package HYS 64/72V64220GU 133.35 4 max. 31.75 4 127.35 *) 3 1 10 3 11 6.35 1.27 40 41 6.35 84 1.27 42.18 2 85 94 95 124 125 168 17.78 3.125 91 x 1.27 = 115.57 *) 3 3 min. *) on ECC modules only 0.2 2.54 min. Detail of Contacts Note: All tolerances according to JEDEC standard 1 1.27 INFINEON Technologies L-DIM-168-30 15 3.01 HYS 64/72V64220GU SDRAM-Modules Change List: 14.1.1999 18.4.1999 12.5.99 3.8.99 23.8.99 6.9.99 20.10.99 2.12.99 20.1.2000 10.3.2000 10.5.2000 5.03.2001 Input capacitances adjusted -8A speed sort added Infineon logo added SPD codes updated according to new 256M speedsorts Some ICC current values changed due to new inputs PC133 merged into this datasheet Byte 126 changed to 64h for PC133 modules Template from R&L CL=2 max. frequency changed to 83 Mhz for -7.5 modules Some timing parameters adjusted according to INTELs PC133 specification Capacitance values for x72 adjusted (new measurements) Implemented differences between 256Mbit S20 and S17 PC133 modules 256Mbit S20 based PC133 modules are backward compatible to PC100 3-2-2 256Mbit S17 based modules are backwards compatible to PC100-2-2-2 leading to changes in SPD code of bytes 23, 63 (checksum) and 126 TPCR issued Reference to JEDEC MO-161-BA added -8A and -8B speed sorts removed PC133 timing parameters only for 256M S17 and later versions References to 256M S20 removed ICC currents according to 256M S17 datasheet INFINEON Technologies 16 3.01