DATA SHEET MOS INTEGRATED CIRCUIT µ PD17704A, 17705A, 17707A, 17708A, 17709A 4-BIT SINGLE-CHIP MICROCONTROLLERS WITH DEDICATED HARDWARE FOR DIGITAL TUNING SYSTEM DESCRIPTION The µ PD17704A, 17705A, 17707A, 17708A, and 17709A are 4-bit single-chip CMOS microcontrollers containing hardware for digital tuning systems. Provided with a wealth of hardware, these microcontrollers are available with many variations of ROM and RAM capacities to support various applications. Therefore, a high-performance, multi-function digital tuning system can be configured with only one chip. In addition, a one-time PROM model, µ PD17P709A, which can be written only once and is ideal for program evaluation and small-scale production of a µ PD17704A, 17705A, 17707A, 17708A, or 17709A system, is also available. FEATURES µ PD17704 Program memory (ROM) 16 KB (8192 × 16 bits) General-purpose data memory (RAM) 672 × 4 bits µ PD17705 µ PD17707 24 KB (12288 × 16 bits) µ PD17708 32 KB (16384 × 16 bits) 1120 × 4 bits • Instruction execution time µ PD17709 1776 × 4 bits • Many interrupts 1.78 µ s (with f X = 4.5 MHz crystal oscillator) • PLL frequency synthesizer External: 6 sources Internal: Dual modulus prescaler (130 MHz MAX.), 6 sources • Power-on reset, CE reset, and power failure programmable divider, phase comparator, charge detector • Supply voltage: V DD = 5 V ±10% pump • Abundant peripheral hardware units General-purpose I/O ports, serial interfaces, A/D converter, D/A converter (PWM output), BEEP output, frequency counter Unless otherwise specified, the µ PD17709A is treated as the representative model in this document. The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. Not all devices/types available in every country. Please check with local NEC representative for availability and additional information. Document No. U15722EJ1V1DS00 (1st edition) Date Published October 2001 N CP (K) Printed in Japan The mark shows major revised points. © 2001 µPD17704A, 17705A, 17707A, 17708A, 17709A ORDERING INFORMATION Part Number Package µ PD17704AGC-×××-3B9 80-pin plastic QFP (14 × 14) µ PD17705AGC-×××-3B9 80-pin plastic QFP (14 × 14) µ PD17707AGC-×××-3B9 80-pin plastic QFP (14 × 14) µ PD17708AGC-×××-3B9 80-pin plastic QFP (14 × 14) µ PD17709AGC-×××-3B9 80-pin plastic QFP (14 × 14) Remark ××× indicates ROM code suffix. FUNCTIONAL OUTLINE Part Number Item Program memory (ROM) µ PD17704A µ PD17705A µ PD17707A 24 KB (12288 × 16 bits) 16 KB µ PD17708A µ PD17709A 32 KB (16384 × 16 bits) (8192 × 16 bits) General-purpose data memory (RAM) 672 × 4 bits Instruction execution time 1.78 µ s (with f X = 4.5 MHz crystal oscillator) General-purpose ports • I/O ports: 46 • Input ports: 12 • Output ports: 4 Stack levels • Address stack: 15 levels • Interrupt stack: 4 levels • DBF stack: 4 levels (can be manipulated via software) Interrupts 1176 × 4 bits • External: 6 sources (falling edge of CE pin, INT0 through INT4) • Internal: Timer 5 • • • • 6 sources (timers 0 through 3, serial interfaces 0 and 1) channels Basic timer (clock: 10, 20, 50, 100 Hz): 8-bit timer with gate counter (clock: 1 k, 2 k, 10 k, 100 kHz): 8-bit timer (clock: 1 kHz, 2 kHz, 10 kHz, 100 kHz): 8-bit timer multiplexed with PWM (clock: 440 Hz, 4.4 kHz): 1 1 2 1 channel channel channels channel A/D converter 8 bits × 6 channels (hardware mode and software mode selectable) D/A converter (PWM) 3 channels (8-bit or 9-bit resolution selectable by software) Output frequency: 4.4 kHz, 440 Hz (with 8-bit PWM selected) 2.2 kHz, 220 Hz (with 9-bit PWM selected) Serial interface 2 units (3 channels) • 3-wire serial I/O: 2 channels • 2-wire serial I/O/I 2 C bus: 1 channel PLL frequency synthesizer 2 1120 × 4 bits Division mode • Direct division mode (VCOL pin (MF mode): 0.5 to 3 MHz) • Pulse swallow mode (VCOL pin (HF mode): 10 to 40 MHz) (VCOH pin (VHF mode): 60 to 130 MHz) Reference frequency 13 types selectable (1, 1.25, 2.5, 3, 5, 6.25, 9, 10, 12.5, 18, 20, 25, 50 kHz) Charge pump Two error-out output pins (EO0, EO1) Phase comparator Unlock status detectable by program Data Sheet U15722EJ1V1DS µPD17704A, 17705A, 17707A, 17708A, 17709A Part Number Item µ PD17704A µ PD17705A µ PD17707A µ PD17708A µ PD17709A Frequency counter • Intermediate frequency (IF) measurement P1C0/FMIFC pin : 10 to 11 MHz in FMIF mode 0.4 to 0.5 MHz in AMIF mode P1C1/AMIFC pin: 0.4 to 0.5 MHz in AMIF mode • External gate width measurement P2A1/FCG1, P2A0/FCG0 pin BEEP output 2 pins Output frequency: 1 kHz, 3 kHz, 4 kHz, 6.7 kHz (BEEP0 pin) 67 Hz, 200 Hz, 3 kHz, 4 kHz (BEEP1 pin) Reset • Power-on reset (on power application) • Reset by RESET pin • Watchdog timer reset Can be set only once on power application: 65536 instructions, 131072 instructions, or no-use selectable • Stack pointer overflow/underflow reset Can be set only once on power application: interrupt stack or address stack selectable • CE reset (CE pin low → high level) CE reset delay timing can be set. • Power failure detection function Standby • Clock stop mode (STOP) • Halt mode (HALT) Supply voltage • PLL operation: VDD = 4.5 to 5.5 V • CPU operation: V DD = 3.5 to 5.5 V Package 80-pin plastic QFP (14 × 14) Data Sheet U15722EJ1V1DS 3 µPD17704A, 17705A, 17707A, 17708A, 17709A PIN CONFIGURATION (TOP VIEW) 80-pin plastic QFP (14 × 14) µ PD17704AGC-×××-3B9 µ PD17705AGC-×××-3B9 µ PD17707AGC-×××-3B9 µ PD17708AGC-×××-3B9 P0C1 P0C0 P0A3/SDA P0A2/SCL P0A1/SCK0 P0A0/SO0 P0B3/SI0 P0B2/SCK1 P0B1/SO1 P0B0/SI1 P2D2 P2D1 P2D0 REG GND0 XIN XOUT CE VDD0 RESET µ PD17709AGC-×××-3B9 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 INT2 1 60 P0C2 P1A3/INT4 2 59 P0C3 P1A2/INT3 3 58 P2C0 P1A1 4 57 P2C1 P1A0/TM0G 5 56 P2C2 P3A3 6 55 P2C3 P3A2 7 54 P3D0 P3A1 8 53 P3D1 P3A0 9 52 P3D2 P3B3 10 51 P3D3 P3B2 11 50 P3C0 P3B1 12 49 P3C1 P3B0 13 48 P3C2 P2A2 14 47 P3C3 P2A1/FCG1 15 46 P2B0 P2A0/FCG0 16 45 P2B1 P1B3 17 44 P2B2 P1B2/PWM2 18 43 P2B3 P1B1/PWM1 19 42 INT0 P1B0/PWM0 20 41 INT1 Data Sheet U15722EJ1V1DS P1D0/BEEP0 P1D2 P1D1/BEEP1 P1D3 TEST EO1 EO0 GND1 VCOL VCOH VDD1 P1C0/FMIFC P1C1/AMIFC P1C2/AD4 P1C3/AD5 P0D0/AD0 P0D1/AD1 P0D2/AD2 GND2 4 P0D3/AD3 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 µPD17704A, 17705A, 17707A, 17708A, 17709A PIN NAMES AD0 to AD5: A/D converter input P2C0 to P2C3: Port 2C AMIFC: AM frequency counter input P2D0 to P2D2: Port 2D BEEP0, BEEP1: BEEP output P3A0 to P3A3: Port 3A CE: Chip enable P3B0 to P3B3: Port 3B EO0, EO1: Error-out output P3C0 to P3C3: Port 3C FCG0, FGC1: Frequency counter gate input P3D0 to P3D3: Port 3D FMIFC: FM frequency counter input REG: CPU regulator GND0 to GND2: Ground 0 to 2 RESET: Reset input INT0 to INT4: External interrupt input SCK0, SCK1: 3-wire serial clock I/O PWM0 to PWM2: D/A converter output SCL: 2-wire serial clock I/O P0A0 to P0A3: Port 0A SDA: 2-wire serial data I/O P0B0 to P0B3: Port 0B SI0, SI1: 3-wire serial data input P0C0 to P0C3: Port 0C SO0, SO1: 3-wire serial data output P0D0 to P0D3: Port 0D TEST: Test input P1A0 to P1A3: Port 1A TM0G: Timer 0 gate input P1B0 to P1B3: Port 1B VCOH: Local oscillation high input P1C0 to P1C3: Port 1C VCOL: Local oscillation low input P1D0 to P1D3: Port 1D V DD0, V DD1: Power supply P2A0 to P2A2: Port 2A X IN, X OUT: Main clock oscillation P2B0 to P2B3: Port 2B Data Sheet U15722EJ1V1DS 5 µPD17704A, 17705A, 17707A, 17708A, 17709A BLOCK DIAGRAM P0A0 to P0A3 4 P0B0 to P0B3 4 VCOH PLL RF VCOL EO0 EO1 P0C0 to P0C3 4 P0D0 to P0D3 4 P1A0 to P1A3 4 P1B0 to P1B3 4 RAM 672 × 4 bits ( µPD17704A, 17705A) 1120 × 4 bits ( µPD17707A, 17708A) 1776 × 4 bits ( µ PD17709A) P1C0 to P1C3 4 SYSREG P1D0 to P1D3 4 SO0/P0A0 SCK0/P0A1 Serial interface 0 SCL/P0A2 SDA/P0A3 SI0/P0B3 SCK1/P0B2 Ports P2A0 to P2A2 3 P2B0 to P2B3 4 P2C0 to P2C3 4 P2D0 to P2D2 3 Serial interface 1 SO1/P0B1 SI1/P0B0 ALU BEEP BEEP0/P1D0 BEEP1/P1D1 P3A0 to P3A3 4 P3B0 to P3B3 4 P3C0 to P3C3 4 P3D0 to P3D3 4 Instruction decoder INT0 INT1 Interrupt control INT2 INT3/P1A2 ROM 8192 × 16 bits ( µ PD17704A) 12288 × 16 bits ( µ PD17705A, 17707A) 16384 × 16 bits ( µ PD17708A, 17709A) INT4/P1A3 FCG0/P2A0 Frequency counter FCG1/P2A1 FMIFC/P1C0 AMIFC/P1C1 AD0/P0D0 AD1/P0D1 AD2/P0D2 AD3/P0D3 A/D converter 8-bit timer 0 gate counter Program counter TM0G/P1A0 AD4/P1C2 AD5/P1C3 8-bit timer 1 Stack PWM0/P1B0 PWM1/P1B1 D/A converter 8-bit timer 2 PWM2/P1B2 8-bit timer 3 CPU Peripheral OSC XIN XOUT CE Basic timer Reset RESET VDD0, VDD1 GND0 to GND2 VCPU 6 Data Sheet U15722EJ1V1DS Regulator REG µPD17704A, 17705A, 17707A, 17708A, 17709A CONTENTS 1. PIN FUNCTIONS .............................................................................................................................. 1.1 Pin Function List .................................................................................................................. 1.2 Equivalent Circuits of Pins ................................................................................................. 1.3 Connections of Unused Pins .............................................................................................. 1.4 Cautions on Using CE, INT0 to INT4, and RESET Pins .................................................... 1.5 Cautions on Using TEST Pin .............................................................................................. 11 11 16 21 23 23 2. PROGRAM MEMORY (ROM) .......................................................................................................... 2.1 Outline of Program Memory ............................................................................................... 2.2 Program Memory ................................................................................................................. 2.3 Program Counter ................................................................................................................. 2.4 Flow of Program .................................................................................................................. 2.5 Cautions on Using Program Memory ................................................................................ 24 24 25 26 26 31 3. ADDRESS STACK (ASK) ................................................................................................................ 3.1 Outline of Address Stack .................................................................................................... 3.2 Address Stack Register (ASR) ........................................................................................... 3.3 Stack Pointer (SP) ................................................................................................................ 3.4 Operation of Address Stack ............................................................................................... 3.5 Cautions on Using Address Stack ..................................................................................... 32 32 32 34 35 36 4. DATA MEMORY (RAM) ................................................................................................................... 4.1 Outline of Data Memory ...................................................................................................... 4.2 Configuration and Function of Data Memory .................................................................... 4.3 Data Memory Addressing ................................................................................................... 4.4 Cautions on Using Data Memory ....................................................................................... 37 37 40 44 45 5. SYSTEM REGISTERS (SYSREG) ................................................................................................... 5.1 Outline of System Registers ............................................................................................... 5.2 System Register List ........................................................................................................... 5.3 Address Register (AR) ........................................................................................................ 5.4 Window Register (WR) ........................................................................................................ 5.5 Bank Register (BANK) ......................................................................................................... 5.6 Index Register (IX) and Data Memory Row Address Pointer (MP: Memory Pointer) .... 5.7 General Register Pointer (RP) ............................................................................................ 5.8 Program Status Word (PSWORD) ...................................................................................... 46 46 47 48 50 51 52 54 56 6. GENERAL REGISTER (GR) ............................................................................................................ 6.1 Outline of General Register ................................................................................................ 6.2 General Register .................................................................................................................. 6.3 Generating Address of General Register by Each Instruction ........................................ 6.4 Cautions on Using General Register ................................................................................. 58 58 58 59 59 Data Sheet U15722EJ1V1DS 7 µPD17704A, 17705A, 17707A, 17708A, 17709A 7. ALU (Arithmetic Logic Unit) BLOCK ............................................................................................. 7.1 Outline of ALU Block .......................................................................................................... 7.2 Configuration and Function of Each Block ....................................................................... 7.3 ALU Processing Instruction List ........................................................................................ 7.4 Cautions on Using ALU ....................................................................................................... 60 60 61 61 65 8. REGISTER FILE (RF) ...................................................................................................................... 8.1 Outline of Register File ....................................................................................................... 8.2 Configuration and Function of Register File ..................................................................... 8.3 Control Registers ................................................................................................................. 8.4 Port I/O Selection Registers ............................................................................................... 8.5 Cautions on Using Register File ........................................................................................ 66 66 67 68 80 86 9. DATA BUFFER (DBF) ..................................................................................................................... 9.1 Outline of Data Buffer .......................................................................................................... 9.2 Data Buffer ........................................................................................................................... 9.3 Relationship Between Peripheral Hardware and Data Buffer .......................................... 9.4 Cautions on Using Data Buffer ........................................................................................... 87 87 88 89 92 10. DATA BUFFER STACK ................................................................................................................... 10.1 Outline of Data Buffer Stack ............................................................................................... 10.2 Data Buffer Stack Register ................................................................................................. 10.3 Data Buffer Stack Pointer ................................................................................................... 10.4 Operation of Data Buffer Stack .......................................................................................... 10.5 Using Data Buffer Stack ...................................................................................................... 10.6 Cautions on Using Data Buffer Stack ................................................................................ 93 93 93 95 96 97 97 11. GENERAL-PURPOSE PORTS ....................................................................................................... 11.1 Outline of General-Purpose Port ........................................................................................ 11.2 General-Purpose I/O Ports (P0A, P0B, P0C, P1D, P2A, P2B, P2C, P2D, P3A, P3B, P3C, P3D) .............................................................................................................................. 11.3 General-Purpose Input Port (P0D, P1A, P1C) ................................................................... 11.4 General-Purpose Output Port (P1B) .................................................................................. 98 98 101 115 118 12. INTERRUPTS ................................................................................................................................... 12.1 Outline of Interrupt Block ................................................................................................... 12.2 Interrupt Control Block ....................................................................................................... 12.3 Interrupt Stack Register ...................................................................................................... 12.4 Stack Pointer, Address Stack Registers, and Program Counter .................................... 12.5 Interrupt Enable Flip-Flop (INTE) ....................................................................................... 12.6 Acknowledging Interrupt .................................................................................................... 12.7 Operations After Interrupt Has Been Acknowledged ....................................................... 12.8 Returning from Interrupt Routine ....................................................................................... 12.9 External Interrupts (CE and INT0 to INT4 Pins) ................................................................ 12.10 Internal Interrupts ................................................................................................................ 119 119 121 135 139 139 140 145 145 146 149 13. TIMERS ............................................................................................................................................ 150 13.1 Outline of Timers ................................................................................................................. 150 8 Data Sheet U15722EJ1V1DS µPD17704A, 17705A, 17707A, 17708A, 17709A 13.2 13.3 13.4 13.5 13.6 Basic Timer 0 ....................................................................................................................... Timer 0 .................................................................................................................................. Timer 1 .................................................................................................................................. Timer 2 .................................................................................................................................. Timer 3 .................................................................................................................................. 152 165 174 181 188 14. A/D CONVERTER ............................................................................................................................ 14.1 Outline of A/D Converter ..................................................................................................... 14.2 Input Selection Block .......................................................................................................... 14.3 Compare Voltage Generation and Compare Blocks ........................................................ 14.4 Comparison Timing Chart ................................................................................................... 14.5 Using A/D Converter ............................................................................................................ 14.6 Cautions on Using A/D Converter ...................................................................................... 14.7 Status After Reset ................................................................................................................ 195 195 196 198 201 202 203 203 15. D/A CONVERTER (PWM MODE) .................................................................................................... 15.1 Outline of D/A Converter ..................................................................................................... 15.2 PWM Clock Selection Register ........................................................................................... 15.3 PWM Output Selection Block ............................................................................................. 15.4 Duty Setting Block ............................................................................................................... 15.5 Clock Generation Block ...................................................................................................... 15.6 D/A Converter Output Wave ............................................................................................... 15.7 Example of Using D/A Converter ....................................................................................... 15.8 Status After Reset ................................................................................................................ 204 204 205 206 209 213 213 216 217 16. SERIAL INTERFACES .................................................................................................................... 16.1 Outline of Serial Interfaces ................................................................................................. 16.2 Serial Interface 0 .................................................................................................................. 16.3 Serial Interface 1 .................................................................................................................. 218 218 219 247 17. PLL FREQUENCY SYNTHESIZER ................................................................................................. 17.1 Outline of PLL Frequency Synthesizer .............................................................................. 17.2 Input Selection Block and Programmable Divider ........................................................... 17.3 Reference Frequency Generator ........................................................................................ 17.4 Phase Comparator (φ-DET), Charge Pump, and Unlock FF ............................................. 17.5 PLL Disabled Status ............................................................................................................ 17.6 Using PLL Frequency Synthesizer ..................................................................................... 17.7 Status After Reset ................................................................................................................ 257 257 258 262 264 268 269 273 18. FREQUENCY COUNTER ................................................................................................................ 18.1 Outline of Frequency Counter ............................................................................................ 18.2 I/O Selection Block and Gate Time Control Block ............................................................ 18.3 Start/Stop Control Block and IF Counter ........................................................................... 18.4 Using IF Counter .................................................................................................................. 18.5 Using External Gate Counter .............................................................................................. 18.6 Status After Reset ................................................................................................................ 274 274 275 278 285 287 288 Data Sheet U15722EJ1V1DS 9 µPD17704A, 17705A, 17707A, 17708A, 17709A 19. BEEP ............................................................................................................................................... 19.1 Outline of BEEP ................................................................................................................... 19.2 I/O Selection Block and Output Selection Block .............................................................. 19.3 Clock Selection Block and Clock Generation Block ........................................................ 19.4 Output Waveform of BEEP ................................................................................................. 19.5 Status After Reset ................................................................................................................ 289 289 290 292 293 293 20. STANDBY ........................................................................................................................................ 20.1 Outline of Standby Function ............................................................................................... 20.2 Halt Function ........................................................................................................................ 20.3 Clock Stop Function ............................................................................................................ 20.4 Device Operation in Halt and Clock Stop Status .............................................................. 20.5 Cautions on Processing of Each Pin in Halt and Clock Stop Status .............................. 20.6 Device Operation Control Function of CE Pin .................................................................. 294 294 295 301 303 303 305 21. RESET .............................................................................................................................................. 21.1 Outline of Reset ................................................................................................................... 21.2 CE Reset ............................................................................................................................... 21.3 Power-on Reset .................................................................................................................... 21.4 Relationship Between CE Reset and Power-on Reset ..................................................... 21.5 Reset by RESET Pin ............................................................................................................ 21.6 WDT&SP Reset .................................................................................................................... 21.7 Power Failure Detection ...................................................................................................... 308 308 309 315 318 322 323 329 22. INSTRUCTION SET ......................................................................................................................... 22.1 Outline of Instruction Set .................................................................................................... 22.2 Legend .................................................................................................................................. 22.3 Instruction List ..................................................................................................................... 22.4 Assembler (RA17K) Embedded Macro Instruction ........................................................... 334 334 335 336 338 23. RESERVED SYMBOLS ................................................................................................................... 23.1 Data Buffer (DBF) ................................................................................................................. 23.2 System Registers (SYSREG) .............................................................................................. 23.3 Port Registers ...................................................................................................................... 23.4 Register File (Control Registers) ........................................................................................ 23.5 Peripheral Hardware Registers .......................................................................................... 23.6 Others ................................................................................................................................... 339 339 339 340 342 347 347 24. ELECTRICAL CHARACTERISTICS ............................................................................................... 348 25. PACKAGE DRAWING ..................................................................................................................... 351 26. RECOMMENDED SOLDERING CONDITIONS ............................................................................... 352 APPENDIX A. CAUTIONS ON CONNECTING CRYSTAL RESONATOR ........................................... 353 APPENDIX B. DEVELOPMENT TOOLS .............................................................................................. 354 10 Data Sheet U15722EJ1V1DS µPD17704A, 17705A, 17707A, 17708A, 17709A 1. PIN FUNCTIONS 1.1 Pin Function List Pin No. Symbol Function Output Form 1 41 42 INT2 INT1 INT0 Edge-detectable vectored interrupt input pins. Rising or falling edge can be specified. – 2 3 4 5 P1A3/INT4 P1A2/INT3 P1A1 P1A0/TM0G Port 1A multiplexed with external interrupt request signal input and event signal input pins. • P1A3 to P1A0 • 4-bit input port • INT4, INT3 • Edge-detectable vectored interrupt • TM0G • Input for gate of 8-bit timer 0 – After reset 6 | 9 P3A3 | P3A0 Power-on reset WDT&SP reset Input (P1A3 to P1A0) Input (P1A3 to P1A0) With clock stopped CE reset Retained Retained 4-bit I/O port. Input or output can be specified in 4-bit units. After reset Power-on reset Input WDT&SP reset Input CMOS push-pull With clock stopped CE reset Retained Retained 10 P3B3 4-bit I/O port. CMOS | 13 | P3B0 Input or output can be specified in 4-bit units. push-pull After reset Power-on reset Input 14 15 16 P2A2 P2A1/FCG1 P2A0/FCG0 WDT&SP reset Input With clock stopped CE reset Retained Retained Port 2A multiplexed with external gate counter input pins. • P2A2 to P2A0 • 3-bit I/O port • Input or output can be specified in 1-bit units. • FCG1, FCG0 • Input for external gate counter After reset Power-on reset WDT&SP reset Input (P2A2 to P2A0) Input (P2A2 to P2A0) CMOS push-pull With clock stopped CE reset Retained (P2A2 to P2A0) Data Sheet U15722EJ1V1DS Retained (P2A2 to P2A0) 11 µPD17704A, 17705A, 17707A, 17708A, 17709A Pin No. Symbol 17 18 | 20 P1B3 P1B2/PWM2 | P1B0/PWM0 Function Output Form Port 1B multiplexed with D/A converter output pins. • P1B3 to P1B0 • 4-bit output port • PWM2 to P2M0 • 8- or 9-bit D/A converter output After reset Power-on reset WDT&SP reset Outputs low level Outputs low level (P1B3 to P1B0) (P1B3 to P1B0) N-ch open-drain (12 V) With clock stopped CE reset Retained Retained (P1B3 to P1B0) 21 33 75 GND2 GND1 GND0 Ground – 22 | 25 P0D3/AD3 | P0D0/AD0 Port 0D multiplexed with A/D converter input pins • P0D3 to P0D0 • 4-bit input port • Pull-down resistors can be connected in 1-bit units. • AD3 to AD0 • Analog input of A/D converter with 8-bit resolution – After reset 26 27 28 29 P1C3/AD5 P1C2/AD4 P1C1/AMIFC P1C0/FMIFC Power-on reset WDT&SP reset Input with pull-down resistor (P0D3 to P0D0) Input with pull-down resistor (P0D3 to P0D0) With clock stopped CE reset Retained Retained Port 1C multiplexed with A/D converter input and IF counter input pins. • P1C3 to P1C0 • 4-bit input port • AD5, AD4 • Analog input to A/D converter with 8-bit resolution • FMIFC, AMIFC • Input to frequency counter After reset 12 Power-on reset WDT&SP reset Input (P1C3 to P1C0) Input (P1C3 to P1C0) With clock stopped CE reset • P1C3/AD5, P1C2/AD4 retained • P1C1/AMIFC, P1C0/FMIFC input (P1C1, P1C0) Data Sheet U15722EJ1V1DS • P1C3/AD5, P1C2/AD4 retained • P1C1/AMIFC, P1C0/FMIFC input (P1C1, P1C0) – µPD17704A, 17705A, 17707A, 17708A, 17709A Pin No. Symbol Function Output Form 30 79 V DD 1 V DD 0 Power supply. Supply the same voltage to these • With CPU and peripheral function operating: • With CPU operating: • With clock stopped: pins. 4.5 to 5.5 V 3.5 to 5.5 V 2.2 to 5.5 V 31 32 VCOH VCOL PLL local oscillation (VCO) frequency input. • VCOH • Active with VHF mode selected by program; otherwise, pulled down. • VCOL • Active with HF or MW mode selected by program; otherwise, pulled down. – – Because the input of these pins goes into an AC amplifier, cut the DC component of the input signal with a capacitor. 34 35 EO0 EO1 Output from charge pump of PLL frequency synthesizer. Outputs the divided frequency of local oscillation and the result of comparison of the phase difference of the reference frequency. After reset CMOS 3-state With clock stopped Power-on reset WDT&SP reset CE reset High-impedance output High-impedance output High-impendance output 36 TEST Test input pin. Be sure to connect this pin to GND. 37 38 39 40 P1D3 P1D2 P1D1/BEEP1 P1D0/BEEP0 Port 1D and BEEP output. • P1D3 to P1D0 • 4-bit I/O port • Input or output can be specified in 1-bit units. • BEEP1, BEEP0 High-impedance output – CMOS push-pull • BEEP output After reset Power-on reset 43 | 46 P2B3 | P2B0 Input Retained Retained (P1D3 to P1D0) (P1D3 to P1D0) (P1D3 to P1D0) (P1D3 to P1D0) 4-bit I/O port. Input or output can be specified in 1-bit units. After reset Input P3C3 | P3C0 CE reset Input Power-on reset 47 | 50 WDT&SP reset With clock stopped WDT&SP reset Input CMOS push-pull With clock stopped CE reset Retained Retained 4-bit I/O port. Input or output can be specified in 4-bit units. After reset Power-on reset Input WDT&SP reset Input CMOS push-pull With clock stopped CE reset Retained Data Sheet U15722EJ1V1DS Retained 13 µPD17704A, 17705A, 17707A, 17708A, 17709A Pin No. 51 | 54 Symbol P3D3 | P3D0 Function 4-bit I/O port. Input or output can be specified in 4-bit units. Input P2C3 | P2C0 65 66 67 68 69 70 P0A1/SCK0 P0A0/SO0 P0B3/SI0 P0B2/SCK1 P0B1/SO1 P0B0/SI1 WDT&SP reset Input CE reset Retained P2D2 | P2D0 WDT&SP reset Input CMOS push-pull CE reset Retained Retained Ports P0A and P0B are multiplexed with I/O of serial interface. • P0A3 to P0A0 • 4-bit I/O port • Input or output can be specified in 1-bit units. • P0B3 to P0B0 • 4-bit I/O port • Input or output can be specified in 1-bit units. • SDA, SCL • Serial data and serial clock I/O of serial interface 0 in 2-wire serial I/O or I 2 C bus mode • SCK0, SO0, SI0 • Serial clock I/O, serial data output, and serial data input of serial interface 0 in 3-wire serial I/O mode • SCK1, SO1, SI1 • Serial clock I/O, serial data output, serial data input of serial interface 1 in 3-wire serial I/O mode WDT&SP reset CE reset Input P0A3 to P0A0, P0B3 to P0B0 Input P0A3 to P0A0, P0B3 to P0B0 Retained P0A3 to P0A0, P0B3 to P0B0 After reset Input Input CMOS push-pull Retained P0A3 to P0A0, P0B3 to P0B0 3-bit I/O port. Input or output can be specified in 1-bit units. WDT&SP reset N-ch open-drain With clock stopped Power-on reset Power-on reset 14 Retained With clock stopped After reset 71 | 73 CMOS push-pull With clock stopped After reset Input P0A3/DSA P0A2/SCL Retained 4-bit I/O port. Input or output can be specified in 4-bit units. Power-on reset 63 64 Retained After reset Input P0C3 | P0C0 Input CE reset 4-bit I/O port. Input or output can be specified in 4-bit units. Power-on reset 59 | 62 WDT&SP reset CMOS push-pull With clock stopped After reset Power-on reset 55 | 58 Output Form CMOS push-pull With clock stopped CE reset Retained Data Sheet U15722EJ1V1DS Retained µPD17704A, 17705A, 17707A, 17708A, 17709A Pin No. Symbol Function Output Form 74 REG CPU regulator. Connect this pin to GND via 0.1 µ F capacitor. – 76 77 X OUT X IN Ground pins of crystal resonator. – 78 CE Device operation selection, CE reset, and interrupt signal input pin. • Device operation selection When CE is high, the PLL frequency synthesizer can operate. When CE is low, the PLL frequency synthesizer is automatically disabled internally. • CE reset When CE goes high, the device is reset at the rising edge of the internal basic timer setting pulse. This pin also has a reset timing delay function. • Interrupt – A vectored interrupt occurs at the falling edge of this pin. 80 RESET Reset input – Data Sheet U15722EJ1V1DS 15 µPD17704A, 17705A, 17707A, 17708A, 17709A 1.2 Equivalent Circuits of Pins (1) P0A (P0A1/SCK0, P0A0/SO0) P0B (P0B3/SI0, P0B2/SCK1, P0B1/SO1, P0B0/SI1) P0C (P0C3, P0C2, P0C1, P0C0) P1D (P1D3, P1D2, P1D1/BEEP1, P1D0/BEEP0) P2A (P2A2, P2A1/FCG1, P2A0/FCG0) P2B (P2B3, P2B2, P2B1, P2B0) (I/O) P2C (P2C3, P2C2, P2C1, P2C0) P2D (P2D2, P2D1, P2D0) P3A (P3A3, P3A2, P3A1, P3A0) P3B (P3B3, P3B2, P3B1, P3B0) P3C (P3C3, P3C2, P3C1, P3C0) P3D (P3D3, P3D2, P3D1, P3D0) VDD CKSTOPNote VDD Note This is an internal signal that is output when the clock stop instruction is executed. Its circuit is designed not to increase the current consumption due to noise even if it is floated. 16 Data Sheet U15722EJ1V1DS µPD17704A, 17705A, 17707A, 17708A, 17709A (2) P0A (P0A3/SDA, P0A2/SCL) (I/O) VDD CKSTOPNote Note This is an internal signal that is output when the clock stop instruction is executed. Its circuit is designed not to increase the current consumption due to noise even if it is floated. (3) P1B (P1B3, P1B2/PWM2, P1B1/PWM1, P1B0/PWM0) (output) (4) P0D (P0D3/AD3, P0D2/AD2, P0D1/AD1, P0D0/AD0) (input) A/D converter VDD CKSTOPNote P0DPLD flag High on-resistance Note This is an internal signal that is output when the clock stop instruction is executed. Its circuit is designed not to increase the current consumption due to noise even if it is floated. Data Sheet U15722EJ1V1DS 17 µPD17704A, 17705A, 17707A, 17708A, 17709A (5) P1A (P1A1) (input) VDD CKSTOPNote Note This is an internal signal output on execution of the clock stop instruction. Its circuit is designed not to increase the current consumption due to noise even if the pin is floated. (6) P1C (P1C3/AD5, P1C2/AD4) (input) VDD A/D converter CKSTOPNote Note This is an internal signal output on execution of the clock stop instruction. Its circuit is designed not to increase the current consumption due to noise even if the pin is floated. (7) P1C (P1C1/AMIFC, P1C0/FMIFC) (input) VDD General-purpose port CKSTOPNote VDD High on-resistance VDD Frequency counter Note This is an internal signal output on execution of the clock stop instruction. Its circuit is designed not to increase the current consumption due to noise even if the pin is floated. 18 Data Sheet U15722EJ1V1DS µPD17704A, 17705A, 17707A, 17708A, 17709A (8) CE RESET INT0, INT1, INT2 (Schmitt-triggered input) P1A (P1A3/INT4, P1A2/INT3, P1A0/TM0G) VDD (9) X OUT (output), X IN (input) VDD High on-resistance VDD XIN Internal clock High onresistance XOUT (10) EO1, EO0 (output) VDD DWN UP Data Sheet U15722EJ1V1DS 19 µPD17704A, 17705A, 17707A, 17708A, 17709A (11) VCOH, VCOL (input) VDD High on-resistance VDD High onresistance 20 Data Sheet U15722EJ1V1DS µPD17704A, 17705A, 17707A, 17708A, 17709A 1.3 Connections of Unused Pins It is recommended to connect unused pins as follows. Table 1-1. Connections of Unused Pins (1/2) Pin Name Port pin P0D3/AD3 to P0D0/AD0 I/O Mode Recommended Connection Independently connect to GND via a resistorNote 1 . Input P1C3/AD5 P1C2/AD4 P1C1/AMIFC Note 2 Set to port mode and individually connect to V DD or GND P1C0/FMIFC Note 2 via a resistor Note 1 . P1A3/INT4 Independently connect to GND via a resistor Note 1 . P1A2/INT3 P1A1 P1A0/TM0G P1B3 N-ch open-drain P1B2/PWM2 to P1B0/PWM0 output P0A3/SDA I/O Note 3 P0A2/SCL Set to low-level output by software and leave open. Set to general-purpose input port mode by software and independently connect to V DD or GND via a resistor Note 1 . P0A1/SCK0 P0A0/SO0 P0B3/SI0 P0B2/SCK1 P0B1/SO1 P0B0/SI1 P0C3 to P0C0 P1D3 P1D2 P1D1/BEEP1 P1D0/BEEP0 P2A2 P2A1/FCG1 P2A0/FCG0 P2B3 to P2B0 P2C3 to P2C0 P2D2 to P2D0 Notes 1. If a pin is externally pulled up (connected to V DD via a resistor) or pulled down (connected to GND via a resistor) with a high resistance, the pin almost enters a high-impedance state, increasing the current (through-current) consumption of the port. Generally, the resistance of a pull-up or pulldown resistor is several 10 kΩ, although it depends on the application circuit. 2. Do not set these pins as AMIFC and FMIFC pins; otherwise, the current consumption will increase. 3. The I/O ports are set in the general-purpose I/O port mode at power-on reset, when reset by the RESET pin, or when reset by an overflow or underflow of the watchdog timer or the stack. Data Sheet U15722EJ1V1DS 21 µPD17704A, 17705A, 17707A, 17708A, 17709A Table 1-1. Connections of Unused Pins (2/2) Pin Name Port pin P3A3 to P3A0 I/O Mode I/O Note 2 Recommended Connection Set in general-purpose input port mode by software and independently connect to V DD or GND via a resistor Note 1 . P3B3 to P3B0 P3C3 to P3C0 P3D3 to P3D0 Non-port pins CE Input Connect to V DD via a resistor Note 1. EO1 Output Leave open INT0 to INT2 Input Independently connect to GND via a resistorNote 1 . RESET Input Connect to V DD via a resistor Note 1. EO0 TEST VCOH – Input Directly connect to GND. Disable PLL via software and leave open. VCOL Notes 1. If a pin is externally pulled up (connected to V DD via a resistor) or pulled down (connected to GND via a resistor) with a high resistance, the pin almost enters a high-impedance state, increasing the current (through-current) consumption of the port. Generally, the resistance of a pull-up or pulldown resistor is several 10 kΩ, although it depends on the application circuit. 2. The I/O ports are set in the general-purpose input port mode at power-on reset, when reset by the RESET pin, or when reset by an overflow or underflow of the watchdog timer or the stack. 22 Data Sheet U15722EJ1V1DS µPD17704A, 17705A, 17707A, 17708A, 17709A 1.4 Cautions on Using CE, INT0 to INT4, and RESET Pins The CE, INT0 to INT4, and RESET pins have a function to set a test mode in which the internal operations of the µ PD17709A are tested (IC test), in addition to the functions listed in 1.1 Pin Function List. When a voltage exceeding V DD is applied to any of these pins, the device is set in the test mode. If a noise exceeding V DD is superimposed during normal operation, therefore, the test mode is set by mistake, affecting the normal operation. Especially if the wiring length of pins is too long, noise is superimposed on these pins. In consequence, the above problem occurs. Therefore, keep the wiring length as short as possible to prevent noise from being superimposed. If superimposition of noise is unavoidable, connect an external component as illustrated below to suppress the noise. • Connect a diode with a low V F • Connect a capacitor between the pin and between the pin and V DD . V DD. VDD Diode with low VF VDD VDD VDD CE, INT0 to INT4, RESET CE, INT0 to INT4, RESET 1.5 Cautions on Using TEST Pin When V DD is applied to the TEST pin, the device is set in the test mode. Therefore, be sure to keep the wiring length of this pin as short as possible, and directly connect it to the GND pin. If the wiring length between the TEST pin and GND pin is too long, or if external noise is superimposed on the TEST pin, generating a potential difference between the TEST pin and GND pin, your program may not run normally. GND TEST Short Data Sheet U15722EJ1V1DS 23 µPD17704A, 17705A, 17707A, 17708A, 17709A 2. PROGRAM MEMORY (ROM) 2.1 Outline of Program Memory Figure 2-1 outlines the program memory. As shown in this figure, the addresses of the program memory are specified by the program counter. The program memory has the following two major functions. • To store programs • To store constant data Figure 2-1. Outline of Program Memory Address specification Program memory … Program counter … … Instruction … Constant data 24 Data Sheet U15722EJ1V1DS µPD17704A, 17705A, 17707A, 17708A, 17709A 2.2 Program Memory Figure 2-2 shows the configuration of the program memory. As shown in this figure, the µ PD17704A has 16 KB (8192 × 16 bits) of program memory, the µ PD17705A and 17707A have 24 KB (12288 × 16 bits), and the µ PD17708A and 17709A have 32 KB (16384 × 16 bits). Therefore, the program memory addresses of the µ PD17704A are 0000H to 1FFFH, those of the µ PD17705A, 17707A are 0000H to 2FFFH, and those of the µ PD17708A and 17709A are 0000H to 3FFFH. Because all instructions are one-word instructions, one instruction can be stored in one address of the program memory. The contents of the program memory are read to the data buffer as constant data by using a table reference instruction. Figure 2-2. Configuration of Program Memory Address 0 0 0 0 H Reset start address 0 0 0 1 H Serial interface 1 interrupt vector 0 0 0 2 H Serial interface 0 interrupt vector 0 0 0 3 H Timer 3 interrupt vector Page 0 0 0 0 4 H Timer 2 interrupt vector 0 0 0 5 H Timer 1 interrupt vector CALL addr instruction subroutine entry address 0 0 0 6 H Timer 0 interrupt vector BR @AR instruction branch address CALL @AR instruction subroutine entry address 0 0 0 7 H INT4 pin interrupt vector 0 0 0 8 H INT3 pin interrupt vector 0 0 0 9 H INT2 pin interrupt vector 0 0 0 A H INT1 pin interrupt vector 0 0 0 B H INT0 pin interrupt vector MOVT DBF, @AR instruction table reference address Segment 0 BR addr instruction branch address 0 0 0 C H Falling edge interrupt vector of CE pin 0 7 FFH Page 1 0 FFFH Page 2 1 7 FFH Page 3 1 FFFH 2000H ( µ PD17704A) Page 0 CALL addr instruction subroutine entry address Page 1 2 FFFH ( µ PD17705A, 17707A) Segment 1 BR addr (system instruction segment) branch address Page 2 Page 3 3 FFFH ( µ PD17708A, 17709A) 16 bits Data Sheet U15722EJ1V1DS 25 µPD17704A, 17705A, 17707A, 17708A, 17709A 2.3 Program Counter 2.3.1 Configuration of program counter Figure 2-3 shows the configuration of the program counter. As shown in this figure, the program counter consists of a 13-bit binary counter and a 1-bit segment register (SGR). Bits 11 and 12 of the program counter indicate a page. The program counter specifies an address of the program memory. Figure 2-3. Configuration of Program Counter SGRNote PC12 PC11 PC10 PC9 PC8 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 Page PC Note This bit is fixed to 0 in the µ PD17704A. 2.3.2 Segment register (SGR) The segment register specifies a segment of the program memory. Table 2-1 shows the relationship between the segment register and program memory. The segment register is set only when the SYSCAL entry instruction is executed. Remark The segment register is not available in the µ PD17704A. Table 2-1. Relationship Between Segment Register and Program Memory Value of Segment Register Segment of Program Memory 0 Segment 0 1 Segment 1 2.4 Flow of Program The flow of the program is controlled by the program counter, which specifies an address of the program memory. The program flow when each instruction is executed is described below. Figure 2-5 shows the value that is set to the program counter when each instruction is executed. Table 2-2 shows the vector address when an interrupt is acknowledged. 2.4.1 Branch instruction (1) Direct branch (“BR addr”) The branch destination address of the direct branch instruction is in the same segment of the program memory. In other words, a branch exceeding a segment cannot be executed. (2) Indirect branch (“BR @AR”) The branch destination addresses of the indirect branch instruction are all the addresses of the program memory, i.e., addresses 0000H to 1FFFH for the µ PD17704A, addresses 0000H to 2FFFH for the µ PD17705A, 17707A, and 0000H to 3FFFH for the µ PD17708A and 17709A. For further information, also refer to 5.3 Address Register (AR). 26 Data Sheet U15722EJ1V1DS µPD17704A, 17705A, 17707A, 17708A, 17709A 2.4.2 Subroutine (1) Direct subroutine call (“CALL addr”) The first address of a subroutine that can be called by the direct subroutine instruction is in page 0 of each segment (addresses 0000H to 07FFH). (2) Indirect subroutine call (CALL @AR) The first addresses of a subroutine that can be called by the indirect subroutine call instruction are all the addresses of the program memory, i.e., addresses 0000H to 1FFFH for the µ PD17704A, addresses 0000H to 2FFFH for the µ PD17705A, 17707A, and 0000H to 3FFFH for the µ PD17708A and 17709A. For further information, also refer to 5.3 Address Register (AR). 2.4.3 Table reference The addresses that can be referenced by the table reference instruction (“MOVT DBF, @AR”) are all the addresses of the program memory, i.e., addresses 0000H to 1FFFH for the µ PD17704A, addresses 0000H to 2FFFH for the µ PD17705A, 17707A, and 0000H to 3FFFH for the µ PD17708A and 17709A. For further information, also refer to 5.3 Address Register (AR) and 9.2.2 Table reference instruction (MOVT, DBF, @AR). 2.4.4 System call The first address of a subroutine that can be called by the system call instruction (“SYSCAL entry”) is the first 16 steps of each block (blocks 0 to 7) in page 0 of segment 1 (system segment). Remark The system call instruction is not available in the µ PD17704A. Data Sheet U15722EJ1V1DS 27 µPD17704A, 17705A, 17707A, 17708A, 17709A Figure 2-4. Outline of System Call Instruction Segment 1 (system segment) Segment 0 00000H Block 0 of segment 1 02000H 02000H Block 0 0 2 0FFH 02100H 0 2 0 0FH Block 1 0 2 1FFH 02200H Block 2 Page 0 (16 bits × 2K steps) 0 2 2FFH Area where entry address of system segment can be specified . . . . 02700H Block 7 0 0 7FFH 00800H 0 2 7FFH 02800H Page 1 0 0FFFH 01000H Page 1 0 2FFFH 03000H Page 2 0 1 7FFH 01800H Page 2 0 3 7FFH 03800H Page 3 0 1FFFH 0 3FFFH (16 bits × 8K steps) 28 Page 3 (16 bits × 8K steps) Data Sheet U15722EJ1V1DS Entry address of SYSCAL instruction µPD17704A, 17705A, 17707A, 17708A, 17709A Figure 2-5. Value of Program Counter Upon Execution of Instruction Program counter Instruction Contents of program counter (PC) SGR b12 Page 0 BR addr Page 1 Page 2 0 0 0 1 1 0 1 1 Retained 0 0 1 0 0 Retained b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 Operand of instruction (addr) Page 3 CALL addr b11 Operand of instruction (addr) SYSCAL entry 0 entryH 0 0 0 entryL BR @AR CALL @AR Contents of address register MOVT DBF, @AR RET RETSK Contents of address stack register (ASR) (return address) specified by stack pointer (SP) RETI Other instructions (including skip instruction) Retained Increment 0 Vector address of each interrupt When interrupt is acknowledged Power-on reset, watchdog timer reset, 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RESET pin, CE reset entryH: Higher 3 bits of entry entryL: Lower 4 bits of entry Remark The segment register and system call instruction are not available in the µ PD17704A. Data Sheet U15722EJ1V1DS 29 µPD17704A, 17705A, 17707A, 17708A, 17709A Table 2-2. Interrupt Vector Address Order 30 Internal/External Interrupt Source Vector Address 1 External Falling edge of CE pin 00CH 2 External INT0 pin 00BH 3 External INT1 pin 00AH 4 External INT2 pin 009H 5 External INT3 pin 008H 6 External INT4 pin 007H 7 Internal Timer 0 006H 8 Internal Timer 1 005H 9 Internal Timer 2 004H 10 Internal Timer 3 003H 11 Internal Serial interface 0 002H 12 Internal Serial interface 1 001H Data Sheet U15722EJ1V1DS µPD17704A, 17705A, 17707A, 17708A, 17709A 2.5 Cautions on Using Program Memory 2.5.1 Last address in each segment The segment register is not connected to the binary counter. Therefore, address 0000H of segment 0 is specified next to address 1FFFH, which is the last address of segment 0. To specify between segments, a dedicated instruction such as an indirect branch, indirect subroutine call, or system call instruction is used. Remark The segment register and system call instruction are not available in the µ PD17704A. Data Sheet U15722EJ1V1DS 31 µPD17704A, 17705A, 17707A, 17708A, 17709A 3. ADDRESS STACK (ASK) 3.1 Outline of Address Stack Figure 3-1 outlines the address stack. The address stack consists of a stack pointer and address stack registers. The address of an address stack register is specified by the stack pointer. The address stack saves a return address when a subroutine call instruction is executed or when an interrupt is acknowledged. The address stack is also used when the table reference instruction is executed. Figure 3-1. Outline of Address Stack Stack pointer Address stack register Address specification Return address 3.2 Address Stack Register (ASR) Figure 3-2 shows the configuration of the address stack register. The address stack register consists of sixteen 16-bit registers ASR0 to ASR15. Actually, however, it consists of fifteen 16-bit registers (ASR0 to ASR14) because no register is allocated to ASR15. The address stack saves a return address when a subroutine is called, when an interrupt is acknowledged, and when the table reference instruction is executed. 32 Data Sheet U15722EJ1V1DS µPD17704A, 17705A, 17707A, 17708A, 17709A Figure 3-2. Configuration of Address Stack Register Address stack register (ASR) Stack pointer (SP) Bit b3 b2 Address b1 SP3 SP2 SP1 SP0 Bit b15 b14 b13 b12 b11 b10 b0 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 0H ASR0 1H ASR1 2H ASR2 3H ASR3 4H ASR4 5H ASR5 6H ASR6 7H ASR7 8H ASR8 9H ASR9 AH ASR10 BH ASR11 CH ASR12 DH ASR13 EH ASR14 FH ASR15 (Undefined) Data Sheet U15722EJ1V1DS ←Cannot be used 33 µPD17704A, 17705A, 17707A, 17708A, 17709A 3.3 Stack Pointer (SP) 3.3.1 Configuration and function of stack pointer Figure 3-3 shows the configuration and functions of the stack pointer. The stack pointer consists of a 4-bit binary counter. It specifies the address of an address stack register. A value can be directly read from or written to the stack pointer by using a register manipulation instruction. Figure 3-3. Configuration and Function of Stack Pointer Name Flag symbol Address Read/write 01H R/W b3 b2 b1 b0 Stack pointer ( ( ( ( (SP) S S S S P P P P 3 2 1 0 ( ( ( ( After reset Specifies address of address stack register (ASR) 0 0 0 0 Address 0 (ASR0) 0 0 0 1 Address 1 (ASR1) 0 0 1 0 Address 2 (ASR2) 0 0 1 1 Address 3 (ASR3) 0 1 0 0 Address 4 (ASR4) 0 1 0 1 Address 5 (ASR5) 0 1 1 0 Address 6 (ASR6) 0 1 1 1 Address 7 (ASR7) 1 0 0 0 Address 8 (ASR8) 1 0 0 1 Address 9 (ASR9) 1 0 1 0 Address 10 (ASR10) 1 0 1 1 Address 11 (ASR11) 1 1 0 0 Address 12 (ASR12) 1 1 0 1 Address 13 (ASR13) 1 1 1 0 Address 14 (ASR14) 1 1 1 1 Setting prohibited Power-on reset 1 1 1 1 WDT&SP reset 1 1 1 1 CE reset 1 1 1 1 Clock stop Retained Power-on reset: Reset by RESET pin up on power application WDT&SP reset: Reset by watchdog timer and stack pointer 34 CE reset: CE reset Clock stop: Upon execution of clock stop instruction Data Sheet U15722EJ1V1DS µPD17704A, 17705A, 17707A, 17708A, 17709A 3.4 Operation of Address Stack 3.4.1 Subroutine call instruction (“CALL addr”, “CALL @AR”) and return instruction (“RET”, “RETSK”) When a subroutine call instruction is executed, the value of the stack pointer is decremented by one, and the return address is stored in the address stack register specified by the stack pointer. When the return instruction is executed, the contents of the address stack register (return address) specified by the stack pointer are restored to the program counter, and the value of the stack pointer is incremented by one. 3.4.2 Table reference instruction (“MOVT DBF, @AR”) When the table reference instruction is executed, the value of the stack pointer is incremented by one, and the return address is stored in the address stack register specified by the stack pointer. Next, the contents of the program memory specified by the address register are read to the data buffer, the contents of the address stack register (return value) specified by the stack pointer are restored to the program counter, and the value of the stack pointer is incremented by one. 3.4.3 When interrupt is acknowledged and on execution of return instruction (“RETI”) When an interrupt is acknowledged, the value of the stack pointer is decremented by one, and the return address is stored in the address stack register specified by the stack pointer. When the return instruction is executed, the contents of an address stack register (return value) specified by the stack pointer are restored to the program counter, and the value of the stack pointer is incremented by one. 3.4.4 Address stack manipulation instruction (“PUSH AR”, “POP AR”) When the “PUSH” instruction is executed, the value of the stack pointer is decremented by one, and the contents of the address register are transferred to the address stack register specified by the stack pointer. When the “POP” instruction is executed, the contents of an address stack register specified by the stack pointer are transferred to the address register, and the value of the stack pointer is incremented by one. 3.4.5 System call instruction (“SYSCAL entry”) and return instruction (“RET”, “RETSK”) When the “SYSCAL entry” instruction is executed, the value of the stack pointer is decremented by one, and the return address and the value of the segment register are stored in the address stack register specified by the stack pointer. When the return instruction is executed, the contents of an address stack register (return value) specified by the stack pointer are restored to the program counter and segment register, and the value of the stack pointer is incremented by one. Remark The segment register and system call instruction are not available in the µ PD17704A. Data Sheet U15722EJ1V1DS 35 µPD17704A, 17705A, 17707A, 17708A, 17709A 3.5 Cautions on Using Address Stack 3.5.1 Nesting level and operation on overflow The value of address stack register (ASR15) is undefined when the value of the stack pointer is 0FH. Accordingly, if a subroutine call or system call exceeding 15 levels or an interrupt is used without manipulating the stack, execution returns to an undefined address. 3.5.2 Reset on detection of overflow or underflow of address stack Whether the device is reset on detection of overflow or underflow of the address stack can be specified by program. After reset, the program is started from address 0, and some control registers are initialized. This reset function is valid after power-on reset or reset by the RESET pin. For details, refer to 21. RESET. 36 Data Sheet U15722EJ1V1DS µPD17704A, 17705A, 17707A, 17708A, 17709A 4. DATA MEMORY (RAM) 4.1 Outline of Data Memory Figure 4-1 outlines the data memory. As shown in the figure, system registers, a data buffer, port registers, and port I/O selection registers are located on the data memory. The data memory stores data, transfers data with the peripheral hardware or ports, and controls the CPU. Figure 4-1. Outline of Data Memory (1/3) (a) µ PD17709A Peripheral hardware Data transfer Column address 0 1 2 3 4 5 6 7 8 9 A B C 0 D E F Data buffer Row address 1 2 Data memory 3 4 5 6 7 BANK0 Port registers BANK1 Port registers Port registers Port registers BANK2 BANK3 BANK4 ... ... .. BANK14 BANK15Note System registers Data transfer Ports Note Port I/O selection registers are allocated to addresses 60H to 6FH of BANK 15. Data Sheet U15722EJ1V1DS 37 µPD17704A, 17705A, 17707A, 17708A, 17709A Figure 4-1. Outline of Data Memory (2/3) (b) µ PD17707A, 17708A Peripheral hardware Data transfer Column address 0 1 2 3 4 5 6 7 8 9 A B C D 0 E F Data buffer Row address 1 2 Data memory 3 4 5 6 7 BANK0 Port registers BANK1 Port registers Port registers Port registers BANK2 BANK3 BANK4 .. ... ... BANK9 BANK15Note System registers Data transfer Ports Note Port I/O selection registers are allocated to addresses 60H to 6FH of BANK 15. Cautions 1. The µ PD17707A and 17708A do not have BANKs 10 to 14. 2. Nothing is allocated to addresses 00H to 5FH of BANK15. 38 Data Sheet U15722EJ1V1DS µPD17704A, 17705A, 17707A, 17708A, 17709A Figure 4-1. Outline of Data Memory (3/3) (c) µ PD17704A, 17705A Peripheral hardware Data transfer Column address 0 1 2 3 4 5 6 7 8 9 A B C 0 D E F Data buffer Row address 1 2 Data memory 3 4 5 6 7 BANK0 Port registers BANK1 Port registers Port registers Port registers BANK2 BANK3 BANK4 BANK5 BANK15Note System registers Data transfer Ports Note Port I/O selection registers are allocated to addresses 60H to 6FH of BANK 15. Cautions 1. The µ PD17704A and 17705A do not have BANKs 6 to 14. 2. Nothing is allocated to addresses 00H to 5FH of BANK15. Data Sheet U15722EJ1V1DS 39 µPD17704A, 17705A, 17707A, 17708A, 17709A 4.2 Configuration and Function of Data Memory Figure 4-2 shows the configuration of the data memory. As shown in this figure, the data memory is divided into several banks with each bank made up of a total of 128 nibbles with 7H row addresses and 0FH column addresses. The data memory can be divided into five functional blocks. Each block is described in 4.2.1 through 4.2.5 below. The contents of the data memory can be operated on, compared, judged, and transferred in 4-bit units with a single data memory manipulation instruction. Table 4-1 lists the data memory manipulation instructions. 4.2.1 System registers (SYSREG) The system registers are allocated to addresses 74H to 7FH. Because the system registers are allocated to all banks, the same system registers exist at addresses 74H to 7FH of any bank. For details, refer to 5. SYSTEM REGISTER (SYSREG). 4.2.2 Data buffer (DBF) The data buffer is allocated to addresses 0CH to 0FH of BANK 0. For details, refer to 9. DATA BUFFER (DBF). 4.2.3 Port registers The port registers are allocated to addresses 70H to 73H of BANKs 0 to 3. For details, refer to 11. GENERAL-PURPOSE PORTS. 4.2.4 Port I/O selection registers Port I/O selection registers are allocated to addresses 60H to 6FH of BANK15. For details, refer to 8.4 Port I/O Selection Register. 4.2.5 General-purpose data memory The general-purpose data memory is allocated to the addresses of the data memory excluding those of the system registers, port registers, and port I/O selection registers. (a) µ PD17709A The general-purpose data memory of the µ PD17709A consists of a total of 1776 nibbles of the 112 nibbles each of BANKs 0 to 15 (BANK15 only has 96 nibbles). (b) µ PD17707A, 17708A The general-purpose data memory of the µPD17707A and 17708A consists of a total of 1120 nibbles of the 112 nibbles each of BANKs 0 to 9. (c) µ PD17704A, 17705A The general-purpose data memory of the µ PD17704A and 17705A consists of a total of 672 nibbles of the 112 nibbles each of BANKs 0 to 5. 40 Data Sheet U15722EJ1V1DS µPD17704A, 17705A, 17707A, 17708A, 17709A Figure 4-2. Configuration of Data Memory (1/3) (a) µ PD17709A BANK0 Column address 0 1 2 3 4 5 6 7 8 9 A B C D E F 0 Data buffer Row address 1 Data memory BANK0 BANK1 BANK2 2 General registers 3 4 5 … 6 7 Port register BANK14 BANK15 System registers System registers (SYSREG)Note BANK1 to BANK3 Column address 0 1 2 3 4 5 6 7 8 9 A B C D E F 0 Example Address 51H of BANK 0 Row address 1 b3 b2 b1 b0 2 3 4 5 6 7 Port register System registers (SYSREG)Note BANK4 to BANK14 Column address 0 1 2 3 4 5 6 7 8 9 A B C D E F 0 1 Row address 0 1 2 3 4 5 6 7 2 3 4 5 6 7 Fixed to 0 System registers (SYSREG)Note BANK15 Column address 0 1 2 3 4 5 6 7 8 9 A B C D E F 0 1 Row address Row address Column address 0 1 2 3 4 5 6 7 8 9 ABCDE F 2 3 4 5 6 7 Port I/O selection registers Fixed to 0 System registers (SYSREG)Note Note An identical system register exists. Data Sheet U15722EJ1V1DS 41 µPD17704A, 17705A, 17707A, 17708A, 17709A Figure 4-2. Configuration of Data Memory (2/3) (b) µ PD17707A, 17708A BANK0 Column address 0 1 2 3 4 5 6 7 8 9 A B C D E F 0 1 2 3 4 5 6 7 0 Data buffer 1 Row address Row address Column address 0 1 2 3 4 5 6 7 8 9 ABCDE F Data memory BANK0 BANK1 BANK2 2 General registers 3 4 5 … 6 7 Port register BANK9 BANK15 System registers System registers (SYSREG)Note BANK1 to BANK3 Column address 0 1 2 3 4 5 6 7 8 9 A B C D E F 0 Example Address 51H of BANK 0 Row address 1 b3 b2 b1 b0 2 3 4 5 6 7 Port register System registers (SYSREG)Note BANK4 to BANK9 Column address 0 1 2 3 4 5 6 7 8 9 A B C D E F 0 Row address 1 2 3 4 5 6 7 Fixed to 0 System registers (SYSREG)Note BANK15 Column address 0 1 2 3 4 5 6 7 8 9 A B C D E F 0 Row address 1 2 Nothing is allocated 3 4 5 6 7 Port I/O selection registers Fixed to 0 System registers (SYSREG)Note Note An identical system register exists. Cautions 1. The µ PD17707A and 17708A do not have BANKs 10 to 14. 2. Nothing is allocated to addresses 00H to 5FH of BANK15. 42 Data Sheet U15722EJ1V1DS µPD17704A, 17705A, 17707A, 17708A, 17709A Figure 4-2. Configuration of Data Memory (3/3) (c) µ PD17704A, 17705A BANK0 Column address 0 1 2 3 4 5 6 7 8 9 A B C D E F 0 1 2 3 4 5 6 7 0 Data buffer 1 Row address Row address Column address 0 1 2 3 4 5 6 7 8 9 ABCDE F Data memory BANK0 BANK1 BANK2 2 General registers 3 4 5 … 6 7 Port register BANK5 BANK15 System registers System registers (SYSREG)Note BANK1 to BANK3 Column address 0 1 2 3 4 5 6 7 8 9 A B C D E F 0 Example Address 51H of BANK 0 Row address 1 b3 b2 b1 b0 2 3 4 5 6 7 Port register System registers (SYSREG)Note BANK4, BANK5 Column address 0 1 2 3 4 5 6 7 8 9 A B C D E F 0 Row address 1 2 3 4 5 6 7 Fixed to 0 System registers (SYSREG)Note BANK15 Column address 0 1 2 3 4 5 6 7 8 9 A B C D E F 0 Row address 1 2 Nothing is allocated 3 4 5 6 7 Port I/O selection registers Fixed to 0 System registers (SYSREG)Note Note An identical system register exists. Cautions 1. The µ PD17704A and 17705A do not have BANKs 6 to 14. 2. Nothing is allocated to addresses 00H to 5FH of BANK15. Data Sheet U15722EJ1V1DS 43 µPD17704A, 17705A, 17707A, 17708A, 17709A Table 4-1. Data Memory Manipulation Instructions Function Operation Instruction Add ADD ADDC Subtract SUB SUBC Logic AND OR XOR Compare SKE SKGE SKLT SKNE Transfer MOV LD ST Judge SKT SKF 4.3 Data Memory Addressing Figure 4-3 shows address specification of the data memory. An address of the data memory is specified by a bank, row address, and column address. A row address and a column address are directly specified by a data memory manipulation instruction. However, a bank is specified by the contents of a bank register. For details of the bank register, refer to 5. SYSTEM REGISTER (SYSREG). Figure 4-3. Address Specification of Data Memory Bank b3 b2 b1 Row address b0 b2 b1 b0 Column address b3 b2 Data memory address Bank register 44 Data Sheet U15722EJ1V1DS Instruction operand b1 b0 µPD17704A, 17705A, 17707A, 17708A, 17709A 4.4 Cautions on Using Data Memory 4.4.1 After power-on reset The contents of the general-purpose data memory are undefined after power-on reset. Initialize the data memory as necessary. 4.4.2 Cautions on data memory not provided If a data memory manipulation instruction that reads the data memory is executed to a data memory address that is not provided, undefined data is read. Nothing is changed even if data is written to such an address. Data Sheet U15722EJ1V1DS 45 µPD17704A, 17705A, 17707A, 17708A, 17709A 5. SYSTEM REGISTERS (SYSREG) 5.1 Outline of System Registers Figure 5-1 shows the location of the system registers on the data memory and their outline. As shown in the figure, the system registers are allocated to addresses 74H to 7FH of all the banks of the data memory. Therefore, identical system registers exist at addresses 74H to 7FH of any bank. Because the system registers are located on the data memory, they can be manipulated by all data memory manipulation instructions. Seven types of system registers are available classified by function. Figure 5-1. Location and Outline of System Registers on Data Memory Column address 0 1 2 3 4 5 6 7 8 9 A B C D E F 0 Row address 1 2 Data memory 3 4 5 6 BANK0 7 BANK1 BANK2 ... ... BANK14 BANK15 System register Remark The µPD17704A and 17705A do not have BANK 6 to 14. The µPD17707A and 17708A do not have BANK 10 to 14. Address Name Function 46 74H 75H 76H 77H 78H 79H 7AH 7BH 7DH 7EH 7FH Address register Window Bank (AR) register register (IX) (WR) (BANK) Data memory row word address pointer (MP) (PSWORD) Controls program memory address Index register 7CH General register Program pointer (RP) status Transfers Specifies Modifies address of data memory Specifies Controls data with bank of address of operation register data general register file memory Data Sheet U15722EJ1V1DS µPD17704A, 17705A, 17707A, 17708A, 17709A 5.2 System Register List Figure 5-2 shows the configurations of the system registers. Figure 5-2. Configuration of System Registers Address 74H 75H 76H 77H 78H Name 79H 7AH 7BH 7CH 7DH 7EH 7FH System registers Address register Window Bank Index register (AR) register register (WR) (BANK) Data memory row General register Program (IX) pointer (RP) status word (PSWORD) address pointer (MP) Symbol Bit Data AR3 AR2 AR1 AR0 WR BANK IXH IXM MPH MPL IXL RPH RPL PSW b3 b 2 b1 b 0 b 3 b2 b 1 b0 b 3 b2 b 1 b0 b 3 b2 b 1 b0 b3 b2 b 1 b 0 b3 b 2 b1 b 0 b3 b 2 b1 b 0 b 3 b2 b 1 b0 b3 b2 b 1 b 0 b3 b2 b1 b0 b3 b 2 b1 b 0 b 3 b 2 b1 b 0 M (RP) P 0 E Data Sheet U15722EJ1V1DS B C C Z I (IX) (MP) CMY X D P E 47 µPD17704A, 17705A, 17707A, 17708A, 17709A 5.3 Address Register (AR) 5.3.1 Configuration of address register Figure 5-3 shows the configuration of the address register. As shown in the figure, the address register consists of 16 bits at system register addresses 74H to 77H (AR3 to AR0). Figure 5-3. Configuration of Address Register Address 74H 75H Name 76H 77H Address register (AR) Symbol AR3 Data b2 b1 b0 b3 b2 b1 b0 b3 b2 b1 AR0 b0 b3 b2 b1 M L S S B B After reset 48 〉 〉 Power-on reset 0 0 0 0 WDT&SP reset 0 0 0 0 CE reset 0 0 0 0 Retained Retained Retained Retained Clock stop b0 〈 b3 AR1 〈 Bit AR2 Power-on reset: Reset by RESET pin on power application WDT&SP reset: Reset by watchdog timer and stack pointer CE reset: CE reset Clock stop: On execution of clock stop instruction Data Sheet U15722EJ1V1DS µPD17704A, 17705A, 17707A, 17708A, 17709A 5.3.2 Function of address register The address register specifies a program memory address when the table reference instruction (“MOVT DBF, @AR”), stack manipulation instruction (“PUSH AR”, “POP AR”), indirect branch instruction (“BR @AR”), or indirect subroutine call instruction (“CALL @AR”) is executed. A dedicated instruction (“INC AR”) is available that can increment the contents of the address instruction by one. The following paragraphs (1) through (5) describe the operation of the address register when the respective instructions are executed. (1) Table reference instruction (“MOVT DBF, @AR”) When the table reference instruction is executed, the constant data (16 bits) of a program memory address specified by the contents of the address register are read to the data buffer. The constant data that can be specified by the address register is stored to address 0000H to 1FFFH in the case of µ PD17704A, address 0000H to 2FFFH in the case of the µ PD17705A and 17707A, and address 0000H to 3FFFH in the case of the µ PD17708A and 17709A. (2) Stack manipulation instruction (“PUSH AR”, “POP AR”) When the “PUSH AR” instruction is executed, the value of the stack pointer is decremented by one, and the contents of the address register (AR) are transferred to an address stack register specified by the stack pointer whose value has been decremented by one. When the “POP AR” instruction is executed, the contents of an address stack register specified by the stack pointer are transferred to the address register, and the value of the stack pointer is incremented by one. (3) Indirect branch instruction (“BR @AR”) When this instruction is executed, the program branches to a program memory address specified by the contents of the address register. The branch address that can be specified by the address register is 0000H to 1FFFH in the case of µ PD17704A, 0000H to 2FFFH in the case of the µ PD17705A and 17707A, and 0000H to 3FFFH in the case of the µ PD17705A and 17708A and 17709A. (4) Indirect subroutine call instruction (“CALL @AR”) The subroutine at a program memory address specified by the contents of the address register can be called. The first address of the subroutine that can be specified by the address register is 0000H to 1FFFH in the case of the µ PD17704A, 0000H to 2FFFH in the case of the µ PD17705A and 17707A, and 0000H to 3FFFH in the case of the µ PD17708A and 17709A. (5) Address register increment instruction (“INC AR”) This instruction increments the contents of the address register by one. 5.3.3 Address register and data buffer The address register can transfer data as part of the peripheral hardware via the data buffer. For details, refer to 9. DATA BUFFER (DBF). Data Sheet U15722EJ1V1DS 49 µPD17704A, 17705A, 17707A, 17708A, 17709A 5.3.4 Cautions on using address register Because the address register is configured in 16 bits, it can specify an address up to FFFFH. However, the program memory exists at addresses 0000H to 1FFFH in the case of µ PD17704A, 0000H to 2FFFH in the case of the µ PD17705A and 17707A and 0000H to 3FFFH in the case of the µ PD17708A and 17709A. Therefore, the maximum value that can be set to the address register of the µ PD17704 is address 1FFFH. In the case of the µ PD17705A and 17707A, it is address 2FFFH. In the case of the µ PD17708A and 17709A, it is address 3FFFH. 5.4 Window Register (WR) 5.4.1 Configuration of window register Figure 5-4 shows the configuration of the window register. As shown in the figure, the window register consists of 4 bits at system register address 78H (WR). Figure 5-4. Configuration of Window Register Address 78H Name Window register (WR) Symbol WR Data b2 b1 M L S S B B 〉 〉 After reset b0 〈 b3 〈 Bit Power-on reset Undefined WDT&SP reset Retained CE reset Clock stop 5.4.2 Function of window register The window register is used to transfer data with the register file (RF) to be described later. Data transfer between the window register and register file is manipulated by using dedicated instructions “PEEK WR, rf” and “POKE, rf WR” (rf: address of register file). The following paragraphs (1) and (2) describe the operation of the window register when these instructions are executed. For further information, also refer to 8. REGISTER FILE (RF). (1) “PEEK WR, rf” instruction When this instruction is executed, the contents of the register file addressed by “rf” are transferred to the window register. (2) “POKE rf, WR” instruction When this instruction is executed, the contents of the window register are transferred to the register file addressed by “rf”. 50 Data Sheet U15722EJ1V1DS µPD17704A, 17705A, 17707A, 17708A, 17709A 5.5 Bank Register (BANK) 5.5.1 Configuration of bank register Figure 5-5 shows the configuration of the bank register. As shown in the figure, the bank register consists of 4 bits at system register address 79H (BANK). Figure 5-5. Configuration of Bank Register Address 79H Name Bank register (BANK) Symbol BANK b1 b0 〈 Data b2 〈 Bit b3 M L S S B B After reset 〉 〉 Power-on reset 0 WDT&SP reset 0 CE reset 0 Clock stop Retained 5.5.2 Function of bank register The bank register specifies a bank of the data memory. Table 5-1 shows the relationships between the value of the bank register and a bank of the data memory that is specified. Because the bank register is one of the system registers, its contents can be rewritten regardless of the bank currently specified. When manipulating a bank register, therefore, the status of the bank at that time is irrelevant. Table 5-1. Data Memory Bank Specification Bank Register Bank of Data (BANK) Memory b3 b2 b1 b0 0 0 0 0 0 0 0 0 0 0 Bank Register Bank of Data (BANK) Memory b3 b2 b1 b0 BANK0 1 0 0 0 BANK8Note 1 BANK1 1 0 0 1 BANK9Note 1 0 BANK2 1 0 1 0 BANK10Note 0 1 1 BANK3 1 0 1 1 BANK11Note 0 1 0 0 BANK4 1 1 0 0 BANK12Note 0 1 0 1 BANK5 1 1 0 1 BANK13Note 0 1 1 0 BANK6Note 1 1 1 0 BANK14Note 1 Note 1 1 1 1 BANK15 0 1 1 BANK7 Note Do not set BANKs 6 to 14 in the µ PD17704A and 17705A, and BANKs 10 to 14 in the µ PD17707A and 17708A because these banks are not provided. Caution The area to which the data memory is allocated varies depending on the model. For details, refer to Figure 4-2 Configuration of Data Memory. Data Sheet U15722EJ1V1DS 51 µPD17704A, 17705A, 17707A, 17708A, 17709A 5.6 Index Register (IX) and Data Memory Row Address Pointer (MP: Memory Pointer) 5.6.1 Configuration of index register and data memory row address pointer Figure 5-6 shows the configuration of the index register and data memory row address pointer. As shown in the figure, the index register consists of an index register (IX) made up of 11 bits (the lower 3 bits (IXH) at system register address 7AH, 7BH, and 7CH (IXM, IXL)) and an index enable flag (IXE) at the least significant bit position of 7FH (PSW). The data memory row address pointer (memory pointer) consists of a data memory row address pointer (MP) that is made up of 7 bits of the lower 3 bits at 7AH (MPH) and 7BH (MPL), and a data memory row address pointer enable flag (memory pointer enable flag: MPE) at the most significant bit position of 7AH (MPH). In other words, the higher 7 bits of the index register are shared with the data memory row address pointer. Figure 5-6. Configuration of Index Register and Data Memory Row Address Pointer Address 7BH 7AH 7EH 7CH Index register (IX) Name Program status word (PSWORD) Memory pointer (MP) IXH IXM MPH MPL Symbol Bit b3 b1 b0 b3 b2 b1 b3 b2 b1 b0 b3 b2 b1 b0 b3 b2 b1 b0 〈 M L I P S S X E B B E 〉 〉 IX 〈 〈 M L S S B 〉 MP 〉 After reset b0 M B Power-on reset 0 0 0 0 WDT&SP reset 0 0 0 0 CE reset 0 0 0 0 Retained Retained Retained R Clock stop R: Retained 52 PSW IXL 〈 Data b2 7FH Data Sheet U15722EJ1V1DS µPD17704A, 17705A, 17707A, 17708A, 17709A 5.6.2 Functions of index register and data memory row address pointer The index register and data memory row address pointer modify the addresses of the data memory. The following paragraphs (1) and (2) describe their functions. A dedicated instruction (“INC IX”) that increments the value of the index register by one is available. For details of address modification, refer to 7. ALU (Arithmetic Logic Unit) BLOCK. (1) Index register (IX) When a data memory manipulation instruction is executed, the data memory address is modified by the contents of the index register. This modification, however, is valid only when the IXE flag is set to 1. To modify the address, the bank, row address, and column address of the data memory are ORed with the contents of the index register, and the instruction is executed to a data memory address (called real address) specified by the result of this OR operation. All data memory manipulation instructions are subject to address modification by the index register. The following instructions, however, are not subject to address modification by the index register. INC AR RORC r INX IX CALL addr MOVT DBF, @AR CALL @AR PUSH AR RET POP AR RETSK PEEK WR,rf RETI POKE rf,WR EI GET DBF,p DI PUT p, DBF STOP s BR addr HALT h BR @AR NOP (2) Data memory row address pointer (MP) When the general register indirect transfer instruction (“MOV @r,m” or “MOV m,@r”) is executed, the indirect transfer destination address is modified. This modification, however, is valid only when the MPE flag is set to 1. To modify the address, the bank and row address at the indirect transfer destination are replaced by the contents of the data memory row address pointer. Instructions other than the general register indirect transfer instruction are not subject to address modification. (3) Index register increment instruction (“INC IX”) This instruction increments the contents of the index register by one. Because the index register is configured of 10 bits, its contents are incremented to 000H if the “INC IX” instruction is executed when the contents of the index register are 3FFH. Data Sheet U15722EJ1V1DS 53 µPD17704A, 17705A, 17707A, 17708A, 17709A 5.7 General Register Pointer (RP) 5.7.1 Configuration of General Register Pointer Figure 5-7 shows the configuration of the general register pointer. As shown in the figure, the general register pointer consists of 7 bits including 4 bits at system register address 7DH (RPH) and the higher 3 bits at address 7EH (RPL). Figure 5-7. Configuration of General Register Pointer 7DH Address Name 7EH General register pointer (RP) RPH Symbol b1 b0 b3 b2 〈 M L B S S C B B D 〉 〉 After reset b0 Power-on reset 0 0 WDT&SP reset 0 0 CE reset 0 0 Retained Retained Clock stop 54 b1 〉 Data b2 〈 b3 〈 Bit RPL Data Sheet U15722EJ1V1DS µPD17704A, 17705A, 17707A, 17708A, 17709A 5.7.2 Function of general register pointer The general register pointer specifies a general register on the data memory. Figure 5-8 shows the addresses of the general registers specified by the general register pointer. As shown in the figure, a bank is specified by the higher 4 bits (RPH: address 7DH) of the general register pointer, and a row address is specified by the lower 3 bits (RPL: address 7EH). Because the valid number of bits of the general register pointer is 7, all the row addresses (0H to 7FH) of all the banks can be specified as general registers. For details of the operation of the general register, refer to 6. GENERAL REGISTER (GR). Figure 5-8. Address of General Register Specified by General Register Pointer General register pointer (RP) 〉 b3 b2 M S B L S B B C D 〈 b0 〉 b0 〈 b1 〈 b1 b3 b2 RPL 〉 RPH Specifies row address of each bank Specifies bank Bank Remark Row address 0 0 0 0 0 0 0 0H 0 0 0 0 0 0 1 1H 0 0 0 0 0 1 0 0 0 0 0 0 1 1 3H 1 1 1 1 1 0 0 4H 1 1 1 1 1 0 1 1 1 1 1 1 1 0 6H 1 1 1 1 1 1 1 7H BANK0 BANK15 2H 5H The µ PD17704A and 17705A do not have BANKs 6 to 14. The µ PD17707A and 17708A do not have BANKs 10 to 14. Caution The area to which the data memory is allocated varies depending on the model. For details, refer to Figure 4-2 Configuration of Data Memory. 5.7.3 Cautions on using general register pointer The least significant bit at address 7EH (RPL) of the general register pointer is allocated as the BCD flag of the program status word. When rewriting RPL, therefore, pay attention to the value of the BCD flag. Data Sheet U15722EJ1V1DS 55 µPD17704A, 17705A, 17707A, 17708A, 17709A 5.8 Program Status Word (PSWORD) 5.8.1 Configuration of program status word Figure 5-9 shows the configuration of the program status word. As shown in the figure, the program status word consists of a total of 5 bits including the least significant bit at system register address 7EH (RPL) and 4 bits at address 7FH (PSW). Each bit of the program status word has its own function. The 5 bits of the program status word are BCD flag (BCD), compare flag (CMP), carry flag (CY), zero flag (Z), and index enable flag (IXE). Figure 5-9. Configuration of Program Status Word 7EH Address Name 7FH Program status word (PSWORD) RPL Symbol Bit b3 b2 b1 After reset Data b0 b3 b2 b1 b0 B C C Z I C M Y D P X E Power-on reset 0 0 WDT&SP reset 0 0 CE reset 0 0 Retained Retained Clock stop 56 PSW Data Sheet U15722EJ1V1DS µPD17704A, 17705A, 17707A, 17708A, 17709A 5.8.2 Function of program status word The program status word is a register that sets the conditions under which the ALU (Arithmetic Logic Unit) executes an operation or data transfer, or indicates the result of an operation. Table 5-2 outlines the function of each flag of the program status word. For details, refer to 7. ALU (Arithmetic Logic Unit) BLOCK. Table 5-2. Outline of Function of Each Flag of Program Status Word (RP) Program Status Word (PSWORD) RPL b3 b2 b1 PSW b0 b3 b2 b1 b0 B C C Z I C M Y D P X E Flag Name Function Index enable flag Modifies address of data memory when data memory (IXE) manipulation instruction is executed. 0: Does not modify 1: Modifies Zero flag Indicates result of arithmetic operation is zero. (Z) Status of this flag differs depending on contents of compare flag. Carry flag Indicates occurrence of carry or borrow as result of execution (CY) of addition or subtraction instruction. This flag is reset to 0 if no carry or borrow occurs. It is set to 1 if carry or borrow occurs. This flag is also used as shift bit of “RORC r” instruction. Compare flag Indicates whether result of arithmetic operation is stored to (CMP) data memory or general register. 0: Stores result. 1: Does not store result. BCD flag Indicates whether arithmetic operation is performed in decimal (BCD) or binary. 0: Binary operation 1: Decimal operation 5.8.3 Cautions on using program status word When an arithmetic operation (addition or subtraction) is executed to the program status word, the result of the arithmetic operation is stored. For example, even if an operation that generates a carry is executed, if the result of the operation is 0000B, 0000B is stored to the PSW. Data Sheet U15722EJ1V1DS 57 µPD17704A, 17705A, 17707A, 17708A, 17709A 6. GENERAL REGISTER (GR) 6.1 Outline of General Register Figure 6-1 outlines the general register. As shown in the figure, the general register is specified in the data memory by the general register pointer. The bank and row address of the general register are specified by the general register pointer. The general register is used to transfer or operate data between data memory addresses. Figure 6-1. Outline of General Register Column address General register pointer Row address Data memory General register Transfer, operation BANK0 BANK1 BANK2 ⋅⋅⋅ ⋅⋅⋅ BANK14 BANK15 System register Remark The µ PD17704A and 17705A do not have BANKs 6 to 14. The µ PD17707A and 17708A do not have BANKs 10 to 14. 6.2 General Register The general register consists of 16 nibbles (16 × 4 bits) of the same row address on the data memory. For the range of the banks and row addresses that can be specified by the general register pointer as a general register, refer to 5.7 General Register Pointer (RP). The 16 nibbles of the same row address specified as a general register operate or transfer data with the data memory by a single instruction. In other words, operation or data transfer between data memory addresses can be executed by a single instruction. The general register can be controlled by the data memory manipulation instruction, like the other data memory areas. 58 Data Sheet U15722EJ1V1DS µPD17704A, 17705A, 17707A, 17708A, 17709A 6.3 Generating Address of General Register by Each Instruction The following sections 6.3.1 and 6.3.2 explain how the address of the general register is generated when each instruction is executed. For details of the operation of each instruction, refer to 7. ALU (Arithmetic Logic Unit) BLOCK. 6.3.1 Add (“ADD r, m”, “ADDC r, m”) , subtract (“SUB r, m”, “SUBC r, m”) , logical operation (“AND r, m”, “OR r, m”, “XOR r, m”), direct transfer (“LD r, m”, “ST m, r”), and rotation (“RORC r”) instructions Table 6-1 shows the address of the general register specified by operand “r” of an instruction. Operand “r” of an instruction specifies only a column address. Table 6-1. Generating Address of General Register Bank b3 General register address b2 b1 Row Address b0 b2 b1 b0 Column Address b3 b2 Contents of general register pointer b1 b0 r 6.3.2 Indirect transfer (“MOV @r, m”, “MOV m, @r”) instruction Table 6-2 shows a general register address specified by instruction operand “r” and an indirect transfer address specified by “@r”. Table 6-2. Generating Address of General Register Bank b3 b2 b1 Row Address b0 b2 b1 b0 Column Address b3 b2 b1 b0 General register address Contents of general register pointer r Same as data memory Contents of “r” Indirect transfer address 6.4 Cautions on Using General Register 6.4.1 Row address of general register Because the row address of the general register is specified by the general register pointer, the currently specified bank may differ from the bank of the general register. 6.4.2 Operation between general register and immediate data No instruction is available that executes an operation between the general register and immediate data. To execute an operation between the general register and immediate data, the general register must be treated as a data memory area. Data Sheet U15722EJ1V1DS 59 µPD17704A, 17705A, 17707A, 17708A, 17709A 7. ALU (Arithmetic Logic Unit) BLOCK 7.1 Outline of ALU Block Figure 7-1 outlines the ALU block. As shown in the figure, the ALU block consists of an ALU, temporary registers A and B, program status word, decimal adjustment circuit, and memory address controller. The ALU operates on, judges, compares, rotates, and transfers 4-bit data in the data memory. Figure 7-1. Outline of ALU Block Data bus Address control Temporary register A Temporary register B Program status word Carry/borrow/zero detection/decimal/storage specification Index modification memory pointer Data memory ALU • Arithmetic operation • Logical operation • Bit judgment • Comparison • Rotation • Transfer Decimal adjustment 60 Data Sheet U15722EJ1V1DS µPD17704A, 17705A, 17707A, 17708A, 17709A 7.2 Configuration and Function of Each Block 7.2.1 ALU The ALU performs arithmetic operation, logical operation, bit judgment, comparison, rotation, and transfer of 4-bit data according to instructions specified by the program. 7.2.2 Temporary registers A and B Temporary registers A and B temporarily store 4-bit data. These registers are automatically used when an instruction is executed, and cannot be controlled by program. 7.2.3 Program status word The program status word controls the operation of and stores the status of the ALU. For further information on the program status word, also refer to 5.8 Program Status Word (PSWORD). 7.2.4 Decimal adjustment circuit The decimal adjustment circuit converts the result of an arithmetic operation into a decimal number if the BCD flag of the program status word is set to 1 during arithmetic operations. 7.2.5 Address controller The address controller specifies an address of the data memory. At this time, address modification by the index register and data memory row address pointer is also controlled. 7.3 ALU Processing Instruction List Table 7-1 lists the ALU operations when each instruction is executed. Table 7-2 shows how data memory addresses are modified by the index register and data memory row address pointer. Table 7-3 shows decimal adjustment data when a decimal operation is performed. Data Sheet U15722EJ1V1DS 61 µPD17704A, 17705A, 17707A, 17708A, 17709A Table 7-1. List of ALU Processing Instruction Operations ALU Instruction Function Add Difference in Operation Depending on Program Status Word (PSWORD) Value of Value of BCD Flag CMP Flag ADD r, m 0 0 m, #n4 ADDC r, m 0 1 m, #n4 Subtract SUB r, m 1 0 m, #n4 SUBC r, m 1 1 m, #n4 Logical OR operation r, m Operation Operation of Z Flag Stores result of Set if carry or Set if result of operation binary operation borrow occurs; is 0000B; otherwise, reset Index Memory Pointer Modifies Does not modify Does not store result otherwise, reset Retains status if result of operation of binary operation is 0000B; otherwise, reset Stores result of Set if result of operation decimal operation is 0000B; otherwise, reset Does not store result Retains status if result of operation of decimal operation is 0000B; otherwise, reset Don’t care Don’t care Not affected m, #n4 (retained) (retained) AND Operation of CY Flag Address Modification Retains previous Retains previous status Modifies Does not status modify r, m m, #n4 XOR r, m m, #n4 Judge SKT m, #n Don’t care Don’t care Not affected Retains previous Retains previous status SKF m, #n (retained) status Compare SKE (reset) m, #n4 Don’t care Don’t care Not affected SKNE m, #n4 (retained) (retained) Modifies Does not modify Retains previous Retains previous status Modifies Does not status modify SKGE m, #n4 SKLT m, #n4 Transfer LD r, m Don’t care Don’t care Not affected Retains previous Retains previous status ST m, r (retained) (retained) status MOV m, #n4 Modifies Does not modify @r, m Modifies m, @r Rotate 62 RORC r Don’t care Don’t care Not affected Value of b 0 of (retained) (retained) general register Data Sheet U15722EJ1V1DS Retains previous status Does not Does not modify modify µPD17704A, 17705A, 17707A, 17708A, 17709A Table 7-2. Modification of Data Memory Address and Indirect Transfer Address by Index Register and Data Memory Row Address Pointer IXE MPE General Register Address Specified by “r” Bank Row Column Address Address Data Memory Address Specified by “m” Bank Row Column Address Address Indirect Transfer Address Specified by “@r” Bank Row Column Address Address b3 b 2 b 1 b 0 b 2 b 1 b 0 b3 b 2 b 1 b 0 b3 b 2 b1 b0 b2 b1 b0 b3 b2 b1 b0 b 3 b2 b1 b0 b2 b1 b0 b3 b 2 b1 b0 0 0 RP 0 r BANK m BANK mR (r) 1 ditto 1 ditto 0 BANK ditto 1 MP m Logical OR BANK (r) mR IX Logical IXH, IXM ditto MP OR (r) 1 ditto (r) BANK: Bank register IX: IXE: Index register Index enable flag IXH: Bits 10 to 8 of index register IXM: Bits 7 to 4 of index register IXL: m: Bits 3 to 0 of index register Data memory address indicated by mR, m C m R: Bata memory row address (higher) m C: Data memory column address (lower) MP: Data memory row address pointer MPE: Memory pointer enable flag r: General register column address RP: General register pointer (X): Contents addressed by X X: Direct address such as “m” and “r” Data Sheet U15722EJ1V1DS 63 µPD17704A, 17705A, 17707A, 17708A, 17709A Table 7-3. Decimal Adjustment Data Operation Hexadecimal Addition Decimal Addition Operation Hexadecimal Addition Decimal Addition Result CY Operation Result CY Operation Result Result CY Operation Result CY Operation Result 0 0 0000B 0 0000B 0 0 0000B 0 0000B 1 0 0001B 0 0001B 1 0 0001B 0 0001B 2 0 0010B 0 0010B 2 0 0010B 0 0010B 3 0 0011B 0 0011B 3 0 0011B 0 0011B 4 0 0100B 0 0100B 4 0 0100B 0 0100B 5 0 0101B 0 0101B 5 0 0101B 0 0101B 6 0 0110B 0 0110B 6 0 0110B 0 0110B 7 0 0111B 0 0111B 7 0 0111B 0 0111B 8 0 1000B 0 1000B 8 0 1000B 0 1000B 9 0 1001B 0 1001B 9 0 1001B 0 1001B 10 0 1010B 1 0000B 10 0 1010B 1 1100B 11 0 1011B 1 0001B 11 0 1011B 1 1101B 12 0 1100B 1 0010B 12 0 1100B 1 1110B 13 0 1101B 1 0011B 13 0 1101B 1 1111B 14 0 1110B 1 0100B 14 0 1110B 1 1100B 15 0 1111B 1 0101B 15 0 1111B 1 1101B 16 1 0000B 1 0110B –16 1 0000B 1 1110B 17 1 0001B 1 0111B –15 1 0001B 1 1111B 18 1 0010B 1 1000B –14 1 0010B 1 1100B 19 1 0011B 1 1001B –13 1 0011B 1 1101B 20 1 0100B 1 1110B –12 1 0100B 1 1110B 21 1 0101B 1 1111B –11 1 0101B 1 1111B 22 1 0110B 1 1100B –10 1 0110B 1 0000B 23 1 0111B 1 1101B –9 1 0111B 1 0001B 24 1 1000B 1 1110B –8 1 1000B 1 0010B 25 1 1001B 1 1111B –7 1 1001B 1 0011B 26 1 1010B 1 1100B –6 1 1010B 1 0100B 27 1 1011B 1 1101B –5 1 1011B 1 0101B 28 1 1100B 1 1010B –4 1 1100B 1 0110B 29 1 1101B 1 1011B –3 1 1101B 1 0111B 30 1 1110B 1 1100B –2 1 1110B 1 1000B 31 1 1111B 1 1101B –1 1 1111B 1 1001B Remark 64 Decimal adjustment is not correctly carried out in the shaded area in the above table. Data Sheet U15722EJ1V1DS µPD17704A, 17705A, 17707A, 17708A, 17709A 7.4 Cautions on Using ALU 7.4.1 Cautions on execution operation to program status word If an arithmetic operation is executed to the program status word, the result of the operation is stored to the program status word. The CY and Z flags in the program status word are usually set or reset by the result of the arithmetic operation. If an arithmetic operation is executed to the program status word itself, the result of the operation is stored to the program status word, and consequently, it cannot be judged whether a carry or borrow occurs or whether the result of the operation is zero. If the CMP flag is set, however, the result of the operation is not stored in the program status word. Therefore, the CY and Z flags are set or reset normally. 7.4.2 Cautions on executing decimal operation The decimal operation can be executed only when the result of the operation falls within the following ranges. (1) Result of addition: 0 to 19 in decimal (2) Result of subtraction: 0 to 9 or –10 to –1 in decimal If a decimal operation is executed exceeding or falling below the above ranges, the result is a value greater than 1010B (0AH). Data Sheet U15722EJ1V1DS 65 µPD17704A, 17705A, 17707A, 17708A, 17709A 8. REGISTER FILE (RF) 8.1 Outline of Register File Figure 8-1 outlines the register file. As shown in the figure, the register file consists of the control registers existing on a space different from the data memory, and a portion overlapping the data memory. The control registers set conditions of the peripheral hardware units. The data on the register file can be read or written via window register. Figure 8-1. Outline of Register File Register file 0 1 Peripheral hardware Control register (on separate space from data memory) Row address 2 3 4 (Same space as data memory) Data manipulation via window register 5 6 7 System register Window register 66 Data Sheet U15722EJ1V1DS µPD17704A, 17705A, 17707A, 17708A, 17709A 8.2 Configuration and Function of Register File Figure 8-2 shows the configuration of the register file and the relationship between the register file and data memory. The register file is assigned addresses in 4-bit units, like the data memory, and consists of a total of 128 nibbles with row addresses 0H to 7FH and column addresses 0H to 0FH. Addresses 00H to 3FH are control registers that sets the conditions of the peripheral hardware units. Addresses 40H to 7FH overlap the data memory. In other words, addresses 40H to 7FH of the register file are addresses 40H to 7FH of the currently-selected bank of data memory. Because addresses 40H to 7FH of the register file overlap the same addresses of the data memory, these addresses of the register file can be manipulated in the same manner as the data memory, except that the addresses of the register file can also be manipulated by using register file manipulation instructions (“PEEK WR, rf” and “POKE rf, WR”). Note, however, that addresses 60H to 6FH of BANK15 are assigned port I/O selection registers (for details, refer to 8.4 Port I/O Selection Registers). Figure 8-2. Configuration of Register File and Relationship with Data Memory Column address 0 1 2 3 4 5 6 7 8 9 A B C D E F 0 Row address 1 2 3 Data memory 4 5 6 7 BANK0 BANK1 BANK2 ⋅⋅⋅ ⋅⋅⋅ BANK14 BANK15 Port I/O selection registers System registers 0 1 2 Control registers 3 Register file Remark The µ PD17704A and 17705A do not have BANK 6 to 14. The µ PD17707A and 17708A do not have BANK 10 to 14. Data Sheet U15722EJ1V1DS 67 µPD17704A, 17705A, 17707A, 17708A, 17709A 8.2.1 Register file manipulation instructions (“PEEK WR, rf”, “POKE rf, WR”) Data is read from or written to the register file via the window register of the system registers, by using the following instructions. (1) “PEEK WR, rf” Reads data of the register file addressed by “rf” to the window register. (2) “POKE rf, WR” Writes the data of the window register to the register file addressed by “rf”. 8.3 Control Registers Figure 8-3 shows the configuration of the control registers. As shown in the figure, the control registers consist of a total of 64 nibbles (64 × 4 bits) of addresses 00H to 3FH of the register file. Of these 64 nibbles, however, only 53 nibbles are actually used. The remaining 11 nibbles are unused registers and prohibited from being written or read. Each control register has an attribute of 1 nibble that identifies four types of registers: read/write (R/W), readonly (R), write-only (W), and read-and-reset (R&Reset) registers. Nothing is changed even if data is written to a read-only (R and R&Reset) register. An undefined value is read if a write-only (W) register is read. Among the 4-bit data in 1 nibble, the bit fixed to 0 is always 0 when it is read, and is also 0 when it is written. The 11 nibbles of unused registers are undefined when their contents are read, and nothing changes even when they are written. Table 8-1 lists the peripheral hardware control functions of the control registers. 68 Data Sheet U15722EJ1V1DS µPD17704A, 17705A, 17707A, 17708A, 17709A [MEMO] Data Sheet U15722EJ1V1DS 69 µPD17704A, 17705A, 17707A, 17708A, 17709A Figure 8-3. Configuration of Control Registers (1/2) Column address Row address 1 Name 0 (8) 0 Item Note 3 Stack Watchdog Watchdog pointer timer clock selection R/W R/W PLL reference PLL unlock Stack overflow/ 6 7 CE reset MOVT bit timer counter stack pointer underflow reset timer carry selection reset counter selection W 0 D T R E S 0 0 0 0 W & Reset D B F S P 1 D B F S P 0 ) ) ) ) ) Read/ W D T C K 0 Data buffer ) 0 W D T C K 1 5 ( 0 S S S S P P P P 3 2 1 0 4 ( ( ( ( ( Symbol 2 0 R 0 I S P R E S A S P R E S C E C N T 3 R/W C E C N T 2 C E C N T 1 C 0 E C N T 0 R/W 0 M O V T S E L 1 M O V T S E L 0 R/W write Name 1 (9)Note PLL mode selection FF frequency Read/ R/W P L L R F C K 1 Watchdog purpose port timer/stack pin function selection P 0 L L R F C K 0 R/W 0 P 0 L L U L 0 R&Reset 0 B E E P 1 S E L Basic timer 0 carry pointer reset selection selection Symbol P 0 P P P P L L L L L L L L L L M M R R S C D D F F 1 0 C C N F K K 3 2 BEEP/general- BEEP clock status detection B E E P 0 S E L B E E P 1 C K 1 R/W B E E P 1 C K 0 B E E P 0 C K 1 0 B E E P 0 C K 0 R/W 0 0 W 0 D T C Y 0 0 B T M 0 C Y R&Reset R&Reset PWM/general- write Name 2 (A) Note Symbol 0 Read/ FCG IF counter IF counter IF counter A/D converter A/D converter PWM clock channel gate status mode control channel mode selection selection detection selection selection selection 0 F C G C H 1 R/W F 0 C G C H 0 0 0 R I F C G O S T T I F C M D 1 I F C M D 0 I F C C K 1 R/W I 0 F C C K 0 0 I F C S T R T purpose port pin function selection I 0 A A A 0 A A A 0 P 0 P 0 P P P W W W W W D D D D D D F M M M M M C C C C C C C 2 1 0 C B M S C C C C R S S S K I D T M H H H E E E E T T P 2 1 0 S L L L W R/W R/W R R/W R/W write 3 (B) Name Note Symbol Read/ Serial interface 1 interrupt request 0 0 0 R/W Serial interface 0 interrupt request I 0 R Q S I O 1 0 0 R/W write Note ( ) indicates an address that is used when the assembler is used. 70 Data Sheet U15722EJ1V1DS I 0 R Q S I O 0 Timer 3 Timer 2 interrupt interrupt request request 0 0 R/W I 0 R Q T M 3 0 0 R/W I R Q T M 2 µPD17704A, 17705A, 17707A, 17708A, 17709A Figure 8-3. Configuration of Control Register (2/2) 8 A B System register Serial I/O0 Serial I/O0 interrupt stack wait status pointer judgment S Y S R S P 0 0 0 R C D E F Serial I/O0 Serial I/O0 Serial I/O0 Serial I/O0 clock interrupt mode status wait control mode selection selection detection 0 S 0 S S S 0 I B I I O M O O 0 D 0 0 W C C S K K T 1 0 T ) ( S Y S R S P 1 ) ( S Y S R S P 2 ) ( 0 9 R 0 R/W S I O 0 I M D 1 S I O 0 I M D 0 S I O 0 S F 8 S I O 0 S F 9 R/W S B S T T selection S B B S Y S B A C K S I O 0 N W T R S I O 0 W R Q 1 S I O 0 W R Q 0 S S S S I B I I O O O 0 0 0 C M T H S X R/W R/W Basic timer 0 Serial I/O1 Interrupt Interrupt clock mode edge edge selection 1 selection 2 selection 0 0 B T M 0 C K 1 selection B T M 0 C K 0 S I O 1 T S R/W S I O 1 C K 1 S I I I I 0 I I I E E E I E N E N G G G O G T G T 2 1 0 1 4 4 3 3 S S C E E K L L 0 R/W R/W R/W Timer 3 Timer 2 Timer 1 Timer 0 Timer 0 Interrupt Interrupt Interrupt control counter clock counter clock counter clock mode enable 1 enable 2 enable 3 selection selection selection selection T 0 T T T T M M M M M 3 3 3 2 2 S E R E R E N E N E S L S 0 S I O 1 H I Z T M 2 C K 1 T M 2 C K 0 T M 1 E N T M 1 R E S T M 1 C K 1 T M 1 C K 0 T M 0 E N T M 0 R E S T M 0 C K 1 T M 0 C K 0 T M 0 O V F T M 0 G C E G T M 0 G O E G T I I I I M P P P P 0 S S T T M I I M M D O O 3 2 1 0 I P T M 1 I I I I I I I P P P P P P P T 4 3 2 1 0 C M E 0 R/W R/W R/W R/W R/W R/W R/W R/W Timer 1 Timer 0 INT4 pin INT3 pin INT2 pin INT1 pin INT0 pin CE pin interrupt interrupt interrupt interrupt interrupt interrupt interrupt interrupt request request request request request request request request 0 0 R/W I 0 R Q T M 1 0 0 R/W I I R N Q T T 4 M 0 0 0 R/W I I 0 R N Q T 4 3 0 R/W I I 0 R N Q T 3 2 0 I I 0 R N Q T 2 1 R/W Data Sheet U15722EJ1V1DS 0 R/W I I 0 R N Q T 1 0 0 R/W I C 0 C I R E E R Q C Q 0 N C T E S T T R R / W 71 µPD17704A, 17705A, 17707A, 17708A, 17709A Table 8-1. Peripheral Hardware Control Functions of Control Registers (1/8) Peripheral Hardware Control Register Name Peripheral Hardware Control Function Address Read/ b 3 Function Set Value b2 Write Symbol b1 b0 Stack Stack pointer 01H After Reset Power- WDT on 0 1 R/W (SP3) & SP Clock CE Stop Reset Reset Reset F F F Retained 5 5 5 Retained 0 0 0 Retained (SP2) (SP1) (SP0) Interrupt stack 08H R 0 pointer of (SYSRSP2) system register (SYSRSP1) (SYSRSP0) Data buffer 04H R stack pointer Stack overflow/ 0 Fixed to 0 0 05H (DBFSP1) Detects nesting level (DBFSP0) of data buffer stack R/W 0 underflow reset 0 selection ISPRES 0 0 1 1 Level 0 Level 1 Level 2 Level 3 0 1 0 1 Fixed to 0 Selects interrupt stack overflow/underflow reset Reset 3 Retained Retained Retained 3 Retained Retained Retained Reset valid prohibited (can be set only once following power application) ASPRES Selects address stack overflow/underflow reset (can be set only once following power application) Watchdog Watchdog timer timer 02H R/W 0 clock selection 0 WDTCK0 0 Not used set only once following power application) 0 0 65536 instruction 1 WDTRES Resets watchdog timer counter Invalid WDTCK1 Watchdog timer Fixed to 0 03H counter reset W& Reset 0 Selects clock of watchdog timer (can be 1 Setting prohibited 0 1 131072 instruction 1 Reset if written Undefined Undefined Undefined Undefined Fixed to 0 0 0 WDT&SP reset status detection 16H R& 0 0 Reset 0 0 WDTCY 72 Detects resetting of watchdog No reset timer/stack pointer request Data Sheet U15722EJ1V1DS Reset request 1 Retained Retained µPD17704A, 17705A, 17707A, 17708A, 17709A Table 8-1. Peripheral Hardware Control Functions of Control Registers (2/8) Peripheral Hardware Control Register Name Peripheral Hardware Control Function Address Read/ b 3 Function Set Value b2 Write Symbol b1 b0 CE CE reset timer 06H R/W CECNT3 carry counter CECNT2 0 R/W 0 selection 1 carry counts 1: 1 count 2: 2 counts 3: 3 counts 4: 4 counts 5: 5 counts 6: 6 counts 7: 7 counts 8: 8 counts 9: 9 counts A: 10 counts B: 11 counts C: 12 counts D: 13 counts E: 14 counts F: 15 counts Fixed to 0 MOVTSEL0 to DBF1, 0 during 8-bit transfer) Serial I/O0 wait CE Stop Reset 1 Retained Retained 1 0 0 0 Retained 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MOVTSEL1 Sets bit transferred by MOVT (transferred 00 16-bit Serial & SP Clock Reset Reset Sets number of CE reset timer 0: Setting prohibited CECNT0 07H Power- WDT on CECNT1 MOVT bit After Reset 0AH R interface status judgment 0 0 Higher transfer 8-bit transfer 01 1 1 Lower 8-bit transfer 0 Fixed to 0 0 0 SIO0WSTT Judges wait status of serial During wait During serial interface 0 Serial I/O0 0BH R/W 0 clock selection Serial I/O0 SBMD 0CH Selects operation mode of I2 C Continues bus during slave transmission processing SIO0CK1 Sets internal clock of serial SIO0CK0 interface 0 R/W 0 0 selection SIO0IMD1 Sets interrupt condition of SIO0IMD0 serial interface 0 SIO0SF8 Detects clock counter 0DH status detection R SIO0SF9 SBSTT Serial I/O0 wait 0EH R/W SBACK Detects number of clocks SIO0NWT bus mode) 1 46.875 kHz 1 0 7th clock 0 8th clock 0 1 1 7th clock after start condition 0 1 Stop condition 1 Set at 8th clock Set from start condition to 9th clock Set from start condition to (I 2C bus mode) stop condition Sets and detects acknowledge Sets and detects 0, 1 bus mode) Enables wait SIO0WRQ1 Sets wait mode SIO0WRQ0 1 281.25 kHz 0 Detects start condition (I 2C control set automatically 0 375 kHz 1 Set at 9th clock (I 2C SBBSY 0 93.75 kHz 0 Reception mode is Fixed to 0 interrupt mode Serial I/O0 communication Fixed to 0 Enabled 0 No wait 0 Data Sheet U15722EJ1V1DS Cleared 0 1 1 Data Acknowledge Address wait wait wait 1 0 1 73 µPD17704A, 17705A, 17707A, 17708A, 17709A Table 8-1. Peripheral Hardware Control Functions of Control Registers (3/8) Peripheral Hardware Control Register Name Peripheral Hardware Control Function Address Read/ b 3 Function Set Value b2 Write Symbol b1 b0 Serial Serial I/O0 0FH Serial I/O1 on 0 0 I 2C mode 1 Sets master/slave Slave operation Master operation SIO0TX Sets transfer direction Reception SIO1HIZ Sets status of P0B1/SO1 pin General-purpose SIO1CK1 Sets I/O clock 0 External clock 0 PLL mode selection 10H R/W PLLSCNF synthesizer Sets lower bits of swallow counter 0 Fixed to 0 PLLMD1 Sets division mode of PLL PLLMD0 PLL reference 11H PLLRFCK2 selection PLLRFCK1 0 Disabled 0 0 MF 1 R& 0 Reset 0 0 0 0 0 0 0 0 U U R R 0 0 0 0 F F F F output pin 1 375.00 kHz 0 1 46.875 kHz 1 LSB is 1 1 VHF 0 1 HF 1 3: 10 kHz 4: 6.25 kHz 5: 12.5 kHz 6: 25 kHz 7: 50 kHz 8: 3 kHz 9: 9 kHz A: 18 kHz B: Setting prohibited C: 1 kHz D: 20 kHz E: Setting prohibited F: PLL disabled PLLRFCK0 12H LSB is 0 Stop Serial data R/W PLLRFCK3 Sets reference frequency of PLL 0: 1.25 kHz 1: 2.5 kHz 2: 5 kHz frequency PLL unlock FF 0 187.50 kHz 1 CE Transmission Stops operation Starts operation SIO1CK0 frequency 1 3-wire mode 1 Starts or stops operation I/O port PLL 1 2-wire mode 0 & SP Clock Reset Reset SIO0MS R/W SIO1TS mode selection 1 Selects serial I/O0 mode SB 1DH Power- WDT 0 Not used 0 R/W SIO0CH interface mode selection After Reset Fixed to 0 Undefined Undefined Retained Retained Reset 0 0 PLLUL BEEP BEEP/general- 13H R/W 0 Detects status of unlock FF Locked Fixed to 0 purpose port pin 0 function selection BEEP1SEL Selects function of P1D1/BEEP1 pin General-purpose BEEP0SEL Selects function of P1D0/BEEP0 pin BEEP clock selection 14H R/W BEEP1CK1 BEEP1CK0 U: Undefined 74 0 0 0 0 0 0 0 0 BEEP I/O port Sets output frequency of BEEP1 0 4 kHz 0 BEEP0CK1 Sets output frequency of BEEP0 0 BEEP0CK0 Unlocked 1 kHz 0 R: Retained Data Sheet U15722EJ1V1DS 0 3 kHz 1 1 200 Hz 0 1 67 Hz 1 0 3 kHz 1 1 4 kHz 0 1 6.7 kHz 1 µPD17704A, 17705A, 17707A, 17708A, 17709A Table 8-1. Peripheral Hardware Control Functions of Control Registers (4/8) Peripheral Hardware Control Register Name Peripheral Hardware Control Function Address Read/ b 3 Function Set Value b2 Write Symbol b1 b0 Timer Basic timer 17H 0 carry R& 0 After Reset Power- WDT on 0 1 & SP Clock CE Stop Reset Reset Reset Fixed to 0 0 Retained 1 0 0 Retained Retained 0 0 Retained 0 0 0 Retained 0 0 0 Retained 0 0 0 Retained 0 0 0 Retained 0 Retained Reset 0 0 BTM0CY Basic timer 0 18H clock selection R/W 0 Detects basic timer 0 carry FF Fixed to 0 Selects clock of basic timer 0 BTM0CK0 28H Timer 2 counter 29H clock selection clock selection Fixed to 0 TM3EN Starts or stops timer 3 counter TM3RES Resets timer 3 counter R/W TM2EN clock selection Resets timer 2 counter Sets basic clock of timer TM2CK0 2 counter TM1CK0 1 counter TM0CK1 Sets basic clock of timer TM0CK0 0 counter R/W TM0OVF TM0GCEG Timer 3 Not affected Reset Stops Starts Not affected 0 0 100 kHz 10 kHz 0 1 Stops Resets timer 0 counter 1 100 Hz 1 Starts Stops Starts or stops timer 0 counter 1 50 Hz 0 Stops Not affected Resets timer 1 counter Sets basic clock of timer R/W TM0EN 0 20 Hz 1 0 0 100 kHz 10 kHz 0 1 Starts or stops timer 1 counter TM1CK1 TM0RES 2CH Starts or stops timer 2 counter TM2CK1 R/W TM1EN 0 10 Hz 0 Selects timer 3 and D/A converter D/A converter 0 TM1RES Timer 0 counter 2BH selection R/W TM3SEL TM2RES Timer 1 counter 2AH Timer 0 mode FF set 0 BTM0CK1 Timer 3 control FF reset Not affected 0 0 100 kHz 10 kHz 0 1 Reset 1 2 kHz 0 1 1 kHz 1 Starts Reset 1 2 kHz 0 1 1 kHz 1 Starts Reset 1 2 kHz 0 1 1 kHz 1 Detects timer 0 overflow No overflow Overflow Sets edge of gate close input Rising edge Falling edge signal TM0GOEG Sets edge of gate open input signal TM0MD Selects modulo counter/gate Modulo counter Gate counter counter of timer 0 Data Sheet U15722EJ1V1DS 75 µPD17704A, 17705A, 17707A, 17708A, 17709A Table 8-1. Peripheral Hardware Control Functions of Control Registers (5/8) Peripheral Hardware Control Register Name Peripheral Hardware Control Function Address Read/ b 3 Function Set Value b2 Write Symbol b1 b0 Interrupt Interrupt edge 1EH R/W IEG4 selection 1 After Reset Power- WDT on Sets interrupt issuance edge 0 1 Rising edge Falling edge Enables Disables & SP Clock CE Stop Reset Reset Reset 0 0 Retained Retained 0 0 Retained Retained 0 0 Retained Retained 0 0 Retained Retained 0 0 Retained Retained 0 0 Retained Retained (INT4 pin) INT4SEL Sets interrupt request flag of P1A3/INT4 pin IEG3 setting of flag setting of flag Sets interrupt issuance edge Rising edge Falling edge Enables Disables (INT3 pin) INT3SEL Sets interrupt request flag of P1A2/INT3 pin Interrupt edge 1FH selection 2 R/W 0 setting of flag setting of flag Fixed to 0 IEG2 Sets interrupt issuance edge Rising edge Falling edge IEG1 Sets interrupt issuance edge Enables serial interface 1 Disables Enables interrupt interrupt interrupt (INT2 pin) (INT1 pin) IEG0 Sets interrupt issuance edge (INT0 pin) Interrupt enable 1 2DH R/W IPSIO1 IPSIO0 Enables serial interface 0 interrupt IPTM3 Interrupt enable 2 Interrupt enable 3 2EH 2FH Serial interface 1 34H interrupt request Enables timer 3 interrupt IPTM2 Enables timer 2 interrupt R/W IPTM1 Enables timer 1 interrupt Disables Enables IPTM0 Enables timer 0 interrupt interrupt interrupt IP4 Enables INT4 pin interrupt IP3 Enables INT3 pin interrupt R/W IP2 Enables INT2 pin interrupt Disables Enables IP1 Enables INT1 pin interrupt interrupt interrupt IP0 Enables INT0 pin interrupt IPCE Enables CE pin interrupt R/W 0 Fixed to 0 0 0 IRQSIO1 Detects serial interface 1 interrupt request 76 Data Sheet U15722EJ1V1DS No interrupt Interrupt request request µPD17704A, 17705A, 17707A, 17708A, 17709A Table 8-1. Peripheral Hardware Control Functions of Control Registers (6/8) Peripheral Hardware Control Register Name Peripheral Hardware Control Function Address Read/ b 3 Function b2 Write Symbol b1 b0 Interrupt Serial interface 0 35H interrupt request R/W 0 After Reset Set Value Power- WDT on 0 1 Fixed to 0 & SP Clock CE Stop Reset Reset Reset 0 0 Retained Retained 0 0 Retained Retained 0 0 Retained Retained 0 0 Retained Retained 0 0 Retained Retained U U 0 0 U U 0 0 U U 0 0 U U 0 0 0 0 IRQSIO0 Detects serial interface 0 No interrupt request Interrupt request interrupt request Timer 3 interrupt 36H request R/W 0 Fixed to 0 0 0 IRQTM3 Timer 2 interrupt 37H request R/W 0 Detects timer 3 interrupt request No interrupt request Interrupt request Fixed to 0 0 0 IRQTM2 Timer 1 interrupt 38H request R/W 0 Detects timer 2 interrupt request No interrupt request Interrupt request Fixed to 0 0 0 IRQTM1 Timer 0 interrupt 39H request R/W 0 Detects timer 1 interrupt request No interrupt request Interrupt request Fixed to 0 0 0 IRQTM0 INT4 pin interrupt 3AH request R/W INT4 0 Detects timer 0 interrupt request No interrupt request Interrupt request Detects INT4 pin status Low level High level Fixed to 0 U U Retained Retained 0 IRQ4 INT3 pin interrupt 3BH request R/W INT3 0 Detects INT4 pin interrupt request No interrupt request Interrupt request Detects INT3 pin status Low level High level Fixed to 0 U U Retained Retained 0 IRQ3 INT2 pin interrupt 3CH request R/W INT2 0 Detects INT3 pin interrupt request No interrupt request Interrupt request Detects INT2 pin status Low level High level Fixed to 0 U U Retained Retained 0 IRQ2 INT1 pin interrupt request 3DH R/W INT1 0 Detects INT2 pin interrupt request No interrupt request Interrupt request Detects INT1 pin status Low level High level Fixed to 0 U U Retained Retained 0 IRQ1 Detects INT1 pin interrupt request No interrupt request Interrupt request U: Undefined Data Sheet U15722EJ1V1DS 77 µPD17704A, 17705A, 17707A, 17708A, 17709A Table 8-1. Peripheral Hardware Control Functions of Control Registers (7/8) Peripheral Hardware Control Register Name Peripheral Hardware Control Function Address Read/ b 3 Function b2 Write Symbol b1 b0 Interrupt INT0 pin interrupt 3EH R/W INT0 request 0 After Reset Set Value Power- WDT on Detects INT0 pin status 0 1 Low level High level & SP Clock CE Stop Reset Reset Reset Fixed to 0 U U U U 0 0 U U U U 0 0 0 0 Retained Retained 0 CE pin interrupt 3FH R request IRQ0 Detects INT0 pin interrupt request No interrupt request Interrupt request CE Detects CE pin status 0 Fixed to 0 Low level CECNTSTT Detects CE reset counter status IF FCG channel counter selection 20H Operates R/W IRQCE Detects CE pin interrupt request No interrupt request Interrupt request 0 0 R R R/W 0 Fixed to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FCGCH1 Sets pin to be used as FCG FCGCH0 IF counter gate Stops High level 21H R status detection 0 0 FCG not used 0 0 FCG0 pin 1 1 FCG1 pin 0 1 Setting prohibited 1 Fixed to 0 0 0 IFCGOSTT Detects IF counter gate status IF counter 22H R/W IFCMD1 mode selection IFCCK0 IF counter 23H W control A/D A/D converter 0 FCG 0 Sets IF counter gate time and 0 0 1 1 1ms, 4 ms, 8 ms, Open, 1 kHz 100 kHz 900 kHz Setting prohibited 0 1 0 1 0 FCG count frequency 1 FMIFC 0 1 AMIFC2 1 Fixed to 0 0 24H IFCSTRT Starts or stops IF counter Nothing affected Starts counter IFCRES Resets IF counter data Nothing affected Starts counter R/W 0 converter channel ADCCH2 selection Fixed to 0 1: P0D0/AD0 pin 2: P0D1/AD1pin 3: P0D2/AD2 pin 4: P0D3/AD3 pin 5: P1C2/AD4 pin 6: P1C3/AD5 pin 7: Setting prohibited ADCCH1 25H R/W 0 mode selection ADCMD Retained Retained Selects pin used for A/D converter 0: A/D converter not used ADCCH0 A/D converter 0 AMIFC 1 Open Sets IF counter mode IFCMD0 IFCCK1 Closed Fixed to 0 Selects comparison mode of Software mode Hardware mode 0 0 Retained Retained A/D converter R ADCSTT Detects operating status of ADCCMP Detects comparison result of Conversion ends Converting 0 0 0 Retained A/D converter V ADCREF > VADCIN V ADCREF < VADCIN A/D converter U: Undefined 78 R: Retained Data Sheet U15722EJ1V1DS µPD17704A, 17705A, 17707A, 17708A, 17709A Table 8-1. Peripheral Hardware Control Functions of Control Registers (8/8) Peripheral Hardware Control Register Name Peripheral Hardware Control Function Address Read/ b 3 Function b2 Write Symbol b1 b0 D/A PWM clock 26H converter selection R/W 0 PWMBIT After Reset Set Value Power- WDT on 0 1 Fixed to 0 Selects number of bits of PWM 8 bits 9 bits 4.4 kHz (8)/ 440 Hz (8)/ 2.2 kHz (9) 220 Hz (9) & SP Clock CE Stop Reset Reset Reset 0 0 Retained 0 0 0 Retained 0 counter PWM/general- 27H 0 Fixed to 0 PWMCK Selects output clock of timer 3 R/W 0 Fixed to 0 purpose port pin PWM2SEL Selects function of P1B2/PWM2 pin General-purpose D/A converter function selection PWM1SEL Selects function of P1B1/PWM1 pin PWM0SEL Selects function of P1B0/PWM0 pin Data Sheet U15722EJ1V1DS output port 79 µPD17704A, 17705A, 17707A, 17708A, 17709A 8.4 Port I/O Selection Registers Figure 8-4 shows the configuration of the port I/O selection registers. As shown in this figure, the port I/O selection registers consist of a total of 16 nibbles (16 × 4 bits) at addresses 60H to 6FH of BANK 15 of the data memory. Table 8-2 lists the control functions of the port I/O selection registers. 80 Data Sheet U15722EJ1V1DS µPD17704A, 17705A, 17707A, 17708A, 17709A [MEMO] Data Sheet U15722EJ1V1DS 81 µPD17704A, 17705A, 17707A, 17708A, 17709A Figure 8-4. Configuration of Port I/O Selection Registers (1/2) (BANK15) Column Address Row Address Item 0 1 2 3 4 5 6 7 Name Port 0D pull-down resistor selection Group I/O selection Symbol P P P P P P P P 0 0 0 0 3 3 3 3 D D D D D C B A 6 P P P P G G G G L L L L I I I I D D D D O O O O 3 Read/ Write 82 2 1 R/W Data Sheet U15722EJ1V1DS 0 R/W µPD17704A, 17705A, 17707A, 17708A, 17709A Figure 8-4. Configuration of Port I/O Selection Registers (2/2) 8 9 A B C D E F Port 2D bit Port 2C bit Port 2B bit Port 2A bit Port 1D bit Port 0C bit Port 0B bit Port 0A bit I/O selection I/O selection I/O selection I/O selection I/O selection I/O selection I/O selection I/O selection 0 P P P P P P P P P P P 2 2 2 2 2 2 2 2 2 2 2 0 P P P P P P P P P P P P P P P P P P P 2 2 2 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 D D D C C C C B B B B A A A D D D D C C C C B B B B A A A A B B B B B B B B B B B B B B B B B B B B B B B B B B B B B B I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O 2 1 2 1 R/W 0 3 2 1 R/W 0 3 2 1 R/W 0 R/W 0 3 2 1 0 R/W Data Sheet U15722EJ1V1DS 3 2 1 R/W 0 3 2 1 R/W 0 3 2 1 0 R/W 83 µPD17704A, 17705A, 17707A, 17708A, 17709A Table 8-2. Control Functions of Port I/O Selection Registers (1/2) Peripheral Hardware Port I/O Selection Register Name Control Function Address Read/ b 3 Function b2 (BANK15) Write Symbol b1 b0 I/O port Port 0D pull- 66H Set Value Power- WDT on Selects pull-down resistor of P0D3 pin 0 1 Pull-down Pull-down down resistor P0DPLD2 Selects pull-down resistor of P0D2 pin resistor used resistor not used selection P0DPLD1 Selects pull-down resistor of P0D1 pin P0DPLD0 Selects pull-down resistor of P0D0 pin Group I/O 67H selection Port 2D bit I/O 68H selection Port 2C bit I/O 69H selection Port 2B bit I/O 6AH selection Port 2A bit I/O 6BH selection Port 1D bit I/O 6CH selection Port 0C bit I/O 6DH selection Port 0B bit I/O selection 84 R/W P0DPLD3 After Reset 6EH R/W P3DGIO Selects input/output of port 3D P3CGIO Selects input/output of port 3C P3BGIO Selects input/output of port 3B P3AGIO Selects input/output of port 3A R/W 0 Output Fixed to 0 P2DBIO2 Selects input/output of port P2D2 P2DBIO1 Selects input/output of port P2D1 P2DBIO0 Selects input/output of port P2D0 R/W P2CBIO3 Selects input/output of port P2C3 P2CBIO2 Selects input/output of port P2C2 P2CBIO1 Selects input/output of port P2C1 P2CBIO0 Selects input/output of port P2C0 R/W P2BBIO3 Selects input/output of port P2B3 P2BBIO2 Selects input/output of port P2B2 P2BBIO1 Selects input/output of port P2B1 P2BBIO0 Selects input/output of port P2B0 R/W 0 Input Selects input/output of port P2A2 P2ABIO1 Selects input/output of port P2A1 P2ABIO0 Selects input/output of port P2A0 R/W P1DBIO3 Selects input/output of port P1D3 P1DBIO2 Selects input/output of port P1D2 P1DBIO1 Selects input/output of port P1D1 P1DBIO0 Selects input/output of port P1D0 R/W P0CBIO3 Selects input/output of port P0C3 P0CBIO2 Selects input/output of port P0C2 P0CBIO1 Selects input/output of port P0C1 P0CBIO0 Selects input/output of port P0C0 R/W P0BBIO3 Selects input/output of port P0B3 P0BBIO2 Selects input/output of port P0B2 P0BBIO1 Selects input/output of port P0B1 P0BBIO0 Selects input/output of port P0B0 Data Sheet U15722EJ1V1DS CE Stop Reset Reset Reset 0 0 Retained Retained 0 0 Retained Retained 0 0 Retained Retained Input Output Input Output 0 0 Retained Retained Input Output 0 0 Retained Retained 0 0 Retained Retained Fixed to 0 P2ABIO2 & SP Clock Input Output Input Output 0 0 Retained Retained Input Output 0 0 Retained Retained Input Output 0 0 Retained Retained µPD17704A, 17705A, 17707A, 17708A, 17709A Table 8-2. Control Functions of Port I/O Selection Registers (2/2) Peripheral Hardware Port I/O Selection Register Name Address Read/ b 3 Control Function Function b2 (BANK15) Write Symbol b1 b0 I/O port Port 0A bit I/O selection 6FH After Reset Set Value Power- WDT on R/W P0ABIO3 Selects input/output of port P0A3 P0ABIO2 Selects input/output of port P0A2 P0ABIO1 Selects input/output of port P0A1 P0ABIO0 Selects input/output of port P0A0 Data Sheet U15722EJ1V1DS 0 1 Input Output & SP Clock CE Stop Reset Reset Reset 0 0 Retained Retained 85 µPD17704A, 17705A, 17707A, 17708A, 17709A 8.5 Cautions on Using Register File Keep in mind the following points (1) through (3) when using the write-only (W), read-only (R), and unused registers of the control registers (addresses 00H to 3FH of the register file). (1) An undefined value is read if a write-only register is read. (2) Nothing is affected even if a read-only register is written. (3) An undefined value is read if an unused register is read. Nothing is affected if this register is written. 86 Data Sheet U15722EJ1V1DS µPD17704A, 17705A, 17707A, 17708A, 17709A 9. DATA BUFFER (DBF) 9.1 Outline of Data Buffer Figure 9-1 outlines the data buffer. The data buffer is located on the data memory and has the following two functions. • Reads constant data on the program memory (table reference) • Transfers data with the peripheral hardware units Figure 9-1. Outline of Data Buffer Data buffer Data write (PUT) Table reference (MOVT) Data read (GET) Peripheral hardware Constant data Program memory Data Sheet U15722EJ1V1DS 87 µPD17704A, 17705A, 17707A, 17708A, 17709A 9.2 Data Buffer 9.2.1 Configuration of data buffer Figure 9-2 shows the configuration of the data buffer. As shown in the figure, the data buffer consists of a total of 16 bits at addresses 0CH to 0FH of BANK 0 on the data memory. The 16-bit data is configured with bit 3 of address 0CH as the MSB and bit 0 of address 0FH as the LSB. Because the data buffer is located on the data memory, it can be manipulated by all data memory manipulation instructions. Figure 9-2. Configuration of Data Buffer Column address 0 1 2 3 4 5 6 7 8 9 A B C 0 D E F Data buffer (DBF) Row address 1 2 3 Data memory 4 5 6 BANK0 BANK1 7 BANK2 ⋅⋅⋅ ⋅⋅⋅ BANK14 BANK15 System register Remark The µ PD17704A and 17705A do not have BANK 6 to 14. The µ PD17707A and 17705A do not have BANK 6 to 14. Data buffer Address 0CH 0EH 0FH Bit b3 b2 b1 b0 b3 b2 b1 b0 b3 b2 b1 b0 b3 b2 b1 b0 Bit b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 DBF3 DBF0 〉 DBF1 M S B L S B 〈 Data DBF2 〉 Signal 88 0DH Data Data Sheet U15722EJ1V1DS 〈 Data memory µPD17704A, 17705A, 17707A, 17708A, 17709A 9.2.2 Table reference instruction (“MOVT DBF, @AR”) This instruction moves the contents of the program memory addressed by the contents of the address register to the data buffer. The number of bits transferred by the table reference instruction can be specified by the MOVT selection register (address 07H) of the control registers. When 8-bit data is transferred, it is read to DBF1 and 0. When the table reference instruction is used, one stack level is used. All the addresses of the program memory can be referenced by the table reference instruction. 9.2.3 Peripheral hardware control instructions (PUT and GET) The operations of the PUT and GET instructions are as follows. (1) GET DBF, p Reads the data of a peripheral register addressed by “p” to the data buffer. (2) PUT p, DBF Sets the data of the data buffer to a peripheral register addressed by “p”. 9.3 Relationship Between Peripheral Hardware and Data Buffer Table 9-1 shows the relationship between the peripheral hardware and the data buffer. Data Sheet U15722EJ1V1DS 89 µPD17704A, 17705A, 17707A, 17708A, 17709A Table 9-1. Relationship Between Peripheral Hardware and Data Buffer (1/2) Peripheral Hardware Peripheral Register Transferring Data with Data Buffer Name Symbol Peripheral Address Execution of PUT/GET Instruction I/O Bit Actual Bit A/D converter A/D converter reference voltage setting register ADCR 02H PUT/GET 8 8 Serial interface Serial interface 0 Presettable shift register 0 SIO0SFR 03H PUT/GET 8 8 Serial interface 1 Presettable shift register 1 SIO1SFR 04H Timer 0 modulo register TM0M 1AH PUT/GET 8 8 Timer 0 counter TM0C 1BH GET 8 8 Timer 1 modulo register TM1M 1CH PUT/GET 8 8 Timer 1 counter TM1C 1DH GET 8 8 Timer 2 modulo register TM2M 1EH PUT/GET 8 8 Timer 2 counter TM2C 1FH GET 8 8 Address register Address register AR 40H PUT/GET 16 16 Data buffer stack DBF stack DBFSTK 41H PUT/GET 16 16 PLL data register PLLR 42H PUT/GET 16 16 Frequency counter IF counter data register IFC 43H GET 16 16 D/A converter P1B0/PWM0 pin PWM data register 0 PWMR0 44H PUT/GET 16 9 (PWM output) P1B1/PWM1 pin PWM data register 1 PWMR1 45H P1B2/PWM2 pin PWM data register 2 PWMR2 46H PUT/GET 16 9 Timer 3 modulo register TM3M Timer 0 Timer 1 Timer 2 PLL frequency Timer 3 synthesizerNote 8 Note The programmable counter of the PLL frequency synthesizer is configured of 17 bits, of which the higher 16 bits indicate the PLL data register (PLLR) and the lower bits are allocated to the PLLSCNF flag (the third bit of address 10H). For details, refer to 17. PLL FREQUENCY SYNTHESIZER. 90 Data Sheet U15722EJ1V1DS µPD17704A, 17705A, 17707A, 17708A, 17709A Table 9-1. Relationship Between Peripheral Hardware and Data Buffer (2/2) After Reset Power-on WDT&SP Reset Reset 0 0 CE Reset 0Note Clock Stop 0Note Undefined Undefined Undefined Undefined Function Sets compare voltage V ADCREF of A/D converter Sets serial-out data and reads serial-in data FF FF Retained FF Sets modulo register value of timer 0 0 0 Retained 0 Reads count value of timer 0 counter FF FF Retained FF Sets modulo register value of timer 1 0 0 Retained 0 Reads count value of timer 1 counter FF FF Retained FF Sets modulo register value of timer 2 0 0 Retained 0 Reads count value of timer 2 counter 0 0 0 Retained Transfers data with address register Undefined Undefined Retained Retained Saves data of data buffer Undefined Undefined Retained Retained Sets division value (N value) of PLL 0 0 0 0 1FF 1FF Retained 1FF Reads count value of frequency counter Sets duty of output signal of D/A converter Sets duty of output signal of D/A converter (multiplexed with modulo register of timer 3) Sets modulo register value of timer 3 Note Value in hardware mode. “Retained” in software mode. Data Sheet U15722EJ1V1DS 91 µPD17704A, 17705A, 17707A, 17708A, 17709A 9.4 Cautions on Using Data Buffer Keep the following points in mind concerning the unused peripheral addresses, write-only peripheral register (PUT only), and read-only peripheral register (GET only) when transferring data with the peripheral hardware via data buffer. • An undefined value is read if a write-only register is read. • Nothing is affected even if a read-only register is written. • An undefined value is read if an unused address is read. Nothing is affected if this address is written. 92 Data Sheet U15722EJ1V1DS µPD17704A, 17705A, 17707A, 17708A, 17709A 10. DATA BUFFER STACK 10.1 Outline of Data Buffer Stack Figure 10-1 outlines the data buffer stack. As shown in the figure, the data buffer stack consists of a data buffer stack pointer and data buffer stack registers. The data buffer stack saves or restores the contents of the data buffer when the PUT or GET instruction is executed. Therefore, the contents of the data buffer can be saved by one instruction when an interrupt is acknowledged. Figure 10-1. Outline of Data Buffer Stack DBF Data buffer stack pointer Data buffer stack registers Address specification 10.2 Data Buffer Stack Register Figure 10-2 shows the configuration of the data buffer stack registers. As shown in the figure, the data buffer stack registers consist of four 16-bit registers. The contents of the data buffer are saved by executing the PUT instruction, and the saved data is restored by executing the GET instruction. The data buffer contents can be successively saved up to 4 levels. Data Sheet U15722EJ1V1DS 93 µPD17704A, 17705A, 17707A, 17708A, 17709A Figure 10-2. Configuration of Data Buffer Stack Register Data buffer DBF3 DBF2 DBF1 DBF0 Transfer data GET 16 bits PUT Name Data buffer stack register Symbol DBFSTK Address 41H Bit b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 Data Valid data Saves contents of data buffer up to 4 levels 94 Data Sheet U15722EJ1V1DS µPD17704A, 17705A, 17707A, 17708A, 17709A 10.3 Data Buffer Stack Pointer The data buffer stack pointer detects the multiplexing level of the data buffer stack registers. When the PUT instruction is executed to the data buffer stack, the value of the data buffer stack pointer is incremented by one; when the GET instruction is executed, the value of the pointer is decremented by one. The data buffer stack pointer can be only read and cannot be written. The configuration and function of the data buffer stack pointer are illustrated below. Name Flag symbol Address Read/write 04H R b3 b2 b1 b0 Data buffer stack pointer 0 0 D D B B F F S S P P 1 0 Detects multiplexing level of data buffer stack 0 0 Level 0 0 1 Level 1 1 0 Level 2 1 1 Level 3 After reset Fixed to 0 0 0 WDT&SP reset 0 0 CE reset 0 0 Power-on reset Clock stop 0 0 Retained Data Sheet U15722EJ1V1DS 95 µPD17704A, 17705A, 17707A, 17708A, 17709A 10.4 Operation of Data Buffer Stack Figure 10-3 shows the operation of the data buffer stack. As shown in the figure, when the PUT instruction is executed, the contents of the data buffer are transferred to a data buffer stack register specified by the stack pointer, and the stack pointer is incremented by one. When the GET instruction is executed, the contents of a data buffer stack register specified by the stack pointer are transferred to the data buffer, and the stack pointer is decremented by one. Therefore, note that the value of the stack pointer is set to 1 if data has been written once because its initial value is 0, and that the stack pointer is set to 0 when data has been written four times. Note that when writing (PUT) exceeding four levels, the first data are discarded. Figure 10-3. Operation of Data Buffer Stack (a) If writing does not exceed level 4 0 Undefined A A A A 1 Undefined Undefined B B B 2 Undefined Undefined Undefined Undefined Undefined 3 Undefined Undefined Undefined Undefined Undefined VDD PUT PUT GET GET (b) If writing exceeds level 4 0 A A A A E E E 1 Undefined B B B B B B 2 Undefined Undefined C C C C C 3 Undefined Undefined Undefined D D D D PUT 96 PUT PUT PUT PUT Data Sheet U15722EJ1V1DS GET GET µPD17704A, 17705A, 17707A, 17708A, 17709A 10.5 Using Data Buffer Stack A program example is shown below. Example To save the contents of the data buffer and address register by using INT0 interrupt routine (the contents of the data buffer and address register are not automatically saved when an interrupt occurs). START: BR INITIAL ; Reset address ; Interrupt vector address NOP ; SI01 NOP ; SI00 NOP ; TM3 NOP ; TM2 NOP ; TM1 NOP ; TM0 NOP ; INT4 NOP ; INT3 NOP ; INT2 NOP ; INT1 BR INTINT0 ; INT0 NOP ; Down edge of CE INTINT0: PUT GET PUT DBFSTK, DBF ; ; DBF, AR ; DBFSTK, DBF ; ; Processing B Saves contents of DBF to first level of data buffer stack (DBFSTK) Transfers contents of address register (AR) to DBF Saves contents of AR to second level of data buffer stack ; INT0 interrupt processing GET DBF, DBFSTK ; Restores second level of data buffer stack to data buffer, PUT AR, DBF ; and restores contents of data buffer to address register GET DBF, DBFSTK ; Restores first level of data buffer stack to data buffer EI RETI INITIAL: SET1 IP0 EI LOOP: Processing A BR LOOP END 10.6 Cautions on Using Data Buffer Stack The contents of the data buffer stack are not automatically saved when an interrupt is acknowledged, and therefore, must be saved by software. Even when a bank of the data memory other than BANK0 is specified, the contents of the data buffer (existing in BANK0) can be saved or restored by using the PUT and GET instructions. Data Sheet U15722EJ1V1DS 97 µPD17704A, 17705A, 17707A, 17708A, 17709A 11. GENERAL-PURPOSE PORTS The general-purpose ports output high-level, low-level, or floating signals to external circuits, and read highlevel or low-level signals from external circuits. 11.1 Outline of General-Purpose Port Table 11-1 shows the relationship between each port and port register. The general-purpose ports are classified into I/O, input, and output ports. The I/O ports are further subclassified into bit I/O ports that can be set to the input or output mode in 1-bit (1-pin) units, and group I/O ports that can be set to the input or output mode in 4-bit (4-pin) units. The input or output mode of each I/O port is specified by the port I/O selection registers (addresses 60H to 6FH) of BANK15. Table 11-1. Relationship Between Port (Pin) and Port Register (1/3) Port Pin No. Symbol Data Setting Method I/O Port Register (Data Memory) Bank Port 0A Port 0B Port 0C Port 0D 98 63 P0A3 64 I/O (bit I/O) BANK0 Address P0A3 P0A2 b2 P0A2 65 P0A1 b1 P0A1 66 P0A0 b0 P0A0 67 P0B3 b3 P0B3 68 P0B2 b2 P0B2 69 P0B1 b1 P0B1 70 P0B0 b0 P0B0 59 P0C3 b3 P0C3 60 P0C2 b2 P0C2 61 P0C1 b1 P0C1 62 P0C0 b0 P0C0 22 P0D3 b3 P0D3 23 P0D2 b2 P0D2 24 P0D1 b1 P0D1 25 P0D0 b0 P0D0 I/O (bit I/O) Input Data Sheet U15722EJ1V1DS 71H 72H 73H P0A Bit Symbol (Reserved Word) b3 I/O (bit I/O) 70H Symbol P0B P0C P0D µPD17704A, 17705A, 17707A, 17708A, 17709A Table 11-1. Relationship Between Port (Pin) and Port Register (2/3) Port Pin No. Data Setting Method Symbol I/O Port Register (Data Memory) Bank Port 1A Port 1B Port 1C Port 1D Port 2A Port 2B Port 2C Port 2D 2 P1A3 3 BANK1 P1A2 b2 P1A2 4 P1A1 b1 P1A1 5 P1A0 b0 P1A0 17 P1B3 b3 P1B3 18 P1B2 b2 P1B2 19 P1B1 b1 P1B1 20 P1B0 b0 P1B0 26 P1C3 b3 P1C3 27 P1C2 b2 P1C2 28 P1C1 b1 P1C1 29 P1C0 b0 P1C0 37 P1D3 b3 P1D3 38 P1D2 b2 P1D2 39 P1D1 b1 P1D1 40 P1D0 b0 P1D0 b3 – 71H Input 72H I/O (bit I/O) I/O (bit I/O) 73H BANK2 70H P1A Bit Symbol (Reserved Word) P1A3 Output 70H Symbol b3 No pin Input Address P1B P1C P1D P2A 14 P2A2 b2 P2A2 15 P2A1 b1 P2A1 16 P2A0 b0 P2A0 43 P2B3 b3 P2B3 44 P2B2 b2 P2B2 45 P2B1 b1 P2B1 46 P2B0 b0 P2B0 55 P2C3 I/O b3 P2C3 56 P2C2 (bit I/O) b2 P2C2 57 P2C1 b1 P2C1 58 P2C0 b0 P2C0 b3 – No pin I/O (bit I/O) 71H 72H I/O (bit I/O) 73H P2B P2C P2D 71 P2D2 b2 P2D2 72 P2D1 b1 P2D1 73 P2D0 b0 P2D0 Data Sheet U15722EJ1V1DS 99 µPD17704A, 17705A, 17707A, 17708A, 17709A Table 11-1. Relationship Between Port (Pin) and Port Register (3/3) Port Pin No. Data Setting Method Symbol I/O Port Register (Data Memory) Bank Port 3A Port 3B Port 3C Port 3D – 6 P3A3 I/O 7 P3A2 (group I/O) 8 70H b2 P3A2 P3A1 b1 P3A1 9 P3A0 b0 P3A0 10 P3B3 I/O b3 P3B3 11 P3B2 (group I/O) b2 P3B2 12 P3B1 b1 P3B1 13 P3B0 b0 P3B0 47 P3C3 I/O b3 P3C3 48 P3C2 (group I/O) b2 P3C2 49 P3C1 b1 P3C1 50 P3C0 b0 P3C0 51 P3D3 I/O b3 P3D3 52 P3D2 (group I/O) b2 P3D2 53 P3D1 b1 P3D1 54 P3D0 b0 P3D0 71H 72H 73H – BANK4 70H to 73H BANK15 Note Note The µ PD17704A and 17705A do not have BANK 6 to 14. The µ PD17707A and 17708A do not have BANK 10 to 14. Data Sheet U15722EJ1V1DS P3A Bit Symbol (Reserved Word) P3A3 | 100 Symbol b3 No pin BANK3 Address P3B P3C P3D – Fixed to 0 µPD17704A, 17705A, 17707A, 17708A, 17709A 11.2 General-Purpose I/O Ports (P0A, P0B, P0C, P1D, P2A, P2B, P2C, P2D, P3A, P3B, P3C, P3D) 11.2.1 Configuration of I/O port The following paragraphs (1) and (2) show the configuration of the I/O ports. (1) P0A (P0A1, P0A0) P0B (P0B3, P0B2, P0B1, P0B0) P0C (P0C3, P0C2, P0C1, P0C0) P1D (P1D3, P1D2, P1D1, P1D0) P2A (P2A2, P2A1, P2A0) P2B (P2B3, P2B2, P2B1, P2B0) P2C (P2C3, P2C2, P2C1, P2C0) P2D (P2D2, P2D1, P2D0) P3A (P3A3, P3A2, P3A1, P3A0) P3B (P3B3, P3B2, P3B1, P3B0) P3C (P3C3, P3C2, P3C1, P3C0) P3D (P3D3, P3D2, P3D1, P3D0) VDD I/O selection flag Output latch Write instruction Port register (1 bit) VDD 1 0 Read instruction CKSTOP Note Note This is an internal signal that is output when the clock stop instruction is executed. This circuit is designed not to increase the current consumption due to noise even if it is floated. Data Sheet U15722EJ1V1DS 101 µPD17704A, 17705A, 17707A, 17708A, 17709A (2) P0A (P0A3, P0A2) I/O selection flag Output latch Write instruction Port register (1 bit) VDD Read instruction CKSTOP Note Note This is an internal signal that is output when the clock stop instruction is execute. This circuit is designed not to increase the current consumption due to noise even if it is floated. 11.2.2 Using I/O port The input or output mode of the I/O ports is set by I/O selection register P0A, P0B, P0C, P1D, P2A, P2B, P2C, P2D, P3A, P3B, P3C, or P3D of the control registers. Because P0A, P0B, P0C, P1D, P2A, P2B, P2C, and P2D are bit I/O ports, they can be set to the input or output mode in 1-bit units. P3A, P3B, P3C, and P3D are group I/O ports, and therefore they are set to the input or output mode in 4bit units. Setting the output data of or reading the input data of a port is carried out by executing an instruction that writes data to or reads data from the port. 11.2.3 shows the configuration of the I/O selection register of each port. 11.2.4 and 11.2.5 describe how each port is used as an input or output port. 11.2.6 describes the points to be noted when using the I/O ports. 102 Data Sheet U15722EJ1V1DS µPD17704A, 17705A, 17707A, 17708A, 17709A 11.2.3 I/O port I/O selection register The following I/O selection registers of the I/O ports are available. • Port 0A bit I/O selection register • Port 0B bit I/O selection register • Port 0C bit I/O selection register • Port 1D bit I/O selection register • Port 2A bit I/O selection register • Port 2B bit I/O selection register • Port 2C bit I/O selection register • Port 2D bit I/O selection register • Group I/O selection registers (port 3A, port 3B, port 3C, port 3D) Each I/O selection register sets the input or output mode of the corresponding port pin. The following paragraphs (1) through (9) describe the configuration and functions of the above I/O selection registers. Data Sheet U15722EJ1V1DS 103 µPD17704A, 17705A, 17707A, 17708A, 17709A (1) Port 0A bit I/O selection register Name Flag symbol Address Read/write P (BANK15) R/W 6FH b3 b2 b1 b0 Port 0A bit I/O selection P P P 0 0 0 0 A A A A B B B B I I I I O O O O 3 1 2 0 Sets input/output mode of port 0 Sets P0A0 pin to input mode 1 Sets P0A0 pin to output mode Sets input/output mode of port 0 Sets P0A1 pin to input mode 1 Sets P0A1 pin to output mode Sets input/output mode of port 0 Sets P0A2 pin to input mode 1 Sets P0A2 pin to output mode After reset Sets input/output mode of port Sets P0A3 pin to input mode 1 Sets P0A3 pin to output mode Power-on reset 0 0 0 0 WDT&SP reset 0 0 0 0 CE reset Clock stop 104 0 Retained Retained Data Sheet U15722EJ1V1DS µPD17704A, 17705A, 17707A, 17708A, 17709A (2) Port 0B bit I/O selection register Name Flag symbol Address Read/write P (BANK15) R/W 6EH b3 b2 b1 b0 Port 0B bit I/O selection P P P 0 0 0 0 B B B B B B B B I I I I O O O O 3 1 2 0 Sets input/output mode of port 0 Sets P0B0 pin to input mode 1 Sets P0B0 pin to output mode Sets input/output mode of port 0 Sets P0B1 pin to input mode 1 Sets P0B1 pin to output mode Sets input/output mode of port 0 Sets P0B2 pin to input mode 1 Sets P0B2 pin to output mode After reset Sets input/output mode of port 0 Sets P0B3 pin to input mode 1 Sets P0B3 pin to output mode Power-on reset 0 0 0 0 WDT&SP reset 0 0 0 0 CE reset Clock stop Retained Retained Data Sheet U15722EJ1V1DS 105 µPD17704A, 17705A, 17707A, 17708A, 17709A (3) Port 0C bit I/O selection register Name Flag symbol Address Read/write P (BANK15) R/W 6DH b3 b 2 b 1 b 0 Port 0C bit I/O selection P P P 0 0 0 0 C C C C B B B B I I I I O O O O 3 1 2 0 Sets input/output mode of port 0 Sets P0C0 pin to input mode 1 Sets P0C0 pin to output mode Sets input/output mode of port 0 Sets P0C1 pin to input mode 1 Sets P0C1 pin to output mode Sets input/output mode of port 0 Sets P0C2 pin to input mode 1 Sets P0C2 pin to output mode After reset Sets input/output mode of port Sets P0C3 pin to input mode 1 Sets P0C3 pin to output mode Power-on reset 0 0 0 0 WDT&SP reset 0 0 0 0 CE reset Clock stop 106 0 Retained Retained Data Sheet U15722EJ1V1DS µPD17704A, 17705A, 17707A, 17708A, 17709A (4) Port 1D bit I/O selection register Name Address Read/write P (BANK15) R/W 6CH Flag symbol b3 b2 b1 b 0 Port 1D bit I/O selection P P P 1 1 1 1 D D D D B B B B I I I I O O O O 3 1 2 0 Sets input/output mode of port 0 Sets P1D0 pin to input mode 1 Sets P1D0 pin to output mode Sets input/output mode of port 0 Sets P1D1 pin to input mode 1 Sets P1D1 pin to output mode Sets input/output mode of port 0 Sets P1D2 pin to input mode 1 Sets P1D2 pin to output mode After reset Sets input/output mode of port 0 Sets P1D3 pin to input mode 1 Sets P1D3 pin to output mode Power-on reset 0 0 0 0 WDT&SP reset 0 0 0 0 CE reset Clock stop Retained Retained Data Sheet U15722EJ1V1DS 107 µPD17704A, 17705A, 17707A, 17708A, 17709A (5) Port 2A bit I/O selection register Name Address Read/write P (BANK15) R/W 6BH Flag symbol b3 b2 b1 b0 Port 2A bit I/O selection 0 P P 2 2 2 A A A B B B I I I O O O 2 1 0 Sets input/output mode of port 0 Sets P2A0 pin to input mode 1 Sets P2A0 pin to output mode Sets input/output mode of port 0 Sets P2A1 pin to input mode 1 Sets P2A1 pin to output mode Sets input/output mode of port 0 Sets P2A2 pin to input mode 1 Sets P2A2 pin to output mode After reset Fixed to 0 Power-on reset 0 0 0 WDT&SP reset 0 0 0 CE reset Retained Clock stop 108 0 Retained Data Sheet U15722EJ1V1DS µPD17704A, 17705A, 17707A, 17708A, 17709A (6) Port 2B bit I/O selection register Name Address Read/write P (BANK15) R/W 6AH Flag symbol b3 b2 b1 b0 Port 2B bit I/O selection P P P 2 2 2 2 B B B B B B B B I I I I O O O O 3 1 2 0 Sets input/output mode of port 0 Sets P2B0 pin to input mode 1 Sets P2B0 pin to output mode Sets input/output mode of port 0 Sets P2B1 pin to input mode 1 Sets P2B1 pin to output mode Sets input/output mode of port 0 Sets P2B2 pin to input mode 1 Sets P2B2 pin to output mode After reset Sets input/output mode of port 0 Sets P2B3 pin to input mode 1 Sets P2B3 pin to output mode Power-on reset 0 0 0 0 WDT&SP reset 0 0 0 0 CE reset Clock stop Retained Retained Data Sheet U15722EJ1V1DS 109 µPD17704A, 17705A, 17707A, 17708A, 17709A (7) Port 2C bit I/O selection register Name Address Read/write P (BANK15) R/W 69H Flag symbol b3 b 2 b 1 b 0 Port 2C bit I/O selection P P P 2 2 2 2 C C C C B B B B I I I I O O O O 3 1 2 0 Sets input/output mode of port 0 Sets P2C0 pin to input mode 1 Sets P2C0 pin to output mode Sets input/output mode of port 0 Sets P2C1 pin to input mode 1 Sets P2C1 pin to output mode Sets input/output mode of port 0 Sets P2C2 pin to input mode 1 Sets P2C2 pin to output mode After reset Sets input/output mode of port Sets P2C3 pin to input mode 1 Sets P2C3 pin to output mode Power-on reset 0 0 0 0 WDT&SP reset 0 0 0 0 CE reset Clock stop 110 0 Retained Retained Data Sheet U15722EJ1V1DS µPD17704A, 17705A, 17707A, 17708A, 17709A (8) Port 2D bit I/O selection register Name Address Read/write P (BANK15) R/W 68H Flag symbol b3 b2 b1 b0 Port 2D bit I/O selection 0 P P 2 2 2 D D D B B B I I I O O O 2 1 0 Sets input/output mode of port 0 Sets P2D0 pin to input mode 1 Sets P2D0 pin to output mode Sets input/output mode of port 0 Sets P2D1 pin to input mode 1 Sets P2D1 pin to output mode Sets input/output mode of port 0 Sets P2D2 pin to input mode 1 Sets P2D2 pin to output mode After reset Fixed to 0 Power-on reset 0 0 0 WDT&SP reset 0 0 0 CE reset Retained Clock stop 0 Retained Data Sheet U15722EJ1V1DS 111 µPD17704A, 17705A, 17707A, 17708A, 17709A (9) Group I/O selection register (ports 3A, 3B, 3C, 3D) Name Flag symbol Address Read/write R/W b3 b2 b1 b0 Group I/O selection P P P P (BANK15) 3 3 3 3 67H D C B A G G G G I I I O O I O O Sets input/output mode of port 0 Sets P3A0 to P3A3 pins to input mode 1 Sets P3A0 to P3A3 pins to output mode Sets input/output mode of port 0 Sets P3B0 to P3B3 pins to input mode 1 Sets P3B0 to P3B3 pins to output mode Sets input/output mode of port 0 Sets P3C0 to P3C3 pins to input mode 1 Sets P3C0 to P3C3 pins to output mode After reset Sets input/output mode of port Sets P3D0 to P3D3 pins to input mode 1 Sets P3D0 to P3D3 pins to output mode Power-on reset 0 0 0 0 WDT&SP reset 0 0 0 0 CE reset Clock stop 112 0 Retained Retained Data Sheet U15722EJ1V1DS µPD17704A, 17705A, 17707A, 17708A, 17709A 11.2.4 When using I/O port as input port The port pin to be set to the input mode is selected by the I/O selection register corresponding to the port. Ports P0A, P0B, P0C, P1D, P2A, P2B, P2C, and P2D can be set to the input or output mode in 1-bit units. P3A, P3B, P3C, and P3D can be set to the input or output mode in 4-bit units. The pin set to the input mode is floated (Hi-Z) and waits for input of an external signal. The input data is read by executing a read instruction (such as SKT) to the port register corresponding to the port pin. 1 is read from the port register when a high level is input to the corresponding port pin; when a low level is input to the port pin, 0 is read from the register. When a write instruction (such as MOV) is executed to the port register corresponding to the pin set in the input mode, the contents of the output latch are rewritten. 11.2.5 When using I/O port as output port The port pin to be set to the output mode is selected by the I/O selection register corresponding to the port. Ports P0A, P0B, P0C, P1D, P2A, P2B, P2C, and P2D can be set to the input or output mode in 1-bit units. P3A, P3B, P3C, and P3D can be set to the input or output mode in 4-bit units. The pin set to the output mode outputs the contents of the output latch. The output data is set by executing a write instruction (such as MOV) to the port register corresponding to the port pin. Write 1 to the port register to output a high level to the port pin; write 0 to output a low level. The port pin can be also floated (Hi-Z) if it is set to the input mode. If a read instruction (such as SKT) is executed to the port register corresponding to a port pin set to the output mode, the contents of the output latch are read. Note, however, that the contents of the output latch of the P0A3 and P0A2 pins may differ from the read contents because the status of these pins are read as are (refer to 11.2.6). 11.2.6 Cautions on using I/O port (P0A3 and P0A2 pins) When using the P0A3 and P0A2 pins in the output mode, the contents of the output latch may be rewritten as shown in the example below. Example To set the P0A3 and P0A2 pins to the output mode BANK15 INITFLG P0ABI03, P0ABI02, NOT P0ABI01, NOT P0ABI00 ; Sets P0A3 and P0A2 pins to output mode INITFLG P0A3, P0A2, NOT P0A1, NOT P0A0 ; Outputs high level to P0A3 and P0A2 pins ; <1> CLR1 P0A3 ; Outputs low level to P0A3 pin MACRO EXTEND AND .MF.P0A3 SHR 4, #.DF.(NOT P0A3 AND 0FH) If the P0A2 pin is externally made low when the instruction in the above example <1> is executed, the contents of the output latch of the P0A2 pin are rewritten to 0 by the CLR1 instruction. In other words, if an instruction that reads the contents of port register P0A is executed while the P0A3 or P0A2 pin is set to the output mode, the contents of the output latch are rewritten to the pin level at that time, regardless of the previous status. Data Sheet U15722EJ1V1DS 113 µPD17704A, 17705A, 17707A, 17708A, 17709A 11.2.7 Status of I/O port after reset (1) After power-on reset All the I/O ports are set to the input mode. The contents of the output latch are reset to 0. (2) After WDT&SP reset All the I/O ports are set to the input mode. The contents of the output latch are reset to 0. (3) After CE reset The setting of the input or output mode is retained. The contents of the output latch are also retained. (4) On execution of clock stop instruction The setting of the input or output mode is retained. The contents of the output latch are also retained. (5) In halt status The previous status is retained. 114 Data Sheet U15722EJ1V1DS µPD17704A, 17705A, 17707A, 17708A, 17709A 11.3 General-Purpose Input Port (P0D, P1A, P1C) 11.3.1 Configuration of input port The following paragraphs (1) and (2) show the configuration of the input port. (1) P0D (P0D3, P0D2, P0D1, P0D0) Write instruction To A/D converter VDD Port register (1 bit) Input latch Read instruction CKSTOP Note High-ON resistance P0DPLD flag Note This is an internal signal output on execution of the clock stop instruction. Its circuit is designed not to increase the current consumption due to noise even if the pin is floated. (2) P1A (P1A3, P1A2, P1A1, P1A0) P1C (P1C3, P1C2, P1C1, P1C0) To frequency counter or A/D converter Write instruction VDD Port register (1 bit) Read instruction CKSTOP Note Note This is an internal signal output on execution of the clock stop instruction. Its circuit is designed not to increase the current consumption due to noise even if the pin is floated. (Except P1A3, P1A2, P1A0) Data Sheet U15722EJ1V1DS 115 µPD17704A, 17705A, 17707A, 17708A, 17709A 11.3.2 Using input port The input data is read by executing a read instruction (such as SKT) to the port register corresponding to the port pin. 1 is read from the port register when a high level is input to the corresponding port pin; when a low level is input to the port pin, 0 is read from the register. Nothing is affected even if a write instruction (such as MOV) is executed to the port register. P0D has a pull-down resistor that can be connected or disconnected by software in 1-bit units. The pull-down resistor is connected when 0 is written to the corresponding bit of the port 0D pull-down resistor selection register. When 1 is written to the corresponding bit of this register, the pull-down resistor is disconnected. 11.3.3 Port 0D pull-down resistor selection register The port 0D pull-down resistor selection register specifies whether a pull-down resistor is connected to P0D3 through P0D0 pins. The configuration and function of this register are illustrated below. • Port 0D pull-down resistor selection register Name Address Read/write P (BANK15) R/W 66H Flag symbol b3 b 2 b 1 b 0 Port 0D pull-down resistor selection P P P 0 0 0 0 D D D D P P P P L L L L D D D D 3 2 1 0 Selects pull-down resistor of P0D0 pin 0 Connects pull-down resistor to P0D0 pin 1 Disconnects pull-down resistor from P0D0 pin Selects pull-down resistor of P0D1 pin 0 Connects pull-down resistor to P0D1 pin 1 Disconnects pull-down resistor from P0D1 pin Selects pull-down resistor of P0D2 pin 0 Connects pull-down resistor to P0D2 pin 1 Disconnects pull-down resistor from P0D2 pin After reset Selects pull-down resistor of P0D3 pin Connects pull-down resistor to P0D3 pin 1 Disconnects pull-down resistor from P0D3 pin Power-on reset 0 0 0 0 WDT&SP reset 0 0 0 0 CE reset Clock stop 116 0 Retained Retained Data Sheet U15722EJ1V1DS µPD17704A, 17705A, 17707A, 17708A, 17709A 11.3.4 Status of input port after reset (1) After power-on reset All the input ports are set to the input mode. All the pull-down resistors of P0D are connected. (2) After WDT&SP reset All the input ports are set to the input mode. All the pull-down resistors of P0D are connected. (3) After CE reset The input ports are set to the input mode. The pull-down resistors of P0D retain the previous status. (4) On execution of clock stop instruction The input ports are set to the input mode. The pull-down resistors of P0D retain the previous status. (5) In halt status The previous status is retained. Data Sheet U15722EJ1V1DS 117 µPD17704A, 17705A, 17707A, 17708A, 17709A 11.4 General-Purpose Output Port (P1B) 11.4.1 Configuration of output port The configuration of the output port is shown below. (1) P1B (P1B3, P1B2, P1B1, P1B0) Output latch Write instruction Port register (1 bit) Read instruction 11.4.2 Using output port The output port outputs the contents of the output latch to each pin. The output data is set by executing a write instruction (such as MOV) to the port register corresponding to the port pin. Write 1 to the port register to output a high level to the port pin; write 0 to output a low level. However, because P1B is an N-ch open-drain output port, it is floated when it outputs a high level. Therefore, an external pull-up resistor must be connected to this port. If a read instruction (such as SKT) is executed to the port register, the contents of the output latch are read. 11.4.3 Status of output port after reset (1) After power-on reset The contents of the output latch are output. The contents of the output latch are reset to 0. (2) After WDT&SP reset The contents of the output latch are output. The contents of the output latch are reset to 0. (3) After CE reset The contents of the output latch are output. The contents of the output latch are retained. (4) On execution of clock stop instruction The contents of the output latch are output. The contents of the output latch are retained. (5) In halt status The contents of the output latch are output. The contents of the output latch are retained. 118 Data Sheet U15722EJ1V1DS µPD17704A, 17705A, 17707A, 17708A, 17709A 12. INTERRUPTS 12.1 Outline of Interrupt Block Figure 12-1 outlines the interrupt block. As shown in the figure, the interrupt block temporarily stops the currently executed program and branches execution to a vector address in response to an interrupt request output by a peripheral hardware unit. The interrupt block consists of an interrupt request servicing block corresponding to each peripheral hardware unit, interrupt enable flip-flop that enables all interrupts, stack pointer that is controlled when an interrupt is acknowledged, address stack register, program counter, and interrupt stack. The interrupt control block of each peripheral hardware unit consists of an interrupt request flag (IRQ×××) that detects the corresponding interrupt request, interrupt enable flag (IP×××) that enables the interrupt, and vector address generator (VAG) that specifies a vector address when the interrupt is acknowledged. The µ PD17709A has the following 12 types of maskable interrupts. • CE pin falling edge interrupt • INT0 to INT4 interrupts • Timer 0 to timer 3 interrupts • Serial interface 0 and serial interface 1 interrupts When an interrupt is acknowledged, execution branches to a predetermined address, and the interrupt is serviced. Data Sheet U15722EJ1V1DS 119 µPD17704A, 17705A, 17707A, 17708A, 17709A Figure 12-1. Outline of Interrupt Block Interrupt control block Program counter IPSIO1 flag Serial interface 1 IRQSIO1 flag Vector address generator 01H Stack pointer Address stack registers IPSIO0 flag Serial interface 0 IRQSIO0 flag Vector address generator 02H System registers IPTM3 flag Timer 3 IRQTM3 flag Vector address generator 03H Pointer IPTM2 flag Timer 2 IRQTM2 flag Vector address generator 04H IPTM1 flag Timer 1 IRQTM1 flag Vector address generator 05H IPTM0 flag Timer 0 IRQTM0 flag Vector address generator 06H IP4 flag INT4 pin IRQINT4 flag Vector address generator 07H IP3 flag INT3 pin IRQINT3 flag Vector address generator 08H IP2 flag INT2 pin IRQINT2 flag Vector address generator 09H IP1 flag INT1 pin IRQINT1 flag Vector address generator 0AH IP0 flag INT0 pin IRQINT0 flag Vector address generator 0BH IPCE flag CE pin falling IRQCE flag Vector address generator 0CH DI, EI instruction 120 Interrupt enable flip-flop Data Sheet U15722EJ1V1DS Interrupt stack µPD17704A, 17705A, 17707A, 17708A, 17709A 12.2 Interrupt Control Block An interrupt control block is provided for each peripheral hardware unit. This block detects issuance of an interrupt request, enables the interrupt, and generates a vector address when the interrupt is acknowledged. 12.2.1 Configuration and function of interrupt request flag (IRQ×××) Each interrupt request flag is set to 1 when an interrupt request is issued by the corresponding peripheral hardware unit, and is reset to 0 when the interrupt is acknowledged. Writing the interrupt request flag to 1 via a window register is equivalent to issuance of the interrupt request. By detecting the interrupt request flag when an interrupt is not enabled, issuance status of each interrupt request can be detected. Once the interrupt request flag has been set, it is not reset until the corresponding interrupt is acknowledged, or until 0 is written to the flag via a window register. Even if two or more interrupt requests are issued at the same time, the interrupt request flag corresponding to the interrupt that has not been acknowledged is not reset. Figures 12-2 through 12-13 show the configuration and function of the respective interrupt request registers. Figure 12-2. Configuration of Serial Interface 1 Interrupt Request Register Name Flag symbol Address Read/write 34H R/W b3 b2 b1 b0 Serial interface 1 0 0 0 I R interrupt request Q S I O 1 Indicates interrupt request issuance status of serial interface 1 0 Interrupt request not issued 1 Interrupt request issued After reset Fixed to 0 Power-on reset 0 0 0 0 WDT&SP reset 0 CE reset R Clock stop R R: Retained Data Sheet U15722EJ1V1DS 121 µPD17704A, 17705A, 17707A, 17708A, 17709A Figure 12-3. Configuration of Serial Interface 0 Interrupt Request Register Name Flag symbol Address Read/write 35H R/W b3 b2 b1 b0 Serial interface 0 0 0 0 I R interrupt request Q S I O 0 Indicates interrupt request issuance status of serial interface 0 0 Interrupt request not issued 1 Interrupt request issued Fixed to 0 After reset Power-on reset 0 0 0 0 WDT&SP reset 0 CE reset R Clock stop R R: Retained Figure 12-4. Configuration of Timer 3 Interrupt Request Register Name Flag symbol Address Read/write 36H R/W b3 b2 b1 b0 Timer 3 0 0 0 I R interrupt request Q T M 3 Indicates interrupt request issuance status of timer 3 0 Interrupt request not issued 1 Interrupt request issued After reset Fixed to 0 Power-on reset 0 0 0 0 WDT&SP reset 0 CE reset R Clock stop R R: Retained 122 Data Sheet U15722EJ1V1DS µPD17704A, 17705A, 17707A, 17708A, 17709A Figure 12-5. Configuration of Timer 2 Interrupt Request Register Name Flag symbol Address Read/write 37H R/W b3 b2 b1 b0 0 Timer 2 0 0 I R interrupt request Q T M 2 Indicates interrupt request issuance status of timer 2 0 Interrupt request not issued 1 Interrupt request issued After reset Fixed to 0 Power-on reset 0 0 0 0 WDT&SP reset 0 CE reset R Clock stop R R: Retained Figure 12-6. Configuration of Timer 1 Interrupt Request Register Name Flag symbol Address Read/write 38H R/W b3 b2 b1 b0 Timer 1 0 0 0 I R interrupt request Q T M 1 Indicates interrupt request issuance status of timer 1 0 Interrupt request not issued 1 Interrupt request issued After reset Fixed to 0 Power-on reset 0 0 0 0 WDT&SP reset 0 CE reset R Clock stop R R: Retained Data Sheet U15722EJ1V1DS 123 µPD17704A, 17705A, 17707A, 17708A, 17709A Figure 12-7. Configuration of Timer 0 Interrupt Request Register Name Flag symbol Address Read/write 39H R/W b3 b2 b1 b0 Timer 0 0 0 0 I R interrupt request Q T M 0 Indicates interrupt request issuance status of timer 0 0 Interrupt request not issued 1 Interrupt request issued After reset Fixed to 0 Power-on reset 0 0 0 0 WDT&SP reset 0 CE reset R Clock stop R R: Retained 124 Data Sheet U15722EJ1V1DS µPD17704A, 17705A, 17707A, 17708A, 17709A Figure 12-8. Configuration of INT4 Pin Interrupt Request Register Name Flag symbol Address Read/write 3AH R/W b3 b2 b1 b0 INT4 pin I 0 0 I interrupt request N R T Q 4 4 Indicates interrupt request issuance status of INT4 pin 0 Interrupt request not issued 1 Interrupt request issued Fixed to 0 After reset Detects status of INT4 pin 0 Low level is input 1 High level is input Power-on reset U WDT&SP reset U 0 CE reset U R U R Clock stop 0 0 0 U: Undefined, R: Retained Data Sheet U15722EJ1V1DS 125 µPD17704A, 17705A, 17707A, 17708A, 17709A Figure 12-9. Configuration of INT3 Pin Interrupt Request Register Name Flag symbol Address Read/write 3BH R/W b3 b2 b1 b0 INT3 pin I 0 0 I interrupt request N R T Q 3 3 Indicates interrupt request issuance status of INT3 pin 0 Interrupt request not issued 1 Interrupt request issued Fixed to 0 After reset Detects status of INT3 pin 0 Low level is input 1 High level is input Power-on reset U WDT&SP reset U 0 CE reset U R U R Clock stop 0 0 0 U: Undefined, R: Retained 126 Data Sheet U15722EJ1V1DS µPD17704A, 17705A, 17707A, 17708A, 17709A Figure 12-10. Configuration of INT2 Pin Interrupt Request Register Name Flag symbol Address Read/write 3CH R/W b3 b2 b1 b0 INT2 pin I interrupt request N R T Q 2 2 0 0 I Indicates interrupt request issuance status of INT2 pin 0 Interrupt request not issued 1 Interrupt request issued Fixed to 0 After reset Detects status of INT2 pin 0 Low level is input 1 High level is input Power-on reset U WDT&SP reset U 0 CE reset U R U R Clock stop 0 0 0 U: Undefined, R: Retained Data Sheet U15722EJ1V1DS 127 µPD17704A, 17705A, 17707A, 17708A, 17709A Figure 12-11. Configuration of INT1 Pin Interrupt Request Register Name Flag symbol Address Read/write 3DH R/W b3 b2 b1 b0 INT1 pin I interrupt request N R T Q 1 1 0 0 I Indicates interrupt request issuance status of INT1 pin 0 Interrupt request not issued 1 Interrupt request issued Fixed to 0 After reset Detects status of INT1 pin 0 Low level is input 1 High level is input Power-on reset U WDT&SP reset U 0 CE reset U R U R Clock stop 0 0 0 U: Undefined, R: Retained 128 Data Sheet U15722EJ1V1DS µPD17704A, 17705A, 17707A, 17708A, 17709A Figure 12-12. Configuration of INT0 Pin Interrupt Request Register Name Flag symbol Address Read/write 3EH R/W b3 b2 b1 b0 INT0 pin I 0 0 I interrupt request N R T Q 0 0 Indicates interrupt request issuance status of INT0 pin 0 Interrupt request not issued 1 Interrupt request issued Fixed to 0 After reset Detects status of INT0 pin 0 Low level is input 1 High level is input Power-on reset U WDT&SP reset U 0 CE reset U R U R Clock stop 0 0 0 U: Undefined, R: Retained Data Sheet U15722EJ1V1DS 129 µPD17704A, 17705A, 17707A, 17708A, 17709A Figure 12-13. Configuration of CE Pin Interrupt Request Register Name Flag symbol Address Read/write 3FH R/W b3 b2 b1 b0 CE pin interrupt request C 0 E C I E R C Q N C T E S T T Indicates interrupt request issuance status of CE pin 0 Interrupt request not issued 1 Interrupt request issued Detects status of CE reset counter 0 Stops 1 Operates Fixed to 0 After reset Detects status of CE pin 0 Low level is input 1 High level is input Power-on reset U WDT&SP reset CE reset Clock stop 0 0 0 U 0 0 U 0 R U 0 R U : Undefined, R: Retained 130 Data Sheet U15722EJ1V1DS µPD17704A, 17705A, 17707A, 17708A, 17709A 12.2.2 Function and configuration of interrupt request flag (IP×××) Each interrupt request flag enables the interrupt of the corresponding peripheral hardware unit. In order for an interrupt to be acknowledged, all the following conditions must be satisfied. • The interrupt must be enabled by the corresponding interrupt request flag. • The interrupt request must be issued by the corresponding interrupt request flag. • The EI instruction (which enables all interrupts) must be executed. The interrupt enable flags are located on the interrupt enable register on the register file. Figures 12-14 through 12-16 show the configuration and function of each interrupt enable register. Figure 12-14. Configuration of Interrupt Enable Register 1 Name Flag symbol Address Read/write 2DH R/W b3 b2 b1 b0 Interrupt enable 1 I I I I P P P P S S T T I I M M O O 1 3 2 0 Enables or disables timer 2 interrupt 0 Disables 1 Enables Enables or disables timer 3 interrupt 0 Disables 1 Enables Enables or disables serial interface 0 interrupt 0 Disables 1 Enables After reset Enables or disables serial interface 1 interrupt 0 Disables 1 Enables Power-on reset 0 0 0 0 WDT&SP reset 0 0 0 0 CE reset Retained Clock stop Retained Data Sheet U15722EJ1V1DS 131 µPD17704A, 17705A, 17707A, 17708A, 17709A Figure 12-15. Configuration of Interrupt Enable Register 2 Name Flag symbol Address Read/write 2EH R/W b3 b2 b1 b0 Interrupt enable 2 I I I I P P P P T T 4 3 M M 1 0 Enables or disables INT3 pin interrupt 0 Disables 1 Enables Enables or disables INT4 pin interrupt 0 Disables 1 Enables Enables or disables timer 0 interrupt 0 Disables 1 Enables After reset Enables or disables timer 1 interrupt Disables 1 Enables Power-on reset 0 0 0 0 WDT&SP reset 0 0 0 0 CE reset Retained Clock stop 132 0 Retained Data Sheet U15722EJ1V1DS µPD17704A, 17705A, 17707A, 17708A, 17709A Figure 12-16. Configuration of Interrupt Enable Register 3 Name Flag symbol Address Read/write 2FH R/W b3 b2 b1 b0 Interrupt enable 3 I I I I P P P P 2 1 0 C E Enables or disables CE pin interrupt 0 Disables 1 Enables Enables or disables INT0 pin interrupt 0 Disables 1 Enables Enables or disables INT1 pin interrupt 0 Disables 1 Enables After reset Enables or disables INT2 pin interrupt 0 Disables 1 Enables Power-on reset 0 0 0 0 WDT&SP reset 0 0 0 0 CE reset Retained Clock stop Retained Data Sheet U15722EJ1V1DS 133 µPD17704A, 17705A, 17707A, 17708A, 17709A 12.2.3 Vector address generator (VAG) The vector address generator generates a branch address (vector address) of the program memory corresponding to an interrupt source that has been acknowledged from the corresponding peripheral hardware. Table 12-1 shows the vector addresses of the respective interrupt sources. Table 12-1. Interrupt Sources and Vector Addresses Interrupt Source 134 Vector Address Falling edge of CE pin 00CH INT0 pin 00BH INT1 pin 00AH INT2 pin 009H INT3 pin 008H INT4 pin 007H Timer 0 006H Timer 1 005H Timer 2 004H Timer 3 003H Serial interface 0 002H Serial interface 1 001H Data Sheet U15722EJ1V1DS µPD17704A, 17705A, 17707A, 17708A, 17709A 12.3 Interrupt Stack Register 12.3.1 Configuration and function of interrupt stack register Figure 12-17 shows the configuration of the interrupt stack register. The interrupt stack register saves the contents of the following system registers (except the address register (AR)) when an interrupt is acknowledged. • Window register (WR) • Bank register (BANK) • Index register (IX) • General pointer (RP) • Program status word (PSWORD) When an interrupt is acknowledged and the contents of the above system registers are saved to the interrupt stack, the contents of the above system registers, except the window register, are reset to 0. The interrupt stack can save the contents of the above system registers at up to four levels. Therefore, interrupts can be nested up to four levels. The contents of the interrupt stack register are restored to the system registers when the interrupt return (RETI) instruction is executed. The contents of the interrupt stack register are undefined after power-on reset. The previous contents are retained after CE reset and on execution of the clock stop instruction. Figure 12-17. Configuration of Interrupt Stack Register Interrupt stack pointer of system register Bit Interrupt stack register (INTSK) Name Bank stack Index stack H Index stack M Index stack L Pointer stack H Pointer stack L Status stack WRSK BANKSK IXHSK IXHSK IXHSK RPHSK RPLSK PSWSK Bit Address b 3 b2 b1 b 0 b3 b2 b1 b0 b 3 b2 b 1 b0 b3 b2 b 1 b0 b 3 b2 b1 b0 b3 b2 b 1 b0 b3 b 2 b1 b0 b3 b2 b 1 b 0 b3 b 2 b1 b0 0 Window stack S S S Y Y Y S S S S S S P P P 2 1 0 0H Undefined 1H I N T S K 1 2H I N T S K 2 3H I N T S K 3 4H I N T S K 4 5H Undefined Data Sheet U15722EJ1V1DS 135 µPD17704A, 17705A, 17707A, 17708A, 17709A 12.3.2 Interrupt stack pointer of system register The interrupt stack pointer of the system register detects the nesting level of interrupts. The interrupt stack pointer can be only read and cannot be written. The configuration and function of the interrupt stack pointer are illustrated below. Name Flag symbol Address Read/write 08H R ) ) S S Y Y Y S S S R R R S S S P P P 2 1 0 ( system registers S ( 0 ) Interrupt stack pointer of ( b3 b2 b1 b0 Detects level of interrupt stack of system registers 0 0 0 Use prohibited 0 0 1 4 levels (INTSK1) 0 1 0 3 levels (INTSK2) 0 1 1 2 levels (INTSK3) 1 0 0 1 level (INTSK4) 1 0 1 0 level After reset Fixed to 0 1 0 1 WDT&SP reset 1 0 1 CE reset 1 0 1 Power-on reset Clock stop 136 0 Retained Data Sheet U15722EJ1V1DS µPD17704A, 17705A, 17707A, 17708A, 17709A 12.3.3 Interrupt stack operation Figure 12-8 shows the operation of the interrupt stack. When nested interrupts exceeding four levels are acknowledged, since the contents saved first are discarded they therefore must be saved by the program. Figure 12-18. Operation of Interrupt Stack (1/2) (a) Where interrupt nesting level is 4 or less Undefined MAIN A Undefined Undefined MAIN Undefined Undefined Undefined Undefined Undefined Undefined Main routine MAIN Interrupt A A Interrupt B B RETI RETI Undefined MAIN A Undefined Undefined MAIN Undefined Undefined Undefined Undefined Undefined Undefined Data Sheet U15722EJ1V1DS 137 µPD17704A, 17705A, 17707A, 17708A, 17709A Figure 12-18. Operation of Interrupt Stack (2/2) (b) Where interrupt nesting level is 5 or more Undefined MAIN A C D Undefined Undefined MAIN B C Undefined Undefined A B Undefined Undefined MAIN A Main routine Interrupt A MAIN A Interrupt level 1 Interrupt C B Interrupt level 2 Interrupt D Interrupt E D E Interrupt level 4 Interrupt level 5 System reset Caution The system is reset when an interrupt of level 5 is acknowledged. However, the ISPRES flag, which resets the non-maskable interrupt if the interrupt stack overflows or underflows, must be set to 1. This flag is 1 after system reset, and can then be written only once. 138 Data Sheet U15722EJ1V1DS µPD17704A, 17705A, 17707A, 17708A, 17709A 12.4 Stack Pointer, Address Stack Registers, and Program Counter The address stack registers save a return address when execution returns from an interrupt routine. The stack pointer specifies the address of an address stack register. When an interrupt is acknowledged, the value of the stack pointer is decremented by one, and the value of the program counter at that time is saved to an address stack register specified by the stack pointer. Next, the interrupt routine is executed. When the interrupt return (RETI) instruction is executed after that, the contents of an address stack register specified by the stack pointer are restored to the program counter, and the value of the stack pointer is incremented by one. For further information, also refer to 3. ADDRESS STACK (ASK). 12.5 Interrupt Enable Flip-Flop (INTE) The interrupt enable flip-flop enables or disables the 12 types of maskable interrupts. When this flip-flop is set, all the interrupts are enabled. When it is reset, all the interrupts are disabled. This flip-flop is set or reset by dedicated instructions EI (to set) and DI (to reset). The EI instruction sets this flip-flop when the instruction next to EI is executed, and the DI instruction resets the flip-flop while it is being executed. When an interrupt is acknowledged, this flip-flop is automatically reset. This flip-flop is also reset after a power-on reset, after a reset by the RESET pin, at a watchdog timer, overflow or underflow of the stack, and after CE reset. The flip-flop retains the previous status on execution of the clock stop instruction. Data Sheet U15722EJ1V1DS 139 µPD17704A, 17705A, 17707A, 17708A, 17709A 12.6 Acknowledging Interrupt 12.6.1 Acknowledging interrupt and priority The following operations are performed before an interrupt is acknowledged. (1) Each peripheral hardware unit outputs an interrupt request signal to the corresponding interrupt request block if a given interrupt condition (for example, input of the falling signal to the INT0 pin) is satisfied. (2) When each interrupt request block acknowledges an interrupt request signal from the corresponding peripheral hardware unit, it sets the corresponding interrupt request flag (for example, IRQ0 flag if it is the INT0 pin that has issued the interrupt request) to 1. (3) The interrupt enable flag corresponding to each interrupt request flag (for example, IP0 flag if the interrupt request flag is IRQ0) is set to 1 when each interrupt request flag is set to 1, and each interrupt request block outputs 1. (4) The signal output by the interrupt request block is ORed with the output of the interrupt enable flip-flop, and an interrupt acknowledge signal is output. This interrupt enable flip-flop is set to 1 by the EI instruction, and reset to 0 by the DI instruction. If 1 is output by each interrupt request processing block while the interrupt enable flip-flop is set to 1, the interrupt is acknowledged. As shown in Figure 12-1, the output of the interrupt enable flip-flop is input to each interrupt request block via an AND circuit when an interrupt is acknowledged. The signal input to each interrupt request block causes the interrupt request flag corresponding to each interrupt request flag to be reset to 0 and the vector address corresponding to each interrupt to be output. If the interrupt request block outputs 1 at this time, the interrupt acknowledge signal is not transferred to the next stage. If two or more interrupt requests are issued at the same time, therefore, the interrupts are acknowledged according to the priority shown in Table 12-2. Unless the interrupt request enable flag is set to 1, the corresponding interrupt is not acknowledged. Therefore, by resetting the interrupt enable flag to 0, the interrupt with a high hardware priority can be disabled. Table 12-2. Interrupt Priority Interrupt Source 140 Priority Falling edge of CE pin 1 INT0 pin 2 INT1 pin 3 INT2 pin 4 INT3 pin 5 INT4 pin 6 Timer 0 7 Timer 1 8 Timer 2 9 Timer 3 10 Serial interface 0 11 Serial interface 1 12 Data Sheet U15722EJ1V1DS µPD17704A, 17705A, 17707A, 17708A, 17709A 12.6.2 Timing chart when interrupt is acknowledged The timing charts in Figure 12-19 illustrate the operations performed when an interrupt or interrupts are acknowledged. Figure 12-19 (1) is the timing chart when one interrupt is acknowledged. (a) in (1) is the timing chart where the interrupt request flag is set to 1 after all the others, and (b) is the timing chart where the interrupt enable flag is set to 1 after all the others. In either case, the interrupt is acknowledged when the interrupt request flag, interrupt enable-flip flop, and interrupt enable flag all have been set to 1. If the flag or flip-flop that has been set last is set in the first instruction cycle of the “MOVT DBF, @AR” instruction or by an instruction that satisfies a given skip condition, the interrupt is acknowledged in the second instruction cycle of the “MOVT DBF, @AR” instruction or after the instruction that is skipped (this instruction is treated as NOP) has been executed. The interrupt enable flip-flop is set in the instruction cycle next to that in which the EI instruction is executed. Therefore, the interrupt is acknowledged after the instruction next to the EI instruction has been executed even when the interrupt request flag is set in the execution cycle of the EI instruction. (2) in Figure 12-19 is the timing chart where two or more interrupts are used. When two or more interrupts are used, the interrupts are acknowledged according to the hardware priority if all the interrupt enable flags are set. However, the hardware priority can be changed by setting the interrupt enable flags by the program. “Instruction cycle” shown in Figure 12-19 is a special cycle in which the interrupt request flag is reset, a vector address is specified, and the contents of the program counter are saved after an interrupt has been acknowledged. It takes 1.78 µ s, which is equivalent to one instruction execution time, to be completed. For details, refer to 12.7 Operation After Interrupt Has Been Acknowledged. Data Sheet U15722EJ1V1DS 141 µPD17704A, 17705A, 17707A, 17708A, 17709A Figure 12-19. Timing Charts When Interrupt Is Acknowledged (1/3) (1) When one interrupt (e.g., rising of INT0 pin) is used (a) If there is no interrupt mask time by the interrupt flag (IP×××) <1> If a normal instruction which is not “MOVT” or an instruction that satisfies a skip condition is executed when interrupt is acknowledged Instruction EI MOV POKE WR, #0010B INTPM3, WR Normal Interrupt instruction cycle INTE INT0 pin IRQ0 flag IP0 flag 1 instruction cycle Interrupt enable period INT0 pin interrupt service 1.78 µ s INT0 pin interrupt acknowledged <2> If “MOVT” or an instruction that satisfies a skip condition is executed when interrupt is acknowledged Instruction EI MOV POKE WR, #0010B INTPM3, WR MOVT DBF, @AR or skip instruction Interrupt cycle INTE INT0 pin IRQ0 flag IP0 flag 1 instruction cycle Interrupt enable period INT0 pin interrupt service 1.78 µ s INT0 pin interrupt acknowledged 142 Data Sheet U15722EJ1V1DS µPD17704A, 17705A, 17707A, 17708A, 17709A Figure 12-19. Timing Charts When Interrupt Is Acknowledged (2/3) (b) If interrupt is kept pending by the interrupt enable flag Instruction Interrupt MOV POKE cycle WR, #0010B INTPM3, WR EI INTE INT0 pin IRQ0 flag IP0 flag INT0 pin interrupt pending period INT0 pin interrupt service INT0 pin interrupt acknowledged (2) If two or more interrupts (e.g., INT0 pin and INT1 pin) are used (a) Hardware priority Instruction MOV POKE WR, #0110B INTPM3, WR Interrupt cycle EI EI Interrupt cycle INTE INT0 pin IRQ0 flag INT1 pin IRQ1 flag IP0 flag IP1 flag INT0 pin interrupt pending period INT0 pin interrupt service INT1 pin interrupt pending period INT0 pin interrupt acknowledged Data Sheet U15722EJ1V1DS INT1 pin interrupt service INT1 pin interrupt acknowledged 143 µPD17704A, 17705A, 17707A, 17708A, 17709A Figure 12-19. Timing Charts When Interrupt Is Acknowledged (3/3) (b) Software priority Instruction MOV POKE WR, #0100B INTPM3, WR EI Interrupt MOV POKE cycle WR, #0110B INTPM3, WR EI Interrupt cycle INTE INT0 pin IRQ0 flag INT1 pin IRQ1 flag IP0 flag IP1 flag INT1 pin interrupt pending period INT1 pin interrupt service INT0 pin interrupt pending period INT1 pin interrupt acknowledged 144 Data Sheet U15722EJ1V1DS INT0 pin interrupt service INT0 pin interrupt acknowledged µPD17704A, 17705A, 17707A, 17708A, 17709A 12.7 Operations After Interrupt Has Been Acknowledged When an interrupt is acknowledged, the following operations are sequentially performed automatically. (1) The interrupt enable flip-flop and the interrupt request flag corresponding to the acknowledged interrupt request are reset to 0. As a result, the other interrupts are disabled. (2) The contents of the stack pointer are decremented by one. (3) The contents of the program counter are saved to an address stack register specified by the stack pointer. At this time, the contents of the program counter are the program memory address after the address at which the interrupt has been acknowledged. For example, if a branch instruction is executed when the interrupt has been acknowledged, the contents of the program counter are the branch destination address. If a subroutine call instruction is executed, the contents of the program counter are the call destination address. If the skip condition of a skip instruction is satisfied, the next instruction is executed as NOP and then the interrupt is acknowledged. Consequently, the contents of the program counter are the address after that of the instruction that is skipped. (4) The contents of the system registers (except the address register) are saved to the interrupt stack. (5) The contents of the vector address generator corresponding to the interrupt that has been acknowledged are transferred to the program counter. In other words, execution branches to the interrupt routine. The operations (1) through (5) above require the time of one special instruction cycle (1.78 µ s) in which normal instruction execution is not performed. This instruction cycle is called an “interrupt cycle”. In other words, the time of one instruction cycle (1.78 µ s) is required after an interrupt has been acknowledged until execution branches to the corresponding vector address. 12.8 Returning from Interrupt Routine The interrupt return (RETI) instruction is used to return from an interrupt routine to the processing during which an interrupt was acknowledged. When the RETI instruction is executed, the following operations are sequentially performed automatically. (1) The contents of an address stack register specified by the stack pointer are restored to the program counter. (2) The contents of the interrupt stack are restored to the system registers. (3) The contents of the stack pointer are incremented by one. The operations (1) through (3) above require one instruction cycle (1.78 µ s) in which the RETI instruction is executed. The only difference between the RETI instruction and the RET and RETSK instructions, which are subroutine return instructions, is the restoration of the bank register and index register in step (2) above. Data Sheet U15722EJ1V1DS 145 µPD17704A, 17705A, 17707A, 17708A, 17709A 12.9 External Interrupts (CE and INT0 to INT4 Pins) 12.9.1 Outline of external interrupts Figure 19-20 outlines the external interrupts. As shown in the figure, external interrupt requests are issued at the rising or falling edges of signals input to the INT0 to INT4 pins, and at the falling edge of the CE pin. Whether an interrupt request is issued at the rising or falling edge of an INT pin is independently specified by the program. The INT0 to INT4 and CE pins are Schmitt-triggered input pins to prevent malfunctioning due to noise. These pins do not acknowledge a pulse input of less than 100 ns. Figure 12-20. Outline of External Interrupts Interrupt control block INT0 flag IEG0 flag Edge detection block INT0 IRQ0 flag Schmitt trigger INT1 flag IEG1 flag Edge detection block INT1 IRQ1 flag Schmitt trigger INT2 flag IEG2 flag Edge detection block INT2 IRQ2 flag Schmitt trigger INT3 flag IEG3 flag Edge detection block INT3 IRQ3 flag Schmitt trigger INT3SEL INT4 flag IEG4 flag Edge detection block INT4 IRQ4 flag Schmitt trigger INT4SEL CE flag Edge detection block CE Schmitt trigger 146 Data Sheet U15722EJ1V1DS IRQCE flag µPD17704A, 17705A, 17707A, 17708A, 17709A 12.9.2 Edge detection block The edge detection block specifies the valid edge (rising or falling edge) of an input signal that issues the interrupt request of INT0 to INT4 pins, by using the interrupt edge selection register. Figure 12-21 shows the configuration and function of the interrupt edge selection register. Figure 12-21. Configuration of Interrupt Edge Selection Register (1/2) Name Flag symbol Address Read/write 1EH R/W b3 b2 b1 b0 Interrupt edge selection 1 I I I I E N E N G T G T 4 4 3 3 S S E E L L Selects function of P1A2/INT3 pin 0 Interrupt pin (edge detector operates) 1 General-purpose port pin (edge detector stops) Selects input edge to issue interrupt request (INT3 pin) 0 Rising edge 1 Falling edge Selects function of P1A3/INT4 pin 0 Interrupt pin (edge detector operates) 1 General-purpose port pin (edge detector stops) After reset Selects input edge to issue interrupt request (INT4 pin) 0 Rising edge 1 Falling edge Power-on reset 0 0 0 0 WDT&SP reset 0 0 0 0 CE reset Retained Clock stop Caution Retained The external input is delayed about 100 ns. Data Sheet U15722EJ1V1DS 147 µPD17704A, 17705A, 17707A, 17708A, 17709A Figure 12-21. Configuration of Interrupt Edge Selection Register (2/2) Name Flag symbol Address Read/write 1FH R/W b3 b2 b1 b0 Interrupt edge selection 2 0 I I I E E E G G G 2 1 0 Selects input edge to issue interrupt request (INT0 pin) 0 Rising edge 1 Falling edge Selects input edge to issue interrupt request (INT1 pin) 0 Rising edge 1 Falling edge Selects input edge to issue interrupt request (INT2 pin) 0 Rising edge 1 Falling edge After reset Fixed to 0 0 0 0 WDT&SP reset 0 0 0 CE reset Retained Power-on reset Clock stop Caution 0 Retained The external input is delayed about 100 ns. Note that an interrupt request signal may be issued at the time when the interrupt request issuance edge is switched by the interrupt edge selection flags (IEG0 to IEG4). As indicated in Table 12-3, for example, if the IEG0 flag is set to 1 (falling edge), the high level is input from the INT0 pin and the IEG0 flag is reset to 0, the edge detector judges that the rising edge is input and an interrupt request is issued. 148 Data Sheet U15722EJ1V1DS µPD17704A, 17705A, 17707A, 17708A, 17709A Table 12-3. Issuance of Interrupt Request by Changing IEG Flag Changes in IEG0 to IEG4 Flags 1 → Issuance of Interrupt Request Status of Interrupt Request Flag Low level Not issued Retains previous status (Falling) (Rising) High level Issued Set to 1 → Low level Issued Set to 1 High level Not issued Retains previous status 0 0 Status of INT0 to INT4 Pins 1 (Rising) (Falling) 12.9.3 Interrupt control block The signal levels that are input to the INT0 to INT4 pins can be detected by using the INT0 to INT4 flags. Because these flags are reset independently of interrupts, when the interrupt function is not used the INT0 to INT2 pins can be used as a 3-bit input port, and P1A2/INT3 and P1A3/INT4 pins can be used as a 2-bit generalpurpose input port. If the interrupts are not enabled, these ports can be used as general-purpose port pins whose rising or falling edge can be detected by reading the corresponding interrupt request flags. At this time, however, the interrupt request flags are not automatically reset and must be reset by the program. For further information, also refer to 12.2.1 Configuration and function of interrupt request flag (IRQ×××). 12.10 Internal Interrupts The following six internal interrupts are available. • Timer 0 • Timer 1 • Timer 2 • Timer 3 • Serial interface 0 • Serial interface 1 12.10.1 Timer 0, timer 1, timer 2, and timer 3 interrupts Interrupt requests are issued at fixed intervals. For details, refer to 13. TIMER. 12.10.2 Serial interface 0 and serial interface 1 interrupts Interrupt requests can be issued at the end of a serial output or serial input operation. For details, refer to 16. SERIAL INTERFACE. Data Sheet U15722EJ1V1DS 149 µPD17704A, 17705A, 17707A, 17708A, 17709A 13. TIMERS Timers are used to manage the program execution time. 13.1 Outline of Timers Figure 13-1 outlines the timers. The following five timers are available. • Basic timer 0 • Timer 0 • Timer 1 • Timer 2 • Timer 3 Basic timer 0 detects the status of a flip-flop that is set at fixed time intervals in software. Timers 0 to 3 are modulo timers and can use interrupts. Basic timer 0 can also be used to detect a power failure. Timer 3 is multiplexed with the D/A converter. The clock of each timer is created by dividing the system clock (4.5 MHz). Figure 13-1. Outline of Timers (1/2) (1) Basic timer 0 4.5 MHz Clock selection Flip-flop BTM0CY flag (2) Timer 0 4.5 MHz Clock selection Start/stop 8-bit counter Overflow Interrupt control TM0G Gate control Match detection Modulo register (3) Timer 1 4.5 MHz Clock selection Start/stop 8-bit counter Match detection Modulo register 150 Data Sheet U15722EJ1V1DS Interrupt control µPD17704A, 17705A, 17707A, 17708A, 17709A Figure 13-1. Outline of Timers (2/2) (4) Timer 2 4.5 MHz Clock selection Start/stop 8-bit counter Match detection Interrupt control Modulo register (5) Timer 3 4.5 MHz Clock divider Start/stop 8-bit counter or 9-bit counter Match detection Interrupt control Modulo register Multiplexed with D/A converter Data Sheet U15722EJ1V1DS 151 µPD17704A, 17705A, 17707A, 17708A, 17709A 13.2 Basic Timer 0 13.2.1 Outline of basic timer 0 Figure 13-2 outlines basic timer 0. Basic timer 0 is used as a timer by detecting in software the BTM0CY flag that is set at fixed intervals (100, 50, 20, or 10 ms). If the BTM0CY flag is read first after power-on reset, 0 is always read. After that, the flag is set to 1 at fixed intervals. If the CE pin goes high, CE reset is effected in synchronization with the timing at which the BTM0CY flag is set next. Therefore, a power failure can be detected by reading the content of the BTM0CY flag after system reset (power-on reset or CE reset). For details of power failure detection, refer to 21. RESET. Figure 13-2. Outline of Basic Timer 0 Clock selection block BTM0CK0 flag BTM0CK1 flag 4.5 MHz Divider Selector Flip-flop BTM0CY flag Remarks 1. BTM0CK1 and BTM0CK0 (bits 1 and 0 of basic timer 0 clock selection register: refer to Figure 13-3) set the time intervals at which the BTM0CY flag is set. 2. BTM0CY (bit 0 of basic timer 0 carry register: refer to Figure 13-4) detects the status of the flip-flop. 152 Data Sheet U15722EJ1V1DS µPD17704A, 17705A, 17707A, 17708A, 17709A 13.2.2 Clock selection block The clock selection block divides the system clock (4.5 MHz) and sets the time interval at which the BTM0CY flag is to be set, by using the BTM0CK0 and BTM0CK1 flags. Figure 13-3 shows the configuration of the basic timer 0 clock selection register. Figure 13-3. Configuration of Basic Timer 0 Clock Selection Register Name Flag symbol Address Read/write 18H R/W b3 b2 b1 b0 Basic timer 0 clock selection 0 0 B B T T M M 0 0 C C K K 1 0 Sets time interval at which BTM0CY flag is set 0 0 10 Hz (100 ms) 0 1 20 Hz (50 ms) 1 0 50 Hz (20 ms) 1 1 100 Hz (10 ms) After reset Fixed to 0 Power-on reset WDT&SP reset CE reset Clock stop 0 0 0 0 0 0 Retained Retained Data Sheet U15722EJ1V1DS 153 µPD17704A, 17705A, 17707A, 17708A, 17709A 13.2.3 Flip-flop and BTM0CY flag The flip-flop is set at fixed intervals and its status is detected by the BTM0CY flag of the basic timer 0 carry register. When the BTM0CY flag is read, it is reset to 0 (Read & Reset). The BTM0CY flag is 0 after power-on reset, and is 1 at CE reset and on execution of the clock stop instruction. Therefore, this flag can be used to detect a power failure. The BTM0CY flag is not set after power application until an instruction that reads it is executed. Once the read instruction has been executed, the flag is set at fixed intervals. Figure 13-4 shows the configuration of the basic timer 0 carry register. Figure 13-4. Configuration of Basic Timer 0 Carry Register Name Flag symbol Address Read/write 17H R & Reset b3 b2 b1 b0 Basic timer 0 carry 0 0 0 B T M 0 C Y Detects status of flip-flop 0 Flip-flop is not set 1 Flip-flop is set After reset Fixed to 0 Power-on reset 0 0 0 0 WDT&SP reset R CE reset 1 Clock stop R R: Retained 154 Data Sheet U15722EJ1V1DS µPD17704A, 17705A, 17707A, 17708A, 17709A 13.2.4 Example of using basic timer 0 An example of a program using basic timer 0 is shown below. This program executes processing A every 1 second. Example CLR2 MOV LOOP: SKT1 BR ADD SKE BR MOV BTM0CK1, BTM0CK0 ; Sets BTM0CY flag setting pulse to 10 Hz (100 ms) M1, #0 BTM0CY NEXT M1, #1 M1, #0AH NEXT M1, #0 ; Branches to NEXT if BTM0CY flag is 0 ; Adds 1 to M1 ; Executes processing A if M1 is 10 (1 second has elapsed) Processing A NEXT: Processing B BR ; Executes processing B and branches to LOOP LOOP Data Sheet U15722EJ1V1DS 155 µPD17704A, 17705A, 17707A, 17708A, 17709A 13.2.5 Errors of basic timer 0 Errors of basic timer 0 include an error due to the detection time of the BTM0CY flag, and an error that occurs when the time interval at which the BTM0CY flag is to be set is changed. The following paragraphs (1) and (2) describe each error. (1) Error due to detection time of BTM0CY flag The time to detect the BTM0CY flag must be shorter than the time at which the BTM0CY flag is set (refer to 13.2.6 Notes on using basic timer 0). Where the time interval at which the BTM0CY flag is detected is t CHECK and the time interval at which the flag is set is t SET (100, 50, 20, or 10 ms), tCHECK and t SET must relate as follows. t CHECK < tSET At this time, the error of the timer when the BTM0CY flag is detected is shown in Figure 13-5. 0 < Error < t SET Figure 13-5. Error of Basic Timer 0 Due to Detection Time of BTM0CY Flag BTM0CY flag setting pulse H L tSET 1 BTM0CY flag 0 tCHECK2 tCHECK1 SKT1 BTM0CY <1> SKT1 BTM0CY <2> tCHECK3 SKT1 BTM0CY <3> SKT1 BTM0CY <4> As shown in Figure 13-5, the timer is updated because the BTM0CY flag is 1 when it is detected in step <2>. When the flag is detected next in step <3>, it is 0. Therefore, the timer is not updated until the flag is detected again in <4>. This means that the timer is extended by the time of t CHECK3 . 156 Data Sheet U15722EJ1V1DS µPD17704A, 17705A, 17707A, 17708A, 17709A (2) Error when time interval to set BTM0CY flag is changed The BTM0CK1 and BTM0CK0 flags set the time of the BTM0CY flag. As described in 13.2.2, four types of timer time-setting pulses can be selected: 10 Hz, 20 Hz, 50 Hz, and 100 Hz. At this time, these four pulses operate independently. If the timer time-setting pulse is changed by using the BTM0CK1 and BTM0CK0 flags, an error occurs as described in the example below. Example ; <1> INTIFLG NOT BTM0CK1, NOT BTM0CK0 ; Sets BTM0CY flag setting pulse to 10 Hz (100 ms) Processing A ; <2> INITFLG BTM0CK1, NOT BTM0CK0 ; Sets BTM0CY flag setting pulse to 50 Hz (20 ms) Processing A ; <3> INITFLG NOT BTM0CK1, NOT BTM0CK0 ; Sets BTM0CY flag setting pulse to 10 Hz (100 ms) At this time, the BTM0CY flag setting pulse is changed as shown in Figure 13-6. Figure 13-6. Changing BTM0CY Flag Setting Pulse H Internal pulse 10 HZ L Internal pulse H 50 HZ L BTM0CY flag H setting pulse L 1 <1> <2> <3> BTM0CY flag 0 SKT1 BTM0CY As shown in Figure 13-6, if the BTM0CY flag setting time is changed and the new pulse falls, the BTM0CY flag retains the previous status (<2> in the figure). If the new pulse rises, however, the BTM0CY flag is set to 1 (<3> in the figure). Although changing the pulse setting between 10 Hz (100 ms) and 50 Hz (20 ms) is described in this example, the same applies to changing the pulse in respect to 20 Hz (50 ms) and 100 Hz (10 ms). Data Sheet U15722EJ1V1DS 157 µPD17704A, 17705A, 17707A, 17708A, 17709A Therefore, as shown in Figure 13-7, the error of the time until the BTM0CY flag is first set after the BTM0CY flag setting time has been changed is as follows. –tSET < Error < t CHECK t SET: New setting time of BTM0CY flag t CHECK : Time to detect BTM0CY flag Phase differences are provided among the internal pules of 10, 20, 50, and 100 Hz. Because these phase differences are shorter than the newly set pulse time, they are included in the above error. Figure 13-7. Timer Error When BTM0CY Flag Setting Time Is Changed from A to B H Internal pulse A L H Internal pulse B L tSET BTM0CY flag setting pulse tSET H L H BTM0CY flag L tCHECK SKT1 BTM0CY Intrinsic timer time Actual timer time Time changed Intrinsic timer time Actual timer time Time changed An error of -tSET occurs if BTM0CY flag is detected immediately after the timer time has been changed because the flag then becomes 1. 158 Data Sheet U15722EJ1V1DS An error of tCHECK occurs if the timer time is changed immediately after BTM0CY flag has been detected because the flag is then reset once. µPD17704A, 17705A, 17707A, 17708A, 17709A 13.2.6 Cautions on using basic timer 0 (1) BTM0CY flag detection time interval Keep the time to detect the BTM0CY flag shorter than the time at which the BTM0CY flag is set. This is because, if the time of processing B is longer than the time interval at which the BTM0CY flag is set as shown in Figure 13-8, setting of the BTM0CY flag is overlooked. Figure 13-8. BTM0CY Flag Detection and BTM0CY Flag BTM0CY flag setting pulse H L tSET <1> <2> <3> <4> <5> 1 BTM0CY flag 0 SKT1 BTM0CY SKT1 BTM0CY Processing A SKT1 BTM0CY Processing B Because execution time of processing B takes too long after detection of BTM0CY flag that has been set to 1 in <2>, BTM0CY flag that is set to 1 in <3> cannot be detected. (2) Timer updating processing time and BTM0CY flag detection time interval As described in (1) above, time interval t SET at which the BTM0CY flag is detected must be shorter than the time for which to set the BTM0CY flag. At this time, even if the time interval at which the BTM0CY flag is detected is short, if the updating processing time of the timer is long the processing of the timer may not be executed normally after CE reset. Therefore, the following condition must be satisfied. t CHECK + tTIMER < tSET t CHECK: Time to detect BTM0CY flag t TIMER: Timer updating processing time t SET: Time to set BTM0CY flag An example is given below. Data Sheet U15722EJ1V1DS 159 µPD17704A, 17705A, 17707A, 17708A, 17709A Example Example of timer updating processing and BTM0CY flag detection time interval START: CLR2 BTIMER: ; <1> SKT1 BR BTM0CK1, BTM0CK0 ; Sets BTM0CY flag setting pulse to 10 Hz (100 ms) BTM0CY AAA ; Updates timer if BTM0CY flag is 1 Timer updating BR BTIMER AAA: Processing A BR BTIMER The timing chart of the above program is shown below. H CE pin L BTM0CY flag setting pulse H L tSET 1 BTM0CY flag 0 BTM0CY detection interval tCHECK <1> SKT1 BTM0CY <2> SKT1 BTM0CY Timer updating processing tTIMER CE reset If this timer updating processing time is too long, CE reset is effected during processing. (3) Compensating basic timer 0 carry after CE reset Next, an example of compensating the timer after CE reset is described below. As shown in the example below, the timer must be compensated after CE reset “if the BTM0CY flag is used for power failure detection and if the BTM0CY flag is used for a watch timer”. The BTM0CY flag is reset first on power application (power-on reset), and is disabled from being set until it is read once by the PEEK instruction. If the CE pin goes high, CE reset is effected in synchronization with the rising edge of the BTM0CY flag setting pulse. At this time, the BTM0CY flag is set and the timer is started. By detecting the status of the BTM0CY flag after system reset (power-on reset or CE reset), therefore, it can be identified whether a power-on reset or CE reset has been effected (power failure detection). That is, power-on reset has been effected if the flag is 0, and CE reset has been effected if it is 1. At this time, the watch timer must continue operating even if CE reset has been effected. However, because the BTM0CY flag is reset to 0 when it is read to detect a power failure, the set status (1) of the BTM0CY flag is overlooked once. If the delay function of CE reset is used, the value set to the CE reset timer carry counter (control register address 06H) is overlooked. Consequently, the watch timer must be updated if CE reset is identified by means of power failure detection. For details of power failure detection, refer to 21. RESET. 160 Data Sheet U15722EJ1V1DS µPD17704A, 17705A, 17707A, 17708A, 17709A Example Example of compensating timer after CE reset (to detect power failure and update watch timer using BTM0CY flag) START: ; Program address 0000H Processing A ; <1> SKT1 BR BACKUP: ; <2> BTM0CY ; Embedded macro ; Tests BTM0CY flag ; if 0, branches to INITIAL (power failure detection) INITIAL 100-ms watch updating ; Compensates watch timer because of backup (CE reset) ; Initial value 1 is stored as CE reset timer carry ; counter value LOOP: ; <3> Processing B SKF1 BR BR BTM0CY BACKUP LOOP : While performing processing B, ; tests BTM0CY flag and updates watch timer INITIAL: CLR2 BTM0CK1, BTM0CK0 ; Embedded macro ; Because power failure (power-on reset) occurs, ; sets setting time of BTM0CY flag to 100 ms, and ; executes processing C Processing C BR LOOP Figure 13-9 shows the timing chart of the above program. Data Sheet U15722EJ1V1DS 161 µPD17704A, 17705A, 17707A, 17708A, 17709A Figure 13-9. Timing Chart VDD 5V 0V CE H L BTM0CY flag setting pulse (10 Hz) BTM0CY flag H L 1 0 A Program processing Program instruction <1> C B <3> Power-on reset Start from address 0 Application of supply voltage B <3> B B B <3> <3> B <3> <3> Watch UP Watch UP B B <3> <3> <1> CE reset Watch UP Start from address 0 BTM0CY flag detected Point A B A B <3> <3> Watch UP Updates watch timer because setting of BTM0CY flag (to 1) is detected Point B Point C Point D Point E As shown in Figure 13-9, the program is started from address 0000H because the internal 10 Hz pulse rises when supply voltage V DD is first applied. When the BTM0CY flag is detected at point A, it is judged that the BTM0CY flag is reset (to 0) and that a power failure (power-on reset) has occurred because the power has just been applied. Therefore, processing C is executed, and the BTM0CY flag setting pulse is set to 100 ms. Because the content of the BTM0CY flag is read once at point A, the BTM0CY flag will be set to 1 every 100 ms. Next, even if the CE pin goes low at point B and high at point C, the program counts up the watch timer while executing processing B, unless the clock stop instruction is executed. At point C, because the CE pin goes high, CE reset is effected at point D at which the BTM0CY flag setting pulse rises next time, and the program is started from address 0000H. When the BTM0CY flag is detected at point E at this time, it is set to 1. Therefore, this is judged to be a backup (CE reset). As is evident from the above figure, unless the watch is updated by 100 ms at point E, the watch is delayed by 100 ms each time CE reset is effected. If processing A takes longer than 100 ms when a power failure is detected at point E, the setting of the BTM0CY flag is overlooked two times. Therefore, processing A must be completed within 100 ms. The above description also applies when the BTM0CY flag setting pulse is set to 50, 20, or 10 ms. Therefore, the BTM0CY flag must be detected for power failure detection within the BTM0CY flag setting time after the program has been started from address 0000H. 162 Data Sheet U15722EJ1V1DS µPD17704A, 17705A, 17707A, 17708A, 17709A (4) If BTM0CY flag is detected at the same time as CE reset As described in (3) above, CE reset is effected as soon as the BTM0CY flag is set to 1. If the instruction that reads the BTM0CY flag happens to be executed at the same time as CE reset at this time, the BTM0CY flag reading instruction takes precedence. Therefore, if the next setting the BTM0CY flag (rising of BTM0CY flag setting pulse) after the CE pin has gone high matches execution of the BTM0CY flag reading instruction, CE reset is effected at “the next timing at which the BTM0CY flag is set”. This operation is illustrated in Figure 13-10. Figure 13-10. Operation When CE Reset Matches BTM0CY Flag Reading Instruction H CE pin L H BTM0CY flag setting pulse L 1 BTM0CY flag 0 SKT1 BTM0CY BTM0CY flag setting pulse SKT1 BTM0CY CE reset H L 1 BTM0CY flag 0 Instruction SKT1 BTM0CY (PEEK ···) (SKT ···) Embedded macro PEEK WR, . MF. BTM0CY SHR 4 SKT WR, #. DF. BTM0CY AND 000FH 1.78 µ s If BTM0CY flag is read at this time, CE reset is effected delayed once. Originally, program is started from address 0000H here. However, CE reset is not effected because it happens to match program that reads BTM0CY flag. Consequently, if the BTM0CY flag detection time interval matches the BTM0CY flag setting time in a program that cyclically detects the BTM0CY flag, CE reset is never effected. Therefore, the following point must be noted. Because one instruction cycle is 1.78 µ s (1/562.5 kHz), a program that detects the BTM0CY flag once, say, every 1125 instructions, reads the BTM0CY flag every 1.78 µ s × 1125 = 2 ms. Because the timer time setting pulse is 100 ms at this time, if setting and detection of the BTM0CY flag match once, CE reset is never effected. Data Sheet U15722EJ1V1DS 163 µPD17704A, 17705A, 17707A, 17708A, 17709A Therefore, do not create a cyclic program that satisfies the following condition. t SET × 1125 X = n (n: Natural number) t SET: BTM0CY flag setting time X: Cycle X step of instruction that reads BTM0CY flag An example of a program that satisfies the above condition is shown below. Do not create such a program. Example Processing A CLR2 BTM0CK1, BTM0CK0 ; Embedded macro ; Sets BTM0CY flag setting pulse to 100 ms LOOP: ; <1> SKT1 BR BTM0CY BBB ; Embedded macro AAA: 1121 steps BR LOOP BBB: 1121 steps BR LOOP Because the BTM0CY flag reading instruction in <1> is repeatedly executed every 1125 instructions in this example, CE reset is not effected if the BTM0CY flag happens to be set at the timing of instruction in <1>. 164 Data Sheet U15722EJ1V1DS µPD17704A, 17705A, 17707A, 17708A, 17709A 13.3 Timer 0 13.3.1 Outline of timer 0 Figure 13-11 shows the outline of timer 0. Timer 0 is used as timer (modulo mode) by comparing the count value with the previously set value after the basic clock (100 kHz, 10 kHz, 2 kHz, and 1 kHz) has counted by the 8-bit counter. The pulse width of the signal input from the TM0G pin can be measured (external gate counter). Figure 13-11. Outlines Timer 0 TM0CK1 flag TM0CK0 flag DBF TM0OVF flag 8 4.5 MHz Clock selection Start/stop Timer 0 counter (TM0C) Overflow TM0RES flag TM0GCEG flag TM0GOEG flag P1A0/TM0G Sets IRQTM0 flag Match detector Gate control TM0MD flag TM0MD flag Timer 0 modulo register (TM0M) 8 DBF Gate closed Remarks 1. TM0CK1 and TM0CK0 (bits 1 and 0 of timer 0 counter clock selection register: refer to Figure 13-13) set a basic clock frequency. 2. TM0MD (bit 0 of timer 0 mode selection register: refer to Figure 13-14) selects the modulo counter and gate counter. 3. TM0GOEG (bit 1 of timer 0 mode selection register: refer to Figure 13-14) sets the open edge of an external gate. 4. TM0GCEG (bit 2 of timer 0 mode selection register: refer to Figure 13-14) sets the close edge of an external gate. 5. TM0OVF (bit 3 of timer 0 mode selection register: refer to Figure 13-14) detects an overflow of timer 0 counter. 6. TM0RES (bit 2 of timer 0 counter clock selection register: refer to Figure 13-13) resets the timer 0 counter. Data Sheet U15722EJ1V1DS 165 µPD17704A, 17705A, 17707A, 17708A, 17709A 13.3.2 Clock selection, start/stop control, and gate control blocks Figure 13-12 shows the configuration of these blocks. The clock selection block selects a basic clock to operate the timer 0 counter. Four types of basic clocks can be selected by using the TM0CK1 and TM0CK0 flags. Figure 13-13 shows the configuration and function of each flag. The start/stop block controls the TM0MD flag and open/close signal from the gate control block, and starts or stops the basic clock to be input to timer 0 counter by the TM0EN flag. The gate control block sets the opening or closing conditions of the gate. It sets whether the gate is opened or closed by a rising or falling of the input signal, by using the TM0GOEG and TM0GCEG flags. This block also issues an interrupt request when the closing condition of the gate is detected. Figure 13-14 shows the configuration and function of each flag. Figure 13-12. Configuration of Clock Selection, Start/Stop Control, and Gate Control Blocks Clock selection Start/stop TM0CK1 TM0CK0 Divider Selector 100 kHz 4.5 MHz Timer 0 counter 10 kHz 2 kHz 1 kHz TM0EN flag TM0MD flag TM0MD flag Gate control TM0GOEG TM0GCEG P1A0/TM0G Edge detection Open/ close Timer 0 interrupt 166 Data Sheet U15722EJ1V1DS µPD17704A, 17705A, 17707A, 17708A, 17709A Figure 13-13. Configuration of Timer 0 Counter Clock Selection Register Name Flag symbol Address Read/write 2BH R/W b3 b2 b1 b0 Timer 0 counter T T T T clock selection M M M M 0 0 0 0 E R C C N E K K S 1 0 Sets basic clock of timer 0 counter 0 0 100 kHz (10 µ s) 0 1 10 kHz (100 µ s) 1 0 2 kHz (500 µ s) 1 1 1 kHz (1 ms) Resets timer 0 counter 0 Does not change 1 Resets counter After reset Starts or stops timer 0 0 Stops 1 Starts Power-on reset 0 0 0 0 WDT&SP reset 0 0 0 0 CE reset Retained Clock stop Caution 0 0 0 0 When the TM0RES flag is read, 0 is always read. Data Sheet U15722EJ1V1DS 167 µPD17704A, 17705A, 17707A, 17708A, 17709A 13.3.3 Count block The count block counts the basic clock with an 8-bit timer 0 counter, reads the count value, and issues an interrupt request if the value of the timer 0 modulo register matches its value. The timer 0 counter can be reset by the TM0RES flag. The TM0OVF flag can detect an overflow of the counter. When an overflow occurs, an interrupt request can be issued. The value of the timer 0 counter can be read via data buffer. The value of the timer 0 modulo register can be written or read via data buffer. Figure 13-14 shows the configuration of the timer 0 mode selection register. Figure 13-15 shows the configuration of the timer 0 counter. Figure 13-16 shows the configuration of the timer 0 modulo register. Figure 13-14. Configuration of Timer 0 Mode Selection Register Name Flag symbol Address Read/write 2CH R/W b3 b2 b1 b0 Timer 0 mode selection T T T T M M M M 0 0 0 0 O G G M V C O D F E E G G Selects modulo counter or gate counter of timer 0 0 Modulo counter 1 Gate counter Specifies edge of gate open input signal 0 Rising edge 1 Falling edge Specifies edge of gate close input signal 0 Rising edge 1 Falling edge After reset Detects timer 0 overflow No overflow 1 Overflow Power-on reset 0 0 0 0 WDT&SP reset 0 0 0 0 CE reset Retained Clock stop 168 0 0 0 0 0 Data Sheet U15722EJ1V1DS µPD17704A, 17705A, 17707A, 17708A, 17709A Figure 13-15. Configuration of Timer 0 Counter Data buffer DBF3 DBF2 Don't care Don't care DBF1 DBF0 Transfer data GET 8 bits PUT must not be executed Name Timer 0 counter Symbol TM0C Address 1BH Bit b7 b6 b 5 b4 b 3 b 2 b 1 b0 Data Valid data Reads count value of timer 0 0 • Modulo mode Reset if count value of timer 0 matches value of modulo counter. • External gate mode After reset 0FFH Resets counting to 00H if overflow occurs Power-on reset 0 0 0 0 0 0 0 0 WDT&SP reset 0 0 0 0 0 0 0 0 CE reset Retained 0 0 0 0 0 Clock stop 0 0 0 Data Sheet U15722EJ1V1DS 169 µPD17704A, 17705A, 17707A, 17708A, 17709A Figure 13-16. Configuration of Timer 0 Modulo Register Data buffer DBF3 DBF2 Don't care Don't care DBF1 DBF0 Transfer data GET 8 bits PUT Name Timer 0 modulo register Symbol TM0M Address 1AH Bit b7 b 6 b5 b4 b 3 b2 b1 b0 Data Valid data Sets modulo data of timer 0 0 • Modulo mode Issues interrupt request when value of modulo counter matches count value of timer 0. • External gate mode Does not issue interrupt request when value of modulo After reset 0FFH Power-on reset 1 1 1 1 1 1 1 1 WDT&SP reset 1 1 1 1 1 1 1 1 CE reset Retained 1 1 1 1 1 Clock stop 170 counter matches count value of timer 0. 1 1 1 Data Sheet U15722EJ1V1DS µPD17704A, 17705A, 17707A, 17708A, 17709A 13.3.4 Example of using timer 0 (1) Modulo counter mode The modulo counter mode is used for time management by generating timer 0 interrupt at fixed intervals. An example of a program is shown below. This program executes processing B every 500 µ s. TM0DATA DAT 0032H ; MODULO DATA = 50 START: BR INITIAL ; Interrupt vector address NOP NOP NOP NOP NOP BR INT_TM0 NOP NOP NOP NOP NOP NOP ; Reset address ; ; ; ; ; ; ; ; ; ; ; ; INITFLG ; CLR1 MOV MOV PUT SET1 EI SET1 ; Starts timer 0 SIO1 SIO0 TM3 TM2 TM1 TM0 INT4 INT3 INT2 INT1 INT0 Down edge of CE INITIAL: NOT TM0EN, TM0RES, NOT TM0CK1, NOT TM0CK0 (Stop) , (Reset) , (Basic clock = 10 µ s) TM0MD ; Modulo mode DBF0, #(TM0MDATA SHR 0) AND 0FH DBF1, #(TM0MDATA SHR 4) AND 0FH TM0M, DBF ; Sets count data IPTM0 ; Enables timer 0 interrupt TM0EN LOOP: Processing A BR LOOP INT_TM0: Processing B EI RETI ; Timer 0 interrupt service ; Return Data Sheet U15722EJ1V1DS 171 µPD17704A, 17705A, 17707A, 17708A, 17709A (2) Gate counter mode The gate counter mode is used to count the width of a pulse input to the TM0G pin. An example of a program is shown below. In this program example, the width of the pulse input to the TM0G pin is counted from the falling edge to the falling edge. If the pulse width is 800 to 1200 µ s, processing C is executed; otherwise, processing B is executed. If the pulse width is 2560 µ s or more, processing D is executed. TM0800 TM01200 DAT DAT 0050H 0078H ; Count data = 80 ; Count data = 120 START: BR INITIAL ; Interrupt vector address NOP NOP NOP NOP NOP BR INT_TM0 NOP NOP NOP NOP NOP NOP ; Reset address ; ; ; ; ; ; ; ; ; ; ; ; SIO1 SIO0 TM3 TM2 TM1 TM0 INT4 INT3 INT2 INT1 INT0 Down edge of CE INITIAL: INITFLG ; INITFLG ; SET1 SET1 EI NOT TM0EN, TM0RES, NOT TM0CK1, NOT TM0CK0 (Stop) , (Reset) , (Basic clock = 10 µ s) TM0GCEG , TM0GOEG , TM0MD (Falling close), (Falling open), (Gate counter) TM0EN ; START IPTM0 ; Enables timer 0 interrupt LOOP: Processing A BR LOOP PUT GET INITFLG SKT1 BR DBFSTK, DBF DBF, TM0C TM0EN, TM0RES TM0OVF AAA INT_TM0: ; Saves data buffer ; Detects overflow status (2560 µ s or more?) Processing D BR EI_RETI SUB SUBC SKF1 BR SUB DBF0, #TM0800 AND 0FH DBF1, #TM0800 SHR4 AND 0FH CY ; 800 µ s or more? BBB DBF0, #TM01200 AND 0FH AAA: 172 Data Sheet U15722EJ1V1DS µPD17704A, 17705A, 17707A, 17708A, 17709A SUBC SKT1 BR DBF1, #TM01200 SHR4 AND 0FH CY ; 1200 µ s or more? BBB Processing C BR EI_RETI BBB: Processing B EI_RETI: GET EI RETI DBF, DBFSTK ; Restores data buffer ; Return END 13.3.5 Error of timer 0 Timer 0 has an error of up to 1 basic clock in the following cases. (1) On starting/stopping counter The counter is started or stopped by ANDing the open/close condition of the gate and TM0EN flag setting condition. Therefore, an error of 0 to +1 clocks occurs when the gate is opened or the TM0EN flag is set, and an error of –1 to 0 clocks occurs when the gate is closed or the flag is reset. In all, an error of ±1 count occurs. (2) On resetting counter operation An error of 0 to +1 clocks occurs when the counter is reset. (3) On selecting basic clock during counter operation An error of 0 to +1 clocks of the newly selected clock occurs. 13.3.6 Cautions on using timer 0 Timer 0 interrupt may occur simultaneously with the other timer interrupts and CE reset. If it is necessary to update the timer after CE reset, do not use timer 0, use basic timer 0 instead. Data Sheet U15722EJ1V1DS 173 µPD17704A, 17705A, 17707A, 17708A, 17709A 13.4 Timer 1 13.4.1 Outline of timer 1 Figure 13-17 outlines timer 1. Timer 1 counts the basic clock (100, 10, 2, or 1 kHz) with an 8-bit counter, and compares the count value with a preset value. Figure 13-17. Outline of Timer 1 Interrupt control TM1CK1 flag TM1CK0 flag 4.5 MHz Clock selection DBF Start/stop Timer 1 counter (TM1C) TM1RES flag TM1EN flag Match detector Timer 1 IRQTM1 flag Timer 1 modulo register (TM1M) DBF Remarks 1. TM1CK1 and TM1CK0 (bits 1 and 0 of timer 1 counter clock selection register: refer to Figure 13-18) set the basic clock frequency. 2. TM1EN (bit 3 of timer 1 counter clock selection register: refer to Figure 13-18) starts or stops timer 1. 3. TM1RES (bit 2 of timer 1 counter clock selection register: refer to Figure 13-18) resets the timer 1 counter. 174 Data Sheet U15722EJ1V1DS µPD17704A, 17705A, 17707A, 17708A, 17709A 13.4.2 Clock selection and start/stop control blocks The clock selection block selects a basic clock to operate the timer 1 counter. Four types of basic clocks can be selected by using the TM1CK1 and TM1CK0 flags. The start/stop block starts or stops the basic clock input to timer 1 by using the TM1EN flag. Figure 13-18 shows the configuration and function of each flag. 13.4.3 Count block The count block counts the basic clock with the timer 1 counter, reads the count value, and issues an interrupt request when its count value matches the value of the timer 1 modulo register. The timer 1 counter can be reset by the TM1RES flag. The timer 1 counter is automatically reset when its value matches the value of the timer 1 modulo register. The value of the timer 1 counter can be read via data buffer. Data can be written to the value of the timer 1 modulo register via data buffer. Figure 13-18 shows the configuration of the timer 1 counter clock selection register. Figure 13-19 shows the configuration of the timer 1 counter. Figure 13-20 shows the configuration of the timer 1 modulo register. Data Sheet U15722EJ1V1DS 175 µPD17704A, 17705A, 17707A, 17708A, 17709A Figure 13-18. Configuration of Timer 1 Counter Clock Selection Register Name Flag symbol Address Read/write 2AH R/W b3 b2 b1 b0 Timer 1 counter clock selection T T T T M M M M 1 1 1 1 E R C C N E K K S 1 0 Sets basic clock of timer 1 counter 0 0 100 kHz (10 µ s) 0 1 10 kHz (100 µ s) 1 0 2 kHz (500 µ s) 1 1 1 kHz (1 ms) Resets timer 1 counter (valid on writing) 0 Does not change 1 Resets counter After reset Starts or stops timer 1 Stops 1 Starts Power-on reset 0 0 0 0 WDT&SP reset 0 0 0 0 CE reset Retained Clock stop Caution 176 0 0 0 0 0 When the TM1RES flag is read, 0 is always read. Data Sheet U15722EJ1V1DS µPD17704A, 17705A, 17707A, 17708A, 17709A Figure 13-19. Configuration of Timer 1 Counter Data buffer DBF3 DBF2 Don't care Don't care DBF1 DBF0 Transfer data GET 8 bits PUT must not be executed Name Timer 1 counter Symbol TM1C Address 1DH Bit b7 b6 b 5 b4 b 3 b 2 b 1 b0 Data Valid data Reads count value of timer 1 0 Count value x After reset 0FFH Power-on reset 0 0 0 0 0 0 0 0 WDT&SP reset 0 0 0 0 0 0 0 0 CE reset Retained 0 0 0 0 0 Clock stop 0 0 0 Data Sheet U15722EJ1V1DS 177 µPD17704A, 17705A, 17707A, 17708A, 17709A Figure 13-20. Configuration of Timer 1 Modulo Register Data buffer DBF3 DBF2 Don't care Don't care DBF1 DBF0 Transfer data GET 8 bits PUT Name Timer 1 modulo register Symbol TM1M Address 1CH Bit b7 b 6 b5 b4 b 3 b2 b1 b0 Data Valid data Sets modulo data of timer 1 0 Setting prohibited 1 x Modulo counter value After reset 0FFH Power-on reset 1 1 1 1 1 1 1 1 WDT&SP reset 1 1 1 1 1 1 1 1 CE reset Retained 1 1 1 1 1 Clock stop 178 1 1 1 Data Sheet U15722EJ1V1DS µPD17704A, 17705A, 17707A, 17708A, 17709A 13.4.4 Example of using timer 1 (1) Modulo timer The modulo timer is used for time management by generating timer 1 interrupt at fixed intervals. An example of a program is shown below. This program executes processing B every 500 µ s. TM1DATA DAT 0032H ; Count data = 50 START: BR INITIAL ; Interrupt vector address NOP NOP NOP NOP BR INT_TM1 NOP NOP NOP NOP NOP NOP NOP ; Reset address ; ; ; ; ; ; ; ; ; ; ; ; SIO1 SIO0 TM3 TM2 TM1 TM0 INT4 INT3 INT2 INT1 INT0 Down edge of CE INITIAL: INITFLG ; MOV MOV PUT SET1 SET1 EI NOT TM1EN, TM1RES, NOT TM1CK1, NOT TM1CK0 (Stop) , (Reset) , (Basic clock = 10 µ s) DBF0, #TM1DATA DBF1, #TM1DATA SHR4 AND 0FH TM1, DBF TM1EN ; START IPTM1 ; Enables timer 1 interrupt LOOP: Processing A BR LOOP PUT DBFSTK, DBF INT_TM1: ; Saves data buffer Processing B GET EI RETI DBF, DBFSTK ; Return END Data Sheet U15722EJ1V1DS 179 µPD17704A, 17705A, 17707A, 17708A, 17709A 13.4.5 Error of timer 1 Timer 1 has an error of up to 1 basic clock in the following cases. (1) On starting/stopping counter The counter is started or stopped by setting the TM1EN flag. Therefore, an error of 0 to +1 clocks occurs when the TM1EN flag is set, and an error of –1 to 0 clocks occurs when the flag is reset. In all, an error of ±1 count occurs. (2) On resetting counter operation An error of 0 to +1 clocks occurs when the counter is reset. (3) On selecting basic clock during counter operation An error of 0 to +1 clocks of the newly selected clock occurs. 13.4.6 Cautions on using timer 1 Timer 1 interrupt may occur simultaneously with the other timer interrupts and CE reset. If it is necessary to update the timer after CE reset, do not use timer 1, use basic timer 0 instead. 180 Data Sheet U15722EJ1V1DS µPD17704A, 17705A, 17707A, 17708A, 17709A 13.5 Timer 2 13.5.1 Outline of timer 2 Figure 13-21 outlines timer 2. Timer 2 counts the basic clock (100, 10, 2, or 1 kHz) with an 8-bit counter, and compares the count value with a value set in advance. Figure 13-21. Outline of Timer 2 Interrupt control TM2CK1 flag TM2CK0 flag 4.5 MHz Clock selection DBF Start/stop Timer 2 counter (TM2C) TM2RES flag TM2EN flag Match detector Timer 2 IRQTM2 flag Timer 2 modulo register (TM2M) DBF Remarks 1. TM2CK1 and TM2CK0 (bits 1 and 0 of timer 2 counter clock selection register: refer to Figure 13-22) set the basic clock frequency. 2. TM2EN (bit 3 of timer 2 counter clock selection register: refer to Figure 13-22) starts or stops timer 2. 3. TM2RES (bit 2 of timer 2 counter clock selection register: refer to Figure 13-22) resets the timer 2 counter. Data Sheet U15722EJ1V1DS 181 µPD17704A, 17705A, 17707A, 17708A, 17709A 13.5.2 Clock selection and start/stop control blocks The clock selection block selects a basic clock to operate the timer 2 counter. Four types of basic clocks can be selected by using the TM2CK1 and TM2CK0 flags. The start/stop block starts or stops the basic clock input to timer 2 by using the TM2EN flag. Figure 13-22 shows the configuration and function of each flag. 13.5.3 Count block The count block counts the basic clock with the timer 2 counter, reads the count value, and issues an interrupt request when its count value matches the value of the timer 2 modulo register. The timer 2 counter can be reset by the TM2RES flag. The timer 2 counter is automatically reset when its value matches the value of the timer 2 modulo register. The value of the timer 2 counter can be read via data buffer. Data can be written to the value of the timer 2 modulo register via data buffer. Figure 13-22 shows the configuration of timer 2 counter clock selection register. Figure 13-23 shows the configuration of the timer 2 counter. Figure 13-24 shows the configuration of the timer 2 modulo register. 182 Data Sheet U15722EJ1V1DS µPD17704A, 17705A, 17707A, 17708A, 17709A Figure 13-22. Configuration of Timer 2 Counter Clock Selection Register Name Flag symbol Address Read/write 29H R/W b3 b2 b1 b0 Timer 2 counter clock selection T T T T M M M M 2 2 2 2 E R C C N E K K S 1 0 Sets basic clock of timer 2 counter 0 0 100 kHz (10 µ s) 0 1 10 kHz (100 µ s) 1 0 2 kHz (500 µ s) 1 1 1 kHz (1 ms) Resets timer 2 counter (valid on writing) 0 Does not change 1 Resets counter After reset Starts or stops timer 2 0 Stops 1 Starts Power-on reset 0 0 0 0 WDT&SP reset 0 0 0 0 CE reset Retained Clock stop Caution 0 0 0 0 When the TM2RES flag is read, 0 is always read. Data Sheet U15722EJ1V1DS 183 µPD17704A, 17705A, 17707A, 17708A, 17709A Figure 13-23. Configuration of Timer 2 Counter Data buffer DBF3 DBF2 Don't care Don't care DBF1 DBF0 Transfer data GET 8 bits PUT must not be executed Name Timer 2 counter Symbol TM2C Address 1FH Bit b7 b6 b 5 b4 b 3 b2 b 1 b0 Data Valid data Reads count value of timer 2 0 Count value x After reset 0FFH Power-on reset 0 0 0 0 0 0 0 0 WDT&SP reset 0 0 0 0 0 0 0 0 CE reset Retained 0 0 0 0 0 Clock stop 184 0 0 0 Data Sheet U15722EJ1V1DS µPD17704A, 17705A, 17707A, 17708A, 17709A Figure 13-24. Configuration of Timer 2 Modulo Register Data buffer DBF3 DBF2 Don't care Don't care DBF1 DBF0 Transfer data GET 8 bits PUT Name Timer 2 modulo register Symbol TM2M Address 1EH Bit b7 b6 b 5 b4 b 3 b 2 b 1 b0 Data Valid data Sets modulo data of timer 2 0 Setting prohibited 1 x Modulo counter value After reset 0FFH Power-on reset 1 1 1 1 1 1 1 1 WDT&SP reset 1 1 1 1 1 1 1 1 CE reset Retained 1 1 1 1 1 Clock stop 1 1 1 Data Sheet U15722EJ1V1DS 185 µPD17704A, 17705A, 17707A, 17708A, 17709A 13.5.4 Example of using timer 2 (1) Modulo timer The modulo timer is used for time management by generating a timer 2 interrupt at fixed intervals. An example of a program is shown below. This program executes processing B every 500 µ s. TM2DATA DAT 0032H ; Count data = 50 START: BR INITIAL ; Interrupt vector address NOP NOP NOP BR INT_TM2 NOP NOP NOP NOP NOP NOP NOP NOP ; Reset address ; ; ; ; ; ; ; ; ; ; ; ; SIO1 SIO0 TM3 TM2 TM1 TM0 INT4 INT3 INT2 INT1 INT0 Down edge of CE INITIAL: INITFLG ; MOV MOV PUT SET1 SET1 EI NOT TM2EN, TM2RES, NOT TM2CK1, NOT TM2CK0 (Stop) , (Reset) , (Basic clock = 10 µ s) DBF0, #TM2DATA DBF1, #TM2DATA SHR4 AND 0FH TM2, DBF TM2EN ; START IPTM2 ; Enables timer 2 interrupt LOOP: Processing A BR LOOP PUT INITFLG DBFSTK, DBF TM2EN, TM2RES INT_TM2: ; Saves data buffer ; Resets and starts Processing B GET EI RETI DBF, DBFSTK ; Return END 186 Data Sheet U15722EJ1V1DS µPD17704A, 17705A, 17707A, 17708A, 17709A 13.5.5 Error of timer 2 Timer 2 has an error of up to 1 basic clock in the following cases. (1) On starting/stopping counter The counter is started or stopped by setting the TM2EN flag. Therefore, an error of 0 to +1 clocks occurs when the TM2EN flag is set, and an error of –1 to 0 clocks occurs when the flag is reset. In all, an error of ±1 count occurs. (2) On resetting counter operation An error of 0 to +1 clocks occurs when the counter is reset. (3) On selecting basic clock during counter operation An error of 0 to +1 clocks of the newly selected clock occurs. 13.5.6 Cautions on using timer 2 Timer 2 interrupt may occur simultaneously with the other timer interrupts and CE reset. If it is necessary to update the timer after CE reset, do not use timer 2, use basic timer 0 instead. Data Sheet U15722EJ1V1DS 187 µPD17704A, 17705A, 17707A, 17708A, 17709A 13.6 Timer 3 13.6.1 Outline of timer 3 Figure 13-25 outlines timer 3. Timer 3 counts the basic clock (1.125 MHz or 112.5 kHz selectable) with an 8-bit counterNote , and compares the count value with a value set in advance. Because timer 3 is multiplexed with a D/A converter, all the three D/A converter pins are automatically set in the general-purpose port mode when timer 3 is used. Note A 9-bit or 8-bit counter can be selected for the D/A converter, but the 8-bit counter is automatically selected when the timer function is selected. Figure 13-25. Outline of Timer 3 Interrupt control 4.5 MHz PWMCK flag TM3EN flag TM3SEL flag Clock selection Start/stop Timer 3 counter (TM3C) Match detector TM3RES flag IRQTM3 flag Timer 3 modulo register (TM3M) DBF Remarks 1. PWMCK (bit 0 of PWM clock selection register: refer to Figure 13-26) selects the output frequency of timer 3. 2. TM3SEL (bit 3 of timer 3 control register: refer to Figure 13-27) selects timer 3 or D/A converter. 3. TM3EN (bit 1 of timer 3 control register: refer to Figure 13-27) starts or stops counting by timer 3. 4. TM3RES (bit 0 of timer 3 control register: refer to Figure 13-27) controls resetting of the timer 3 counter. 188 Data Sheet U15722EJ1V1DS µPD17704A, 17705A, 17707A, 17708A, 17709A 13.6.2 Clock selection block The clock of timer 3 is selected by the PWMCK flag of the PWM clock selection register. Figure 13-26 shows the configuration of the flag. Figure 13-26. Configuration of PWM Clock Selection Register Name Flag symbol Address Read/write 26H R/W b3 b2 b1 b0 PWM clock selection 0 P 0 P W W M M B C I K T Selects output frequency of timer 3 0 4.4 kHz (8 bits)/2.2 kHz (9 bits) 1 440 Hz (8 bits)/220 Hz (9 bits) Fixed to 0 Selects number of bits of PWM counter 0 8 bits 1 9 bits After reset Fixed to 0 Power-on reset 0 0 0 0 WDT&SP reset 0 0 CE reset R R 0 0 Clock stop R: Retained Data Sheet U15722EJ1V1DS 189 µPD17704A, 17705A, 17707A, 17708A, 17709A 13.6.3 Start/stop control block The start/stop block starts or stops the basic clock to be input to the timer 3 counter by using the TM3EN flag. To control timer 3, timer 3 must be selected by the TM3SEL flag. Figure 13-27 shows the configuration of each flag. Figure 13-27. Configuration of Timer 3 Control Register Name Flag symbol Address Read/write 28H R/W b3 b2 b1 b0 Timer 3 control T 0 T T M M M 3 3 3 S E R E N E L S Resets counter 0 Dose not change 1 Resets Starts or stops counter 0 Stop 1 Starts Fixed to 0 After reset Selects timer 3 or D/A converter 0 D/A converter (PWM output) 1 Timer 3 Power-on reset 0 WDT&SP reset 0 CE reset R Clock stop 0 0 0 0 0 0 Retained 0 0 R: Retained 190 Data Sheet U15722EJ1V1DS µPD17704A, 17705A, 17707A, 17708A, 17709A 13.6.4 Count block The count block counts the basic clock with timer 3 and issues an interrupt request when the count value of timer 3 matches the value of the timer 3 modulo register. The timer 3 counter can be reset by the TM3RES flag. Because PWM data register 2 (PWMR2) and timer 3 modulo register (TM3M) are multiplexed, these registers cannot be used at the same time. When timer 3 is used, PWM data register 1 (PWMR1) and PWM data register 0 (PWMR0) can be used as 9-bit data latches (refer to 15. D/A CONVERTER (PWM MODE)). Figure 13-28. Configuration of Timer 3 Modulo Register Data buffer DBF3 DBF2 DBF1 DBF0 Transfer data GET 16 bits PUT Note Name Timer 3 modulo register Symbol TM3M Address 46H b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 Bit 0 Data 0 0 0 0 0 0 Valid data Sets modulo data of timer 3 0 Modulo counter value x 1FFH After reset Fixed to 0 Power-on reset 1 1 1 1 1 1 1 1 1 WDT&SP reset 1 1 1 1 1 1 1 1 1 CE reset Retained 1 1 1 1 1 1 Clock stop 1 1 1 Note This register is multiplexed with the PWM data register. Data Sheet U15722EJ1V1DS 191 µPD17704A, 17705A, 17707A, 17708A, 17709A 13.6.5 Example of using timer 3 An example of a program using timer 3 (multiplexed with PWM) is given below. This program executes processing B every 888 µ s. TM3DATA DAT 0064H ; Count data = 100 START: BR INITIAL ; Interrupt vector address NOP NOP BR INT_TM3 NOP NOP NOP NOP NOP NOP NOP NOP NOP ; Reset address ; ; ; ; ; ; ; ; ; ; ; ; SIO1 SIO0 TM3 TM2 TM1 TM0 INT4 INT3 INT2 INT1 INT0 Down edge of CE INITIAL: INITFLG ; INITFLG ; INITFLG ; NOT PWMSEL2 , NOT PWMSEL1 , NOT PWMSEL0 (General-purpose port), (General-purpose port), (General-purpose port) NOT PWMBIT, PWMCK ( 8BIT ), (440 Hz) TM3SEL , NOT TM3EN, TM3RES (Timer 3 mode), (Stop) , (Reset) MOV MOV PUT SET1 SET1 EI DBF0, #TM3DATA DBF1, #TM3DATA SHR4 AND 0FH TM3M, DBF TM3EN ; START IPTM3 ; Enables timer 3 interrupt LOOP: Processing A BR LOOP PUT DBFSTK, DBF INT_TM3: ; Saves data buffer Processing B GET EI RETI DBF, DBFSTK ; Return END 192 Data Sheet U15722EJ1V1DS µPD17704A, 17705A, 17707A, 17708A, 17709A 13.6.6 Error of timer 3 Timer 3 has an error of up to 1 basic clock in the following cases. (1) On starting/stopping counter The counter is started or stopped by setting the TM3EN flag. Therefore, an error of 0 to +1 clocks occurs when the TM3EN flag is set, and an error of –1 to 0 clocks occurs when the flag is reset. In all, an error of ±1 count occurs. (2) On resetting counter operation An error of 0 to +1 clocks occurs when the counter is reset. (3) On selecting basic clock during counter operation An error of 0 to +1 clocks of the newly selected clock occurs. 13.6.7 Cautions on using timer 3 Timer 3 interrupt may occur simultaneously with the other timer interrupts and CE reset. If it is necessary to update the timer after CE reset, do not use timer 3, use basic timer 0 instead. When timer 3 is used, the three output port pins multiplexed with the D/A converter pins, P1B2/PWM2 to P1B0/ PWM0, are automatically set to the general-purpose output port mode. Data Sheet U15722EJ1V1DS 193 µPD17704A, 17705A, 17707A, 17708A, 17709A 13.6.8 Status after reset (1) After power-on reset The P1B2/PWM2 to P1B0/PWM0 pins are set to the general-purpose output port mode. The output value is low level. The value of each PWM data register (including the timer 3 modulo register) is 1FFH. (2) After WDT&SP reset The P1B2/PWM2 to P1B0/PWM0 pins are set to the general-purpose output port mode. The output value is low level. The value of each PWM data register (including the timer 3 modulo register) is 1FFH. (3) On execution of clock stop instruction The P1B2/PWM2 to P1B0/PWM0 pins are set to the general-purpose output port mode. The output value is the previous contents of the output latch. The value of each PWM data register (including the timer 3 modulo register) is 1FFH. (4) After CE reset The previous status is retained. That is, if the D/A converter is being used, the PWM output is retained as is. If timer 3 is being used, counting continues. While timer 3 is being used, the DI status is set (in which all interrupts are disabled). (5) In halt status The previous status is retained. That is, if the D/A converter is being used, the PWM output is retained as is. If timer 3 is being used, counting continues. 194 Data Sheet U15722EJ1V1DS µPD17704A, 17705A, 17707A, 17708A, 17709A 14. A/D CONVERTER 14.1 Outline of A/D Converter Figure 14-1 outlines the A/D converter. The A/D converter converts an analog voltage input to the AD5 to AD0 pins into an 8-bit digital signal. Two modes can be selected by using the ADCMD flag: software mode and hardware mode. In the software mode, a voltage input to a pin is compared with an internal reference voltage, and the result of the comparison is detected by the ADCCMP flag. By judging this result in software and by sequentially selecting reference voltages, the A/D converter can be used as a successive approximation A/D converter. In the hardware mode, reference voltages are automatically selected, and the input voltage is directly detected as 8-bit digital data. Figure 14-1. Outline of A/D Converter ADCCH2 flag ADCCH1 flag ADCCH0 flag P1C3/AD5 P1C2/AD4 P0D3/AD3 P0D2/AD2 Input selection block P0D1/AD1 P0D0/AD0 Compare block ADCCMP flag DBF ADCSTT flag Compare voltage generation block R-string D/A converter Start/stop control block ADCMD flag Remarks 1. ADCCH2 to ADCCH0 (bits 2 to 0 of A/D converter channel selection register: refer to Figure 14-3) select pins used for the A/D converter. 2. ADCCMP (bit 0 of A/D converter mode selection register: refer to Figure 14-5) detects the result of comparison. 3. ADCSTT (bit 1 of A/D converter mode selection register: refer to Figure 14-5) detects the operating status. 4. ADCMD (bit 2 of A/D converter mode selection register: refer to Figure 14-5) selects software or hardware mode. Data Sheet U15722EJ1V1DS 195 µPD17704A, 17705A, 17707A, 17708A, 17709A 14.2 Input Selection Block Figure 14-2 shows the configuration of the input selection block. The input selection block selects a pin to be used by using the ADCCH2 to ADCCH0 flags. Only one pin can be used for the A/D converter. When one of the P0D0/AD0 to P0D3/AD3, P1C2/AD4, and P1C3/AD5 pins is selected, the other five pins are forcibly set in the input port mode. The P0D0/AD0 to P0D3/AD3 pins can be connected to a pull-down resistor if so specified by the P0DPL0 to P0DPLD3 flags. To use the P0D0/AD0 to P0D3/AD3 pins for the A/D converter, therefore, disconnect their pull-down resistors to correctly detect an external input analog voltage. Figure 14-3 shows the configuration of the A/D converter channel selection register. Figure 14-2. Configuration of Input Selection Block ADCCH2 ADCCH1 ADCCH0 Selector P1C3/AD5 P1C2/AD4 P0D3/AD3 Compare block VADCIN P0D2/AD2 P0D1/AD1 P0D0/AD0 Each I/O port 196 Data Sheet U15722EJ1V1DS µPD17704A, 17705A, 17707A, 17708A, 17709A Figure 14-3. Configuration of A/D Converter Channel Selection Register Name Flag symbol Address Read/write 24H R/W b3 b2 b1 b0 A/D converter channel selection 0 A A A D D D C C C C C C H H H 2 1 0 Selects pin used for A/D converter 0 0 0 A/D converter not used (general-purpose input port) 0 0 1 P0D0/AD0 pin 0 1 0 P0D1/AD1 pin 0 1 1 P0D2/AD2 pin 1 0 0 P0D3/AD3 pin 1 0 1 P1C2/AD4 pin 1 1 0 P1C3/AD5 pin 1 1 1 Setting prohibited After reset Fixed to 0 Power-on reset 0 0 0 WDT&SP reset 0 0 0 CE reset Retained Clock stop 0 Retained Data Sheet U15722EJ1V1DS 197 µPD17704A, 17705A, 17707A, 17708A, 17709A 14.3 Compare Voltage Generation and Compare Blocks Figure 14-4 shows the configuration of the compare voltage generation block and compare block. The compare voltage generation block switches a tap decoder according to the 8-bit data set to the A/D converter reference voltage setting register and generates 256 different of compare voltages VADCREF. In other words, this block is an R-string D/A converter. The supply voltage to this R-string D/A converter is the same as the supply voltage V DD of the device. The compare block compares voltage V ADCIN input from a pin with compare voltage V ADCREF . Comparison can be made in two modes, software mode and hardware mode, which can be selected by the ADCMD flag. In the software mode, a compare voltage is set to the A/D converter reference voltage setting register by software, and one set compare voltage is compared with the input voltage, and the result of the comparison is detected by the ADCCMP flag. In the hardware mode, once comparison has been started, the hardware automatically changes the value of the A/D converter reference voltage setting register. On completion of the comparison, the value of the A/D converter reference voltage setting register is read and is loaded as an 8-bit data. Figures 14-5 and 14-6 show the configuration of each flag and A/D converter reference voltage setting register. Figure 14-4. Configuration of Compare Voltage Generation and Compare Blocks 1/2 VDD − VADCIN DBF 2 pF VADCREF Comparator + A/D converter reference voltage setting register (ADCR) Tap decoder 0 1 1 R 2 2 R 254 R 255 3 R 2 VDD Soft/hard, start/stop control block ADCMD flag 198 Data Sheet U15722EJ1V1DS ADCSTT flag ADCCMP flag µPD17704A, 17705A, 17707A, 17708A, 17709A Figure 14-5. Configuration of A/D Converter Mode Selection Register Name Flag symbol Address Read/write 25H R/W b3 b2 b1 b0 A/D converter mode selection 0 A A A D D D C C C M S C D T M T P Detects result of comparison by A/D converter 0 VADCIN < VADCREF 1 VADCIN > VADCREF Detects operating status of A/D converter in hardware mode 0 End of conversion 1 Conversion in progress Selects compare mode of A/D converter and starts or stops A/D converter 0 Software modeNote 1 1 Hardware modeNote 2 After reset Fixed to 0 Power-on reset 0 0 0 WDT&SP reset 0 0 0 CE reset R 0 0 R 0 R Clock stop 0 R: Retained Notes 1. A/D conversion under execution is stopped if 0 is written to this bit. 2. A/D operation is started in the hardware mode when 1 is written to this bit. In the software mode, operation is started as soon as data has been written (by the PUT instruction) to the A/D converter reference voltage setting register (ADCR). Data Sheet U15722EJ1V1DS 199 µPD17704A, 17705A, 17707A, 17708A, 17709A Figure 14-6. Configuration of A/D Converter Reference Voltage Setting Register Data buffer DBF3 DBF2 Don't care Don't care DBF1 DBF0 Transfer data GET 8 bits PUT Name A/D converter reference voltage setting register Symbol ADCR Address 02H Bit b7 b 6 b5 b4 b 3 b2 b1 b0 Data Valid data Sets or reads compare voltage VADCREF of A/D converter · In software mode: Sets compare voltage · In hardware mode: Reads result of comparison 0 VADCREF = 0 V x VADCREF = x−0.5 × VDD (V) 256 After reset FFH Power-on reset 0 WDT&SP reset CE reset Clock stop 0 RetainedNote RetainedNote Note “0” in the hardware mode. 200 Data Sheet U15722EJ1V1DS µPD17704A, 17705A, 17707A, 17708A, 17709A 14.4 Comparison Timing Chart 14.4.1 In software mode Comparison is completed three instructions after data has been set (by the PUT instruction) to the A/D converter reference voltage setting register (ADCR). Figure 14-7 shows the timing chart. Figure 14-7. Timing Chart of Comparison by A/D Converter Instruction cycle PUT ADCR, DBF 2 1 3 Comparison starts Sample & hold ADCSTT flag “0” Result of comparison ADCCMP flag 14.4.2 In hardware mode When the ADCMD flag is set to 1, A/D conversion is started. The ADCSTT flag is set to 1, and comparison is completed after 17 instructions have been executed. At this time, the ADCSTT flag is reset to 0 after 15 instructions have been executed after the ADCMD flag was set to 1. This is because execution time of two instructions is required to judge the status of the ADCSTT flag. For details, also refer to 14.5 Using A/D Converter. Figure 14-8 shows the timing chart. Figure 14-8. Timing Chart of Comparison by A/D Converter Instruction cycle 1 2 3 15 16 17 Sample & hold ADCSTT flag A/D converter 1st 8th Result of comparison Reference voltage setting register ADCMD flag (=1) set. Comparison starts End of comparison Data Sheet U15722EJ1V1DS 201 µPD17704A, 17705A, 17707A, 17708A, 17709A 14.5 Using A/D Converter 14.5.1 Software mode The software mode is convenient for comparing one compare voltage. An example of a program in this mode is shown below. Example To compare input voltage V ADCIN of AD0 pin with compare voltage VADCREF (127.5/256 VDD ), and branch to AAA if V ADCIN < V ADCREF, or to BBB if V ADCIN > V ADCREF ADCR7 ADCR6 ADCR5 ADCR4 ADCR3 ADCR2 ADCR1 ADCR0 FLG FLG FLG FLG FLG FLG FLG FLG BANK15 INITFLG BANK0 INITFLG CLR1 INITFLG INITFLG PUT NOP NOP NOP SKT1 BR BR 0.0EH.3 ; Defines each bit of DBF as ADCR data setting flag 0.0EH.2 0.0EH.1 0.0EH.0 0.0EH.3 0.0EH.2 0.0EH.1 0.0EH.0 NOT P0DPLD3, NOT P0DPLD2, NOT P0DPLD1, P0DPLD0 ; Disconnects pull-down resistor of P0D0 pin NOT ADCCH2, NOT ADCCH1, ADCCH0 ADCMD ADCR7, NOT ADCR6, NOT ADCR5, NOT ADCR4 NOT ADCR3, NOT ADCR2, NOT ADCR1, NOT ADCR0 ADCR, DBF ; ; ; ; ; ; ; ; ; ADCCMP AAA BBB Selects AD0 pin for A/D converter Sets software mode Sets compare voltage VADCREF Waits for duration of three instructions Judges result of comparison 14.5.2 Hardware mode Here is a program example. Example To detect the value of analog input voltage V ADCIN of AD0 pin. BANK15 INITFLG NOT P0DPLD3, NOT P0DPLD2, NOT P0DPLD1, P0DPLD0 ; Disconnects pull-down resistor of P0D0 pin BANK0 INITFLG NOT ADCCH2, NOT ADCCH1, ADCCH0 ; Selects AD0 pin for A/D converter SET1 ADCMD ; Sets hardware mode and starts conversion LOOP: SKT1 202 ADCSTT ; Detects end of A/D conversion ; Embedded macro instruction ;PEEK WR, .MF. ADCSTT SHR4 AND 0FH ;SKT1 WR,#.DF.ADCSTT AND 0FH BR LOOP ; Conversion in progress GET ; Stores result of conversion to DBF DBF,ADCR Data Sheet U15722EJ1V1DS µPD17704A, 17705A, 17707A, 17708A, 17709A 14.6 Cautions on Using A/D Converter 14.6.1 Cautions on selecting A/D converter pin When one of the P0D0/AD0 to P0D3/AD3, P1C2/AD4, and P1C3/AD5 pins is selected, the other five pins are forcibly set in the input port mode. The P0D0/AD0 to P0D3/AD3 pins can be connected to a pull-down resistor if so specified by the P0DPL0 to P0DPLD3 flags in bank 15. To use the P0D0/AD0 to P0D3/AD3 pins for the A/D converter, therefore, disconnect their pull-down resistors to correctly detect an external input analog voltage. 14.7 Status After Reset 14.7.1 After power-on reset All the P0D0/AD0 to P0D3/AD3, P1C2/AD4, and P1C3/AD5 pins are set to the general-purpose input port mode. The P0D0 to P0D3 pins are connected with a pull-down resistor. 14.7.2 After WDT&SP reset All the P0D0/AD0 to P0D3/AD3, P1C2/AD4, and P1C3/AD5 pins are set to the general-purpose input port mode. The P0D0 to P0D3 pins are connected with a pull-down resistor. 14.7.3 After CE reset The status of the pin selected for the A/D converter is retained as is. The previous status of the pull-down resistor of the P0D0 to P0D3 pins is retained. 14.7.4 On execution of clock stop instruction The status of the pin selected for the A/D converter is retained as is. The previous status of the pull-down resistor of the P0D0 to P0D3 pins is retained. 14.7.5 In halt status The status of the pin selected for the A/D converter is retained as is. The previous status of the pull-down resistor of the P0D0 to P0D3 pins is retained. Data Sheet U15722EJ1V1DS 203 µPD17704A, 17705A, 17707A, 17708A, 17709A 15. D/A CONVERTER (PWM MODE) 15.1 Outline of D/A Converter Figure 15-1 outlines the D/A converter. The D/A converter outputs a signal whose duty factor is varied by means of PWM (Pulse Width Modulation). By connecting an external lowpass filter to the D/A converter, a digital signal can be converted into an analog signal. Each pin of the D/A converter can output a variable-duty signal independently of the others. Whether an 8-bit counter or 9-bit counter is used for the D/A converter can be specified by software. When the 8-bit counter is selected, two output frequencies, 4.4 kHz and 440 Hz can be selected, and the duty factor of the output signal can be varied in 256 steps. When the 9-bit counter is selected, two output frequencies, 2.2 kHz and 220 Hz, can be selected, and the duty factor can be varied in 512 steps. When the D/A converter is not used, it can be used as timer 3, which counts the basic clock (1.125 or 0.1125 MHz) with an 8-bit counter. For details of timer 3, refer to 13. TIMER 3. Figure 15-1. Outline of D/A Converter Duty setting block Multiplexed with timer 3 DBF DBF DBF PWM data register 0 (PWMR0) PWM data register 1 (PWMR1) PWM data register 2 (PWMR2) Comparator Comparator Comparator TM3SEL flag PWM0SEL flag P1B0/PWM0 Output selection block IRQTM3 PWM1SEL flag P1B1/PWM1 Output selection block PWM2SEL flag TM3RES flag RES P1B2/PWM2 Output selection block 9-bit or 8-bit counter PWMBIT Remarks 1. fPWM Clock generation block PWMCK PWM2SEL to PWM0SEL (bits 2 to 0 of PWM/general-purpose port pin function selection register: refer to Figure 15-4) select a general-purpose output port of D/A converter. 2. PWMBIT (bit 2 of PWM clock selection register: refer to Figure 15-2) selects the number of bits (8 or 9 bits) of the PWM counter. 3. PWMCK (bit 0 of PWM clock selection register: refer to Figure 15-2) selects the output frequency of PWM timer. 4. TM3SEL (bit 3 of timer 3 control register: refer to Figure 15-5) selects timer 3 or D/A converter. 5. TM3RES (bit 0 of timer 3 control register: refer to Figure 15-5) controls resetting of the timer 3 counter. 204 Data Sheet U15722EJ1V1DS µPD17704A, 17705A, 17707A, 17708A, 17709A 15.2 PWM Clock Selection Register The PWM clock selection register specifies whether the PWM counter is used as an 8-bit counter or 9-bit counter when the D/A converter is used for PWM output. Figure 15-2 shows the configuration of the PWM clock selection register. Figure 15-2. Configuration of PWM Clock Selection Register Name Flag symbol Address Read/write 26H R/W b3 b2 b1 b0 PWM clock selection 0 P 0 P W W M M B C I K T Selects output frequency of timer 3 0 4.4 kHz (8 bits) /2.2 kHz (9 bits) 1 440 Hz (8 bits) /220 Hz (9 bits) Fixed to 0 Selects number of bits of PWM counter 0 8 bits 1 9 bits After reset Fixed to 0 Power-on reset 0 0 0 0 WDT&SP reset 0 0 CE reset R R 0 0 Clock stop R: Retained Data Sheet U15722EJ1V1DS 205 µPD17704A, 17705A, 17707A, 17708A, 17709A 15.3 PWM Output Selection Block The output selection block specifies whether each output pin of the D/A converter is used for the D/A converter or as a general-purpose output port, by using the PWM2SEL to PWM0SEL flags of the PWM/general-purpose port pin function selection register. Figure 15-3 shows the configuration of the output selection block, and Figure 15-4 shows the configuration of the PWM/general-purpose port pin function selection register. Each pin can be changed between the D/A converter mode and general-purpose output port mode independently of the others. Because each output pin is an N-ch open-drain output pin, an external pull-up resistor is necessary. When the D/A converter is used as timer 3, the P1B2/PWM2 to P1B0/PWM0 pins are automatically set in the general-purpose output port mode, regardless of the values set to the PWM2SEL to PWM0SEL flags. Figure 15-3. Configuration of Output Selection Block PWM2SEL to PWM0SEL flags TM3SEL Each output pin 1 Comparator output 0 Output latch 206 Data Sheet U15722EJ1V1DS µPD17704A, 17705A, 17707A, 17708A, 17709A Figure 15-4. Configuration of PWM/General-Purpose Port Pin Function Selection Register Name Flag symbol Address Read/write 27H R/W b3 b2 b1 b0 PWM/general-purpose port 0 P P P W W W pin function selection M M M 2 1 0 S S S E E E L L L Selects function of P1B0/PWM0 pin 0 General-purpose output port 1 D/A converter Selects function of P1B1/PWM1 pin 0 General-purpose output port 1 D/A converter Selects function of P1B2/PWM2 pin 0 General-purpose output port 1 D/A converter After reset Fixed to 0 Power-on reset 0 0 0 WDT&SP reset 0 0 0 CE reset Retained Clock stop 0 0 0 0 Data Sheet U15722EJ1V1DS 207 µPD17704A, 17705A, 17707A, 17708A, 17709A Figure 15-5. Configuration of Timer 3 Control Register Name Flag symbol Address Read/write 28H R/W b3 b2 b1 b0 Timer 3 control T 0 T T M M M 3 3 3 S E R E N E L S Resets counter 0 Does not change 1 Resets Starts or stops counter 0 Stops 1 Starts Fixed to 0 After reset Selects timer 3 or D/A converter 0 D/A converter (PWM output) 1 Timer 3 Power-on reset 0 WDT&SP reset 0 CE reset R Clock stop 0 0 0 0 0 0 Retained 0 0 R: Retained 208 Data Sheet U15722EJ1V1DS µPD17704A, 17705A, 17707A, 17708A, 17709A 15.4 Duty Setting Block 15.4.1 PWM duty with 8-bit counter selected The duty setting block compares the value set to each PWM data register (PWMR2 to PWMR0) with the value of the basic clock counted by each 8-bit counter. If the value of the PWM data register is greater, the block outputs a high level. If the value of the PWM data register is less, it outputs a low level. Where the value set to the PWM data register is “x”, therefore, the duty factor can be calculated by the following expression. Duty: D = x + 0.25 256 × 100% Remark 0.25 is an offset, and a high level is output even where x = 0. Data is set to each PWM data register for each pin via a data buffer (DBF). However, the same basic clock, PWM counter, and output frequency must be selected for each pin. This means that each pin cannot output a duty factor of a different cycle independently of the others. Because the basic clock frequency is 1.125 or 0.1125 MHz, the frequency and cycle of the output signal can be calculated as follows. (1) Where output frequency is 4.4 kHz and basic clock frequency is 1.125 MHz Frequency: f = Cycle: T= 1.125 MHz 256 256 1.125 MHz = 4.3945 kHz = 227.56 µs (2) Where output frequency is 440 Hz and basic clock frequency is 0.1125 MHz Frequency: f = Cycle: T= 0.1125 MHz 256 256 0.1125 MHz = 439.45 Hz = 2.2756 ms Because the duty setting register of the PWM data registers and timer 3 modulo register are the same register, they cannot be used at the same time. When timer 3 is used, PWM data registers 1 and 0 can be used as 8-bit data latches. Data Sheet U15722EJ1V1DS 209 µPD17704A, 17705A, 17707A, 17708A, 17709A Figure 15-6. Configuration of PWM Data Registers (with 8-Bit Counter Selected) Data buffer DBF3 DBF2 DBF1 DBF0 Transfer data GET 16 bits PUT Name PMW data register 2 Symbol PWMR2 Address 46H Bit Data Note b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 0 0 0 0 0 0 0 0 Valid data GET PUT Name PMW data register 1 Symbol PWMR1 Address 45H Bit Data b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 0 0 0 0 0 0 0 0 Valid data GET PUT Name PWM data register 0 Symbol PWMR0 Address 44H Bit Data b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 0 0 0 0 0 0 0 0 Valid data Sets PWM output duty of each pin 0 Duty: D = x FFH After reset Fixed to 0 Power-on reset 1 1 1 1 1 1 1 1 WDT&SP reset 1 1 1 1 1 1 1 1 CE reset Retained 1 1 1 1 1 Clock stop Note 210 1 1 1 This register is multiplexed with the timer 3 modulo register. Data Sheet U15722EJ1V1DS x + 0.25 × 100% 256 µPD17704A, 17705A, 17707A, 17708A, 17709A 15.4.2 PWM duty with 9-bit counter selected The duty setting block compares the value set to each PWM data register (PWMR2 to PWMR0) with the value of the basic clock counted by each 9-bit counter. If the value of the PWM data register is greater, the block outputs a high level. If the value of the PWM data register is less, it outputs a low level. Where the value set to the PWM data register is “x”, therefore, the duty factor can be calculated by the following expression. Duty: D = x + 0.25 512 × 100% Remark 0.25 is an offset, and a high level is output even where x = 0. Data is set to each PWM data register for each pin via data buffer (DBF). However, the same basic clock, PWM counter, and output frequency must be selected for each pin. This means that each pin cannot output a duty factor of a different cycle independently of the others. Because the basic clock frequency is 1.125 or 0.1125 MHz, the frequency and cycle of the output signal can be calculated as follows. (1) Where output frequency is 2.2 kHz and basic clock frequency is 1.125 MHz Frequency: f = Cycle: T= 1.125 MHz 512 512 1.125 MHz = 2.197 kHz = 455.11 µs (2) Where output frequency is 220 Hz and basic clock frequency is 0.1125 MHz Frequency: f = Cycle: T= 0.1125 MHz 512 512 0.1125 MHz = 219.73 Hz = 4.5511 ms Because the duty setting register of the PWM data registers and timer 3 modulo register are the same register, they cannot be used at the same time. When timer 3 is used, PWM data registers 1 and 0 can be used as 8-bit data latches. Data Sheet U15722EJ1V1DS 211 µPD17704A, 17705A, 17707A, 17708A, 17709A Figure 15-7. Configuration of PWM Data Registers (with 9-Bit Counter Selected) Data buffer DBF3 DBF2 DBF1 DBF0 Transfer data GET 16 bits PUT Name PWM data register Symbol PWMR2 Address 46H 2Note b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 Bit 0 Data 0 0 0 0 0 0 Valid data GET PUT Name PWM data register 1 Symbol PWMR1 Address 45H b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 Bit 0 Data 0 0 0 0 0 0 Valid data GET PUT Name PWM data register 0 Symbol PWMR0 Address 44H b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 Bit 0 Data 0 0 0 0 0 0 Valid data Sets PWM output duty of each pin 0 Duty: D = x 1FFH After reset Fixed to 0 Power-on reset 1 1 1 1 1 1 1 1 1 WDT&SP reset 1 1 1 1 1 1 1 1 1 CE reset Retained 1 1 1 1 1 1 Clock stop Note 212 1 1 1 This register is multiplexed with the timer 3 modulo register. Data Sheet U15722EJ1V1DS x + 0.25 × 100% 512 µPD17704A, 17705A, 17707A, 17708A, 17709A 15.5 Clock Generation Block The clock generation block outputs a basic clock to set the duty factor of each output signal. Two output frequencies, 1.125 MHz and 112.5 kHz, can be selected. 15.6 D/A Converter Output Wave (1) shows the relationship between the duty factor and output wave. (2) shows the output wave of each pin. Each output pin has a phase different from the others. (1) Duty and output wave (a) With 8-bit counter and 4.4 kHz selected x=0 x=1 ……… x=2 222 ns 888 ns 888 ns x = 255 227.56 µ s 667 ns (b) With 8-bit counter and 440 Hz selected x=0 x=1 x=2 ……… 2.22 µ s 8.88 µs 8.88 µs x = 255 2.2756 ms Data Sheet U15722EJ1V1DS 6.67 µ s 213 µPD17704A, 17705A, 17707A, 17708A, 17709A (c) With 9-bit counter and 2.2 kHz selected x=0 x=1 x=2 ……… 222 ns 888 ns 888 ns x = 511 455.11 µs 667 ns (d) With 9-bit counter and 220 Hz selected x=0 x=1 x=2 ……… 2.22 µs 8.88 µs 8.88 µs x = 511 4.5511 ms (2) Each pin and output wave (a) With 8-bit counter and 4.4 kHz selected PWM0 (x = 0) PWM1 (x = 0) PWM2 (x = 0) 222 ns 222 ns 222 ns 227.56 µ s 227.56 µs 227.56 µ s 214 Data Sheet U15722EJ1V1DS 6.67 µ s µPD17704A, 17705A, 17707A, 17708A, 17709A (b) With 8-bit counter and 440 Hz selected PWM0 (x = 0) PWM1 (x = 0) PWM2 (x = 0) 2.22 µs 2.22 µ s 2.22 µs 2.2756 ms 2.2756 ms 2.2756 ms (c) With 9-bit counter and 2.2 kHz selected PWM0 (x = 0) PWM1 (x = 0) PWM2 (x = 0) 222 ns 222 ns 222 ns 455.11 µ s 455.11 µ s 455.11 µ s (d) With 9-bit counter and 220 Hz selected PWM0 (x = 0) PWM1 (x = 0) PWM2 (x = 0) 2.22 µ s 2.22 µ s 2.22 µ s 4.5511 ms 4.5511 ms 4.5511 ms Data Sheet U15722EJ1V1DS 215 µPD17704A, 17705A, 17707A, 17708A, 17709A 15.7 Example of Using D/A Converter An example of a program using the D/A converter is shown below. Example This program increments the duty factor of the PWM1 pin every 1 second. PWM1DATA DAT 0000H INITIAL: INITFLG NOT PWM2SEL, NOT PWM1SEL, NOT PWM0SEL ; (General-purpose port), (General-purpose port), (General-purpose port) INITFLG ; PWMBIT , NOT PWMCK (9-bit counter), (1.125 MHz) LOOP0: BANK1 CLR1 P1B1 BANK0 CLR1 TM3SEL ; Selects D/A converter MOV DBF2, #PWM1DATA SHR 8 AND 0FH MOV DBF1, #PWM1DATA SHR 4 AND 0FH MOV DBF0, #PWM1DATA AND 0FH SET1 PWM1SEL ; Sets PWM1/P1B1 pin to PWM output port mode LOOP1: ; Duty: 0.25/512 to 511.25/512 (PWM output) PUT PWM1R, DBF GET2 TM3RES, TM3EN ; Resets and starts counter Waits for 1 second GET DBF, PWM1R ADD DBF0, #1 ADDC DBF1, #0 ADDC DBF2, #1 SKGE DBF2, #2 BR LOOP1 LOOP2: ; Port outputs high level BANK1 SET1 P1B1 BANK0 CLR1 PWM1SEL ; Sets PWM1/P1B1 pin to general-purpose output port mode Waits for 1 second BR 216 LOOP0 Data Sheet U15722EJ1V1DS µPD17704A, 17705A, 17707A, 17708A, 17709A 15.8 Status After Reset 15.8.1 After power-on reset The P1B0/PWM0 to P1B2/PWM2 pins are set to the general-purpose output port mode. The output value is low level. The value of each PWM data register (including the timer 3 modulo register) is 1FFH. 15.8.2 After WDT&SP reset The P1B0/PWM0 to P1B2/PWM2 pins are set to the general-purpose output port mode. The output value is low level. The value of each PWM data register (including the timer 3 modulo register) is 1FFH. 15.8.3 After CE reset The P1B0/PWM2 to P1B2/PWM2 pins retain the previous status. That is, if the D/A converter is being used, the PWM output is retained as is. If timer 3 is being used, counting continues. 15.8.4 On execution of clock stop instruction The P1B0/PWM0 to P1B2/PWM2 pins are set to the general-purpose output port mode. The output value is the previous contents of the output latch. The value of each PWM data register (including the timer 3 modulo register) is 1FFH. 15.8.5 In halt status The P1B0/PWM0 to P1B2/PWM2 pins retain the previous status. That is, if the D/A converter is being used, the PWM output is retained as is. If timer 3 is being used, counting continues. Data Sheet U15722EJ1V1DS 217 µPD17704A, 17705A, 17707A, 17708A, 17709A 16. SERIAL INTERFACES 16.1 Outline of Serial Interfaces Figure 16-1 outlines the serial interfaces. Table 16-1 classifies the serial interfaces and shows their communication modes. As shown in Figure 16-1, two serial interfaces, 0 (SIO0) and 1 (SIO1), are available. Serial interfaces 0 and 1 can be used at the same time. Serial interface 0 can be used in two modes: 2-wire and 3-wire mode. In the 2-wire mode, two pins, SDA and SCL, are used. In the 3-wire mode, three pins, SCK0, SO0, and SI0, are used. In the 2-wire mode, two communication modes, I2C bus and serial I/O mode, can be selected. Serial interface 1 can be used only in 3-wire mode, and uses three pins, SCK1, SO1, and SI1. The communication mode is the serial I/O mode. Figure 16-1. Outline of Serial Interfaces SCL/P0A2 SCK0/P0A1 SO0/P0A0 I/O control SDA/P0A3 SI0/P0B3 Presettable shift register 0 (SIO0SFR) Clock control block 4.5 MHz Interrupt control block IRQSIO0 flag Serial interface 0 SO1/P0B1 SI1/P0B0 I/O control SCK1/P0B2 Presettable shift register 1 (SIO1SFR) Clock control block 4.5 MHz IRQSIO1 flag Serial interface 1 218 Data Sheet U15722EJ1V1DS µPD17704A, 17705A, 17707A, 17708A, 17709A Table 16-1. Classification and Communication Modes of Serial Interfaces Channel Serial interface 0 Number of Communication Lines Communication Mode 2 lines (2-wire) I2C bus P0A3/SDA Serial I/O P0A2/SCL Serial I/O P0A1/SCK0 3 lines (3-wire) Pins Used P0A0/SO0 P0B3/SI0 Serial interface 1 3 lines (3-wire) Serial I/O P0B2/SCK1 P0B1/SO1 P0B0/SI1 16.2 Serial Interface 0 16.2.1 Outline of serial interface 0 Figure 16-2 outlines the serial interface 0. Serial interface 0 can be used in 2-wire I2C bus or serial I/O mode, or 3-wire serial I/O mode. Figure 16-2. Outline of Serial Interface 0 SIO0CH flag SB flag SIO0MS flag SIO0CK0, 1 flag Wait signal SIO0WSTT flag SIO0WRQ0, 1 flag SIO0NWT flag SCL/P0A2 Clock I/O control block SCK0/P0A1 4.5 MHz Clock control block Wait control block Clock counter SIO0CH flag SB flag SIO0TX flag SIO0SF8, 9 flag SIO0IMD0, 1 flag Count values 8, 9 SBSTT, SBBSY flag Start/stop detection block Interrupt control block SDA/P0A3 SO0/P0A0 Data I/O control block OUT Presettable shift register 0 (SIO0SFR) IN Serial date SI0/P0B3 ACK Acknowledge control block Data Sheet U15722EJ1V1DS SBACK flag 219 µPD17704A, 17705A, 17707A, 17708A, 17709A Remarks 1. SIO0CH and SB (bits 3 and 2 of serial I/O0 mode selection register: refer to Figure 16-3) select the mode of serial I/O0. 2. SIO0MS (bit 1 of serial I/O0 mode selection register: refer to Figure 16-3) selects a master or slave. 3. SIO0TX (bit 0 of serial I/O0 mode selection register: Figure 16-3) selects reception or transmission. 4. SIO0CK1 and SIO0CK0 (bits 1 and 0 of serial I/O0 clock selection register: refer to Figure 16-4) select an internal shift clock frequency. 5. SIO0WRQ1 and SIO0WRQ0 (bits 1 and 0 of serial I/O0 wait control register: refer to Figure 16-7) set wait conditions for communication. 6. 7. SIO0NWT (bit 2 of serial I/O0 wait control register: refer to Figure 16-7) starts communication. SIO0SF9 and SIO0SF8 (bits 2 and 3 of serial I/O0 status detection register: refer to Figure 16-5) detect a clock counter. 8. SBSTT and SBBSY (bits 1 and 0 of serial I/O0 status detection register: refer to Figure 16-5) detect the start and stop conditions, and clock counter in the I2C bus mode. 9. SIO0IMD1 and SIO0IMD0 (bits 1 and 0 of serial I/O0 interrupt mode selection register: refer to Figure 16-9) set the interrupt timing. 10. SBACK (bit 3 of serial I/O0 wait control register: refer to Figure 16-7) reads or sets acknowledge data. 11. SIO0WSTT (bit 0 of serial I/O0 wait status judge register: refer to Figure 16-8) detects serial communication status. 16.2.2 Clock I/O control block and data I/O control block The clock I/O control block and data I/O control block control the communication mode (I2C bus or serial I/O mode), the number of pins used (2-wire or 3-wire mode), and transmission or reception operation of serial interface 0. The 2-wire or 3-wire mode, and I2C bus or serial I/O mode are selected by using the SIO0CH and SB flags. The SIO0MS flag selects the internal clock (master) or external clock (slave) operation, and the SIO0TX flag selects reception (RX) or transmission (TX). Each flag is allocated to the serial I/O0 mode selection register. Figure 16-3 shows the configuration of the serial I/O0 mode selection register. Table 16-2 shows the set status of each pin. As shown in this table, flags that set the input or output mode of each pin must also be manipulated in addition to the control flags of the serial interface, in order to set each pin. 220 Data Sheet U15722EJ1V1DS µPD17704A, 17705A, 17707A, 17708A, 17709A Figure 16-3. Configuration of Serial I/O0 Mode Selection Register Name Flag symbol Address Read/write 0FH R/W b3 b2 b1 b0 Serial I/O0 mode selection S S S S I B I I O O O 0 0 0 C M T H S X Sets serial I/O of SDA/P0A3 pin (2-wire) and SO0/P0A0 pin (3-wire) (selects reception “RX” or transmission “TX”) 2-wire (SDA/P0A3 pin) 3-wire (SO0/P0A0 pin) 0 Serial input (Hi-Z): RX General-purpose port 1 Serial output: Serial output: TX TX Sets direction of shift clock I2C bus mode Serial I/O mode 0 Slave operation (external clock input) External clock input 1 Master operation (internal clock output) Internal clock output After reset Sets mode of serial I/O0 0 0 Serial I/O0 not used 0 1 I2C bus mode 1 0 2-wire serial I/O mode 1 1 3-wire serial I/O mode Power-on reset 0 0 0 0 WDT&SP reset 0 0 0 0 CE reset 0 0 0 0 0 0 0 0 Clock stop Data Sheet U15722EJ1V1DS 221 µPD17704A, 17705A, 17707A, 17708A, 17709A Table 16-2. Status of Each Pin Set by Control Flag Each Flag S I O 0 C H S B 1 0 Communication Mode S I O 0 M S Clock Direction 2-wire serial I/O Pin S I O 0 T X 0 1 0 1 0 1 1 P0A3/SDA 0 Serial input 1 General-purpose output port 0 Serial output Output (transmission) Input (reception) 0 External clock 1 General-purpose output port 0 Internal clock General-purpose I/O port P0A0/SO0 General-purpose I/O port P0B3/SI0 General-purpose I/O port P0A3/SDA 0 Serial input 1 General-purpose output port 0 Serial output 1 P0A2/SCL 0 External clock 1 General-purpose output port 0 Internal clock 1 3-wire serial I/O Internal (master) P0A1/SCK0 General-purpose I/O port P0A0/SO0 General-purpose I/O port P0B3/SI0 General-purpose I/O port P0A3/SDA General-purpose I/O port P0A2/SCL General-purpose I/O port 0 P0A1/SCK0 External clock 1 General-purpose output port 0 Internal clock 1 0 1 General-purpose port P0A0/SO0 Output (transmission) 0 General-purpose input port 1 General-purpose output port 0 Serial output 1 P0B3/SI0 0 222 0 Not used as serial I/O0 Pin Setting Status P0A1/SCK0 Internal (master) 1 P 0 A B I O 0 1 Output (transmission) External (slave) External (slave) P 0 A B I O 0 1 0 0 P 0 A B I O 1 P 0 A B I O 3 P0A2/SCL 1 1 P 0 A B I O 2 Pin Name (internal) (master) I C bus 1 Input (reception) External (slave) 2 0 Serial I/O 0 Serial input 1 General-purpose output port P0A0 to P0A3, 0 0 0 0 0 General-purpose input port P0B3 1 1 1 1 General-purpose output port Data Sheet U15722EJ1V1DS 1 µPD17704A, 17705A, 17707A, 17708A, 17709A 16.2.3 Clock control block The clock control block controls generation of a clock when the internal clock is used (master operation) and the clock output timing. The frequency fSC of the internal clock is set by the SIO0CK1 and SIO0CK0 flags of the serial I/O0 clock selection register. Figure 16-4 shows the configuration of the serial I/O0 clock selection register. The shift clock output from the clock control block is valid only for the master operation (SIO0MS flag = 1). For the clock generation timing, refer to the description of each communication mode. Figure 16-4. Configuration of Serial I/O0 Clock Selection Register Name Flag symbol Address Read/write 0BH R/W b3 b 2 b 1 b 0 Serial I/O0 clock selection 0 S S S B I I M O O D 0 0 C C K K 1 0 Selects internal shift clock frequency fSC of serial interface 0 0 0 93.75 kHz 0 1 375.00 kHz 1 0 281.25 kHz 1 1 46.875 kHz Selects operation mode during slave transmission of I2C bus 0 Continues processing 1 Slave reception mode is set automatically if acknowledge signal is not received (fixed to 1 when serial I/O is selected) After reset Fixed to 0 0 0 0 WDT&SP reset 0 0 0 CE reset 0 0 0 0 0 0 Power-on reset Clock stop 0 Data Sheet U15722EJ1V1DS 223 µPD17704A, 17705A, 17707A, 17708A, 17709A 16.2.4 Clock counter and start/stop detection block The clock counter is a wrap-around counter that counts the rising edges of the clock. Because this counter directly reads the status of the clock pin, whether the clock is an internal clock or external clock cannot be identified. The contents of the clock counter can be detected via the SIO0SF8 and SIO0SF9 flags of the serial I/O0 status detection register, but cannot be directly read by program. The start/stop detection block detects the start and stop conditions when the I2C bus mode is used. The start and stop conditions are detected by the SBSTT and SBBSY flags of the serial I/O0 status detection register. Figure 18-5 shows the configuration of the serial I/O0 status detection register. For the operation and timing chart of the clock counter, refer to the description of each communication mode. 224 Data Sheet U15722EJ1V1DS µPD17704A, 17705A, 17707A, 17708A, 17709A Figure 16-5. Configuration of Serial I/O0 Status Detection Register Name Flag symbol Address Read/write 0DH R b3 b2 b1 b0 Serial I/O0 status detection S S S S I I B B O O S B 0 0 T S S S T Y F F 8 9 Detects start /stop condition of I2C bus mode I2C bus mode 0 Detects stop condition 1 Detects start condition Serial I/O mode Retains 0 Detects start condition and clock counter in I2C bus mode I2C bus mode 0 Serial I/O mode Detects rising of clock when value of Retains 0 clock counter is 9 1 Detects start condition Detects clock counter 2 Serial I/O mode I C bus mode 0 Detects rising of clock when value of Retains 0 clock counter is next to 9 1 Value of clock counter is 9 Detects clock counter After reset I2C bus mode 0 Detects rising of clock when value of clock counter is next to 8 1 Value of clock counter is 8 Power-on reset 0 0 0 0 WDT&SP reset 0 0 0 0 CE reset 0 0 0 0 0 0 0 0 Clock stop Serial I/O mode Data Sheet U15722EJ1V1DS 225 µPD17704A, 17705A, 17707A, 17708A, 17709A 16.2.5 Presettable shift register 0 Presettable shift register 0 is an 8-bit shift register that writes serial out data and reads serial in data. This register writes or reads data via data buffer. It outputs the contents of the most significant bit (MSB) from the serial data I/O pin in synchronization with the falling edge of the shift clock (during transmission operation), and reads data to the least significant bit (LSB) in synchronization with the rising edge of the serial clock. Figure 16-6 shows the configuration of presettable shift register 0. Figure 16-6. Configuration of Presettable Shift Register 0 Data buffer DBF3 DBF2 Don't care Don't care DBF1 DBF0 Transfer data GETNote 8 PUTNote Peripheral register Name b7 Presettable shift M S B register 0 b6 b5 b4 b3 Valid data b2 b1 b0 Symbol Peripheral register L S SIO0SFR B 03H Sets serial out data and reads serial in data D7 D6 D5 D4 D3 D2 D1 D0 D7 ← D6 ← D5 ← D4 ← D3 ← D2 ← D1 ← D0 Serial out Note Data may be destroyed if the PUT or GET instruction is executed during serial communication. For details, refer to 16.2.10 Cautions on setting and reading data. 226 Serial in Data Sheet U15722EJ1V1DS µPD17704A, 17705A, 17707A, 17708A, 17709A 16.2.6 Wait control block and acknowledge control block The wait control block keeps communication waiting or releases communication from the wait status. The condition under which communication is kept waiting is set by the SIO0WRQ0 and 1 flags (bits 0 and 1 of serial I/O0 wait control register). Serial communication is started when the SIO0NWT flag (bit 2 of serial I/O0 wait control register) is set (released from the wait status). The communication status can be detected by the SIO0NWT flag. When 0 is written to the SIO0NWT flag while communication is released from the wait status, the wait status is set. This is called forced wait status. The acknowledge control block outputs and detects an acknowledge signal in the I2C bus mode. An acknowledge signal is set and read by the SBACK flag (bit 3 of serial I/O0 wait control register). Figure 16-7 shows the configuration of the serial I/O0 wait control register. Figure 16-8 shows the configuration of the serial I/O0 wait status judge register. Data Sheet U15722EJ1V1DS 227 µPD17704A, 17705A, 17707A, 17708A, 17709A Figure 16-7. Configuration of Serial I/O0 Wait Control Register Name Flag symbol Address Read/write 0EH R/W b3 b2 b1 b0 Serial I/O0 wait control S S S S B I I I A O O O C 0 0 K N W W 0 W R T Q Q 1 R 0 Sets wait condition 2 0 0 No wait 0 1 Data wait 1 0 Serial I/O mode I C bus mode Name Does not wait Waits at falling edge of shift Wait at rising edge of shift clocks when value of clock clock when value of clock counter is 8 counter is 8 Acknowledge Waits at falling edge of shift Setting prohibited wait clock when value of clock counter is 9 1 1 Address wait Waits at falling edge of clock when value of clock counter is 8 after detection of start condition Sets wait and detects wait status When flag is written 0 Forced wait 1 Releases wait status When flag is read Waits under condition of SIO0WRQ0 and 1 flags Serial communication in progress (serial communication starts) Sets and detects acknowledge signal in I2C bus mode I2C bus mode 0 Reception Transmission (SIO0TX = 0) (SIO0TX = 1) Outputs 0 as Detects acknowledge acknowledge of slave (acknowledge is 0) 1 Outputs 1 as Detects acknowledge acknowledge of slave (acknowledge After reset is 1) Power-on reset 0 0 0 0 WDT&SP reset 0 0 0 0 CE reset 0 0 0 0 0 0 0 0 Clock stop 228 Data Sheet U15722EJ1V1DS Serial I/O mode Retains 0 µPD17704A, 17705A, 17707A, 17708A, 17709A Figure 16-8. Configuration of Serial I/O0 Wait Status Judge Register Name Flag symbol Address Read/write 0AH R b3 b2 b1 b0 Serial I/O0 wait status judge 0 0 0 S I O 0 W S T T Detects serial communication status 0 Waiting or requesting wait by slave 1 Serial communication in progress After reset Fixed to 0 Power-on reset 0 0 0 0 WDT&SP reset 0 CE reset 0 Clock stop 0 Caution If a slave outputs a wait request while the master is operating, 0 is detected on the SIO0WSTT flag. The SIO0NWT flag retains the status of 1. Data Sheet U15722EJ1V1DS 229 µPD17704A, 17705A, 17707A, 17708A, 17709A 16.2.7 Interrupt control block The interrupt control block sets a condition under which an interrupt request is issued by the serial I/O0 interrupt mode selection register. When the interrupt request issuance condition is satisfied, the IRQSIO0 flag is set. Change the interrupt request issuance condition while communication is in the wait status. If it is changed after communication has been released from the wait status, an interrupt request may be issued as soon as the condition has been changed. Figure 16-9 shows the configuration of the serial I/O0 interrupt mode selection register. Figure 16-9. Configuration of Serial I/O0 Interrupt Mode Selection Register Name Flag symbol Address Read/write 0CH R/W b3 b2 b1 b0 Serial I/O0 interrupt mode 0 0 selection S S I I O O 0 0 I I M M D D 1 0 Sets interrupt request issuance condition 2 I C bus mode 0 0 Rising edge of shift clock when value of clock counter reaches 7 0 1 Rising edge of shift clock when value of clock counter reaches 8 1 0 Rising edge of shift clock when value Serial I/O mode Rising edge of shift clock when value of clock counter reaches 7Note 1 Rising edge of shift clock when value of clock counter reaches 8Note 2 Interrupt request is not issued of clock counter reaches 7 after detection of start conditionNote 3 1 1 When stop condition is detectedNote 4 After reset Fixed to 0 0 0 WDT & SP reset 0 0 CE reset 0 0 0 0 Power-on reset Clock stop 0 0 Notes 1. An interrupt request is issued if this mode is set when the value of the clock counter is 7. 2. An interrupt request is issued if this mode is set when the value of the clock counter is 8. 3. An interrupt request is issued if this mode is set when the SBSTT flag = 1 and the value of the clock counter is 7. 4. An interrupt request is issued if this mode is set after the stop condition has been issued. 230 Data Sheet U15722EJ1V1DS µPD17704A, 17705A, 17707A, 17708A, 17709A 16.2.8 I2C bus mode (1) Outline of I2C bus mode In the I2C bus mode, communication is carried out with two pins, SCL and SDA. The features of the I2C bus mode are as follows. • Communication can be controlled under the start/stop conditions and by the acknowledge signal for the ninth clock. • Communication can be kept waiting by externally fixing the clock to low level with an N-ch open-drain pin. (2) Timing chart Figure 16-10 shows the timing chart. Figure 16-10. Timing Chart in I2C Bus Mode Stop condition Start condition 1 Shift clock Serial data 2 D7 Clock counter 0 3 D6 1 7 D5 2 8 D1 6 9 D0 7 ACK 8 9 0 SIO0NWT SIO0WSTT SIO0SF8 SIO0SF9 SBSTT SBBSY <1> <2> <3> <4> INT <9> <10> <5> <11> <6> <7> <8> <12> <1> Initial status (general-purpose input port) <2> Generates start condition by general-purpose I/O port <3> Sets transmission status of master <4> Releases wait <5> Wait timing when data wait status is set <6> Wait timing when acknowledge wait status is set <7> Sets general-purpose I/O port (releases serial operation mode) <8> Generates stop condition by general-purpose I/O port <9> Issues interrupt request when value of clock counter first reaches 7 after detection of start condition <10> Issues interrupt request when value of clock counter reaches 7 <11> Issues interrupt request when value of clock counter reaches 8 <12> Issues interrupt request after stop condition is detected Data Sheet U15722EJ1V1DS 231 µPD17704A, 17705A, 17707A, 17708A, 17709A (3) Operation of clock counter The value of the clock counter is incremented from the initial value 0 each time the rising of the clock pin has been detected. In the I2C bus mode, the value of the clock counter returns to 0 after it has reached 9, and the clock counter continues counting. In the serial I/O mode, the value of the clock counter returns to 0 after it has reached 8, and the clock counter continues counting. The clock counter is also reset in the following cases. • After reset (power-on reset, WDT&SP reset, CE reset) • On execution of clock stop instruction • On detection of start condition • If communication mode is changed from I2C bus mode to 2-wire or 3-wire serial I/O mode (4) Wait operation and cautions When the wait status is released, serial data is output (during transmission operation), and the wait status is kept released until a condition (wait condition) set by the SIO0WRQ0 and 1 flags is satisfied. When the wait condition is satisfied, the shift clock pin is made low, and the operations of the clock counter and presettable shift register 0 are stopped. If the forced wait status is specified while the wait status is released, the forced wait status is set at the falling of the clock next to the one at which 0 has been written to the SIO0NWT flag. Nothing is changed even if the wait status is released again after the wait status has been released once. If the forced wait status is set in the wait status, one pulse of the shift clock is output. In the I2C bus mode, do not set data wait conditions (SIOWRQ0 = 1, WIO0WRQ1 = 0) successively. This is because, if the data wait condition is set two times in succession and the wait status is released, the wait status is set as soon as the wait status has been released the second time. While the device is operating as the master and if the level of the shift clock output pin is forcibly made low externally while the pin outputs a high level (this is called a wait request by slave), the master is placed in the wait status. If this happens, the master resumes its operation when the wait request by the slave has been cleared. (5) Interrupt request issuance timing Interrupt request issuance timing can be selected by the SIO0IMD0 and 1 flags. (6) Acknowledge block and its operation The acknowledge block operates only in the I2C bus mode. This block is used to output an acknowledge signal during a reception operation, or to detect an acknowledge signal during a transmission operation. During reception, the content of the SBACK flag is output to the serial data pin at the falling edge of the shift clock when the value of the clock counter is 8. Once data has been set to the SBACK flag during reception, the value of the data is retained. During transmission, the status of the serial data pin is read to the SBACK flag at the rising edge of the shift clock when the value of the clock counter reaches 9. Figure 16-11 shows the acknowledge signal output and input operations. During reception, set the acknowledge signal (setting of the SBACK flag) as soon as the wait status has been released (by setting the SIO0NWT flag). 232 Data Sheet U15722EJ1V1DS µPD17704A, 17705A, 17707A, 17708A, 17709A This is because, even if only the SBACK flag is set, the SIO0NWT flag is also set because it is in the register at the same address. If the wait status is set at this time, the wait status is released and one pulse of the shift clock is output. Figure 16-11. Acknowledge Output and Input Operations (a) During reception Shift clock Data 7 8 Hi-Z (D1) Hi-Z (D0) Data input 9 SBACK output Hi-Z Acknowledge output At this time, wait status must be released at the same time. (b) During transmission Shift clock Data 7 D1 output 8 D0 output Data output Data Sheet U15722EJ1V1DS 9 ACK at reception side Acknowledge input 233 µPD17704A, 17705A, 17707A, 17708A, 17709A (7) Shift clock generation timing in I2C bus mode (a) On releasing wait status from initial status The initial status is the point where the master operation in the I2C bus mode is selected. In the wait status, a low level is output to the shift clock pin. Figure 16-12. Shift Clock Generation Timing in I2C Bus Mode (1/5) Shift clock 1:1 Wait period 1/fSC Initialization Wait released (b) During wait operation <1> Wait status under condition of SIO0WRQ0 and SIO0WRQ1 flags (normal operation) Figure 16-12. Shift Clock Generation Timing in I2C Bus Mode (2/5) Shift clock Wait released status Wait period Wait under condition of SIO0WRQ1 and SIO0WRQ0 1/fSC Wait released <2> If forced wait status is set in wait status Nothing is affected. 234 Data Sheet U15722EJ1V1DS µPD17704A, 17705A, 17707A, 17708A, 17709A <3> If forced wait status is set after wait status has been released In this case, the wait status is set at the next falling edge of the clock after the one at which the forced wait status was set. When the forced wait status was set, however, the clock counter and presettable shift register 0 stop operating. If the forced wait status is set while the clock pin is low, the clock counter and presettable shift register 0 operate by 1 pulse. Because the internal clock counter and shift register do not operate at this time, communication may not be performed normally even if the wait status is released again. Figure 16-12. Shift Clock Generation Timing in I2C Bus Mode (3/5) Shift clock Wait released status Wait pending Wait period 1/fSC Forced wait set by SIO0NWT Wait released Wait pending Wait period Shift clock Forced wait set by SIO0NWT 1/fSC Wait released <4> If wait status is released after wait status has been released Nothing is affected. <5> If wait request is made by slave after wait status has been released At this time, the clock is output 0 to 3.3 µs after the wait request by the slave has been cleared. The value of T in the figure below is as follows. fSC T 93.75 kHz 666 ns 375.00 kHz 222 ns 281.25 kHz 222 ns 46.875 kHz 666 ns Data Sheet U15722EJ1V1DS 235 µPD17704A, 17705A, 17707A, 17708A, 17709A Figure 16-12. Shift Clock Generation Timing in I2C Bus Mode (4/5) Shift clock Wait released status Wait request by slave 1/fSC 0 to 3.3 µ s Wait request by slave cleared Shift clock T T Wait request by slave 0 to 3.3 µ s Wait request by slave cleared (c) During slave (external clock) operation When the slave operation is specified the first time after application of supply voltage VDD, the SCK pin waits for input of an external clock and the output pin goes into a high-impedance state. If the SCL pin is externally made low at this time, it continues outputting a low level until the wait status is released next time. Figure 16-12. Shift Clock Generation Timing in I2C Bus Mode (5/5) Shift clock I/O port Wait period (originally, Hi-Z) Slave is set Wait released period Wait released (8) Start and stop conditions, and operations of SBSTT and SBBSY flags The start/stop condition recognition timing is shown in Figure 16-13. The SBSTT and SBBSY flags operate only in the I2C bus mode. By detecting these flags, communication status of the other stations can be detected. These flags operate regardless of whether the device operates as the master or slave, whether it performs reception or transmission, and whether communication is in the wait status or released from the wait status. These flags are 0 in the serial I/O mode. For the operations of the SBSTT and SBBSY flags, refer to Figure 16-10 Timing Chart in I2C Bus Mode. 236 Data Sheet U15722EJ1V1DS µPD17704A, 17705A, 17707A, 17708A, 17709A Figure 16-13. Start/Stop Condition Recognition Timing (a) Start condition recognition timing H Shift clock pin L H Serial data pin L H SBSTT SBBSY L H L About 1 µs Start condition is assumed if shift clock pin goes high about 1 µ s after serial data pin has gone low. Detects falling of serial data pin (b) Stop condition recognition timing H Shift clock pin L H Serial data pin L H SBSTT SBBSY L H L About 1 µs Stop condition is assumed if shift clock pin goes high about 1 µs after serial data pin has gone high. Detects rising of serial data pin Data Sheet U15722EJ1V1DS 237 µPD17704A, 17705A, 17707A, 17708A, 17709A 16.2.9 Serial I/O mode (1) Outline of serial I/O mode In the serial I/O mode, communication is carried out by using two pins, SCL and SDA, or three pins, SCK0, SO0, and SI0. (2) Timing chart Figure 16-14 shows the timing chart in the serial I/O mode. Figure 16-14. Timing Chart in Serial I/O Mode Shift clock 1 Serial data La Clock counter 2 D7 0 3 D6 1 7 D5 2 8 1 D1 6 D0 7 8 D7 0 1 SIO0NWT SIO0WSTT SIO0SF8 SIO0SF9 “0” SBSTT “0” SBBSY “0” <1> <2> <3> <4> INT<6> <1> Initial status (general-purpose input port) <2> Sets transmission status of master <3> Releases wait status <4> Wait timing when data wait status is set <5> Releases wait status again <6> Issues interrupt request when value of clock counter is 7 <7> Issues interrupt request when value of clock counter is 8 238 Data Sheet U15722EJ1V1DS <7> <5> µPD17704A, 17705A, 17707A, 17708A, 17709A (3) Operation of clock counter The value of the clock counter is incremented from the initial value 0 each time the rising of the clock pin has been detected. The value of the clock counter returns to 0 after it has reached 8, and the clock counter continues counting. The clock counter is also reset in the following cases. • After reset (power-on reset, WDT&SP reset, CE reset) • On execution of clock stop instruction • If data is written to serial I/O0 wait control register • If communication mode is changed from 2-wire or 3-wire serial I/O mode to I2C bus mode (4) Wait operation and Cautions When the wait status is released, serial data is output (during transmission operation) at the falling of the next clock, and the wait status is kept released until a condition (wait condition) set by the SIO0WRQ0 and 1 flags is satisfied. When the wait condition is satisfied, the shift clock pin is made high, and the operations of the clock counter and presettable shift register 0 are stopped. The value of presettable shift register 0 cannot be read correctly if it is read while the wait status is released and while the shift clock pin is high. Correct data cannot be written to presettable shift register 0 while the wait status is released and while the shift clock pin is low. If the forced wait status is specified while the wait status is released, the forced wait status is set as soon as 0 has been written to the SIO0NWT flag. The clock output wave is not affected even if the wait status is released again when it has been already released once. Note, however, that the clock counter is reset. (5) Interrupt request issuance timing Interrupt request issuance timing can be selected by the SIO0IMD0 and 1 flags. For details, refer to 16.2.7 Interrupt control block. (6) Acknowledge block and its operation The acknowledge block operates only in the I2 C bus mode. (7) Shift clock generation timing in serial I/O mode (a) On releasing wait status from initial status The initial status is the status when the internal clock operation in the serial I/O mode has been selected. In the wait status, a high level is output to the shift clock pin. Data Sheet U15722EJ1V1DS 239 µPD17704A, 17705A, 17707A, 17708A, 17709A Figure 16-15. Shift Clock Generation Timing in Serial I/O Mode (1/4) Shift clock 1:1 Wait period Initialization 1/fSC Wait released (b) When wait operation is performed <1> If wait status is set under condition specified by SIO0WRQ0 and SIO0WRQ1 flags (normal operation) Figure 16-15. Shift Clock Generation Timing in Serial I/O Mode (2/4) Shift clock Wait released status Wait period Wait by SIO0WRQ1 and SIO0WRQ0 1/fSC Wait released <2> If forced wait is set in wait status Figure 16-15. Shift Clock Generation Timing in Serial I/O Mode (3/4) Shift clock Wait period Wait period Forced wait set by SIO0NWT 240 Data Sheet U15722EJ1V1DS µPD17704A, 17705A, 17707A, 17708A, 17709A <3> If forced wait is set after wait status has been released Figure 16-15. Shift Clock Generation Timing in Serial I/O Mode (4/4) a Wait released status b 1/fSC Wait period Forced wait by SIO0NWT Wait released a + b = 1/2fSC a Wait released status b 1/fSC Wait period Forced wait by SIO0NWT Wait released a + b = 1/2fSC <4> If wait status is released when it has been already released once The clock output waveform is not affected. However, note that the clock counter is reset. (8) Operations of SBSTT and SBBSY flags The SBSTT and SBBSY flags operate only in the I2C bus mode. These flags remain 0 in the serial I/O mode. Data Sheet U15722EJ1V1DS 241 µPD17704A, 17705A, 17707A, 17708A, 17709A 16.2.10 Cautions on setting and reading data Data is set to presettable shift register 0 by using the “PUT SIO0SFR, DBF” instruction. To read the data of this register, the “GET DBF, SIO0SFR” instruction is used. Set or read data of the register in the wait status. If the wait status is released, data may not be correctly set or read depending on the status of the shift clock pin. The following table shows the data setting and reading timing, and points to be noted. Table 16-3. Reading and Writing Data of Presettable Shift Register 0 and Cautions Status on Execution Status of Shift of PUT/GET Clock Pin I2C Bus Mode Serial I/O Mode Wait Read (GET) • I2C bus mode: Normal read Normal read status Write (PUT) Fixed to low Normal write Normal write • Serial I/O mode: Fixed to high Outputs contents of MSB when wait Outputs contents of MSB when wait status is released next time status is released next time and shift (during transmission) clock pin goes low (during transmission) H L 1 Data 0 Clock Clock MSB PUT SIO0SFR, DBF Wait released Wait Read (GET) High level released status Low level Write (PUT) High level H L 1 Data 0 MSB PUT SIO0SFR, DBF Wait released Cannot be read normally Cannot be read normally Contents of SIO0SFR are lost Contents of SIO0SFR are lost Normal read Normal read Normal write Normal write Outputs contents of MSB at falling Outputs contents of MSB when PUT of clock next to one at which PUT instruction is executed. instruction has been executed. Clock counter is not reset Clock counter is not reset H L 1 Data 0 Clock MSB PUT SIO0SFR, DBF Low level 242 H L 1 Data 0 Clock MSB PUT SIO0SFR, DBF Cannot be read normally Cannot be read normally Contents of SIO0SFR are lost Contents of SIO0SFR are lost Data Sheet U15722EJ1V1DS µPD17704A, 17705A, 17707A, 17708A, 17709A 16.2.11 Operation of serial interface 0 Tables 16-4 through 16-6 outline the operations in each communication mode. Table 16-4. Outline of Operation in I2C Bus Mode I2C Bus Mode Operation Mode Slave Operation (SIO0MS = 0) Item Status of SDA/P0A3 each pin Transmission Reception Transmission (SIO0TX = 0) (SIO0TX = 1) (SIO0TX = 0) (SIO0TX = 1) When P0ABIO3 = 0 Outputs contents of When P0ABIO3 = 0 Outputs contents of Floating SIO0SFR at falling of Floating SIO0SFR at falling of Waits for input of external clock Waits for input of internal clock external data regardless of external data regardless of P0ABIO3 When P0ABIO3 = 1 SCL/P0A2 Master Operation (SIO0MS = 1) Reception P0ABIO3 When P0ABIO3 = 1 General-purpose General-purpose output port output port Outputs content of Outputs content of output latch output latch When P0ABIO2 = 0 Outputs internal clock regardless of P0ABIO2 Floating Waits for input of external data When P0ABIO2 = 1 General-purpose output port Outputs content of output latch Clock counter Operation of Incremented at rising of SCL pin Output Not output Shifted from MSB Not output Shifted from MSB presettable each time SCL falls each time SCL falls shift register 0 and is output and is output Wait operation ––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––– Input Shifted from LSB each time SCL rise and is input In wait SCL and SDA pins status are floated SCL pin is floated SCL pin outputs low SCL pin outputs low and SDA pin retains level and SDA pin is level and SDA pin its status floated retains its status ––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––– Acknowledge Wait SCL pin is floated SCL pin is floated SCL pin outputs SCL pin outputs released and waits for input of and waits for input of internal clock. internal clock. external clock. external clock. SDA pin is floated SDA pin outputs data SDA pin is floated and SDA pin outputs data and waits for external each time SCL pin falls waits for external data each time SCL pin falls data ACK output at fall ACK input at rise ACK output at fall ACK input at rise of 8th clock of 9th clock of 8th clock of 9th clock Data Sheet U15722EJ1V1DS 243 µPD17704A, 17705A, 17707A, 17708A, 17709A Table 16-5. Outline of Operation in 2-Wire Serial I/O Mode Operation Mode 2-Wire Serial I/O Mode Slave Operation (SIO0MS = 0) Reception Item Status of Transmission (SIO0TX = 0) SDA/P0A3 each pin SCL/P0A2 Master Operation (SIO0MS = 1) Reception (SIO0TX = 1) When P0ABIO3 = 0 Outputs contents of (SIO0TX = 0) When P0ABIO3 = 0 Transmission (SIO0TX = 1) Outputs contents of Floating SIO0SFR at falling of Floating SIO0SFR at falling of Waits for input of external clock Waits for input of internal clock external data regardless of P0ABIO3 external data regardless of P0ABIO3 When P0ABIO3 = 1 When P0ABIO3 = 1 General-purpose General-purpose output port output port Outputs contents Outputs contents of of output latch output latch When P0ABIO2 = 0 Outputs internal clock regardless of P0ABIO2 Floating Waits for input of external data When P0ABIO2 = 1 General-purpose output port Outputs contents of output latch Clock counter Operation of Incremented at rising of SCL pin Output Not output Shifted from MSB presettable shift register 0 Wait operation Not output Shifted from MSB each time SCL falls each time SCL falls and is output and is output ––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––– Input Shifted from LSB each time SCL rise and is input In wait SCL and SDA pins SCL pin is floated SCL pin outputs high SCL pin outputs high status are floated and SDA pin retains level and SDA pin is level and SDA pin its status floated retains its status ––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––– Wait SCL pin is floated SCL pin is floated SCL pin outputs SCL pin outputs released and waits for input of and waits for input internal clock. internal clock. external clock. of external clock. SDA pin is floated and SDA pin outputs data SDA pin is floated and SDA pin outputs data waits for external data 244 each time SCL pin falls Data Sheet U15722EJ1V1DS waits for external data each time SCL pin falls µPD17704A, 17705A, 17707A, 17708A, 17709A Table 16-6. Outline of Operation in 3-Wire Serial I/O Mode Operation Mode 3-Wire Serial I/O Mode Slave Operation (SIO0MS = 0) Item Status of SCK0/P0A1 each pin Reception Transmission (SIO0TX = 0) (SIO0TX = 1) When P0ABIO1 = 0 Master Operation (SIO0MS = 1) Reception Transmission (SIO0TX = 0) (SIO0TX = 1) Outputs internal clock regardless of P0ABIO1 Floating Waits for input of external data When P0ABIO1 = 1 General-purpose output port Outputs contents of output latch SO0/P0A0 When P0ABIO0 = 0 Outputs contents of When P0ABIO0 = 0 Outputs contents of General-purpose SIO0SFR at falling General-purpose SIO0SFR at falling input port edge of external clock input port edge of internal Floating regardless of Floating clock regardless of When P0ABIO0 = 1 SI0/P0B3 P0ABIO0 When P0ABIO0 = 1 General-purpose General-purpose output port output port Outputs contents Outputs contents of output latch of output latch P0ABIO0 When P0BBIO3 = 0 Floating Waits for input of external data When P0BBIO3 = 1 General-purpose output port Outputs contents of output latch Clock counter Operation of Incremented at rising of SCK0 pin Output Not output Shifted from MSB Not output Shifted from MSB presettable each time SCK0 falls each time SCK0 falls shift register 0 and is output and is output Wait operation ––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––– Input Shifted from LSB each time SCK0 falls and is input In wait SCK0 pin is floated. status SO0 pin as general- SC0 pin retains its level level. purpose port. status. SO0 pin as general- SO0 pin retains its SI0 pin is floated SI0 pin is floated purpose port. status. SI0 pin is floated SI0 pin is floated SCK0 pin is floated. SCK0 pin outputs high SCK0 pin outputs high ––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––– Wait SCK0 pin is floated SCK0 pin is floated SCK0 pin is floated SCK0 pin is floated released and waits for input of and waits for input of and waits for input of and waits for input of external clock. external clock. external clock. external clock. SO0 pin as general- SO0 pin outputs data. SO0 pin as general- SO0 pin outputs data. purpose port. SI0 pin is floated and purpose port. SI0 pin is floated and SI0 pin is floated and waits for input of SI0 pin is floated and waits for input of waits for input of external data waits for input of external data external data external data Data Sheet U15722EJ1V1DS 245 µPD17704A, 17705A, 17707A, 17708A, 17709A 16.2.12 Status of serial interface 0 after reset (1) After power-on reset Each pin is set to the general-purpose input port mode. The contents of presettable shift register 0 are undefined. (2) After WDT&SP reset Each pin is set to the general-purpose input port mode. The contents of presettable shift register 0 are undefined. (3) On execution of clock stop instruction Each pin is set to the general-purpose I/O port mode and remains in the previous input or output mode. The contents of presettable shift register 0 are undefined. (4) After CE reset Each pin is set to the general-purpose I/O port mode and remains in the previous input or output mode. The contents of presettable shift register 0 are undefined. (5) In halt status Each pin retains its set status. Output of the internal clock is stopped in the status where the HALT instruction is executed. When an external clock is used, the operation continues even if the HALT instruction is executed. Presettable shift register 0 retains the previous value. 246 Data Sheet U15722EJ1V1DS µPD17704A, 17705A, 17707A, 17708A, 17709A 16.3 Serial Interface 1 16.3.1 Outline of serial interface 1 Figure 16-16 outlines serial interface 1. Serial interface 1 is used in the 3-wire serial I/O mode. Figure 16-16. Outline of Serial Interface 1 SIO1CK0 and 1 flags Wait signal Clock I/O control block SCK1/P0B2 SIO1TS flag 4.5 MHz Clock control block Wait control block Clock counter Count value: 8 IRQSIO1 flag SIO1HIZ flag SO1/P0B1 OUT Presettable shift register 1 (SIO1SFR) IN Data I/O control block SI1/P0B0 Remarks 1. SIO1CK1 and SIO1CK0 (bits 1 and 0 of serial I/O1 mode selection register: refer to Figure 16-17) select a shift clock. 2. SIO1TS (bit 3 of serial I/O1 mode selection register: refer to Figure 16-17) starts or stops communication operation. 3. SIO1HIZ (bit 2 of serial I/O1 mode selection register: refer to Figure 16-17) selects the function of the SO1/P0B1 pin. 16.3.2 Clock I/O control block and data I/O control block The clock I/O control block and data I/O control block control the transmission or reception operation of serial interface 1 and select a shift clock. The internal clock (master) or external clock (slave) operation is selected by the SIO1CK0 and 1 flags. The SIO1HIZ flag selects whether the SO1 pin is used as a serial data output pin. The flags that control the clock I/O control block and data I/O control block are allocated to the serial I/O1 mode selection register. Figure 16-17 shows the configuration and function of the serial I/O1 mode selection register. Table 16-7 shows the set status of each pin. As shown in this table, flags that set the input or output mode of each pin must also be manipulated in addition to the control flags of the serial interface, in order to set each pin . Data Sheet U15722EJ1V1DS 247 µPD17704A, 17705A, 17707A, 17708A, 17709A Figure 16-17. Configuration of Serial I/O1 Mode Selection Register Name Flag symbol Address Read/write 1DH R/W b3 b2 b1 b0 Serial I/O1 mode selection S S S S I I I I O O O O 1 1 1 1 T H C C S I K K Z 1 0 Selects shift clock of serial interface 1 0 0 External clock input 0 1 187.50 kHz 1 0 375.00 kHz 1 1 46.875 kHz Selects function of P0B1/SO1 pin 0 General-purpose I/O port 1 Serial data output pin After reset Start or stops operation of serial communication 0 Stops (wait status) 1 Starts Power-on reset 0 0 0 0 WDT&SP reset 0 0 0 0 CE reset 0 0 0 0 0 0 0 0 Clock stop 16.3.3 Clock counter The clock counter is a wrap-around counter that counts the rising edges of the clock. Because this counter directly reads the status of the clock pin, whether the clock is an internal clock or external clock cannot be identified. The contents of the clock counter cannot be directly read by software. 248 Data Sheet U15722EJ1V1DS µPD17704A, 17705A, 17707A, 17708A, 17709A Table 16-7. Status of Each Pin Set by Control Flag Flag Communication Mode S I O 1 H I Z Setting of SIO1 Pin 3-wire Pin S I O 1 C K 1 S I O 1 C K 0 Clock Setting Pin Name 0 0 External clock SCK1/P0B2 P 0 B B I O 2 P 0 B B I O 1 P 0 B B I O 0 0 Set Status of Pin Wait: General-purpose input port serial I/O Wait released: External clock input 0 1 Internal clock 1 Wait: General-purpose output port Wait released: General-purpose output port 1 0 0 General-purpose input port 1 1 1 Wait: High-level output Wait released: Internal clock output 0 1 General- SO1/P0B1 0 General-purpose input port purpose port 1 General-purpose output port Serial output 0 General-purpose input port 1 Serial data output SI1/P0B0 Data Sheet U15722EJ1V1DS 0 Serial data input 1 General-purpose output port 249 µPD17704A, 17705A, 17707A, 17708A, 17709A 16.3.4 Presettable shift register 1 Presettable shift register 1 is an 8-bit shift register that writes serial out data and reads serial in data. This register writes or reads data via a data buffer. It outputs the contents of the most significant bit (MSB) from the serial data I/O pin in synchronization with the falling edge of the shift clock (during transmission operation), and reads data to the least significant bit (LSB) in synchronization with the rising edge of the serial clock. Figure 16-18 shows the configuration of presettable shift register 1. Figure 16-18. Configuration of Presettable Shift Register 1 Data buffer DBF3 DBF2 Don't care Don't care DBF1 DBF0 Transfer data GETNote 8 PUTNote Peripheral register Name b7 b6 b5 b4 b3 b2 b1 b0 Symbol Presettable M L SIO1SFR shift register 1 S S B Valid data Peripheral register 04H B Sets serial out data and reads serial in data D7 D6 D5 D4 D3 D2 D1 D0 D7 ← D6 ← D5 ← D4 ← D3 ← D2 ← D1 ← D0 Serial out Note Serial in Data may be destroyed if the PUT or GET instruction is executed during serial communication. For details, refer to 16.3.7 Cautions on setting and reading data. 16.3.5 Wait control block The wait control block keeps communication waiting or releases communication from the wait status. Serial communication is started when communication is released from the wait status by using the SIO1TS flag of the serial I/O1 mode selection register. Communication is set in the wait status eight clocks after the wait status has been released and communication has been started. The communication status can be detected by using the SIO1TS flag. To do so, detect the status of the SIO1TS flag after setting this flag to 1. If 0 is written to the SIO1TS flag when communication is released from the wait status, the wait status is set. This wait status is called forced wait status. For the configuration of the serial I/O1 mode selection register, refer to Figure 16-17. 250 Data Sheet U15722EJ1V1DS µPD17704A, 17705A, 17707A, 17708A, 17709A 16.3.6 Operation of serial interface 1 (1) Timing chart Figure 16-19 shows the timing chart. Figure 16-19. Timing Chart of Serial Interface 1 1 Shift clock Serial data La Clock counter 0 2 D7 3 D6 1 7 D5 2 8 D1 6 1 D0 7 8 D7 0 1 SIO1TS <1> <2> <3> INT <5> <4> <1> Initial status (general-purpose input port) <2> Sets transmission status of master/releases wait status <3> Wait timing <4> Releases wait status again <5> Interrupt issuance timing (2) Operation of clock counter The value of the clock counter is incremented from the initial value 0 each time the rising of the clock pin has been detected. The value of the clock counter returns to 0 after it has reached 8, and the clock counter continues counting. The clock counter is also reset in the following cases. • After reset (power-on reset, WDT&SP reset, CE reset) • On execution of clock stop instruction • If 0 is written to SIO1TS flag (3) Wait operation and cautions When the wait status is released, serial data is output (during transmission operation) at the falling of the next clock, and the wait status is released at the eighth clock. After eight clocks have been output, the shift clock pin is made high, and the operations of the clock counter and presettable shift register 1 are stopped. The value of presettable shift register 1 cannot be read correctly if it is read while the wait status is released and while the shift clock pin is high. Correct data cannot be written to presettable shift register 1 while the wait status is released and while the shift clock pin is low. If the forced wait status is specified while the wait status is released, the forced wait status is set as soon as 0 has been written to the SIO1TS flag, and the clock counter is reset. Data Sheet U15722EJ1V1DS 251 µPD17704A, 17705A, 17707A, 17708A, 17709A (4) Interrupt request issuance timing An interrupt request is issued at the rising of the shift clock when the value of the clock counter is 8. (5) Shift clock generation timing (a) On releasing wait status from initial status The initial status is the status when the P0B2/SCK1 pin is set in the output mode and the internal clock operation is selected. In the wait status, a high level is output to the shift clock pin. The wait status can be released and a clock can be selected at the same time. Figure 16-20. Shift Clock Generation Timing of Serial Interface 1 (1/4) Shift clock 1:1 Wait status Initialization 1/fSC Wait released (b) When wait operation is performed (normal operation) <1> If wait status is set at the 8th clock (normal operation) Figure 16-20. Shift Clock Generation Timing of Serial Interface 1 (2/4) Shift clock Wait release period Wait period Wait 252 1/fSC Wait released Data Sheet U15722EJ1V1DS µPD17704A, 17705A, 17707A, 17708A, 17709A <2> If forced wait is set in wait status Figure 16-20. Shift Clock Generation Timing of Serial Interface 1 (3/4) Shif clock Wait period Wait period Forced wait set by SIO1TS <3> If forced wait is set after wait status has been released Note that the clock counter is reset. Figure 16-20. Shift Clock Generation Timing of Serial Interface 1 (4/4) b a Shift clock Wait released status Wait status Forced wait by SIO1TS 1/fSC Wait released a + b = 1/2fSC b a Shift clock Wait released status Wait status Forced wait by SIO1TS 1/fSC Wait released a + b = 1/2fSC <4> If wait status is released when it has been already released The clock output waveform is not affected. The clock counter is not reset. Data Sheet U15722EJ1V1DS 253 µPD17704A, 17705A, 17707A, 17708A, 17709A 16.3.7 Cautions on setting and reading data Data is set to presettable shift register 1 by using the “PUT SIO1SFR, DBF” instruction. To read the data of this register, the “GET DBF, SIO1SFR” instruction is used. Set or read data of the register in the wait status. If the wait status is released, data may not be correctly set or read depending on the status of the shift clock pin. The following table shows the data setting and reading timing, and points to be noted. Table 16-8. Reading and Writing Data of Presettable Shift Register and Cautions Status on Execution Status of Shift of PUT/GET Clock Pin Wait Read (GET) status Write (PUT) • External clock: Floating • Internal clock: Output latch Serial I/O Mode Normal write Normal write Outputs contents of MSB when wait status is released next time and shift clock pin falls (during transmission) (always high) H Clock L 1 Data MSB 0 PUT SIO1SFR, DBF Wait Read (GET) High level released Wait released Cannot be read normally Contents of SIO1SFR are lost status Write (PUT) Low level Normal write High level Normal write Outputs contents of MSB at which PUT instruction has been executed. Clock counter is not reset H Clock L 1 Data 0 MSB PUT SIO1SFR, DBF Low level Cannot be read normally Contents of SIO1SFR are lost 254 Data Sheet U15722EJ1V1DS µPD17704A, 17705A, 17707A, 17708A, 17709A 16.3.8 Operation mode and operation of each part Table 16-9 outlines the operations of the 3-wire serial I/O mode. Table 16-9. Outline of Operation of Serial Interface 1 Operation Mode Item Status of P0B2/SCK1 each pin 3-Wire Serial I/O Mode Slave Operation Master Operation (SIO1CK1 = SIO1CK0 = 0) (SIO1CK1 = SIO1CK0 = Other Than 0) During wait Wait released During wait Wait released (SIO1TS = 0) (SIO1TS = 1) (SIO1TS = 0) (SIO1TS = 1) ––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––– When P0BBIO2 = 0 When P0BBIO2 = 0 Floating Floating General-purpose Waits for input of General-purpose General-purpose input port external clock input port input port When P0BBIO2 = 1 When P0BBIO2 = 1 When P0BBIO2 = 1 General-purpose General-purpose General-purpose output port output port output port Outputs contents of Outputs contents Outputs high level When P0BBIO2 = 1 Outputs internal clock of output latch SIO1HIZ = 0 SIO1HIZ = 1 SIO1HIZ = 0 SIO1HIZ = 1 When P0BBIO1 = 0 When P0BBIO1 = 0 When P0BBIO1 = 0 When P0BBIO1 = 0 ––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––– Floating Floating Floating Floating General-purpose General-purpose General-purpose General-purpose input port input port input port input port When P0BBIO1 = 1 General-purpose P0B0/SI1 When P0BBIO2 = 0 Floating output latch P0B1/SO1 When P0BBIO2 = 0 Floating When P0BBIO1 = 1 Outputs data When P0BBIO1 = 1 General-purpose output port output port Outputs contents of Outputs contents of output latch output latch When P0BBIO1 = 1 Outputs data When P0BBIO0 = 0 Floating Waits for input of serial data When P0BBIO0 = 1 General-purpose output port Outputs contents of output latch Clock counter Operation of Incremented at rising of SCK1 pin Output presettable SIO1HIZ = 0 Not output shift register 1 SIO1HIZ = 1 Shifted from MSB each time SCK1 pin falls and is output ––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––– Input Shifted from LSB each time SCK1 pin rises and is input. SI1 pin outputs contents of output latch when P0BBIO0 = 1 Data Sheet U15722EJ1V1DS 255 µPD17704A, 17705A, 17707A, 17708A, 17709A 16.3.9 Status of serial interface 1 after reset (1) After power-on reset Each pin is set to the general-purpose input port mode. The contents of presettable shift register 1 are undefined. (2) After WDT&SP reset Each pin is set to the general-purpose input port mode. The contents of presettable shift register 1 are undefined. (3) On execution of clock stop instruction Each pin is set to the general-purpose I/O port mode and remains in the previous input or output mode. The contents of presettable shift register 1 are undefined. (4) After CE reset Each pin is set to the general-purpose I/O port mode and remains in the previous input or output mode. The contents of presettable shift register 1 are undefined. (5) In halt status Each pin retains its set status. Output of the internal clock is stopped in the status where the HALT instruction is executed. When an external clock is used, the operation continues even if the HALT instruction is executed. Presettable shift register 1 retains the previous contents. 256 Data Sheet U15722EJ1V1DS µPD17704A, 17705A, 17707A, 17708A, 17709A 17. PLL FREQUENCY SYNTHESIZER The PLL (Phase Locked Loop) frequency synthesizer is used to lock a frequency in the MF (Medium Frequency), HF (High Frequency), and VHF (Very High Frequency) band to a constant frequency by means of phase differential comparison. 17.1 Outline of PLL Frequency Synthesizer Figure 17-1 outlines the PLL frequency synthesizer. A PLL frequency synthesizer can be configured by connecting an external lowpass filter (LPF) and voltage controlled oscillator (VCO). The PLL frequency synthesizer divides a signal input from the VCOH or VCOL pin by using a programmable divider and outputs a phase difference between this signal and a reference frequency from the EO0 and EO1 pins. The PLL frequency synthesizer operates only while the CE pin is high. It is disabled when the CE pin is low. For details of the disabled status of the PLL frequency synthesizer, refer to 17.5 PLL Disabled Status. Figure 17-1. Outline of PLL Frequency Synthesizer DBF VCOH VCOL Input selection block 4.5 MHz PLLSCNF flag Programmable divider (PD) Reference frequency generator Phase comparator (φ -DET) Charge pump EO1 EO0 Note Lowpass filter (LPF) Unlock FF Note Voltage controlled oscillator (VCO) PLLMD1 flag PLLMD0 flag Note PLLRFCK3 flag PLLRFCK2 flag PLLRFCK1 flag PLLRFCK0 flag PLLUL flag External circuit Remarks 1. PLLMD1 and PLLMD0 (bits 1 and 0 of PLL mode selection register: refer to Figure 17-3) selects a division mode of the PLL frequency synthesizer. 2. PLLSCNF (bit 3 of PLL mode selection register: refer to Figure 17-3) selects the least significant bit of the swallow counter. 3. PLLRFCK3 to PLLRFCK0 (bits 3 to 0 of PLL reference frequency selection register: refer to Figure 17-6) selects a reference frequency fr of the PLL frequency synthesizer. 4. PLLUL (bit 0 of PLL unlock FF register: refer to Figure 17-9) detects the PLL unlock FF status. Data Sheet U15722EJ1V1DS 257 µPD17704A, 17705A, 17707A, 17708A, 17709A 17.2 Input Selection Block and Programmable Divider 17.2.1 Configuration and function of input selection block and programmable divider Figure 17-2 shows the configuration of the input selection block and programmable divider. The input selection block selects an input pin and division mode of the PLL frequency synthesizer. The VCOH or VCOL pin can be selected as the input pin. The voltage on the selected pin is at the intermediate level (approx. 1/2 VDD). The pin not selected is internally pulled down. Because these pins are connected to an internal AC amplifier, cut the DC component of the input signal by connecting a capacitor in series to the pin. Direct division mode and pulse swallow mode can be selected as division modes. The programmable divider divides the frequency of the input signal according to the value set to the swallow counter and programmable counter. The pin and division mode to be used are selected by the PLL mode selection register. Figure 17-3 shows the configuration of the PLL mode selection register. The value of the programmable divider is set by using the PLL data register via a data buffer. Figure 17-2. Configuration of Input Selection Block and Programmable Divider DBF PLLMD1 flag PLLMD0 flag 16 PLL data register 12 bits 4 bits R F Note 4 VCOH 2-modulus prescaler 1/32, 1/33 12 Swallow counter 5 bits Programmable counter 12 bits VCOL PLL disable signal Note 258 PLLSCNF flag Data Sheet U15722EJ1V1DS fN To φ -DET µPD17704A, 17705A, 17707A, 17708A, 17709A Figure 17-3. Configuration of PLL Mode Selection Register Name Flag symbol Address Read/write 10H R/W b3 b2 b1 b0 PLL mode selection P 0 P P L L L L L L S M M C D D N 1 0 F Selects division mode of PLL frequency synthesizer 0 0 Disables VCOL and VCOH pins 0 1 Direct division (VCOL pin, MF mode) 1 0 Pulse swallow (VCOH pin, VHF mode) 1 1 Pulse swallow (VCOL pin, HF mode) Fixed to 0 After reset Selects least significant bit of swallow counter 0 Clears least significant bit to 0 1 Sets least significant bit to 1 Power-on reset U WDT&SP reset CE reset Clock stop U: Undefined 0 0 U 0 0 R 0 0 R 0 0 0 R: Retained 17.2.2 Outline of each division mode (1) Direct division mode (MF) In this mode, the VCOL pin is used. The VCOH pin is pulled down. In this mode, only the programmable counter is used for frequency division. (2) Pulse swallow mode (HF) In this mode, the VCOL pin is used. The VCOH pin is pulled down. In this mode, the swallow counter and programmable counter are used for frequency division. Data Sheet U15722EJ1V1DS 259 µPD17704A, 17705A, 17707A, 17708A, 17709A (3) Pulse swallow mode (VHF) In this mode, the VCOH pin is used. The VCOL pin is pulled down. In this mode, the swallow counter and programmable counter are used for frequency division. (4) VCOL and VCOH pin disabled In this mode, only the VCOL and VCOH pins are internally pulled down, but the other blocks operate. 17.2.3 Programmable divider and PLL data register The programmable divider consists of a 5-bit swallow counter and a 12-bit programmable counter. Each counter is a 17-bit binary down counter. The programmable counter is allocated to the higher 12 bits of the PLL data register, and the swallow counter is allocated to the lower 4 bits. Data are set to these counters via data buffer. The least significant bit of the swallow counter sets data to the PLLSCNF flag of the control register. The value by which the input signal frequency is to be divided is called “N value”. For how to set a division value (N value) in each division mode, refer to 17.6 Using PLL Frequency Synthesizer. (1) PLL data register and data buffer Figure 17-4 shows the relationships between the PLL data register and data buffer. In the direct division mode, the higher 12 bits of the PLL data register are valid, and all 17 bits of the register are valid in the pulse swallow mode. In the direct division mode, all 12 bits are used as a programmable counter. In the pulse swallow mode, the higher 12 bits are used as a programmable counter, and the lower 5 bits are used as a swallow counter. (2) Relationship between division value N of programmable divider and divided output frequency The relationship between the value “N” set to the PLL data register and the signal frequency “fN” divided and output by the programmable divider is as shown below. For details, refer to 17.6 Using PLL Frequency Synthesizer. (a) Direct division mode (MF) fIN = fIN N N: 12 bits (b) Pulse swallow mode (HF, VHF) fIN = 260 fIN N N: 17 bits Data Sheet U15722EJ1V1DS µPD17704A, 17705A, 17707A, 17708A, 17709A Figure 17-4. Setting Division Value (N Value) of PLL Frequency Synthesizer Data buffer DBF3 DBF1 DBF2 DBF0 Transfer data GET 16 PUT Peripheral register Name PLL data register Register file b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 Symbol Peripheral address 42H PLLR Name b3 b2 b1 b0 Address PLL mode selection P 0 P P L L L L L L S M M C D D N 1 0 F 10H Valid data Sets least significant bit of division value Note Sets higher 16 bits of division value b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 b3 PLL b16 b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 N value data (17 bits) Sets division value (N value) of PLL frequency synthesizer Direct division mode 0 Don't care Setting prohibited 15 (00FH) Don't care 16 (010H) Don't care x Don't care 212– 1 (FFFH) Pulse swallow mode Division value N: N = x Don't care 0 Setting prohibited 1023 (3FFH) 1024 (400H) x Division value N: N = x 217– 1 (1FFFFH) Note The value of PLLSCNF flag is transferred when a write (PUT) instruction is executed to the PLL data register (PLLR). Therefore, data must be set to the PLLSCNF flag before executing the write instruction to the PLL data register. Data Sheet U15722EJ1V1DS 261 µPD17704A, 17705A, 17707A, 17708A, 17709A 17.3 Reference Frequency Generator Figure 17-5 shows the configuration of the reference frequency generator. The reference frequency generator generates the reference frequency “fr” of the PLL frequency synthesizer by dividing the 4.5 MHz output of a crystal oscillator. Thirteen frequencies can be selected as reference frequency fr: 1, 1.25, 2.5, 3, 5, 6.25, 9, 10, 12.5, 18, 20, 25, and 50 kHz. The reference frequency fr is selected by the PLL reference frequency selection register. Figure 17-6 shows the configuration and function of the PLL reference frequency selection register. Figure 17-5. Configuration of Reference Frequency Generator PLLRFCK3 flag PLLRFCK2 flag PLLRFCK1 flag PLLRFCK0 flag MUX 1 kHz 1.25 kHz 2.5 kHz 4.5 MHz To φ -DET Divider 25 kHz 50 kHz OFF 262 Data Sheet U15722EJ1V1DS PLL disable signal µPD17704A, 17705A, 17707A, 17708A, 17709A Figure 17-6. Configuration of PLL Reference Frequency Selection Register Name Flag symbol Address Read/write 11H R/W b3 b 2 b 1 b 0 PLL reference frequency selection P P P P L L L L L L L L R R R R F F F F C C C C K K K K 3 2 1 0 After reset Sets reference frequency fr of PLL frequency synthesizer 0 0 0 0 1.25 kHz 0 0 0 1 2.5 kHz 0 0 1 0 5 kHz 0 0 1 1 10 kHz 0 1 0 0 6.25 kHz 0 1 0 1 12.5 kHz 0 1 1 0 25 kHz 0 1 1 1 50 kHz 1 0 0 0 3 kHz 1 0 0 1 9 kHz 1 0 1 0 18 kHz 1 0 1 1 Setting prohibited 1 1 0 0 1 kHz 1 1 0 1 20 kHz 1 1 1 0 Setting prohibited 1 1 1 1 PLL disabled Power-on reset 1 1 1 1 WDT&SP reset 1 1 1 1 CE reset 1 1 1 1 1 1 1 1 Clock stop Remark When the PLL frequency synthesizer is disabled by the PLL reference frequency selection register, the VCOH and VCOL pins are internally pulled down. The EO1 and EO0 pins are floated. Data Sheet U15722EJ1V1DS 263 µPD17704A, 17705A, 17707A, 17708A, 17709A 17.4 Phase Comparator (φ-DET), Charge Pump, and Unlock FF 17.4.1 Configuration of phase comparator, charge pump, and unlock FF Figure 17-7 shows the configuration of the phase comparator, charge pump, and unlock FF. The phase comparator compares the phase of the divided frequency “fN” output by the programmable divider with the phase of the reference frequency “fr” output by the reference frequency generator, and outputs an up (UP) or down (DW) request signal. The charge pump outputs the output of the phase comparator from an error out pin (EO1 and EO0 pins). The unlock FF detects the unlock status of the PLL frequency synthesizer. 17.4.2 through 17.4.4 describe the operations of the phase comparator, charge pump, and unlock FF. Figure 17-7. Configuration of Phase Comparator, Charge Pump, and Unlock FF PLLUL flag fr UP Reference frequency generator Unlock FF Phase comparator (φ -DET) Programmable divider EO1 fN DW Charge pump EO0 PLL disable signal 264 Data Sheet U15722EJ1V1DS µPD17704A, 17705A, 17707A, 17708A, 17709A 17.4.2 Function of phase comparator As shown in Figure 17-7, the phase comparator compares the phases of the divided frequency “fN” output by the programmable divider and the reference frequency “fr”, and outputs an up or down request signal. If the divided frequency fN is lower than reference frequency fr, the up request signal is output. If fN is higher than fr, the down request signal is output. Figure 17-8 shows the relationship between reference frequency fr, divided frequency fN, up request signal, and down request signal. When the PLL frequency synthesizer is disabled, neither the up request nor the down request signal is output. The up and down request signals are input to the charge pump and unlock FF, respectively. Figure 17-8. Relationship between fr, fN, UP, and DW (a) If fN lags behind fr fr fN UP DW (b) If fN leads fr fr fN UP DW (c) If fN and fr are in phase fr fN UP DW (d) If fN is lower than fr fr fN UP DW Data Sheet U15722EJ1V1DS 265 µPD17704A, 17705A, 17707A, 17708A, 17709A 17.4.3 Charge pump As shown in Figure 17-7, the charge pump outputs the up request and down request signals output by the phase comparator, from the error out pins (EO1 and EO0 pins). Therefore, the relationship between the output of the error out pins, divided frequency fN and reference frequency fr is as follows. Where reference frequency fr > divided frequency fN: Low-level output Where reference frequency fr < divided frequency fN: High-level output Where reference frequency fr = divided frequency fN: Floating 17.4.4 Unlock FF As shown in Figure 17-7, the unlock FF detects the unlock status of the PLL frequency synthesizer from the up request and down request signals of the phase comparator. Because either the up request or down request signal is low in the unlock status, the unlock status is detected by this low-level signal. In the unlock status, the unlock FF is set to 1. The unlock FF is set in the cycle of the reference frequency fr selected at that time. When the contents of the PLL unlock FF register are read (by the PEEK instruction), the unlock FF is reset (Read & Reset). Therefore, the unlock FF must be detected in a cycle longer than cycle 1/fr of the reference frequency fr. The status of the unlock FF is detected by the PLL unlock FF register. Figure 17-9 shows the configuration of the PLL unlock FF register. Because this register is a read-only register, its contents can be read to the window register by the PEEK instruction. Because the unlock FF is set in a cycle of the reference frequency fr, the contents of the PLL unlock FF register are read to the window register in a cycle longer than cycle 1/fr of the reference frequency. The delay time of the up and down request signals of the phase comparator are fixed to 0.8 to 1.0 µs. 266 Data Sheet U15722EJ1V1DS µPD17704A, 17705A, 17707A, 17708A, 17709A Figure 17-9. Configuration of PLL Unlock FF Register Name Flag symbol Address Read/write 12H R & Reset b3 b2 b1 b0 0 PLL unlock FF 0 0 P L L U L Detects status of unlock FF 0 Unlock FF = 0: PLL locked status 1 Unlock FF = 1: PLL unlocked status After reset Fixed to 0 Power-on reset 0 0 0 U WDT&SP reset U CE reset R Clock stop U: Undefined R R: Retained Data Sheet U15722EJ1V1DS 267 µPD17704A, 17705A, 17707A, 17708A, 17709A 17.5 PLL Disabled Status The PLL frequency synthesizer stops (is disabled) while the CE pin is low. Likewise, it also stops when PLL disabled status is selected by the PLL reference frequency register (RF address 11H). Table 17-1 shows the operation of each block in the PLL disabled status. When the VCOL and VCOH pins are disabled by the PLL mode selection register, only the VCOL and VCOH pins are internally pulled down, and the other blocks operate. Because the PLL frequency selection register and PLL mode selection register are not initialized after CE reset (hold the previous status), these registers return to the previous status when the CE pin has gone low, the PLL frequency synthesizer has been disabled, and then CE pin has gone high. To disable the PLL frequency synthesizer after CE reset, initialize these registers in software. After power-on reset, the PLL frequency synthesizer is disabled. Table 17-1. Operation of Each Block Under Each PLL Disable Condition Condition CE Pin = Low Level (PLL Disabled) Block CE Pin = High Level PLL Reference Frequency Selection Register = 1111B PLL Mode Selection Register = 0000B (PLL Disabled) (VCOH and VCOL Disabled) VCOL, VCOH pins Internally pulled down Internally pulled down Internally pulled down Programmable divider Division stopped Division stopped Operates Reference frequency generator Output stopped Output stopped Operates Phase comparator Output stopped Output stopped Operates Charge pump Error out pins are floated Error out pins are floated Operates. However, usually outputs low level because no signal is input 268 Data Sheet U15722EJ1V1DS µPD17704A, 17705A, 17707A, 17708A, 17709A 17.6 Using PLL Frequency Synthesizer To control the PLL frequency synthesizer, the following data is necessary. (1) Division mode: Direct division (MF), pulse swallow (HF, VHF) (2) Pins used: VCOL and VCOH pins (3) Reference frequency: fr (4) Division value: N 17.6.1 through 17.6.3 below describe how to set PLL data in each division mode (MF, HF, and VHF). 17.6.1 Direct division mode (MF) (1) Selecting division mode Select the direct division mode by using the PLL mode selection register. (2) Pins used The VCOL pin is enabled to operate when the direct division mode is selected. (3) Selecting reference frequency fr Select the reference frequency by using the PLL reference frequency selection register. (4) Calculation of division value N Calculate N as follows. N= fVCOL fr fVCOL: Input frequency of VCOL pin fr: Reference frequency (5) Example of setting PLL data How to set data to receive broadcasting in the following MW band is described below. Reception frequency: 1422 kHz (MW band) Reference frequency: 9 kHz Intermediate frequency: +450 kHz Division value N is calculated as follows. N= fVCOL fr = 1422 + 450 9 = 208 (decimal) = 0D0H (hexadecimal) Set data to the PLL data register, PLL mode selection register, and PLL reference frequency selection register as follows. Data Sheet U15722EJ1V1DS 269 µPD17704A, 17705A, 17707A, 17708A, 17709A PLL mode PLL reference selection frequency Note 1 register selection register PLL data register (PLLR) 0 0 0 0 1 0 1 0 D 1 0 0 0 0 Don't care 0 Notes 1. PLLSCNF flag 2. Don’t care 270 Data Sheet U15722EJ1V1DS Note 2 0 0 MF 11 1 0 9 kHz 1 µPD17704A, 17705A, 17707A, 17708A, 17709A 17.6.2 Pulse swallow mode (HF) (1) Selecting division mode Select the pulse swallow mode by using the PLL mode selection register. (2) Pins used The VCOL pin is enabled to operate when the pulse swallow mode is selected. (3) Selecting reference frequency fr Select the reference frequency by using the PLL reference frequency selection register. (4) Calculation of division value N Calculate N as follows. N= fVCOL fr fVCOL: Input frequency of VCOL pin fr: Reference frequency (5) Example of setting PLL data How to set data to receive broadcasting in the following SW band is described below. Reception frequency: 25.50 MHz (SW band) Reference frequency: 5 kHz Intermediate frequency: +450 kHz Division value N is calculated as follows. N= fVCOL fr 25500 + 450 = = 5190 (decimal) 5 = 1446H (hexadecimal) Set data to the PLL data register, PLL mode selection register, and PLL reference frequency selection register as follows. Caution The division value N is 17 bits long when the pulse swallow mode is selected, and the least significant bit of the swallow counter is bit 3 of the PLL mode selection register (PLLSCNF). To set 1446H as the division value N, the value to be actually set to the PLL data register is 0A23H. PLL mode PLL reference selection frequency Note register selection register PLL data register (PLLR) 0 0 0 0 1 1 Note 0 1 0 0 4 0 1 4 0 0 0 1 1 6 0 0 1 HF 10 0 1 0 5 kHz PLLSCNF flag Data Sheet U15722EJ1V1DS 271 µPD17704A, 17705A, 17707A, 17708A, 17709A 17.6.3 Pulse swallow mode (VHF) (1) Selecting division mode Select the pulse swallow mode by using the PLL mode selection register. (2) Pins used The VCOH pin is enabled to operate when the pulse swallow mode is selected. (3) Selecting reference frequency fr Select the reference frequency by using the PLL reference frequency selection register. (4) Calculation of division value N Calculate N as follows. N= fVCOH fr fVCOH: Input frequency of VCOH pin fr: Reference frequency (5) Example of setting PLL data How to set data to receive broadcasting in the following FM band is described below. Reception frequency: 98.15 MHz (FM band) Reference frequency: 50 kHz Intermediate frequency: +10.7 MHz Division value N is calculated as follows. N= fVCOH 98.15 + 10.7 = fr = 2177 (decimal) 0.050 = 0881H (hexadecimal) Set data to the PLL data register, PLL mode selection register, and PLL reference frequency selection register as follows. Caution The division value N is 17 bits long when the pulse swallow mode is selected, and the least significant bit of the swallow counter is bit 3 of the PLL mode selection register (PLLSCNF). To set 0881H as the division value N, the value to be actually set to the PLL data register is 0440H. PLL mode PLL reference selection frequency Note register selection register PLL data register (PLLR) 0 0 0 0 0 0 Note 272 1 0 0 0 8 1 0 0 0 0 0 0 8 PLLSCNF flag Data Sheet U15722EJ1V1DS 1 1 0 1 VHF 0 0 1 1 50 kHz 1 µPD17704A, 17705A, 17707A, 17708A, 17709A Note that data must be set to the PLLSCNF flag before a write (PUT) instruction is executed to the PLL data register (PLLR). Example SET1 PLLSCNF MOV DBF0, #0 MOV DBF1, #4 MOV DBF2, #4 PUT PLLR, DBF 17.7 Status After Reset 17.7.1 After power-on reset The PLL frequency synthesizer is disabled because the PLL reference frequency selection register is initialized to 1111B. 17.7.2 After WDT&SP reset The PLL frequency synthesizer is disabled because the PLL reference frequency selection register is initialized to 1111B. 17.7.3 On execution of clock stop instruction The PLL frequency synthesizer is disabled because the PLL reference frequency selection register is initialized to 1111B. 17.7.4 After CE reset The PLL frequency synthesizer is disabled because the PLL reference frequency selection register is initialized to 1111B. 17.7.5 In halt status The set status is retained if the CE pin is high. Data Sheet U15722EJ1V1DS 273 µPD17704A, 17705A, 17707A, 17708A, 17709A 18. FREQUENCY COUNTER 18.1 Outline of Frequency Counter Figure 18-1 outlines the frequency counter. The frequency counter has an IF counter function to count the intermediate frequency (IF) of an external input signal and an external gate counter (FCG: Frequency Counter for external Gate signal) to detect the pulse width of an external input signal. The IF counter function counts the frequency input to the P1C0/FMIFC or P1C1/AMIFC pin at fixed intervals (1 ms, 4 ms, 8 ms, or open) by using a 16-bit counter. The external gate counter function counts the frequency of the internal clock (1 kHz, 100 kHz, 900 kHz) from the rising to the falling of the signal input to the P2A1/FCG1 or P2A0/FCG0 pin. The IF counter and external gate counter functions cannot be used at the same time. Figure 18-1. Outline of Frequency Counter FCGCH1 flag FCGCH0 flag IFCCK1 flag IFCCK0 flag IFCSTRT flag DBF P2A1/FCG1 P2A0/FCG0 P1C0/FMIFC I/O selection block Gate time control block Start/stop control block IF counter (16 bits) IFCGOSTT flag IFCRES flag P1C1/AMIFC IFCMD1 flag IFCMD0 flag Remarks 1. FCGCH1 and FCGCH0 (bits 1 and 0 of FCG channel selection register: refer to Figure 18-4) select the pin used for the external gate counter function. 2. IFCMD1 and IFCMD0 (bits 3 and 2 of IF counter mode selection register: refer to Figure 18-3) select the IF counter or external gate counter function. 3. IFCCK1 and IFCCK0 (bits 1 and 0 of IF counter mode selection register: refer to Figure 18-3) select the gate time of the IF counter function and the reference frequency of the external gate counter function. 4. IFCSTRT (bit 1 of IF counter control register: refer to Figure 18-6) controls starting of the IF counter and external gate counter functions. 5. IFCGOSTT (bit 0 of IF counter gate status detection register: refer to Figure 18-7) detects opening/ closing the gate of the IF counter function. 6. IFCRES (bit 0 of IF counter control register: refer to Figure 18-6) resets the count value of the IF counter. 274 Data Sheet U15722EJ1V1DS µPD17704A, 17705A, 17707A, 17708A, 17709A 18.2 I/O Selection Block and Gate Time Control Block Figure 18-2 shows the configuration of the I/O selection block and gate time control block. The I/O selection block consists of an IF counter input selection block and FCG I/O selection block. The IF counter input selection block selects whether the frequency counter is used as an IF counter or an external gate counter, by using the IF counter mode register. When the frequency counter is used as the IF counter, either the P1C0/FMIFC or P1C1/AMIFC pin and a count mode are selected. The pin not used for the IF counter is used as a general-purpose input port pin. The FCG I/O selection block selects the P2A1/FCG1 or P2A0/FCG0 pin by using the FCG channel selection register, when the frequency counter is used as the external gate counter. The pin not used is used as a generalpurpose I/O port pin. When using the frequency counter as the external gate counter, the pin to be used must be set in the input mode by using the port 2A bit I/O selection register. This is because the pin is set in the general-purpose output port mode if it is set in the output mode even if the external gate counter function is selected by the IF counter mode selection register and FCG channel selection register. The gate time control block selects gate time by using the IF counter mode selection register when the frequency counter is used as the IF counter, or a count frequency when the frequency counter is used as the external gate counter. Figure 18-3 shows the configuration of the IF counter mode selection register. Figure 18-4 shows the configuration of the FCG channel selection register. Figure 18-2. Configuration of I/O Selection Block and Gate Time Control Block FCGCH1 flag FCGCH0 flag IFCMD1 flag IFCMD0 flag P2A1/FCG1 FCG Selector Gate signal P2A0/FCG0 Gate signal generator I/O port Selector 1/2 P1C0/FMIFC IFCCK1 flag IFCCK0 flag To start/stop control block Frequency generator Frequency P1C1/AMIFC Input port FMIFC AMIFC Data Sheet U15722EJ1V1DS 275 µPD17704A, 17705A, 17707A, 17708A, 17709A Figure 18-3. Configuration of IF Counter Mode Selection Register Name Flag symbol Address Read/write 22H R/W b3 b2 b1 b0 IF counter mode selection I I I I F F F F C C C C M M C C D D K K 1 0 1 0 Selects gate time of IF counter and reference frequency of external gate counter Reference frequency of external gate counter Gate time of IF counter 0 0 1 ms 1 kHz 0 1 4 ms 100 kHz 1 0 8 ms 900 kHz 1 1 Open Setting prohibited After reset Selects function of IF counter or external gate counter 0 0 External gate counter (FCG) 0 1 IF counter (AMIFC pin, AMIF count mode) 1 0 IF counter (FMIFC pin, FMIF count mode, 1/2 division) 1 1 IF counter (FMIFC pin, AMIF count mode) Power-on reset 0 0 0 0 WDT&SP reset 0 0 0 0 CE reset 0 0 0 0 0 0 0 0 Clock stop Caution The IF counter and external gate counter functions cannot be used at the same time. 276 Data Sheet U15722EJ1V1DS µPD17704A, 17705A, 17707A, 17708A, 17709A Figure 18-4. Configuration of FCG Channel Selection Register Name Flag symbol Address Read/write 20H R/W b3 b2 b1 b0 FCG channel selection 0 0 F F C C G G C C H H 1 0 Selects pin used for FCG 0 0 FCG not used (general-purpose I/O port) 0 1 P2A0/FCG0 pin 1 0 P2A1/FCG1 pin 1 1 Setting prohibited After reset Fixed to 0 Power-on reset 0 0 WDT&SP reset 0 0 CE reset 0 0 0 0 Clock stop 0 0 Data Sheet U15722EJ1V1DS 277 µPD17704A, 17705A, 17707A, 17708A, 17709A 18.3 Start/Stop Control Block and IF Counter 18.3.1 Configuration of start/stop control block and IF counter Figure 18-5 shows the configuration of the start/stop control block and IF counter. The start/stop control block starts the frequency counter or detects the end of counting. The counter is started by the IF counter control register. The end of counting is detected by the IF counter gate status detection register. When the external gate counter function is used, however, the end of counting cannot be detected by the IF counter gate status detection register. Figure 18-6 shows the configuration of the IF counter control register. Figure 18-7 shows the configuration of the IF counter gate status detection register. 18.3.2 and 18.3.3 describe the gate operation when the IF counter function is selected and that when the external gate counter function is selected. The IF counter is a 16-bit binary counter that counts up the input frequency when the IF counter function or external gate counter function is selected. When the IF counter function is selected, the frequency input to a selected pin is counted while the gate is opened by an internal gate signal. The frequency count is counted without alteration in the AMIF count mode. In the FMIF counter mode, however, the frequency input to the pin is halved and counted. When the external gate counter function is selected, the internal frequency is counted while the gate is opened by the signal input to the pin. When the IF counter counts up to FFFFH, it remains at FFFFH until reset. The count value is read by the IF counter data register (IFC) via data buffer. The count value is reset by the IF counter control register. Figure 18-8 shows the configuration of the IF counter data register. Figure 18-5. Configuration of Start/Stop Control Block and IF Counter DBF 16 IF counter data register (IFC) IFCSTRT flag IFCGOSTT flag IFCRES flag 16 Gate signal From gate time selection block RES Start/Stop control Frequency 278 Data Sheet U15722EJ1V1DS IF counter (16 bits) µPD17704A, 17705A, 17707A, 17708A, 17709A Figure 18-6. Configuration of IF Counter Control Register Name Flag symbol Address Read/write 23H W b3 b2 b1 b0 IF counter control 0 0 I I F F C C S R T E R S T Resets data of IF counter and external gate counter 0 Nothing is affected 1 Resets counter Start IF counter and external gate counter 0 Nothing is affected 1 Resets counter After reset Fixed to 0 Power-on reset 0 0 WDT&SP reset 0 0 CE reset 0 0 0 0 Clock stop 0 0 Data Sheet U15722EJ1V1DS 279 µPD17704A, 17705A, 17707A, 17708A, 17709A Figure 18-7. Configuration of IF Counter Gate Status Detection Register Name Flag symbol Address Read/write 21H R b3 b 2 b 1 b 0 IF counter gate status detection 0 0 0 I F C G O S T T Detects opening/closing of gate of frequency counter When IF counter function is selected 0 When external gate counter function is selected Sets IFCSTRT flag to 1 and is set to Sets IFCSTRT flag to 1 and is set to 1 until gate is closed 1 while gate is open, regardless of input of P2A0/FCG0 and P2A1/FCG1 1 pins After reset Fixed to 0 Power-on reset 0 0 0 0 WDT&SP reset 0 CE reset 0 Clock stop 0 Cautions 1. Do not read the contents of the IF counter data register (IFC) to the data buffer while the IFCGOSTT flag is set to 1. 2. The gate of the external gate counter cannot be opened or closed by the IFCGOSTT flag. Use the IFCSTRT flag to open or close the gate. 280 Data Sheet U15722EJ1V1DS µPD17704A, 17705A, 17707A, 17708A, 17709A 18.3.2 Operation of gate when IF counter function is selected (1) When gate time of 1, 4, or 8 ms is selected The gate is opened for 1, 4, or 8 ms from the rising of the internal 1 kHz signal after the IFCSTRT flag has been set to 1, as illustrated below. While this gate is open, the frequency input from a selected pin is counted by a 16-bit counter. When the gate is closed, the IFCG flag is cleared to 0. The IFCGOSTT flag is automatically set to 1 when the IFCSTRT flag is set. H L OPEN CLOSE Internal 1 kHz 1 ms Gate time 4 ms 8 ms Count period (IFCGOSTT flag = 1) Gate is actually opened at this point IFCSTRT flag is set IFCGOSTT flag is set at this point End of counting IFGOSTT flag is cleared (2) When gate is open If opening of the gate is selected by the IFCCK1 and IFCCK0 flags, the gate is opened as soon as its opening has been selected, as illustrated below. If the counter is started by using the IFCSTRT flag while the gate is open, the gate is closed after undefined time. To open the gate, therefore, do not set the IFCSTRT flag to 1. However, the counter can be reset by the IFCRES flag. H Internal 1 kHz L OPEN Gate CLOSE Count period Gate is closed after undefined time if IFCSTRT flag is set during this period Sets IFCCK1 = IFCCK0 = 1 Gate is actually opened at this point. If gate is opened while IFCGOSTT flag is 1, it is closed after undefined time The gate is opened or closed in the following two ways when opening the gate is selected as the gate time. Data Sheet U15722EJ1V1DS 281 µPD17704A, 17705A, 17707A, 17708A, 17709A (a) Resetting gate to other than open by using IFCCK1 and IFCCK0 flags Gate OPEN CLOSE Count period IFCCK1 = IFCCK0 = 1 Resetting the gate to other than open by the IFCCK1 and IFCCK0 flags (b) Unselect pin used by using IFCMD1 and IFCMD0 flags In this way, the gate remains open, and counting is stopped by disabling input from the pin. Gate OPEN CLOSE Count period Sets IFCCK1 = IFCCK0 = 1 Sets IFCMD1 = IFCMD0 = 0 (FCG) The FMIFC and AMIFC pins are unselected and the count signal cannot be input 18.3.3 Gate operation when external gate counter function is selected The gate is opened from the rising of the signal input to a selected pin to its next rising after the IFCSTRT flag has been set to 1, as illustrated below. While the gate is open, the internal frequency (1 kHz, 100 kHz, 900 kHz) is counted by a 16-bit counter. The IFCGOSTT flag is set to 1 from the rising of the external signal to its next rising after the IFCSTRT flag has been set. In other words, the opening or closing of the gate cannot be detected by the IFCG flag when the external gate counter function is selected. H L Gate OPEN CLOSE External signal Count period Gate is opened at this point End of counting IFCGOSTT flag is 0 IFCSTRT flag ← 1 If reset and started while gate is open H L Gate OPEN CLOSE External signal Count period Count period Gate is opened at this point IFCSTRT flag ← 1 282 IFCSTRT flag ← 1 Data Sheet U15722EJ1V1DS End of counting IFCGOSTT flag is 0 µPD17704A, 17705A, 17707A, 17708A, 17709A 18.3.4 Function and operation of 16-bit counter The 16-bit counter counts up the frequency input within selected gate time. The 16-bit counter can be reset by writing 1 to the IFCRES flag of the IF counter control register. Once the 16-bit counter has counted up to FFFFH, it remains at FFFFH until it is reset. The following paragraphs (1) and (2) describe the operations when the IF counter function is selected and when the external gate counter function is selected. The value of the IF counter data register is read via data buffer. Figure 18-8 shows the configuration and function of the IF counter data register. (1) When IF counter is selected The frequency input to the P1C0/FMIFC or P1C1/AMIFC pin is counted while the gate is open. Note, however, that the frequency input to the P1C0/FMIFC is divided by two and counted. The relationship between count value “x (decimal)” and input frequencies (fFMIFC and fAMIFC) is shown below. • FMIFC fFMIFC = x tGATE × 2 (kHz) tGATE: Gate time (1 ms, 4 ms, 8 ms) (kHz) tGATE: Gate time (1 ms, 4 ms, 8 ms) • AMIFC fAMIFC = x tGATE (2) When external gate counter (FCG) is selected The internal frequency is counted while the gate is opened by the signal input to the P2A1/FCG1 or P2A0/ FCG0 pin. The relationship between the count value “x (decimal)” and the gate width tGATE of the input signal is shown below. tGATE = x fr (ms) fr: Internal frequency (1, 100, 900 kHz) Data Sheet U15722EJ1V1DS 283 µPD17704A, 17705A, 17707A, 17708A, 17709A Figure 18-8. Configuration of IF Counter Data Register Data buffer DBF3 DBF1 DBF2 DBF0 Transfer data GET can be executed 16 PUT changes nothing Peripheral register Name IF counter data register b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 Symbol Peripheral address IFC 43H Valid data Count value of frequency counter 0 IF counter function • FMIF count mode of FMIFC pin Counts rising edge of signal input to P1C0/FMIFC pin via 1/2 divider • AMIF count mode of AMIFC pin Counts rising edge of signal input to P1C1/AMIFC pin • AMIF count mode of FMIFC pin Counts rising edge of signal input to x P1C0/FMIFC pin External gate counter function Counts rising edge of internal reference frequency signal from rising edge to next rising edge of signal input to P2A0/FCG0 or P2A1/FCG1 pin 216– 1 (FFFFH) Once the IF counter data register has counted up to FFFFH, it remains at FFFFH until the counter is reset. 284 Data Sheet U15722EJ1V1DS µPD17704A, 17705A, 17707A, 17708A, 17709A 18.4 Using IF Counter The following sections 18.4.1 through 18.4.3 describe how to use the hardware of the IF counter, give a program example, and describe count errors, respectively. 18.4.1 Using hardware of IF counter Figure 18-9 shows the block diagram when the P1C0/FMIFC and P1C1/AMIFC pins are used. As shown in the figure, because the IF counter uses an input pin with an AC amplifier, the DC component of the input signal must be cut with a capacitor. When the P1C0/FMIFC or P1C1/AMIFC pin is selected for the IF counter function, switch SW turns on, and the voltage level on each pin reaches about 1/2VDD. If the voltage has not risen to a sufficient intermediate level at this time, the IF counter does not operate normally because the AC amplifier is not in the normal operating range. Therefore, make sure that a sufficient wait time elapses after each pin has been specified to be used for the IF counter until counting is started. Figure 18-9. IF Count Function Block Diagram of Each Pin R SW C To internal counter External frequecny FMIFC AMIFC Data Sheet U15722EJ1V1DS 285 µPD17704A, 17705A, 17707A, 17708A, 17709A 18.4.2 Program example of IF counter A program example of the IF counter is shown below. As shown in this example, make sure that a wait time elapses after an instruction that selects the P1C0/FMIFC or P1C1/AMIFC pin for the IF counter function has been executed until counting is started. This is because, as described in 18.4.1, the internal AC amplifier does not operate normally immediately after a pin has been selected for the IF counter. Example To count the frequency input to the P1C0/FMIFC pin (FMIF count mode) (gate time: 8 ms) INITFLG IFCMD1, NOT IFCMD0, IFCCK1, NOT IFCCK0 ; Selects FMIFC pin (FMIF count mode), and sets gate time to 8 ms Wait ; Internal AC amplifier stabilization time SET1 IFCRES ; Resets counter SET1 IFCSTRT ; Starts counting LOOP: SKT1 IFCG0STT ; Detects opening or closing of gate BR READ ; Branches to READ: if gate is closed Processing A BR LOOP ; Do not read data of IF counter with this processing A DBF, IFC ; Reads value of IF counter data register to data buffer READ: GET 18.4.3 Error of IF counter The errors of the IF counter include a gate time error and a count error. The following paragraphs (1) and (2) describe each of these errors. (1) Gate time error The gate time of the IF counter is created by dividing the 4.5 MHz clock. Therefore, if the system clock is shifted from 4.5 MHz by “+x” ppm, the gate time is shifted by “–x” ppm. (2) Count error The IF counter counts frequency by the rising edge of the input signal. If a high level is input to the pin when the gate is open, therefore, one excess pulse is counted. If the gate is closed, however, a count error due to the status of the pin does not occur. Therefore, the count error is “+1, –0”. 286 Data Sheet U15722EJ1V1DS µPD17704A, 17705A, 17707A, 17708A, 17709A 18.5 Using External Gate Counter 18.5.1 Program example of external gate counter A program example of the external gate counter is shown below. Example To use the P2A0/FCG0 pin as external gate input pin INITFLG NOT IFCMD1, NOT IFCMD0, IFCCK1, NOT IFCCK0 ; Selects external gate counter function and sets gate time to 8 ms INITFLG NOT FCGCH1, FCGCH0 ; Selects FCG0 pin as external gate input pin SET1 IFCRES ; Resets counter SET1 IFCSTRT ; Starts counting SKF1 IFCGOSTT ; Detects opening or closing of gate BR READ ; Branches to READ: if gate is closed LOOP: Processing A BR ; Do not read data of IF counter with this processing A LOOP READ: GET DBF, IFC ; Reads value of IF counter data register to data buffer 18.5.2 Error of external gate counter The errors of the external gate counter include an internal frequency error and a count error. The following paragraphs (1) and (2) describe each of these errors. (1) Internal frequency error The internal frequency of the external gate counter is created by dividing the 4.5 MHz clock. Therefore, if the system clock is shifted from 4.5 MHz by “+x” ppm, the gate time is shifted by “–x” ppm. (2) Count error The external gate counter counts the frequency by the rising edge of the internal frequency. If the internal frequency is low when the gate is opened (when the signal input to the pin rises), one excess pulse is counted. If the gate is closed (when the signal rises next time), the excess pulse is not counted due to the count level of the internal frequency. Therefore, the count error is “+1, –0”. Data Sheet U15722EJ1V1DS 287 µPD17704A, 17705A, 17707A, 17708A, 17709A 18.6 Status After Reset 18.6.1 After power-on reset The P1C0/FMIFC, P1C1/AMIFC, P2A0/FCG0, and P2A1/FCG1 pins are set to the general-purpose input port mode. 18.6.2 After WDT&SP reset The P1C0/FMIFC, P1C1/AMIFC, P2A0/FCG0, and P2A1/FCG1 pins are set to the general-purpose input port mode. 18.6.3 On execution of clock stop instruction The P1C0/FMIFC and P1C1/AMIFC pins are set to the general-purpose input port mode. The P2A0/FCG0 and P2A1/FCG1 pins are set to the general-purpose I/O port mode, and retain the previous input or output status. 18.6.4 After CE reset The P1C0/FMIFC and P1C1/AMIFC pins are set to the general-purpose input port mode. The P2A0/FCG0 and P2A1/FCG1 pins are set to the general-purpose I/O port mode, and retain the previous input or output status. 18.6.5 In halt status The P1C0/FMIFC, P1C1/AMIFC, P2A0/FCG0, and P2A1/FCG1 pins retain the status immediately before the halt mode is set. 288 Data Sheet U15722EJ1V1DS µPD17704A, 17705A, 17707A, 17708A, 17709A 19. BEEP 19.1 Outline of BEEP Figure 19-1 outlines BEEP. BEEP outputs a clock of 1, 3, 4, or 6.7 kHz from the P1D0/BEEP0 pin, and a clock of 4 kHz, 3 kHz, 200 Hz, or 67 Hz from the P1D1/BEEP1 pin. The duty factor of the BEEP output is 50%. Figure 19-1. Outline of BEEP P1DBIO0 flag P1D0/BEEP0 I/O selection block BEEP0SEL flag Output selection flag BEEP0CK1 flag BEEP0CK0 flag Clock selection block Clock generation block 1 kHz 3 kHz 4 kHz Output latch Output latch 6.7 kHz P1D1/BEEP1 I/O selection block P1DBIO1 flag Remarks 1. Output selection flag BEEP1SEL flag Clock selection block 67 Hz 200 Hz BEEP1CK1 flag BEEP1CK0 flag BEEP0CK1 and BEEP0CK0 (bits 1 and 0 of BEEP clock selection register: refer to Figure 19-4) select the output frequency of BEEP0. 2. BEEP1CK1 and BEEP1CK0 (bits 3 and 2 of BEEP clock selection register: refer to Figure 19-4) select the output frequency of BEEP1. 3. BEEP1SEL and BEEP0SEL (bits 1 and 0 of BEEP/general-purpose port pin function selection register: refer to Figure 19-3) select general-purpose I/O port and BEEP. 4. P1DBIO1 and P1DBIO0 (bits 1 and 0 of port 1D bit I/O selection register: refer to Figure 19-2) select the input or output mode of the port. Data Sheet U15722EJ1V1DS 289 µPD17704A, 17705A, 17707A, 17708A, 17709A 19.2 I/O Selection Block and Output Selection Block The I/O selection block selects the input or output mode of the P1D0/BEEP0 and P1D1/BEEP1 pins by using the port 1D bit I/O selection register. Set the pin to be used as a BEEP pin in the output mode. The output selection block sets the P1D0/BEEP0 and P1D1/BEEP1 pins to the general-purpose output port mode or BEEP output mode by using the BEEP/general-purpose port pin function selection register. Figure 19-2 shows the configuration of the port 1D bit I/O selection register. Figure 19-3 shows the configuration of the BEEP/general-purpose port pin function selection register. Figure 19-2. Configuration of Port 1D Bit I/O Selection Register Name Flag symbol Address Read/write R/W b3 b 2 b 1 b0 Port 1D bit I/O selection P P P P (BANK15) 1 1 1 1 6CH D D D D B B B B I I I I O O O O 3 1 2 0 Selects input or output port mode 0 Sets P1D0/BEEP0 pin to input mode 1 Sets P1D0/BEEP0 pin to output mode. Selects input or output port mode 0 Sets P1D1/BEEP1 pin to input mode 1 Sets P1D1/BEEP1 pin to output mode Selects input or output port mode 0 Sets P1D2 pin to input mode 1 Sets P1D2 pin to output mode After reset Selects input or output port mode Sets P1D3 pin to input mode 1 Sets P1D3 pin to output mode Power-on reset 0 0 0 0 WDT&SP reset 0 0 0 0 CE reset Retained Clock stop 290 0 Retained Data Sheet U15722EJ1V1DS µPD17704A, 17705A, 17707A, 17708A, 17709A Figure 19-3. Configuration of BEEP/General-Purpose Port Pin Function Selection Register Name Flag symbol Address Read/write 13H R/W b3 b2 b1 b0 BEEP/general-purpose port 0 0 pin function selection B B E E E E P P 1 0 S S E E L L Selects general-purpose I/O port or BEEP 0 Uses P1D0/BEEP0 pin as general-purpose I/O port 1 Uses P1D0/BEEP0 pin for BEEP Selects general-purpose I/O port or BEEP 0 Uses P1D1/BEEP1 pin as general-purpose I/O port 1 Uses P1D1/BEEP1 pin for BEEP After reset Fixed to 0 0 0 WDT&SP reset 0 0 CE reset 0 0 0 0 Power-on reset Clock stop 0 0 Data Sheet U15722EJ1V1DS 291 µPD17704A, 17705A, 17707A, 17708A, 17709A 19.3 Clock Selection Block and Clock Generation Block The clock selection block selects the output frequency of BEEP1 and BEEP0 by using the BEEP clock selection register. The clock generation block generates the clock to be output to BEEP0 and BEEP1. The clock frequency generated is 1 kHz, 3 kHz, 4 kHz, 6.7 kHz, 67 Hz, or 200 Hz. Figure 19-4. Configuration of BEEP Clock Selection Register Name Flag symbol Address Read/write 14H R/W b3 b 2 b 1 b0 BEEP clock selection B B B B E E E E E E E E P P P P 1 1 0 0 C C C C K K K K 1 0 1 0 Sets output frequency of BEEP0 0 0 1 kHz 0 1 3 kHz 1 0 4 kHz 1 1 6.7 kHz After reset Sets output frequency of BEEP1 0 0 4 kHz 0 1 3 kHz 1 0 200 Hz 1 1 67 Hz Power-on reset 0 0 0 0 WDT&SP reset 0 0 0 0 CE reset 0 0 0 0 0 0 0 0 Clock stop 292 Data Sheet U15722EJ1V1DS µPD17704A, 17705A, 17707A, 17708A, 17709A 19.4 Output Waveform of BEEP The duty factor of the BEEP output waveform is 50%. Example f = 3 kHz 166.7 µ s 166.7 µ s f = 1 kHz 500 µ s 500 µ s f = 200 Hz 2.5 ms 2.5 ms f: Output frequency of BEEP 19.5 Status After Reset 19.5.1 After power-on reset The P1D0/BEEP0 and P1D1/BEEP1 pins are set to the general-purpose input port mode. 19.5.2 After WDT&SP reset The P1D0/BEEP0 and P1D1/BEEP1 pins are set to the general-purpose input port mode. 19.5.3 On execution of clock stop instruction The P1D0/BEEP0 and P1D1/BEEP1 pins are set to the general-purpose I/O port mode, and retain the previous input or output status. 19.5.4 After CE reset The P1D0/BEEP0 and P1D1/BEEP1 pins are set to the general-purpose I/O port mode, and retain the previous input or output status. 19.5.5 In halt status The previous status is retained. Data Sheet U15722EJ1V1DS 293 µPD17704A, 17705A, 17707A, 17708A, 17709A 20. STANDBY The standby function is used to reduce the current consumption of the device while the device is being backed up. 20.1 Outline of Standby Function Figure 20-1 outlines the standby block. The standby function reduces the current consumption of the device by partly or totally stopping the device operation. The following three types of standby functions are available for selection as the application requires. • Halt function • Clock stop function • Device operation control function by CE pin The halt function reduces the current consumption of the device by stopping the CPU operation by using a dedicated instruction “HALT h”. The clock stop function reduces the current consumption of the device by stopping the oscillation of the oscillator by using a dedicated instruction “STOP s”. The CE pin can be said to be one of the standby functions because it can be used to control the operation of the PLL frequency synthesizer and to reset the device. Figure 20-1. Outline of Standby Block CPU Interrupt control block Halt controller HALT h BTM0CY Program counter Instruction decoder Input latch P0D3/AD3 P0D2/AD2 P0D1/AD1 P0D0/AD0 ALU Clock stop controller STOP s System register Oscillator XOUT Control register XIN 294 Data Sheet U15722EJ1V1DS µPD17704A, 17705A, 17707A, 17708A, 17709A 20.2 Halt Function 20.2.1 Outline of halt function The halt function stops the operating clock of the CPU by executing the “HALT h” instruction. When this instruction is executed, the program is stopped until the halt status is later released. Therefore, the current consumption of the device in the halt status is reduced by the operating current of the CPU. The halt status is released by using the basic timer 0 carry FF, interrupt, or port input (P0D). The release condition is specified by operand “h” of the “HALT h” instruction. 20.2.2 Halt status In the halt status, all the operations of the CPU are stopped. In other words, execution of the program is stopped by the “HALT h” instruction. However, the peripheral hardware units continue the operation specified before execution of the “HALT h” instruction. For the operation of each peripheral hardware unit, refer to 20.4 Device Operation in Halt and Clock Stop Status. 20.2.3 Halt release condition Figure 20-2 shows the halt release condition. The halt release condition is specified by 4-bit data specified by the operand “h” of the “HALT h” instruction. The halt status is released when the condition specified by “1” in operand “h” is satisfied. When the halt status is released, program execution is started from the instruction after the “HALT h” instruction. If the halt status is released by an interrupt, the operation to be performed after the halt status has been released differs depending on whether the interrupts are enabled (EI status) or disabled (DI status) when an interrupt source (IRQxxx = 1) is issued with the interrupt (IPxxx = 1) enabled. If two or more releasing conditions are specified, the halt status is released when one of the specified conditions is satisfied. If 0000B is set as halt release condition “h”, no releasing condition is set. If the device is reset (by means of poweron reset, WDT&SP reset, or CE reset) at this time, the halt status is released. Figure 20-2. Halt Release Condition HALT h (4 bits) Operand b3 b2 b1 b0 Sets halt status releasing condition Released when high level is input to port 0D Released when basic timer 0 carry FF is set to 1 Undefined (Fix this bit to 0.) Released when interrupt is acknowledged 0 Not released even if condition is satisfied 1 Released if condition is satisfied Data Sheet U15722EJ1V1DS 295 µPD17704A, 17705A, 17707A, 17708A, 17709A 20.2.4 Releasing halt by input port (P0D) The halt releasing condition using an input port is specified by the “HALT 0001B” instruction. When the halt releasing condition using an input port is specified, the halt status is released if a high level is input to one of the P0D0 to P0D3 pins. The P0D0 to P0D3 pins are multiplexed with the A/D converter input pins AD0 to AD3, and the halt status is not released when these pins are used as A/D converter input pins. An example is given below. • To use as key matrix The P0D0 to P0D3 pins are general-purpose input port pins which can be set to the input or output mode in 1-bit units and can be connected to an internal pull-down resistor. If connection of the internal pull-down resistor is specified by software, an external resistor can be disconnected as shown in this example (the internal-pull down resistor is connected after power-on reset). P0D3/AD3 Latch P0DPLD3 flag P0D2/AD2 P0D1/AD1 Switch A P0D0/AD0 General-purpose output port The “HALT 0001B” instruction is executed after the general-purpose output ports for key source signal are made high. Note that if an alternate switch is used as shown by switch A in the above figure, the halt status is released immediately because a high level is input to the P0D0/AD0 pin while switch A is closed. 296 Data Sheet U15722EJ1V1DS µPD17704A, 17705A, 17707A, 17708A, 17709A 20.2.5 Releasing halt status by basic timer 0 carry FF Releasing the halt status by using the basic timer 0 carry FF is specified by the “HALT 0010B” instruction. When releasing the halt status by the basic timer 0 carry FF is specified, the halt status is released as soon as the basic timer 0 carry FF has been set to 1. The basic timer 0 carry FF corresponds to the BTM0CY flag on a one-to-one basis and is set at fixed time intervals (100, 50, 20, or 10 ms). Therefore, the halt status can be released at fixed time intervals. Example To release halt status every 100 ms to execute processing A HLTTMR DAT 0010B INITFLG NOT BTM0CK1, NOT BTM0CK0 ; Sets time interval of basic timer 0 to 100 ms ; Symbol definition HALT HLTTMR ; Specifies setting of basic timer 0 carry FF as halt releasing condition SKT1 BTMOCY ; Embedded macro BR LOOP ; Branches to LOOP if BTM0CY flag is not set LOOP: Processing A BR ; Executes processing A if carry occurs LOOP 20.2.6 Releasing halt status by interrupt Releasing the halt status by an interrupt is specified by the “HALT 1000B” instruction. When releasing the halt status by an interrupt is specified, the halt status is released as soon as the interrupt has been acknowledged. Many interrupt sources are available as described in 12. INTERRUPTS. Which interrupt source is used to release the halt status must be specified in advance by software. To acknowledge an interrupt, each interrupt request must be issued from each interrupt source and each interrupt must be enabled (by setting the corresponding interrupt enable flag). Therefore, the interrupt is not acknowledged even if the interrupt request is issued, and the halt status is not released. When the halt status is released by acknowledging an interrupt, the program flow branches to the vector address of the interrupt. When the RETI instruction is executed after interrupt servicing, the program flow is restored to the instruction after the HALT instruction. If all the interrupts are disabled (DI status), the halt status is released by enabling an interrupt (IPxxx = 1) and issuing an interrupt source (IRQxxx = 1), and the flow of the program goes to the instruction after the HALT instruction. Data Sheet U15722EJ1V1DS 297 µPD17704A, 17705A, 17707A, 17708A, 17709A Example Releasing halt status by timer 0 and INT0 pin interrupts In this example, the halt status is released and processing B is executed when timer 0 interrupt is acknowledged. Processing A is executed when the INT0 pin interrupt is acknowledged. Each time the halt status has been released, processing C is executed. HLTINT START: DAT 1000B ; Symbol definition ; Address 0000H BR MAIN ;*** Interrupt vector address *** NOP NOP NOP NOP NOP BR INTTM0 NOP NOP NOP NOP BR INT0 NOP INT0: ; SI01 ; SI00 ; TIMER3 ; TIMER2 ; TIMER1 ; Branches to timer 0 interrupt processing ; INT4 ; INT3 ; INT2 ; INT1 ; Branches to INT0 interrupt processing ; CE DOWN EDGE ; INT0 pin interrupt vector address (000BH) Processing A ; INT0 pin interrupt processing EI RETI INTMM0: Processing B ; Timer 0 interrupt processing EI RETI MAIN: INITFLG NOT TMOCK1, TM0CK0 ; Sets timer 0 count clock to 100 µs MOV MOV PUT SET2 SET2 DBF1, #0 DBF0, #0AH TM0M,DBF TM0RES, TM0EN IPTM0, IP0 ; Sets time interval of timer 0 interrupt to 1 ms ; Resets and starts timer 0 ; Enables INT0 and timer 0 interrupts LOOP: Processing C EI HALT HLTINT BR LOOP ; Main routine processing ; Enables all interrupts ; Specifies releasing halt status by interrupt ;<1> If the INT0 pin interrupt request and timer 0 interrupt request are issued simultaneously in the halt status, processing A for the INT0 pin, which has the higher hardware priority, is executed. After execution of processing A and when “RETI” is executed, the program branches to the “BR LOOP” instruction of <1>. However, the “BR LOOP” instruction is not executed, and the timer 0 interrupt is immediately acknowledged. When the “RETI” instruction is executed after processing B of the timer 0 interrupt has been executed, the “BR LOOP” instruction is executed. 298 Data Sheet U15722EJ1V1DS µPD17704A, 17705A, 17707A, 17708A, 17709A Caution To reset the interrupt request flag (IRQxxx) once before the halt instruction is executed, insert a NOP instruction (or one or more other instructions) between the HALT instruction and the instruction that resets the interrupt request flag (IRQxxx) as shown below. If a NOP instruction (or one or more other instructions) is not inserted, the interrupt request flag is not reset, and therefore, the halt status is released immediately. Example : : ; IRQxxx is set at certain timing : CLR1 IRQ××× NOP ; Resets IRQxxx flag once ; Resets IRQxxx flag at this timing ; If this period is missing, the IRQxxx flag is not reset, ; and the next HALT instruction is immediately released HALT 1000B ; Data Sheet U15722EJ1V1DS 299 µPD17704A, 17705A, 17707A, 17708A, 17709A 20.2.7 If two or more releasing conditions are specified at same time If two or more halt releasing conditions are specified at same time, the halt status is released when one of the conditions is satisfied. The following program example shows how the releasing conditions are identified if two or more conditions are satisfied at the same time. Example HLTINT HLTBTM HLTP0D P0D DAT DAT DAT MEM 1000B 0010B 0001B 0.73H START: BR MAIN ;*** Interrupt vector address *** NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP BR INT0 NOP ; SI01 ; SI00 ; TIMER3 ; TIMER2 ; TIMER1 ; TIMER0 ; INT4 ; INT3 ; INT2 ; INT1 ; Branches to INT0 interrupt processing ; CE DOWN EDGE INT0: ; INT0 pin interrupt vector address (000BH) Processing A ; INT0 pin interrupt processing EI RETI BTMOUP: ; Timer carry FF processing Processing B RET P0DP: ; P0D input processing Processing C RET MAIN: INITFLG NOT BTM0CK1, NOT BTM0CK0 ; Selects 100 ms as clock of basic timer 0 SET1 IP0 ; Enables INT0 pin interrupt EI LOOP: HALT HLTINT OR HLTBTM OR HLTP0C ; Selects interrupt, timer carry FF, and P0D input as halt releasing conditions SKF1 BTM0CY ; Detects BTM0CY flag CALL BTM0UP ; Timer carry FF processing if flag is set to 1 SKF P0D, 1111B ; Detects P0D input CALL P0DP ; Port input processing if P0D is high BR LOOP 300 Data Sheet U15722EJ1V1DS µPD17704A, 17705A, 17707A, 17708A, 17709A In the above example, three halt status releasing conditions, INT0 pin interrupt, 100 ms basic timer 0 carry FF, and port 0D input, are specified. To identify which condition has released the halt status, a vector address (interrupt), BTM0CY flag (timer carry FF), and port register (port input) are detected. To use two or more releasing conditions, the following two points must be noted. • When the halt status is released, all the specified releasing conditions must be detected. • The releasing condition with the higher priority must be detected first. 20.3 Clock Stop Function 20.3.1 Outline of clock stop function The clock stop function stops the oscillator of a 4.5 MHz crystal resonator by executing the “STOP s” instruction (clock stop status). Therefore, the current consumption of the device is reduced to 30 µA MAX. 20.3.2 Clock stop status In the clock stop status, all the device operations of the CPU and peripheral hardware units are stopped because the generator of the crystal resonator is stopped. For the operations of the CPU and peripheral hardware units, refer to 20.4 Device Operation in Halt and Clock Stop Status. In the clock stop status, the power failure detector does not operate even if the supply voltage VDD of the device is raised to 2.2 V. Therefore, the data memory can be backed up at a low voltage. For the power failure detector, refer to 21. RESET. 20.3.3 Releasing clock stop status Figure 20-3 shows the stop status releasing conditions. The stop status releasing condition is specified by 4-bit data specified by the operand “s” of the “STOP s” instruction. The stop status is released when the condition specified by “1” in the operand “s” is satisfied. When the stop status has been released, program execution is started from the instruction next to the “STOP s” instruction after a halt period which is half the time (tSET/2) specified by the basic timer 0 clock selection register as oscillator stabilization wait time has elapsed. If releasing the stop status by an interrupt is specified, however, the program operation after the stop status has been released differs depending on whether interrupts are enabled (EI status) or disabled (DI status) when an interrupt source is issued (IRQxxx = 1) with interrupt enabled (IPxxx = 1). If all the interrupts are enabled (EI status), the stop status is released when the interrupt is enabled (IPxxx = 1) and the interrupt source is issued (IRQxxx = 1), and the program flow returns to the instruction next to the STOP instruction. If all the interrupts are disabled (DI status), the stop status is released when the interrupt is enabled (IPxxx = 1) and the interrupt resource is issued (IRQxxx = 1), and the program flow returns to the instruction next to the STOP instruction. If two or more releasing conditions are specified at one time, and if one of the conditions is satisfied, the stop status is released. If 0000B is specified as stop releasing condition “s”, no releasing condition is satisfied. If the device is reset at this time (by means of power-on reset, or CE reset), the stop status is released. Data Sheet U15722EJ1V1DS 301 µPD17704A, 17705A, 17707A, 17708A, 17709A Figure 20-3. Stop Releasing Conditions STOP s (4 bits) Operand b3 b2 b1 b0 Specifies stop status releasing condition Releases when high level is input to port 0D Undefined (Fix this bit to 0.) Undefined (Fix this bit to 0.) Released by interrupt of falling edge of INT0 to INT4 pins and CE pin 0 Not released even if condition is satisfied 1 Released if condition is satisfied The “STOP s” instruction is executed as a NOP instruction when the CE pin rises and when the CE reset counter operates. The operating status of the CE reset counter can be detected by the CECNTSTT flag (for the CE reset counter, refer to 21. RESET). 20.3.4 Releasing clock stop status by high-level input of port 0D Figure 20-4 illustrates how the clock stop status is released by the high-level input to port 0D. Figure 20-4. Releasing Clock Stop Status by High-Level Input of Port 0D 5V VDD 2.2 V 0V H P0D L XOUT Oscillation stops STOP s instruction tSET/2 HALT period Starts from instruction next to STOP s tSET: Basic timer 0 setting time 20.3.5 Cautions on releasing clock stop status For the cautions on releasing the clock stop status, refer to (2) Releasing from clock stop status in 21.4.4 Cautions on raising supply voltage VDD. 302 Data Sheet U15722EJ1V1DS µPD17704A, 17705A, 17707A, 17708A, 17709A 20.4 Device Operation in Halt and Clock Stop Status Table 20-1 shows the operations of the CPU and peripheral hardware units in the halt and clock stop status. In the halt status, all the peripheral hardware units continue the normal operation until instruction execution is stopped. In the clock stop status, all the peripheral hardware units stop operation. The control registers that control the operations of the peripheral hardware units operate normally (not initialized) in the halt status, but are initialized to specified values when the clock stop instruction is executed. In other words, all peripheral hardware continues the operation specified by the control register in the halt status, and the operation is determined by the initialized value of the control register in the clock stop status. For the values of the control registers in the clock stop status, refer to 8. REGISTER FILE (RF). Table 20-1. Device Operation in Halt and Clock Stop Status Peripheral Hardware Status Halt Clock Stop Program counter Stops at address of HALT instruction Stops at address of STOP instruction System register Retained Retained Peripheral register Retained Partly initializedNote 1 Control register Retained Partly initializedNote 1 Timer Normal operation Operation stops operationNote 2 PLL frequency synthesizer Normal Operation stops A/D converter Normal operation Operation stops D/A converter Normal operation Stops operation and used as generalpurpose output port Serial interface Stops operation when internal clock (master) is selected and continues operation when external clock (slave) is selected Stops operation and used as generalpurpose I/O port Frequency counter Normal operation Stops operation and used as generalpurpose input port BEEP output Normal operation Stops operation and used as generalpurpose I/O port General-purpose I/O port Normal operation Retained General-purpose input port Normal operation Input port General-purpose output port Normal operation Retains output latch Notes 1. For the value to which these registers are initialized, refer to 5. SYSTEM REGISTER (SYSREG) and 8. REGISTER FILE (RF). 2. The PLL frequency synthesizer is automatically disabled by low-level input to the CE pin. 20.5 Cautions on Processing of Each Pin in Halt and Clock Stop Status The halt status is used to reduce the current consumption when, say, only the watch is used. The clock stop function is used to reduce the current consumption of the device to only use the data memory. Therefore, the current consumption must be reduced as much as possible in the halt status or clock stop status. At this time, the current consumption varies significantly depending on the status of each pin, so the points shown in Table 20-2 must be noted. Data Sheet U15722EJ1V1DS 303 µPD17704A, 17705A, 17707A, 17708A, 17709A Table 20-2. Status of Each Pin in Halt and Clock Stop Status and Cautions (1/2) Pin Function Pin Symbol Status of Each Pin and Cautions on Processing Halt Status General- Port 0A P0A3/SDA purpose P0A2/SCL I/O port P0A1/SCK0 Port 0B Port 0C Port 1D port mode (except P0D3/AD3 to P0D0/ (1) When specified as output pin AD0, P1A3/INT4, P1A2/INT3, P1C3/AD5, P0A0/SO0 Current consumption increases if pin and P1C2/AD4) is externally pulled down while it Input or output mode of general-purpose P0B2/SCK1 outputs high level, or externally pulled I/O port set before clock stop status is P0B1/SO1 up while it outputs low level. retained. P0B0/SI1 Exercise care in using N-ch open-drain P0C3 to P0C0 output (P0A3, P0A2, P1B3 to P1B0) P1D3 (1) When specified as general-purpose output port (2) When specified as input pin P1D1/BEEP1 Current consumption increases due P1D0/BEEP0 to noise if pin is floated P2A2 Current consumption increases due to noise if pin is floated (2) When specified as general-purpose P2A1/FCG1 General- Clock Stop Status All port pins are set in general-purpose P0B3/SI0 P1D2 Port 2A Retains status before halt (3) Port 0D (P0D3/AD3 through P0D0/ input port P2A0/FCG0 AD0) Current consumption does not Port 2B P2B3 to P2B0 Current consumption increases if pin increase due to noise even if pin is Port 2C P2C3 to P2C0 is externally pulled up because it is floated Port 2D P2D2 to P2D0 provided with pull-down resistor Port 3A P3A3 to P3A0 selectable by software Port 3B P3B3 to P3B0 Port 3C P3C30P3C0 Port 3D P3D3 to P3D0 P1C1/AMIFC, P1C0/FMIFC) Port 0D P0D3/AD3 When P1C1/AMIFC or P1C0/FMIFC purpose | input port Port 1A Port 1C (3) P1A3/INT4, P1A2/INT3 Set as interrupt pin and current (4) Port 1C (P1C3/AD5, P1C2/AD4, pin is used for IF counter, current consumption increases due to external noise if pin is floated (4) P0D3/AD3 through P0D0/AD0, P0D0/AD0 consumption increases because P1C3/AD5, P1C2/AD4 P1A3/INT4 internal amplifier operates Pin used for A/D converter is retained P1A2/INT3 as is. P1A1 Pull-down resistor of P0D3 to P0D0 P1A0/TM0G pin retains previous status P1C3/AD5 P1C2/AD4 P1C1/AMIFC P1C0/FMIFC Generalpurpose output port Port 1B P1B3 Specified as general-purpose output port. P1B2/PWM2 Output contents are retained as is. If pin | is externally pulled down while it outputs P1B0/PWM0 high level or externally pulled up while it outputs low level, current consumption increases 304 Data Sheet U15722EJ1V1DS µPD17704A, 17705A, 17707A, 17708A, 17709A Table 20-2. Status of Each Pin in Halt and Clock Stop Status and Cautions (2/2) Pin Function Pin Symbol Status of Each Pin and Cautions on Processing Halt Status Clock Stop Status External interrupt INT4 to INT0 Current consumption increases due to noise if pin is floated PLL frequency VCOL Current consumption increases during PLL synthesizer VCOH operation. EO0 When PLL is disabled, pin is in following EO1 status: PLL is disabled VCOH, VCOL: Internally pulled down EO1, EO0: Floated VCOH, VCOL: Internally pulled down EO1, EO0: Floated PLL is automatically disabled if CE pin goes low Crystal oscillation XIN Current consumption changes due to XIN pin is internally pulled down, and XOUT circuit XOUT oscillation waveform of crystal oscillation pin outputs high level circuit. The higher oscillation amplitude, the lower current consumption. Oscillation amplitude must be evaluated because it is influenced by crystal resonator or load capacitor used 20.6 Device Operation Control Function of CE Pin The CE pin controls the following functions by the input level and rising edge of the signal input from an external source. • PLL frequency synthesizer • Interrupt by falling edge of CE pin • Resetting of device 20.6.1 Controlling operation of PLL frequency synthesizer The PLL frequency synthesizer can operate only when the CE pin is high. It is automatically disabled when the CE pin is low. When the synthesizer is disabled, the VCOH and VCOL pins are internally pulled down, and the EO0 and EO1 pins are floated. For details, refer to 17.5 PLL Disabled Status. The PLL frequency synthesizer can be disabled in software even when the CE pin is high. 20.6.2 Controlling interrupt by falling edge input of CE pin An interrupt can be generated by the falling edge of the CE pin. For details, refer to 12. INTERRUPTS. Data Sheet U15722EJ1V1DS 305 µPD17704A, 17705A, 17707A, 17708A, 17709A 20.6.3 Resetting device The device can be reset (CE reset) by raising the CE pin to high level. The device can also be reset as follows. • Power-on reset on application of supply voltage VDD • Watchdog timer reset for inadvertent program loop detection and stack overflow/underflow reset • Reset by RESET pin For details, refer to 21. RESET. 20.6.4 Signal input to CE pin The CE pin does not acknowledge a low level or high level of less than 167 µs to prevent malfunctioning due to noise. The level of the signal input to the CE pin can be detected by the CE pin status detection flag of the CE pin interrupt request register (RF address 3FH). Figure 20-5 shows the relationship between the input signal and CE flag. Figure 20-5. Relationship Between Input Signal of CE Pin and CE Flag H CE pin L 1 CE flag 0 Less than 167µ s 167µ s Less than 167µs PLL can operate PLL disabled 167µ s CE reset PLL disabledNote CE reset is effected in synchronization with next basic timer 0 carry FF (When CE reset count register is 1) Note Unless the PLL mode selection register and PLL reference frequency selection register are rewritten by software, the PLL disabled status is retained. 306 Data Sheet U15722EJ1V1DS µPD17704A, 17705A, 17707A, 17708A, 17709A 20.6.5 Configuration and function of CE pin interrupt request register The CE pin interrupt request register detects the input signal level of the CE pin. Figure 20-6 shows the configuration of the CE pin interrupt request register. Figure 20-6. Configuration of CE Pin Interrupt Request Register Name Flag symbol Address Read/write 3FH RNote b3 b2 b1 b0 CE pin interrupt request C 0 E C I E R C Q N C T E S T T Sets interrupt request issuance status of CE pin 0 No interrupt request 1 Interrupt request Detects status of CE reset counter 0 Stops 1 Operates Fixed to 0 After reset Detects status of CE pin 0 Low level is input 1 High level is input Power-on reset U WDT&SP reset CE reset Clock stop U: Undefined Note 0 0 0 U 0 0 U 0 R U 0 R R: Retained IRQCE is a R/W flag. Data Sheet U15722EJ1V1DS 307 µPD17704A, 17705A, 17707A, 17708A, 17709A 21. RESET 21.1 Outline of Reset The reset function is used to initialize the device. The µPD17709A can be reset in the following ways. • CE reset • Power-on reset • Reset by RESET pin • WDT&SP reset Figure 21-1. Configuration of Reset Block Power failure detection block XOUT Timer FF block Selector Divider XIN BTM0CY flag read R STOP s instruction VDD Voltage detector RESET Falling detector Basic timer 0 carry Q S Basic timer 0 carry disable FF Power-on-clear signal (POC) Reset controller CE Rising detector CE reset timer carry counter Watchdog timer stack overflow/underflow detection block CE reset signal WDT&SP reset signal STOP instruction 308 Data Sheet U15722EJ1V1DS µPD17704A, 17705A, 17707A, 17708A, 17709A 21.2 CE Reset CE reset is effected by raising the CE pin. When the CE pin goes high, the next rising edge of the basic timer 0 carry FF setting pulse is counted. When the count value matches the value set to the CE reset timer carry counter register (1 to 15 counts), the reset signal is generated. When CE reset is effected, the program counter, stack, system registers, and some of the control registers are initialized to the initial values, and program execution is started from address 0000H. For the initial value of each register, refer to the description of each register. Figure 21-2. Configuration of CE Reset Timer Carry Counter Register Name Flag symbol Address Read/write 06H R/W b 3 b2 b1 b0 CE reset timer carry counter C C C C E E E E C C C C N N N N T T T T 3 2 1 0 After reset Sets number of counts of timer carry counter for CE reset 0 0 0 0 Setting prohibited 0 0 0 1 1 count 0 0 1 0 2 counts 0 0 1 1 3 counts 0 1 0 0 4 counts 0 1 0 1 5 counts 0 1 1 0 6 counts 0 1 1 1 7 counts 1 0 0 0 8 counts 1 0 0 1 9 counts 1 0 1 0 10 counts 1 0 1 1 11 counts 1 1 0 0 12 counts 1 1 0 1 13 counts 1 1 1 0 14 counts 1 1 1 1 15 counts Power-on reset 0 0 0 1 WDT&SP reset Retained CE reset Retained Clock stop 0 0 0 1 Data Sheet U15722EJ1V1DS 309 µPD17704A, 17705A, 17707A, 17708A, 17709A The operation of CE reset varies depending on whether the clock stop instruction is used or not. This difference is described in 21.2.1 and 21.2.2 below. 21.2.3 describes the points to be noted when CE reset is effected. 21.2.1 CE reset without clock stop (STOP s) instruction Figure 21-2 shows the operation. When the CE pin has gone high, the CE reset timer carry counter starts counting at the rising edge of the basic timer 0 carry FF setting pulse. Figure 21-3. CE Reset Operation Without Clock Stop Instruction (1/2) (a) Normal operation • When CE reset timer carry counter is set to “N” VDD CE 5V 0V H XOUT BTM0CY flag setting pulse CE reset timer carry counter Set value of CE reset timer carry counter L H L H L tSET H 0 1 2 3 N–2 N–1 N 0 L H N L H CE reset signal L CE reset • When CE reset timer carry counter is set to “1” VDD CE XOUT BTM0CY flag setting pulse CE reset timer carry counter Set value of CE reset timer carry counter CE reset signal 5V 0V H L H L H L H L H tSET 0 1 0 1 L H L CE reset 310 Data Sheet U15722EJ1V1DS µPD17704A, 17705A, 17707A, 17708A, 17709A Figure 21-3. CE Reset Operation Without Clock Stop Instruction (2/2) (b) If status of CE pin changes while CE counter operates At this time, the CE reset timer carry counter status is not affected. VDD CE XOUT BTM0CY flag setting pulse CE reset timer carry counter Set value of CE reset timer carry counter CE reset signal 5V 0V H L H L H L tSET H 0 1 2 3 N–2 N–1 N 0 L H N L H L CE reset 21.2.2 CE reset with clock stop (STOP s) instruction used Figure 21-4 shows the operation. When the clock stop instruction is used, the clock stop signal is output when the “STOP s” instruction is executed, and oscillation is stopped and the device operation is stopped. When the CE pin goes high, the clock stop status is released, and oscillation is started (high-level input of P0D or INT pin interrupt can also be used as the clock stop status releasing conditions. For details, refer to 20. STANDBY). If the basic timer 0 carry FF setting pulse goes high after the CE pin has gone high, the halt status is released, and program execution is started from address 0 (CE reset). As the set time (tSET) of the basic timer 0 carry FF setting pulse, the value immediately before the clock stop instruction is executed is retained. Because the set value of the CE reset timer carry counter is initialized to 1, CE reset is effected tSET/2 after the CE pin has gone high. Data Sheet U15722EJ1V1DS 311 µPD17704A, 17705A, 17707A, 17708A, 17709A Figure 21-4. CE Reset Operation with Clock Stop Instruction 5V VDD 0V H CE L H XOUT L BTM0CY flag setting pulse CE reset timer carry counter Set value of CE reset timer carry counter H L tSET H 0 1 L H N 1 L H CE reset signal L Normal operation Clock stop status Halt status tSET/2 STOP s instruction Clock stop status released. Oscillation starts CE reset Program execution starts from address 0 21.2.3 Cautions on CE reset Because CE reset is effected regardless of the instruction under execution, the following points (1) and (2) must be noted. (1) Time to execute timer processing such as watch When creating a watch program by using the basic timer 0 carry, the processing time of the program must be kept to within a specific time. For details, refer to 13.2.6 Cautions on using basic timer 0. (2) Processing of data and flags used in program Exercise care in rewriting the data and flags whose contents must not be changed even when CE reset is effected, such as security code. An example is shown below. 312 Data Sheet U15722EJ1V1DS µPD17704A, 17705A, 17707A, 17708A, 17709A Example 1. R1 MEM 0.01H ; 1st digit of key input data of security code R2 MEM 0.02H ; 2nd digit of key input data of security code R3 MEM 0.03H ; 1st digit data when security code is changed R4 MEM 0.04H ; 2nd digit data when security code is changed M1 MEM 0.11H ; 1st digit of current security code M2 MEM 0.12H ; 2nd digit of current security code START: Key input processing R1 ← contents of key A ; Security code input wait mode R2 ← contents of key B ; Substitutes contents of pressed key to R1 and R2 SET2 CMP, Z SUB R1, M1 SUB R2, M2 SKT1 Z BR ERROR ; <1> ; Compares security code and input data ; Input data differs from security code MAIN: Key input processing R3 ← contents of key C ; Security code rewriting mode R4 ← contents of key D ; Substitutes contents of pressed key to R3 and R4 ST M1, R3 ; <2> ; Rewrites security code ST M2, R4 ; <3> BR MAIN ERROR: Must not operate Suppose the security code is “12H” in the program in Example 1. The contents of data memory addresses M1 and M2 are “1H” and “2H”, respectively. If CE reset is effected, the contents of key input and security code “12H” are compared in <1>. If the two are the same, the normal processing is performed. If the security code is changed in the main processing, the new code is written to M1 and M2 in <2> and <3>. Suppose the security code is changed to “34H”. Then “3H” and “4H” are written to M1 and M2 in <2> and <3>. If CE reset is effected as soon as <2> has been executed, program execution is started from address 0000H, without <3> being executed. Consequently, the security code is set to “32H”, making it impossible to clear the security system. In this case, create the program shown in Example 2. Data Sheet U15722EJ1V1DS 313 µPD17704A, 17705A, 17707A, 17708A, 17709A Example 2. R1 MEM 0.01H ; 1st digit of key input data of security code R2 MEM 0.02H ; 2nd digit of key input data of security code R3 MEM 0.03H ; 1st digit data when security code is changed R4 MEM 0.04H ; 2nd digit data when security code is changed M1 MEM 0.11H ; 1st digit of current security code M2 MEM 0.12H ; 2nd digit of current security code CHANGE FLG 0.13H.0 ; 1 while security code is changed START: Key input processing R1 ← contents of key A ; Security code input wait mode R2 ← contents of key B ; Substitutes contents of pressed key to R1 and R2 SKT1 CHANGE BR SECURITY_CHK ; <4> ; If CHANGE flag is 1 ST M1, R3 ST M2, R4 CLR1 CHANGE ; Rewrites M1 and M2 SECURITY_CHK: SET2 CMP, Z SUB R1, M1 SUB R2, M2 SKT1 Z BR ERROR ; <1> ; Compares security code and input data ; Input data differs from security code MAIN: Key input processing R3 ← contents of key C ; Security code rewriting mode R4 ← contents of key D ; Substitutes contents of pressed key to R3 and R4 SET1 CHANGE ; <5> ; Until security code is changed, ; Sets CHANGE flag to 1 ST M1, R3 ; <2> ; Rewrites security code ST M2, R4 ; <3> CLR1 CHANGE ; If security code has been changed, ; Sets CHANGE flag to 0 BR MAIN ERROR: Must not operate The program in Example 2 sets the CHANGE flag to 1 in <5> before the security code is rewritten in <2> and <3>. Therefore, even if CE reset is effected before <3> is executed, the security code is rewritten in <4>. 314 Data Sheet U15722EJ1V1DS µPD17704A, 17705A, 17707A, 17708A, 17709A 21.3 Power-on Reset Power-on reset is effected by raising the supply voltage VDD of the device from a specific level (called a power-onclear voltage). If supply voltage VDD is lower than the power-on-clear voltage, a power-on-clear signal (POC) is output from the voltage detector shown in Figure 21-1. When the power-on-clear signal is input to the reset controller, the crystal oscillator is stopped and consequently, the device operation is stopped. At this time, the program counter, stack, system registers, and control registers are initialized (for the initial value, refer to the description of each register). If supply voltage VDD exceeds the power-on-clear voltage, the power-on-clear signal is deasserted, crystal oscillation is started, and the device waits for release of the halt status by the basic timer 0 carry which has been initialized to 100 ms. Program execution is started from address 0 at the rising edge of the basic timer 0 carry FF setting signal 50 ms after the supply voltage has exceeded the power-on-clear voltage. Normally, the power-on-clear voltage is 3.5 V, but it is 2.2 V in the clock stop status. The operations of power-on reset are described in 21.3.1 and 21.3.2. The operation when supply voltage VDD is raised from 0 V is described in 21.3.3. Caution In this document, the power-on-clear voltage is assumed to be 3.5 V (MAX.) in normal operation, and 2.2 V (MAX.) in the clock stopped status. The actual power-on-clear voltage does not exceed these maximum values. Figure 21-5. Operation of Power-on Reset 5V VDD CE Power-onclear voltage 0V H L H XOUT BTM0CY flag setting pulse L H L H Power-on-clear signal L Normal operation Device operation stops Halt status 50 ms Power-on clear released Oscillation starts Data Sheet U15722EJ1V1DS Program starts from address 0 315 µPD17704A, 17705A, 17707A, 17708A, 17709A 21.3.1 Power-on reset during normal operation Figure 21-6 (a) shows the operation. As shown, the power-on-clear signal is output and the device operation is stopped if the supply voltage VDD drops below 3.5 V, regardless of the input level of the CE pin. If VDD rises beyond 3.5 V again, program execution starts from address 0000H after a halt of 50 ms. Normal operation means operation without the clock stop instruction, and includes the halt status set by the halt instruction. 21.3.2 Power-on reset in clock stop status Figure 21-6 (b) shows the operation. As shown, the power-on-clear signal is output and the device operation is stopped when supply voltage VDD drops below 2.2 V. However, it does not appear that device operation has changed because the device is in the clock stop status. If VDD rises beyond 3.5 V, program execution starts from address 0000H after a halt of 50 ms. 21.3.3 Power-on reset when supply voltage VDD rises from 0 V Figure 21-6 (c) shows the operation. As shown, the power-on-clear signal is output until supply voltage VDD rises from 0 V to 3.5 V. When VDD exceeds the power-on-clear voltage, the crystal oscillator starts operating, and program execution starts from address 0000H after a half of 50 ms. 316 Data Sheet U15722EJ1V1DS µPD17704A, 17705A, 17707A, 17708A, 17709A Figure 21-6. Power-on Reset and Supply Voltage VDD (a) Normal operation (including halt status) 5V 3.5 V Power-on-clear voltage VDD 0V H CE L H XOUT Power-onclear signal L H L Normal operation Device operation stops Halt status 50 ms Power-on clear released Program starts from address 0 Oscillation starts (b) In clock stop status 5V 3.5 V 2.2 V VDD Power-on-clear voltage 0V H CE L H XOUT Power-onclear signal L H L Normal operation Clock stop STOP s instruction Device operation stops Halt status 50 ms Power-on clear released Program starts from address 0 Oscillation starts (c) If supply voltage VDD rises from 0 V 5V 3.5 V Power-on-clear voltage VDD 0V H CE L H XOUT Power-onclear signal L H L Device operation stops Halt status 50 ms Power-on clear released Program starts from address 0 Oscillation starts Data Sheet U15722EJ1V1DS 317 µPD17704A, 17705A, 17707A, 17708A, 17709A 21.4 Relationship Between CE Reset and Power-on Reset On the first application of supply voltage VDD, power-on reset and CE reset are performed at the same time. The reset operations at this time are described in 21.4.1 through 21.4.3. 21.4.4 describes the points to be noted when raising supply voltage VDD. 21.4.1 If VDD pin and CE pin go high at the same time Figure 21-7 (a) shows the operation. At this time, the program starts from address 0000H because of power-on reset. 21.4.2 If CE pin rises in forced halt status set by power-on reset Figure 21-7 (b) shows the operation. At this time, the program starts from address 0000H because of power-on reset, in the same manner as 21.4.1. 21.4.3 If CE pin rises after power-on reset Figure 21-7 (c) shows the operation. At this time, the program starts from address 0000H because of power-on reset, and the program starts from address 0000H again at the rising edge of the next basic timer 0 carry FF setting signal because of CE reset. 318 Data Sheet U15722EJ1V1DS µPD17704A, 17705A, 17707A, 17708A, 17709A Figure 21-7. Relationship Between Power-on Reset and CE Reset (a) When VDD and CE pin rise at the same time 5V Power-on-clear voltage 3.5 V VDD 0V H CE BTM0CY flag setting pulse L H L Operation stops Halt status 50 ms Normal operation Power-on reset Program starts (b) If CE pin rises in halt status 5V Power-on-clear voltage 3.5 V VDD 0V H CE L H BTM0CY flag setting pulse L Operation stops Halt status 50 ms Normal operation Power-on reset Program starts (c) If CE pin rises after power-on reset 5V Power-on-clear voltage 3.5 V VDD 0V H CE BTM0CY flag setting pulse L H L Operation stops Halt status 50 ms Normal operation Power-on reset Program starts Data Sheet U15722EJ1V1DS CE reset Program starts (If CE reset timer carry counter is set to 1) 319 µPD17704A, 17705A, 17707A, 17708A, 17709A 21.4.4 Cautions on raising supply voltage VDD The following points (1) and (2) must be noted when raising supply voltage VDD. (1) To raise supply voltage VDD from level lower than power-on-clear voltage Supply voltage VDD must be raised once to a level higher than 3.5 V. Figure 21-8 illustrates this. As shown in the figure, if a voltage less than 3.5 V is applied on application of VDD in a program that backs up VDD at 2.2 V by using the clock stop instruction, the power-on-clear signal continues to be output, and the program is not executed. At this time, the output ports of the device output undefined values, increasing the current consumption in some cases. Consequently, the backup time when the device is backed up by batteries is substantially shortened. Figure 21-8. Cautions on Raising VDD VDD 5V 3.5 V 2.2 V Power-onclear voltage 0V H XOUT BTM0CY flag setting pulse Power-onclear signal L H L H L Operation stops Operation stops Halt status 50 ms Normal operation Initialize during this period and then execute clock stop instruction Because output ports are undefined during this period, current consumption may increase. Power-on reset Program starts 320 Back up Data Sheet U15722EJ1V1DS STOP s instruction µPD17704A, 17705A, 17707A, 17708A, 17709A (2) Releasing from clock stop status If the device is released from the backup status when supply voltage VDD is backed up at 2.2 V by using the clock stop status, VDD must be raised to 3.5 V or more within tSET/2 after the clock stop status has been released by INT pin interrupt or high level input to port 0D. As shown in Figure 21-9, the device is released from the clock stop status by means of CE reset. However, because the power-on-clear voltage is changed to 3.5 V tSET/2 after the clock stop status has been released, power-on reset is effected unless VDD is 3.5 V or higher. The same applies when VDD is raised. Figure 21-9. Releasing from Clock Stop Status VDD 5V 3.5 V 2.2 V Power-onclear voltage 0V H P0D 0V H XOUT BTM0CY flag setting pulse Power-onclear signal L H L H L Backup in clock stop status Halt status tSET/2 Normal operation Program starts Power-on-clear voltage changes to 3.5 V at this point. Therefore, VDD must be 3.5 V or higher before this point. Backup STOP s instruction Power-on-clear voltage changes to 2.2 V at this point. Therefore, VDD must be 3.5 V or higher before this point. tSET: Basic timer 0 setting time Data Sheet U15722EJ1V1DS 321 µPD17704A, 17705A, 17707A, 17708A, 17709A 21.5 Reset by RESET Pin The device is reset by the RESET pin in the following cases. • To reset the device at voltage higher than power-on-clear voltage • External reset input in case of inadvertent program loop Caution If the device is reset by the RESET pin during program execution, the data in the data memory may be corrupted. Therefore, be careful when resetting with the RESET pin. The reset operation is the same as that performed at power-on reset. When a low level is input to the RESET pin, an internal reset signal is generated, the crystal oscillator is stopped, and the device stops operation. At this point, the program counter, stack, system registers, and control registers are initialized (for the initial value, refer to the description of each register). When the RESET pin is raised next time, the crystal oscillation is started, and the device waits to be released from the halt wait status by the basic timer 0 carry which has been initialized to a 100 ms cycle. The program starts from address 0 at the rising edge of the basic timer 0 carry FF setting signal 50 ms after a high level has been input to the RESET pin. Because the µPD17709A has a power-on reset function, connect the RESET pin to VDD via resistor if the RESET pin is not used for the above application. Figure 21-10. Reset Operation by RESET Pin 5V VDD 0V H RESET L H XOUT L BTM0CY flag setting pulse H L Device operation stops Halt status 50 ms Oscillation starts 322 Data Sheet U15722EJ1V1DS Program starts from address 0 µPD17704A, 17705A, 17707A, 17708A, 17709A 21.6 WDT&SP Reset WDT&SP reset includes the following. • Watchdog timer reset • Stack pointer overflow/underflow reset Figure 21-11. Outline of WDT&SP Reset WDTCK1 flag WDTCK0 flag 65536 instruction counter Instruction count clock WDTCY flag WDT&SP reset signal 131072 instruction counter WDTRES Stack overflow/under flow reset detector ASPRES flag ISPRES flag 21.6.1 Watchdog timer reset The watchdog timer is a circuit that generates a reset signal when the execution sequence of the program is abnormal (program loop). A program loop means that the program jumps to an unexpected routine due to external noise, entering a specific infinite loop and causing the system to be deadlocked. By using the watchdog timer, the program can be restored from this program loop status because a reset signal is generated from the watchdog timer at fixed time intervals and program execution is started from address 0. The watchdog timer does not function in the clock stop mode and halt mode. Resetting by the watchdog timer initializes all the registers except the stack overflow selection register, watchdog timer counter reset register, basic timer 0 carry register, and CE reset timer carry counter. The watchdog timer reset is detected by the WDTCY flag (R&Reset). Data Sheet U15722EJ1V1DS 323 µPD17704A, 17705A, 17707A, 17708A, 17709A 21.6.2 Watchdog timer setting flags These flags can be set only once after power-on reset on power application or reset by the RESET pin. The WDTCK0 and WDTCK1 flags select an interval at which the reset signal is output. The reference time can be selected to the following three conditions. • 655356 instructions • 131072 instructions • Watchdog timer not set On power application, 131072 instructions are selected. If the reset signal generation interval is specified to be 131072 instructions, the watchdog timer FF must be reset at intervals not exceeding 131072 instructions. The valid reset period is from 1 to 131071 instructions. If the reset signal generation interval is 65536 instructions, the watchdog timer FF must be reset at intervals not exceeding 65536 instructions. The valid reset period is from 1 to 65535 instructions. Figure 21-12. Configuration of Watchdog Timer Clock Selection Register Name Flag symbol Address Read/write 02H R/WNote b3 b2 b1 b0 Watchdog timer 0 0 clock selection W W D D T T C C K K 1 0 Selects clock of watchdog timer 0 0 Does not set watchdog timer 0 1 65536 instructions 1 0 Setting prohibited 1 1 131072 instructions After reset Fixed to 0 Power-on reset 0 0 324 1 WDT&SP reset Retained CE reset Retained Clock stop Note 1 Retained Can be written only once. Data Sheet U15722EJ1V1DS µPD17704A, 17705A, 17707A, 17708A, 17709A The WDTRES flag is used to reset the watchdog timer counter. When this flag is set to 1, the watchdog timer counter is automatically reset. If the WDTRES flag is set to 1 once within a reference time in which the WDTCK0 and WDTCK1 flags are set, the reset signal is not output by the watchdog timer. Figure 21-13. Configuration of Watchdog Timer Counter Reset Register Name Flag symbol Address Read/write 03H W&Reset b3 b2 b1 b0 Watchdog timer W 0 counter reset D 0 0 T R E S Fixed to 0 After reset Resets watchdog timer counter 0 Invalid 1 Resets watchdog timer counter Power-on reset U WDT&SP reset U CE reset U Clock stop 0 0 0 U U: Undefined Data Sheet U15722EJ1V1DS 325 µPD17704A, 17705A, 17707A, 17708A, 17709A 21.6.3 Stack pointer overflow/underflow reset A reset signal is generated if the address or interrupt stack overflows or underflows. Stack pointer overflow/underflow reset can be used to detect a program loop in the same manner as a watchdog timer reset. The reset signal is generated under the following conditions. • Interrupt due to overflow or underflow of interrupt stack (4 levels) • Interrupt due to overflow or underflow of address stack (15 levels) Reset by stack pointer overflow or underflow initializes all the registers, except the stack overflow selection register, watchdog timer counter reset register, basic timer 0 carry register, and CE reset timer carry counter. Generation of stack pointer overflow or underflow reset is detected by the WDTCY flag (R&Reset). 21.6.4 Stack pointer setting flag The stack overflow/underflow reset selection register can be set only once after power-on reset on power application or reset by the RESET pin. This register specifies whether reset by address stack overflow or underflow and reset by interrupt stack overflow or underflow are enabled or disabled. 326 Data Sheet U15722EJ1V1DS µPD17704A, 17705A, 17707A, 17708A, 17709A Figure 21-14. Configuration of Stack Overflow/Underflow Reset Selection Register Name Flag symbol Address Read/write 05H R/WNote b3 b2 b1 b0 Stack overflow/underflow 0 0 reset selection I A S S P P R R E E S S Selects address stack overflow/underflow reset 0 Disables reset 1 Enables reset Selects interrupt stack overflow/underflow reset 0 Disables reset 1 Enables reset After reset Fixed to 0 Power-on reset 0 0 1 1 WDT&SP reset Retained CE reset Retained Clock stop Note Retained Can be written only once. Data Sheet U15722EJ1V1DS 327 µPD17704A, 17705A, 17707A, 17708A, 17709A Figure 21-15. Configuration of WDT&SP Reset Selection Register Name Flag symbol Address Read/write 16H R&Reset b3 b2 b1 b0 WDT&SP reset 0 0 0 W D status detection T C Y Detects occurrence of WDT&SP reset 0 No reset request 1 Reset request After reset Fixed to 0 Power-on reset 0 0 0 0 WDT&SP reset 1 CE reset R Clock stop R R: Retained 328 Data Sheet U15722EJ1V1DS µPD17704A, 17705A, 17707A, 17708A, 17709A 21.7 Power Failure Detection Power failure detection is used to identify whether the device has been reset by application of supply voltage VDD, RESET pin, or CE pin. Because the contents of the data memory and output ports are undefined on power application, these contents are initialized by using power failure detection. Power failure detection can be performed in two ways: by detecting the BTM0CY flag or by detecting the contents of the data memory (RAM judgment). 21.7.1 and 21.7.2 describe the power failure detector and power failure detection by using the BTM0CY flag. 21.7.3 and 21.7.4 describe power failure detection by the RAM judgment method. Figure 21-16. Power Failure Detection Flowchart Program starts Power failure detection Not power failure Power failure Initializes data memory and output ports 21.7.1 Power failure detector The power failure detector consists of a voltage detector, and the basic timer 0 carry disable flip-flop that is set by the output (power-on-clear signal) of the voltage detector, and timer carry, as shown in Figure 21-1. The basic timer 0 carry disable FF is set to 1 by the power-on-clear signal, and is reset to 0 when an instruction that reads the BTM0CY flag is executed. When the basic timer 0 carry disable FF is set to 1, the BTM0CY flag is not set to 1. If the power-on-clear signal is output (at power-on reset), the program starts with the BTM0CY flag reset. After that, the BTM0CY flag is disabled from being set until an instruction that reads the flag is executed. Once the instruction that reads this flag has been executed, the BTM0CY flag is set each time the basic timer 0 carry FF setting pulse rises. Therefore, by detecting the content of the BTM0CY flag when the device is reset, whether the device has been reset by power-on reset (power failure) or CE reset (not power failure) can be identified. That is, the device has been reset by power-on reset if the BTM0CY flag has been reset to 0. It has been reset by CE reset if the flag has been set to 1. Because the voltage at which a power failure can be detected is the same as that at which power-on reset is executed, VDD = 3.5 V during crystal oscillation and VDD = 2.2 V in the clock stop status. The operation of the BTM0CY flag is the same regardless of whether the device has been reset by the RESET pin or by power-on reset. Data Sheet U15722EJ1V1DS 329 µPD17704A, 17705A, 17707A, 17708A, 17709A 21.7.2 Cautions on detecting power failure by BTM0CY flag The following points must be noted when counting the watch timer by using the BTM0CY flag. (1) Updating watch When creating a watch program using the timer carry, the watch must be updated after a power failure has been detected. This is because the BTM0CY flag is reset to 0 because it is read after a power failure has been detected. As a result, counting of the watch is overlooked once. (2) Watch updating processing time Updating the watch must be completed before the next basic timer 0 carry FF setting pulse rises. This is because CE reset is executed before the watch updating processing has been completed if the CE pin goes high during watch updating processing. For the details of (1) and (2), refer to (3) Compensating basic timer 0 carry after CE reset in 13.2.6. The following points must be noted when performing processing in case of a power failure. (3) Timing to detect power failure When counting the watch by using the BTM0CY flag, the BTM0CY flag must be read to detect a power failure before the next basic timer 0 carry FF setting pulse rises after the program has been started from address 0000H. This is because, if the basic timer 0 carry FF setting time is set to, say, 10 ms, and if the power failure is detected 11 ms after the program has been started, the BTM0CY flag is overlooked once. For further information, refer to (3) Compensating basic timer 0 carry after CE reset in 13.2.6. Power failure detection and initial processing must be performed within the time in which the basic timer 0 carry FF is set, as shown in the example below. This is because, if the CE pin rises and CE reset is executed during power failure processing or initial processing, the processing is stopped in midway, causing a problem. To update the basic timer 0 carry FF setting time in the initial processing, the instruction that changes the setting time must be executed at the end of the initial processing. This is because, if the basic timer 0 carry FF setting time is changed before the initial processing, the initial processing may not be executed to the end because CE reset may be executed. 330 Data Sheet U15722EJ1V1DS µPD17704A, 17705A, 17707A, 17708A, 17709A Example START: ; <1> ; Program address 0000H Processing at reset ; <2> SKT1 BR BACKUP: ; <3> BTM0CY INITIAL ; Power failure detection Watch updating BR INITIAL: ; <4> MAIN Initial processing ; <5> INITFLG BTM0CK1, BTM0CK0 ; Embedded macro ; Sets basic timer 0 carry FF ; Sets time to 10 ms MAIN: Main processing SKT1 BR BTM0CY MAIN Watch updating BR MAIN Operation example (if CE reset timer counter is set to 1) VDD CE 5V 0V H L 10 ms pulse 50 ms 10 ms 50 ms pulse BTM0CY flag setting pulse 50 ms H L <1> <4> <1> <3> <2> Power failure detection <2> Power failure detection If processing time of <1> + <4> is longer If processing time of <1> + <3> is than 100 ms, CE reset is executed too long, CE reset is executed. <5> in the middle of processing <4>. CE reset CE reset CE reset may be executed immediately depending on when the basic timer 0 carry FF setting time is changed. Therefore, if <5> is executed before <4>, power failure processing <4> may not be executed to the end. Data Sheet U15722EJ1V1DS 331 µPD17704A, 17705A, 17707A, 17708A, 17709A 21.7.3 Power failure detection by RAM judgment method By the RAM judgment method, a power failure is detected by judging whether the contents of the data memory at a specific address are a specific value when the device has been reset. An example of a program that detects a power failure by RAM judgment method is shown below. By the RAM judgment method, a power failure is detected by comparing an undefined value and a specific value because the contents of the data memory are undefined on application of supply voltage VDD. Therefore, a power failure may be judged by mistake by this method as described in 21.7.4 Cautions on power failure detection by RAM judgment method. Example Program example of power failure detection by RAM judgment method M012 M034 M056 M107 M128 M16F DATA0 DATA1 DATA2 DATA3 DATA4 DATA5 MEM MEM MEM MEM MEM MEM DAT DAT DAT DAT DAT DAT 0.12H 0.34H 0.56H 1.07H 1.28H 1.6FH 1010B 0101B 0110B 1001B 1100B 0011B SET2 SUB SUB SUB BANK1 SUB SUB SUB BANK0 SKF1 BR CMP, Z M012, #DATA0 M034, #DATA1 M056, #DATA2 ; If M012 = DATA0, and ; M034 = DATA1, and ; M056 = DATA2, and M107, #DATA3 M128, #DATA4 M16F, #DATA5 ; M107 = DATA3, and ; M128 = DATA4, and ; M16F = DATA5, Z BACKUP ; branches to BACKUP START: ; INITIAL: Initial processing MOV MOV MOV BANK1 MOV MOV MOV BR M012, #DATA0 M034, #DATA1 M056, #DATA2 M107, #DATA3 M128, #DATA4 M16F, #DATA5 MAIN BACKUP: Backup processing MAIN: Main processing 332 Data Sheet U15722EJ1V1DS µPD17704A, 17705A, 17707A, 17708A, 17709A 21.7.4 Cautions on power failure detection by RAM judgment method Because the values of the data memory on application of supply voltage VDD are basically undefined, the following points (1) and (2) must be noted. (1) Data to be compared Where the number of bits of the data memory to be compared by the RAM judgment method is “n bits”, the probability that the value of the data memory happens to match the value to be compared on application of VDD is (1/2)n. In other words, a power failure detected by the RAM judgment method may be judged as a backup at a probability of (1/2)n. To minimize this probability, compare as many bits as possible. Because the contents of the data memory on application of VDD are likely to be the same value such as “0000B” and “1111B”, it is recommended that the data to be compared consist of a combination of “0”s and “1”s, such as “1010B” and “0110B”. (2) Cautions on program If VDD rises from a level at which the contents of the data memory are corrupted as shown in Figure 21-17, even if the value of the data memory to be compared is normal, the other parts of the data memory may be corrupted. If a power failure detection is performed by the RAM judgment method at this time, it is judged to be a backup. Therefore, the program must be designed so that a program loop does not occur even if the contents of the data memory are corrupted. Figure 21-17. VDD and Corruption of Data Memory Contents 5V VDD Data memory corruption start voltage 0V Data memory Data memory for RAM judgment (normal) Values of data memory addresses not used for RAM judgment may be corrupted. (3) Cautions on using RESET pin Caution If the device is reset by the RESET pin during program execution, the data in the data memory may be corrupted. Therefore, be careful when resetting with the RESET pin. Data Sheet U15722EJ1V1DS 333 µPD17704A, 17705A, 17707A, 17708A, 17709A 22. INSTRUCTION SET 22.1 Outline of Instruction Set b14 to b11 b15 BIN HEX 0000 0 ADD r,m ADD m,#n4 0001 1 SUB r,m SUB m, #n4 0010 2 ADDC r,m ADDC m,#n4 0011 3 SUBC r,m SUBC m,#n4 0100 4 AND r,m AND m,#n4 0101 5 XOR r,m XOR m,#n4 0110 6 OR r,m OR m,#n4 INC INC RORC MOVT PUSH AR IX r DBF,@AR AR POP GET PUT PEEK POKE BR CALL SYSCALNote RET RETSK RETI EI DI STOP HALT NOP AR DBF,p p,DBF WR,rf rf,WR @AR @AR entry 0111 7 0 1 s h 1000 8 LD r,m ST m,r 1001 9 SKE m,#n4 SKGE m,#n4 1010 A MOV @r,m MOV m,@r 1011 B SKNE m,#n4 SKLT m,#n4 1100 C BR addr (page 0) CALL addr (page 0) 1101 D BR addr (page 1) MOV m,#n4 1110 E BR addr (page 2) SKT m,#n4 1111 F BR addr (page 3) SKF m,#n Remark The system call instruction is not available in the µPD17704A. 334 Data Sheet U15722EJ1V1DS µPD17704A, 17705A, 17707A, 17708A, 17709A 22.2 Legend AR: Address register ASR: Address stack register indicated by stack pointer addr: Program memory address (lower 11 bits) BANK: Bank register CMP: Compare flag CY: Carry flag DBF: Data buffer entry: Program memory address (bits 10 to 8, bits 3 to 0) entryH: Program memory address (bits 10 to 8) entryL: Program memory address (bits 3 to 0) h: Halt release condition INTEF: Interrupt enable flag INTR: Register automatically saved to stack when interrupt occurs INTSK: Interrupt stack register IX: Index register MP: MPE: m: Data memory row address pointer Memory pointer enable flag Data memory address indicated by mR, mC mR: Data memory row address (higher) mC: Data memory column address (lower) n: Bit position (4 bits) n4: Immediate data (4 bits) PAGE: Page (bits 12 and 11 of program counter) PC: Program counter P: Peripheral address p H: Peripheral address (higher 3 bits) p L: Peripheral address (lower 4 bits) r: General register column address rf: Register file address rfR: Register file row address (higher 3 bits) rfC: Register file column address (lower 4 bits) SGR: Segment register (bit 13 of program counter) SP: Stack pointer s: Stop release condition WR: Window register (x): Contents addressed by x Data Sheet U15722EJ1V1DS 335 µPD17704A, 17705A, 17707A, 17708A, 17709A 22.3 Instruction List Instructions Mnemonic Operand Operation Instruction Code Op Code Operand r,m (r) ← (r) + (m) 00000 mR mC r m,#n4 (m) ← (m) + n4 10000 mR mC n4 r,m (r) ← (r) + (m) + CY 00010 mR mC r m,#n4 (m) ← (m) + n4 + CY 10010 mR mC n4 AR AR ← AR + 1 00111 000 1001 0000 IX IX ← IX + 1 00111 000 1000 0000 r,m (r) ← (r) – (m) 00001 mR mC r m,#n4 (m) ← (m) – n4 10001 mR mC n4 r,m (r) ← (r) – (m) – CY 00011 mR mC r m,#n4 (m) ← (m) – n4 – CY 10011 mR mC n4 r,m (r) ← (r) v (m) 00110 mR mC r m,#n4 (m) ← (m) v n4 10110 mR mC n4 r,m (r) ← (r) (m) 00100 mR mC r m,#n4 (m) ← (m) n4 10100 mR mC n4 r,m (r) ← (r) v (m) 00101 mR mC r m,#n4 (m) ← (m) v n4 10101 mR mC n4 SKT m,#n CMP ← 0, if (m) v n = n, then skip 11110 mR mC n SKF m,#n CMP ← 0, if (m) v n = 0, then skip 11111 mR mC n SKE m,#n4 (m) – n4, skip if zero 01001 mR mC n4 SKNE m,#n4 (m) – n4, skip if not zero 01011 mR mC n4 SKGE m,#n4 (m) – n4, skip if not borrow 11001 mR mC n4 SKLT m,#n4 (m) – n4, skip if borrow 11011 mR mC n4 Rotate RORC r 00111 000 0111 r Transfer LD r,m (r) ← (m) 01000 mR mC r ST m,r (m) ← (r) 11000 mR mC r MOV @r,m if MPE = 1 : (MP, (r)) ← (m) if MPE = 0 : (BANK, mR, (r)) ← (m) 01010 mR mC r m, @r if MPE = 1 : (m) ← (MP, (r)) if MPE = 0 : (m) ← (BANK, mR, (r)) 11010 mR mC r m,#n4 (m) ← n4 11101 mR mC n4 MOVT DBF,@AR SP ← SP – 1, ASR ← PC, PC ← AR, DBF ← (PC), PC ← ASR, SP ← SP + 1 00111 000 0001 0000 PUSH AR SP ← SP – 1, ASR ← AR 00111 000 1101 0000 POP AR AR ← ASR, SP ← SP + 1 00111 000 1100 0000 GET DBF,p DBF ← (p) 00111 pH 1011 pL PUT p,DBF (p) ← DBF 00111 pH 1010 pL PEEK WR,rf WR ← (rf) 00111 rfR 0011 rfC POKE rf,WR (rf) ← WR 00111 rfR 0010 rfC ADDC INC Subtract SUB SUBC Logical OR operation AND XOR Judge Compare 336 v ADD v Add CY ← (r) b3 ← (r) b2 ← (r) b1 ← (r) b0 Data Sheet U15722EJ1V1DS µPD17704A, 17705A, 17707A, 17708A, 17709A Instructions Mnemonic Branch BR Subroutine CALL SYSCALNote Interrupt Others Operand Operation Instruction Code Op Code Operand PC10–0 ← addr, PAGE ← 0 01100 addr PC10–0 ← addr, PAGE ← 1 01101 PC10–0 ← addr, PAGE ← 2 01110 PC10–0 ← addr, PAGE ← 3 01111 @AR PC ← AR 00111 addr SP ← SP – 1, ASR ← PC PC11 ← 0, PC10–0 ← addr 11100 @AR SP ← SP – 1, ASR ← PC PC ← AR 00111 000 0101 0000 entry SP ← SP – 1, ASR ← PC, SGR ← 1 PC12, 11 ← 0, PC10–8 ← entryH, PC7–4 ← 0, PC3–0 ← entryL 00111 entryH 0010 entryL addr 000 0100 0000 addr RET PC ← ASR, SP ← SP + 1 00111 000 1110 0000 RETSK PC ← ASR, SP ← SP + 1 and skip 00111 001 1110 0000 RETI PC ← ASR, INTR ← INTSK, SP ← SP + 1 00111 010 1110 0000 EI INTEF ← 1 00111 000 1111 0000 DI INTEF ← 0 00111 001 1111 0000 00111 010 1111 s STOP s STOP HALT h HALT 00111 011 1111 h No operation 00111 100 1111 0000 NOP Remark The system call instruction is not available in the µPD17704A. Data Sheet U15722EJ1V1DS 337 µPD17704A, 17705A, 17707A, 17708A, 17709A 22.4 Assembler (RA17K) Embedded Macro Instruction Legend flag n: FLG symbol n: Bit number < >: Can be omitted Mnemonic Operand Operation n Embedded SKTn flag 1, ... flag n If (flag1) to (flag n) = all “1”, then skip 1≤n≤4 macro SKFn flag 1, ... flag n If (flag 1) to (flag n) = all “0”, then skip 1≤n≤4 SETn flag 1, ... flag n (flag 1) to (flag n) ← 1 1≤n≤4 CLRn flag 1, ... flag n (flag 1) to (flag n) ← 0 1≤n≤4 NOTn flag 1, ... flag n If (flag n) = “0”, then (flag n) ← 1 If (flag n) = “1”, then (flag n) ← 0 1≤n≤4 INITFLG <NOT> flag 1, ... <<NOT> flag n> If description = NOT flag n, then (flag n) ← 0 If description = flag n, then (flag n) ← 1 1≤n≤4 (BANK) ← n BANKn 0 ≤ n ≤ 15 Expanded BRX Label Jump label — instruction CALLX function-name CALL sub routine — function-name or CALL system sub routine — SYSCALX expression INITFLGX 338 <NOT/INV> flag 1, ... <NOT/INV> flag n If description = NOT (or INV) flag, (flag) ← 0 If description = flag, (flag) ← 1 Data Sheet U15722EJ1V1DS n≤4 µPD17704A, 17705A, 17707A, 17708A, 17709A 23. RESERVED SYMBOLS 23.1 Data Buffer (DBF) Symbol Name Attribute Value R/W Description DBF3 MEM 0.0CH R/W Bits 15 to 12 of data buffer DBF2 MEM 0.0DH R/W Bits 11 to 8 of data buffer DBF1 MEM 0.0EH R/W Bits 7 to 4 of data buffer DBF0 MEM 0.0FH R/W Bits 3 to 0 of data buffer 23.2 System Registers (SYSREG) Symbol Name Attribute Value R/W Description AR3 MEM 0.74H R/W Bits 15 to 12 of address register AR2 MEM 0.75H R/W Bits 11 to 8 of address register AR1 MEM 0.76H R/W Bits 7 to 4 of address register AR0 MEM 0.77H R/W Bits 3 to 0 of address register WR MEM 0.78H R/W Window register BANK MEM 0.79H R/W Bank register IXH MEM 0.7AH R/W Bits 10 through 8 of index register MPH MEM 0.7AH R/W Bits 6 through 4 of memory pointer MPE FLG 0.7AH.3 R/W Memory pointer enable flag IXM MEM 0.7BH R/W Bits 7 to 4 of index register MPL MEM 0.7BH R/W Bits 3 to 0 of memory pointer IXL MEM 0.7CH R/W Bits 3 to 0 of index register RPH MEM 0.7DH R/W Bits 6 to 3 of general register pointer RPL MEM 0.7EH R/W Bits 2 to 0 of general register pointer BCD FLG 0.7EH.0 R/W BCD operation flag PSW MEM 0.7FH R/W Program status word CMP FLG 0.7FH.3 R/W Compare flag CY FLG 0.7FH.2 R/W Carry flag Z FLG 0.7FH.1 R/W Zero flag IXE FLG 0.7FH.0 R/W Index enable flag Data Sheet U15722EJ1V1DS 339 µPD17704A, 17705A, 17707A, 17708A, 17709A 23.3 Port Registers Symbol Name Attribute P0A3 FLG Value 0.70H.3 R/W R/W Description Bit 3 of port 0A –––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––– P0A2 FLG 0.70H.2 R/W Bit 2 of port 0A –––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––– P0A1 FLG 0.70H.1 R/W Bit 1 of port 0A –––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––– P0A0 FLG 0.70H.0 R/W Bit 0 of port 0A P0B3 FLG 0.71H.3 R/W Bit 3 of port 0B –––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––– P0B2 FLG 0.71H.2 R/W Bit 2 of port 0B –––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––– P0B1 FLG 0.71H.1 R/W Bit 1 of port 0B –––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––– P0B0 FLG 0.71H.0 R/W Bit 0 of port 0B P0C3 FLG 0.72H.3 R/W Bit 3 of port 0C –––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––– P0C2 FLG 0.72H.2 R/W Bit 2 of port 0C –––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––– P0C1 FLG 0.72H.1 R/W Bit 1 of port 0C –––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––– P0C0 P0D3 FLG FLG 0.72H.0 R/W Bit 0 of port 0C 0.73H.3 RNote Bit 3 of port 0D –––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––– P0D2 FLG 0.73H.2 RNote Bit 2 of port 0D –––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––– P0D1 FLG 0.73H.1 RNote Bit 1 of port 0D –––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––– P0D0 P1A3 FLG FLG 0.73H.0 RNote Bit 0 of port 0D 1.70H.3 RNote Bit 3 of port 1A –––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––– P1A2 FLG 1.70H.2 RNote Bit 2 of port 1A –––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––– P1A1 FLG 1.70H.1 RNote Bit 1 of port 1A –––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––– P1A0 FLG 1.70H.0 RNote P1B3 FLG 1.71H.3 R/W Bit 0 of port 1A Bit 3 of port 1B –––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––– P1B2 FLG 1.71H.2 R/W Bit 2 of port 1B –––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––– P1B1 FLG 1.71H.1 R/W Bit 1 of port 1B –––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––– P1B0 P1C3 FLG FLG 1.71H.0 R/W Bit 0 of port 1B 1.72H.3 RNote Bit 3 of port 1C –––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––– P1C2 FLG 1.72H.2 RNote Bit 2 of port 1C –––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––– P1C1 FLG 1.72H.1 RNote Bit 1 of port 1C –––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––– P1C0 Note FLG 1.72H.0 R/W Bit 0 of port 1C These are input ports. However, even if an instruction that outputs data to these ports is described, the assembler and in-circuit emulator do not output an error message. Moreover, nothing is affected in terms of operation even if such an instruction is actually executed on the device. 340 Data Sheet U15722EJ1V1DS µPD17704A, 17705A, 17707A, 17708A, 17709A Symbol Name Attribute P1D3 FLG Value 1.73H.3 R/W R/W Description Bit 3 of port 1D –––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––– P1D2 FLG 1.73H.2 R/W Bit 2 of port 1D –––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––– P1D1 FLG 1.73H.1 R/W Bit 1 of port 1D –––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––– P1D0 FLG 1.73H.0 R/W Bit 0 of port 1D P2A2 FLG 2.70H.2 R/W Bit 2 of port 2A –––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––– P2A1 FLG 2.70H.1 R/W Bit 1 of port 2A –––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––– P2A0 FLG 2.70H.0 R/W Bit 0 of port 2A P2B3 FLG 2.71H.3 R/W Bit 3 of port 2B –––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––– P2B2 FLG 2.71H.2 R/W Bit 2 of port 2B –––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––– P2B1 FLG 2.71H.1 R/W Bit 1 of port 2B –––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––– P2B0 FLG 2.71H.0 R/W Bit 0 of port 2B P2C3 FLG 2.72H.3 R/W Bit 3 of port 2C P2C2 FLG 2.72H.2 R/W Bit 2 of port 2C P2C1 FLG 2.72H.1 R/W Bit 1 of port 2C P2C0 FLG 2.72H.0 R/W Bit 0 of port 2C P2D2 FLG 2.73H.2 R/W Bit 2 of port 2D –––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––– –––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––– –––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––– –––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––– P2D1 FLG 2.73H.1 R/W Bit 1 of port 2D –––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––– P2D0 FLG 2.73H.0 R/W Bit 0 of port 2D P3A3 FLG 3.70H.3 R/W Bit 3 of port 3A –––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––– P3A2 FLG 3.70H.2 R/W Bit 2 of port 3A –––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––– P3A1 FLG 3.70H.1 R/W Bit 1 of port 3A –––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––– P3A0 FLG 3.70H.0 R/W Bit 0 of port 3A P3B3 FLG 3.71H.3 R/W Bit 3 of port 3B –––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––– P3B2 FLG 3.71H.2 R/W Bit 2 of port 3B –––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––– P3B1 FLG 3.71H.1 R/W Bit 1 of port 3B –––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––– P3B0 FLG 3.71H.0 R/W Bit 0 of port 3B P3C3 FLG 3.72H.3 R/W Bit 3 of port 3C –––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––– P3C2 FLG 3.72H.2 R/W Bit 2 of port 3C –––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––– P3C1 FLG 3.72H.1 R/W Bit 1 of port 3C –––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––– P3C0 FLG 3.72H.0 R/W Bit 0 of port 3C P3D3 FLG 3.73H.3 R/W Bit 3 of port 3D –––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––– P3D2 FLG 3.72H.2 R/W Bit 2 of port 3D –––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––– P3D1 FLG 3.73H.1 R/W Bit 1 of port 3D –––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––– P3D0 FLG 3.73H.0 R/W Bit 0 of port 3D Data Sheet U15722EJ1V1DS 341 µPD17704A, 17705A, 17707A, 17708A, 17709A 23.4 Register File (Control Registers) Symbol Name Attribute Value R/W Description SP MEM 0.81H R/W Stack pointer WDTCK MEM 0.82H R/W Watchdog timer clock selection flag (can be set only once after power application) WDTCK1 FLG 0.82H.1 R/W Watchdog timer clock selection flag (can be set only once after power application) – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – ––– – – – – – – – – – – – WDTCK0 FLG 0.82H.0 R/W Watchdog timer clock selection flag (can be set only once after power application) WDTRES FLG 0.83H.3 R/W Watchdog timer counter reset (when read: 0) DBFSP MEM 0.84H R SPRSEL MEM 0.85H R/W Stack overflow/underflow reset selection flag (can be set only once after power application) ISPRES FLG 0.85H.1 R/W Stack overflow/underflow reset selection flag (can be set only once after power application) DBF stack pointer – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – ––– – – – – – – – – – – – ASPRES FLG 0.85H.0 R/W Stack overflow/underflow reset selection flag (can be set only once after power application) CECNT3 FLG 0.86H.3 R/W CE reset timer carry counter – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – ––– – – – – – – – – – – – CECNT2 FLG 0.86H.2 R/W CE reset timer carry counter – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – ––– – – – – – – – – – – – CECNT1 FLG 0.86H.1 R/W CE reset timer carry counter – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – ––– – – – – – – – – – – – CECNT0 FLG 0.86H.0 R/W CE reset timer carry counter MOVTSEL1 FLG 0.87H.1 R/W MOVT bit selection flag –––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––– MOVTSEL0 FLG 0.87H.0 R/W MOVT bit selection flag SYSRSP MEM 0.88H R System register stack pointer SIO0WSTT FLG 0.8AH.0 R Serial interface 0 wait status judgment flag SBMD FLG 0.8BH.2 R/W I2C bus slave transmission operation mode selection flag – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – ––– – – – – – – – – – – – SIO0CK1 FLG 0.8BH.1 R/W Serial interface 0 I/O clock selection flag – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – ––– – – – – – – – – – – – SIO0CK0 FLG 0.8BH.0 R/W Serial interface 0 I/O clock selection flag SIO0IMD3 FLG 0.8CH.3 R/W Serial interface 0 interrupt mode selection flag (dummy) – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – ––– – – – – – – – – – – – SIO0IMD2 FLG 0.8CH.2 R/W Serial interface 0 interrupt mode selection flag (dummy) – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – ––– – – – – – – – – – – – SIO0IMD1 FLG 0.8CH.1 R/W Serial interface 0 interrupt mode selection flag –––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––– SIO0IMD0 FLG 0.8CH.0 R/W SIO0SF8 FLG 0.8DH.3 R Serial interface 0 interrupt mode selection flag 8-count detection flag of serial interface 0 clock counter – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – ––– – – – – – – – – – – – SIO0SF9 FLG 0.8DH.2 R 9-count detection flag of serial interface 0 clock counter SBSTT FLG 0.8DH.1 R Serial interface 0 (I2C mode) communication status detection flag (1: Start condition detected) –––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––– SBBSY FLG 0.8DH.0 R SBACK FLG 0.8EH.3 R/W` Serial interface 0 (I2C mode) communication status detection flag (1: Start condition detected, 0: Stop condition detected) Serial interface 0 (I2C mode) ACK signal setting/detection flag – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – ––– – – – – – – – – – – – SIO0NWT FLG 0.8EH.2 R/W Serial interface 0 wait status setting/detection flag (1: Wait status released (no wait)) – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – ––– – – – – – – – – – – – SIO0WRQ1 FLG 0.8EH.1 R/W Bit 1 of serial interface 0 wait condition setting flag – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – ––– – – – – – – – – – – – SIO0WRQ0 342 FLG 0.8EH.0 R/W Bit 0 of serial interface 0 wait condition setting flag Data Sheet U15722EJ1V1DS µPD17704A, 17705A, 17707A, 17708A, 17709A Symbol Name Attribute SIO0CH FLG Value 0.8FH.3 R/W R/W Description Serial interface 0 mode selection flag –––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––– SB FLG 0.8FH.2 R/W Serial interface 0 mode selection flag –––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––– SIO0MS FLG 0.8FH.1 R/W Serial interface 0 shift clock mode selection flag –––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––– SIO0TX FLG 0.8FH.0 R/W Serial interface 0 transmission (TX)/reception (RX) selection flag PLLSCNF FLG 0.90H.3 R/W Swallow counter least significant bit setting flag –––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––– PLLMD1 FLG 0.90H.1 R/W PLL mode selection flag –––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––– PLLMD0 FLG 0.90H.0 R/W PLL mode selection flag PLLRFCK3 FLG 0.91H.3 R/W PLL reference frequency selection flag –––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––– PLLRFCK2 FLG 0.91H.2 R/W PLL reference frequency selection flag –––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––– PLLRFCK1 FLG 0.91H.1 R/W PLL reference frequency selection flag –––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––– PLLRFCK0 FLG 0.91H.0 PLLUL FLG 0.92H.0 BEEP1SEL FLG 0.93H.1 R/W PLL reference frequency selection flag R&Reset PLL unlock FF flag R/W BEEP1/general-purpose port pin function selection flag –––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––– BEEP0SEL FLG 0.93H.0 R/W BEEP0/general-purpose port pin function selection flag BEEP1CK1 FLG 0.94H.3 R/W BEEP1 clock selection flag –––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––– BEEP1CK0 FLG 0.94H.2 R/W BEEP1 clock selection flag –––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––– BEEP0CK1 FLG 0.94H.1 R/W BEEP0 clock selection flag –––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––– BEEP0CK0 FLG 0.94H.0 R/W BEEP0 clock selection flag WDTCY FLG 0.96H.0 R Watchdog timer/stack pointer reset status detection flag BTM0CY FLG 0.97H.0 R Basic timer 0 carry flag BTM0CK1 FLG 0.98H.1 R/W Basic timer 0 clock selection flag –––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––– BTM0CK0 FLG 0.98H.0 R/W Basic timer 0 clock selection flag SIO1TS FLG 0.9DH.3 R/W Serial interface 1 transmission/reception start flag –––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––– SIO1HIZ FLG 0.9DH.2 R/W Serial interface 1/general-purpose port selection flag –––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––– SIO1CK1 FLG 0.9DH.1 R/W Serial interface 1 I/O clock selection flag –––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––– SIO1CK0 FLG 0.9DH.0 R/W Serial interface 1 I/O clock selection flag IEG4 FLG 0.9EH.3 R/W Edge direction selection flag for INT4 pin interrupt request detection –––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––– INT4SEL FLG 0.9EH.2 R/W INT4 pin interrupt request flag setting disable –––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––– IEG3 FLG 0.9EH.1 R/W Edge direction selection flag for INT3 pin interrupt request detection –––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––– INT3SEL FLG 0.9EH.0 R/W INT3 pin interrupt request flag setting disable IEG2 FLG 0.9FH.2 R/W Edge direction selection flag for INT2 pin interrupt request detection –––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––– IEG1 FLG 0.9FH.1 R/W Edge direction selection flag for INT1 pin interrupt request detection –––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––– IEG0 FLG 0.9FH.0 R/W Edge direction selection flag for INT0 pin interrupt request detection FCGCH1 FLG 0.0A0H.1 R/W FGC channel selection flag –––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––– FCGCH0 FLG 0.0A0H.0 R/W IFCGOSTT FLG 0.0A1H.0 R FGC channel selection flag IF counter gate status detection flag (1: Open, 0: Closed) Data Sheet U15722EJ1V1DS 343 µPD17704A, 17705A, 17707A, 17708A, 17709A Symbol Name Attribute IFCMD1 FLG Value R/W 0.0A2H.3 R/W Description IF counter mode selection flag (10: AMIF, 11: FCG) –––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––– IFCMD0 FLG 0.0A2H.2 R/W IF counter mode selection flag (00: CGP, 11: FMIF) –––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––– IFCCK1 FLG 0.0A2H.1 R/W IF counter clock selection flag –––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––– IFCCK0 FLG 0.0A2H.0 R/W IFCSTRT FLG 0.0A3H.1 W IF counter clock selection flag IF counter count start flag –––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––– IFCRES ADCCH3 FLG FLG 0.0A3H.0 0.0A4H.3 W R/W IF counter reset flag A/D converter channel selection flag (dummy) –––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––– ADCCH2 FLG 0.0A4H.2 R/W A/D converter channel selection flag –––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––– ADCCH1 FLG 0.0A4H.1 R/W A/D converter channel selection flag –––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––– ADCCH0 FLG 0.0A4H.0 R/W A/D converter channel selection flag ADCMD FLG 0.0A5H.2 R/W A/D converter compare mode selection flag –––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––– ADCSTT FLG 0.0A5H.1 R A/D converter operation status detection flag (0: End of conversion, 1: Conversion in progress) –––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––– ADCCMP FLG 0.0A5H.0 R PWMBIT FLG 0.0A6H.2 R/W A/D converter compare result detection flag PWM counter bit selection flag (0: 8 bits, 1: 9 bits) –––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––– PWMCK FLG 0.0A6H.0 R/W PWM timer output clock selection flag PWM2SEL FLG 0.0A7H.2 R/W PWM2/general-purpose port pin function selection flag –––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––– PWM1SEL FLG 0.0A7H.1 R/W PWM1/general-purpose port pin function selection flag –––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––– PWM0SEL FLG 0.0A7H.0 R/W PWM0/general-purpose port pin function selection flag TM3SEL FLG 0.0A8H.3 R/W PWM/modulo timer 3 selection flag TM3EN FLG 0.0A8H.1 R/W Modulo timer 3 count start flag TM3RES FLG 0.0A8H.0 R/W Modulo timer 3 reset flag (when read: 0) –––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––– –––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––– TM2EN FLG 0.0A9H.3 R/W Modulo timer 2 count start flag –––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––– TM2RES FLG 0.0A9H.2 R/W Modulo timer 2 reset flag (when read: 0) –––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––– TM2CK1 FLG 0.0A9H.1 R/W Modulo timer 2 clock selection flag –––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––– TM2CK0 FLG 0.0A9H.0 R/W Modulo timer 2 clock selection flag TM1EN FLG 0.0AAH.3 R/W Modulo timer 1 count start flag –––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––– TM1RES FLG 0.0AAH.2 R/W Modulo timer 1 reset flag (when read: 0) –––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––– TM1CK1 FLG 0.0AAH.1 R/W Modulo timer 1 clock selection flag –––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––– TM1CK0 FLG 0.0AAH.0 R/W Modulo timer 1 clock selection flag TM0EN FLG 0.0ABH.3 R/W Modulo timer 0 count start flag –––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––– TM0RES FLG 0.0ABH.2 R/W Modulo timer 0 reset flag (when read: 0) –––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––– TM0CK1 FLG 0.0ABH.1 R/W Modulo timer 0 clock selection flag –––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––– TM0CK0 FLG 0.0ABH.0 TM0OVF FLG 0.0ACH.3 R/W R Modulo timer 0 clock selection flag Modulo timer 0 overflow detection flag –––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––– TM0GCEG FLG 0.0ACH.2 R/W Modulo timer 0 gate close input signal edge selection flag –––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––– TM0GOEG FLG 0.0ACH.1 R/W Modulo timer 0 gate open input signal edge selection flag –––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––– TM0MD 344 FLG 0.0ACH.0 R/W Modulo timer 0 modulo counter/gate counter selection flag Data Sheet U15722EJ1V1DS µPD17704A, 17705A, 17707A, 17708A, 17709A Symbol Name Attribute Value R/W Description IPSIO1 FLG 0.0ADH.3 R/W Serial interface 1 interrupt enable flag IPSIO0 FLG 0.0ADH.2 R/W Serial interface 0 interrupt enable flag IPTM3 FLG 0.0ADH.1 R/W PWM timer interrupt enable flag IPTM2 FLG 0.0ADH.0 R/W Modulo timer 2 interrupt enable flag IPTM1 FLG 0.0AEH.3 R/W Modulo timer 1 interrupt enable flag –––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––– –––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––– –––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––– –––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––– IPTM0 FLG 0.0AEH.2 R/W Modulo timer 0 interrupt enable flag –––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––– IP4 FLG 0.0AEH.1 R/W INT4 pin interrupt enable flag –––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––– IP3 FLG 0.0AEH.0 R/W INT3 pin interrupt enable flag IP2 FLG 0.0AFH.3 R/W INT2 pin interrupt enable flag –––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––– IP1 FLG 0.0AFH.2 R/W INT1 pin interrupt enable flag –––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––– IP0 FLG 0.0AFH.1 R/W INT0 pin interrupt enable flag –––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––– IPCE FLG 0.0AFH.0 R/W CE pin interrupt enable flag IRQSIO1 FLG 0.0B4H.0 R/W Serial interface 1 interrupt request detection flag IRQSIO0 FLG 0.0B5H.0 R/W Serial interface 0 interrupt request detection flag IRQTM3 FLG 0.0B6H.0 R/W PWM timer interrupt request detection flag IRQTM2 FLG 0.0B7H.0 R/W Modulo timer 2 interrupt request detection flag IRQTM1 FLG 0.0B8H.0 R/W Modulo timer 1 interrupt request detection flag IRQTM0 FLG 0.0B9H.0 R/W Modulo timer 0 interrupt request detection flag INT4 FLG 0.0BAH.3 R INT4 pin status detection flag –––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––– IRQ4 FLG 0.0BAH.0 R/W INT3 FLG 0.0BBH.3 R INT4 pin interrupt request detection flag INT3 pin status detection flag –––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––– IRQ3 FLG 0.0BBH.0 R/W INT2 FLG 0.0BCH.3 R INT3 pin interrupt request detection flag INT2 pin status detection flag –––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––– IRQ2 FLG 0.0BCH.0 R/W INT1 FLG 0.0BDH.3 R INT2 pin interrupt request detection flag INT1 pin status detection flag –––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––– IRQ1 FLG 0.0BDH.0 R/W INT0 FLG 0.0BEH.3 R INT1 pin interrupt request detection flag INT0 pin status detection flag –––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––– IRQ0 FLG 0.0BEH.0 R/W CE FLG 0.0BFH.3 R INT0 pin interrupt request detection flag CE pin status detection flag –––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––– CECNTSTT FLG 0.0BFH.1 R CE reset counter status detection flag –––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––– IRQCE FLG 0.0BFH.0 R/W CE pin interrupt request detection flag P0DPLD3 FLG 15.66H.3 R/W P0D3 pin pull-down resistor selection flag –––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––– P0DPLD2 FLG 15.66H.2 R/W P0D2 pin pull-down resistor selection flag –––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––– P0DPLD1 FLG 15.66H.1 R/W P0D1 pin pull-down resistor selection flag –––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––– P0DPLD0 FLG 15.66H.0 R/W P0D0 pin pull-down resistor selection flag Data Sheet U15722EJ1V1DS 345 µPD17704A, 17705A, 17707A, 17708A, 17709A Symbol Name Attribute P3DGIO FLG Value R/W 15.67H.3 R/W Description P3D I/O selection flag –––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––– P3CGIO FLG 15.67H.2 R/W P3C I/O selection flag –––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––– P3BGIO FLG 15.67H.1 R/W P3B I/O selection flag –––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––– P3AGIO FLG 15.67H.0 R/W P3A I/O selection flag P2DBIO3 FLG 15.68H.3 R/W P2D3 I/O selection flag (dummy) –––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––– P2DBIO2 FLG 15.68H.2 R/W P2D2 I/O selection flag –––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––– P2DBIO1 FLG 15.68H.1 R/W P2D1 I/O selection flag –––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––– P2DBIO0 FLG 15.68H.0 R/W P2D0 I/O selection flag P2CBIO3 FLG 15.69H.3 R/W P2C3 I/O selection flag –––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––– P2CBIO2 FLG 15.69H.2 R/W P2C2 I/O selection flag –––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––– P2CBIO1 FLG 15.69H.1 R/W P2C1 I/O selection flag –––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––– P2CBIO0 FLG 15.69H.0 R/W P2C0 I/O selection flag P2BBIO3 FLG 15.6AH.3 R/W P2B3 I/O selection flag –––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––– P2BBIO2 FLG 15.6AH.2 R/W P2B2 I/O selection flag –––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––– P2BBIO1 FLG 15.6AH.1 R/W P2B1 I/O selection flag –––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––– P2BBIO0 FLG 15.6AH.0 R/W P2B0 I/O selection flag P2ABIO3 FLG 15.6BH.3 R/W P2A3 I/O selection flag (dummy) –––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––– P2ABIO2 FLG 15.6BH.2 R/W P2A2 I/O selection flag –––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––– P2ABIO1 FLG 15.6BH.1 R/W P2A1 I/O selection flag –––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––– P2ABIO0 FLG 15.6BH.0 R/W P2A0 I/O selection flag P1DBIO3 FLG 15.6CH.3 R/W P1D3 I/O selection flag –––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––– P1DBIO2 FLG 15.6CH.2 R/W P1D2 I/O selection flag –––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––– P1DBIO1 FLG 15.6CH.1 R/W P1D1 I/O selection flag –––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––– P1DBIO0 FLG 15.6CH.0 R/W P1D0 I/O selection flag P0CBIO3 FLG 15.6DH.3 R/W P0C3 I/O selection flag –––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––– P0CBIO2 FLG 15.6DH.2 R/W P0C2 I/O selection flag –––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––– P0CBIO1 FLG 15.6DH.1 R/W P0C1 I/O selection flag –––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––– P0CBIO0 FLG 15.6DH.0 R/W P0C0 I/O selection flag P0BBIO3 FLG 15.6EH.3 R/W P0B3 I/O selection flag –––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––– P0BBIO2 FLG 15.6EH.2 R/W P0B2 I/O selection flag –––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––– P0BBIO1 FLG 15.6EH.1 R/W P0B1 I/O selection flag –––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––– P0BBIO0 FLG 15.6EH.0 R/W P0B0 I/O selection flag P0ABIO3 FLG 15.6FH.3 R/W P0A3 I/O selection flag –––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––– P0ABIO2 FLG 15.6FH.2 R/W P0A2 I/O selection flag –––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––– P0ABIO1 FLG 15.6FH.1 R/W P0A1 I/O selection flag –––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––– P0ABIO0 346 FLG 15.6FH.0 R/W P0A0 I/O selection flag Data Sheet U15722EJ1V1DS µPD17704A, 17705A, 17707A, 17708A, 17709A 23.5 Peripheral Hardware Registers Symbol Name Attribute Value R/W Description ADCR DAT 02H R/W A/D converter reference voltage setting register SIO0SFR DAT 03H R/W Serial interface 0 presettable shift register SIO1SFR DAT 04H R/W Serial interface 1 presettable shift register TM0M DAT 1AH R/W Timer modulo 0 register TM0C DAT 1BH R Timer modulo 0 counter TM1M DAT 1CH R/W Timer modulo 1 register TM1C DAT 1DH R Timer modulo 1 counter TM2M DAT 1EH R/W Timer modulo 2 register TM2C DAT 1FH R Timer modulo 2 counter AR DAT 40H R/W Address register DBFSTK DAT 41H R/W DBF stack register PLLR DAT 42H R/W PLL data register IFC DAT 43H R PWMR0 DAT 44H R/W PWM0 data register PWMR1 DAT 45H R/W PWM1 data register PWMR2 DAT 46H R/W PWM2 data register TM3M DAT 46H R/W Timer modulo 3 register IF counter data register 23.6 Others Symbol Name Attribute Value Description DBF DAT 0FH Operand of GET/PUT/MOVT/MOVTH/MOVL instruction (DBF) IX DAT 01H Operand of INC instruction (IX) AR_EPA1 DAT 8040H Operand of CALL/BR/MOVT/MOVTH/MOVTL instruction (EPA bit on) AR_EPA0 DAT 4040H Operand of CALL/BR/MOVT/MOVTH/MOVTL instruction (EPA bit off) Data Sheet U15722EJ1V1DS 347 µPD17704A, 17705A, 17707A, 17708A, 17709A 24. ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings (TA = 25°C) Parameter Supply voltage Input voltage Symbol Conditions Ratings Unit –0.3 to +6.0 V Other than CE, INT0 to INT4, and RESET pins –0.3 to VDD + 0.3 V CE, INT0 to INT4, and RESET pins –0.3 to VDD + 0.6 V –0.3 to VDD + 0.3 mA VDD VI Output voltage VO Except P1B0 to P1B3 Output current, high IOH Per pin –8.0 mA Total of P2A0 to P2A2, P3A0 to P3A3, and P3B0 to P3B3 –15.0 mA Total of P0A0 to P0A3, P0B0 to P0B3, P0C0 to P0C3, P1D0 to P1D3, P2B0 to P2B3, P2C0 to P2C3, P2D0 to P2D2, P3C0 to P3C3, and P3D0 to P3D3 –25.0 mA Per pin for P1B0 to P1B3 12.0 mA Per pin for P1B0 to P1B3 8.0 mA Total of P2A0 to P2A2, P3A0 to P3A3, 15.0 mA Total of P0A0 to P0A3, P0B0 to P0B3, P0C0 to P0C3, P1D0 to P1D3, P2B0 to P2B3, P2C0 to P2C3, P2D0 to P2D2, P3C0 to P3C3, and P3D0 to P3D3 25.0 mA Total of P1B0 to P1B3 pins 25.0 mA P1B0 to P1B3 14.0 V Output current, low IOL and P3B0 to P3B3 Output voltage VBDS Total power dissipation Pt 200 mW Operating ambient temperature TA –40 to +85 °C Storage temperature Tstg –55 to +125 °C Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. Recommended Operating Range (TA = –40 to +85°C) Parameter Supply voltage Symbol Conditions MIN. TYP. MAX. Unit VDD1 When CPU and PLL are operating 4.5 5.0 5.5 V VDD2 When CPU and PLL are stopped 3.5 5.0 5.5 V MIN. TYP. MAX. Unit 12 V Recommended Output Voltage (TA = –40 to +85°C) Parameter Output voltage 348 Symbol VBDS Conditions P1B0 to P1B3 Data Sheet U15722EJ1V1DS µPD17704A, 17705A, 17707A, 17708A, 17709A DC Characteristics (TA = –40 to +85°C, VDD = 3.5 to 5.5 V) Parameter Supply current Data retention voltage Symbol Conditions MIN. TYP. MAX. Unit IDD1 When CPU is operating and PLL is stopped with sine wave input to XIN pin. (fIN = 4.5 MHz ±1%, VIN = VDD) 1.5 3.0 mA IDD2 When CPU and PLL are stopped with sine-wave input to XIN pin. (fIN = 4.5 MHz ±1%, VIN = VDD) With HALT instruction 0.7 1.5 mA VDDR1 Crystal oscillation 3.5 5.5 V VDDR2 Crystal oscillation Power failure detection by timer FF 2.2 5.5 V VDDR3 stopped 2.0 5.5 V IDDR1 Crystal oscillation VDD = 5 V, TA = 25°C 2.0 4.0 µA IDDR2 stopped 2.0 30.0 µA VIH1 P0A0, P0B1, P0C0 to P0C3, P1A0, P1A1, P1C0 to P1C3, P1D0 to P1D3, P2A2, P2B0 to P2B3, P2C0 to P2C3, P2D0 to P2D2, P3A0 to P3A3, P3B0 to P3B3, P3C0 to P3C3, P3D0 to P3D3 0.7VDD VDD V VIH2 P0A1 to P0A3, P0B0, P0B2, P0B3, P2A0, P2A1, CE, INT0 to INT4, RESET 0.8VDD VDD V VIH3 P0D0 to P0D3 0.55VDD VDD V VIL1 P0A0, P0B1, P0C0 to P0C3, P1A0, P1A1, P1C0 to P1C3, P1D0 to P1D3, P2A2, P2B0 to P2B3, P2C0 to P2C3, P2D0 to P2D2, P3A0 to P3A3, P3B0 to P3B3, P3C0 to P3C3, P3D0 to P3D3 0 0.3VDD V VIL2 P0A1 to P0A3, P0B0, P0B2, P0B3, P2A0, P2A1, CE, INT0 to INT4, RESET 0 0.2VDD V VIL3 P0D0 to P0D3 0 0.15VDD V IOH1 P0A0 to P0A3, P0B0 to P0B3, P0C0 to P0C3, P1D0 to P1D3, P2A0 to P2A2, P2B0 to P2B3, P2C0 to P2C3, P2D0 to P2D2, P3A0 to P3A3, P3B0 to P3B3, P3C0 to P3C3, P3D0 to P3D3 VOH = VDD – 1 V –1.0 mA IOH2 EO0, EO1 VDD = 4.5 to 5.5 V, VOH = VDD – 1 V –3.0 mA IOL1 P0A0 to P0A3, P0B0 to P0B3, P0C0 to P0C3, P1D0 to P1D3, P2A0 to P2A2, P2B0 to P2B3, P2C0 to P2C3, P2D0 to P2D2, P3A0 to PA3A, P3B0 to P3B3, P3C0 to P3C3, P3D0 to P3D3 VOL = 1 V 1.0 mA IOL2 EO0, EO1 VDD = 4.5 to 5.5 V, VOL = 1 V 3.0 mA IOL3 P1B0 to P1B3 VOL = 1 V 7.0 mA Input current, high IIH P0D0 to P0D3 pulled down VIN = VDD 5.0 Output off leakage ILO1 P1B0 to P1B3 current ILO2 EO0, EO1 Input leakage current, high ILIH Input pin Input leakage current, low ILIL Input pin Data retention current Input voltage, high Input voltage, low Output current, high Output current, low Data memory retained 150 µA 1.0 µA ±1.0 µA VIN = VDD 1.0 µA VIN = 0 V –1.0 µA VIN = 12 V VIN = VDD, VIN = 0 V Data Sheet U15722EJ1V1DS 349 µPD17704A, 17705A, 17707A, 17708A, 17709A AC Characteristics (TA = –40 to +85°C, VDD = 5 V ±10%) Parameter Operating frequency Symbol fIN1 Conditions MIN. VCOL pin, MF mode, sine-wave input TYP. MAX. Unit 0.5 3 MHz 10 40 MHz 60 130 MHz 0.4 0.5 MHz VIN = 0.1Vp-pNote fIN2 VCOL pin, HF mode, sine-wave input VIN = 0.1Vp-pNote fIN3 VCOH pin, VHF mode, sine-wave input VIN = 0.1Vp-pNote fIN4 AMIFC pin, sine-wave input VIN = 0.15Vp-pNote fIN5 FMIFC pin, FMIF count mode, sine-wave input VIN = 0.20Vp-p 10 11 MHz fIN6 FMIFC pin, AMIF count mode, sine-wave input VIN = 0.15Vp-p 0.4 0.5 MHz SIO0 input frequency fIN7 External clock 1 MHz SIO1 input frequency fIN8 External clock 0.7 MHz Note The condition of sine wave input VIN = 0.1Vp-p is the rated value when the µPD17704A, 17705A, 17707A, 17708A, or 17709A is operating alone. Where influence of noise must be taken into consideration, operation under input amplitude conditions of VIN = 0.15Vp-p is recommended. A/D Converter Characteristics (TA = –40 to +85°C, VDD = 5 V ±10%) Parameter Symbol Conditions A/D conversion total error 8 bits A/D conversion total error 8 bits MIN. TYP. MAX. Unit ±3.0 LSB ±2.5 LSB TYP. MAX. Unit 6.0 12.0 mA TA = 0 to 85°C Reference Characteristics (TA = +25°C, VDD = 5.0 V) Parameter Supply current 350 Symbol IDD3 Conditions When CPU and PLL are operating with sine-wave input to VCOH pin (fIN = 130 MHz, VIN = 0.3Vp-p) Data Sheet U15722EJ1V1DS MIN. µPD17704A, 17705A, 17707A, 17708A, 17709A 25. PACKAGE DRAWING 80-PIN PLASTIC QFP (14x14) A B 41 40 60 61 detail of lead end S C D Q R 21 20 80 1 F G J H I M K P S N S L M NOTE ITEM Each lead centerline is located within 0.13 mm of its true position (T.P.) at maximum material condition. MILLIMETERS A 17.2±0.4 B 14.0±0.2 C 14.0±0.2 D 17.2±0.4 F 0.825 G 0.825 H I 0.30±0.10 0.13 J 0.65 (T.P.) K 1.6±0.2 0.8±0.2 L M 0.15 +0.10 −0.05 N 0.10 P 2.7±0.1 Q 0.1±0.1 R 5°±5° S 3.0 MAX. S80GC-65-3B9-6 Remark The dimensions and materials of the ES model are the same as those of the mass-produced model. Data Sheet U15722EJ1V1DS 351 µPD17704A, 17705A, 17707A, 17708A, 17709A 26. RECOMMENDED SOLDERING CONDITIONS The µPD17704A, 17705A, 17707A, 17708A, and 17709A should be soldered and mounted under the following recommended conditions. For details of the recommended soldering conditions, refer to the document Semiconductor Device Mounting Technology Manual (C10535E). For soldering methods and conditions other than those recommended below, contact an NEC sales representative. Table 26-1. Surface Mounting Type Soldering Conditions (1) µPD17704AGC-xxx-3B9: 80-pin plastic QFP (14 × 14) µPD17705AGC-xxx-3B9: 80-pin plastic QFP (14 × 14) Soldering Method Soldering Conditions Recommended Condition Symbol Infrared reflow Package peak temperature: 235°C, Time: 30 seconds MAX. (at 210°C or higher.), Count: Three times or less IR35-00-3 VPS Package peak temperature: 215°C, Time: 40 seconds MAX. (at 200°C or higher.), Count: Three times or less VP15-00-3 Wave soldering Solder bath temperature: 260°C MAX., Time: 10 seconds MAX., Count: Once, Preheating temperature: 120°C MAX. (package surface temperature) WS60-00-1 Partial heating Pin temperature: 300°C MAX., Time: 3 seconds MAX. (per pin row) — Caution Do not use different soldering methods together (except for partial heating). (2) µPD17707AGC-xxx-3B9: 80-pin plastic QFP (14 × 14) µPD17708AGC-xxx-3B9: 80-pin plastic QFP (14 × 14) µPD17709AGC-xxx-3B9: 80-pin plastic QFP (14 × 14) Soldering Method Soldering Conditions Recommended Condition Symbol Infrared reflow Package peak temperature: 235°C, Time: 30 seconds MAX. (at 210°C or higher.), Count: Twice or less IR35-00-2 VPS Package peak temperature: 215°C, Time: 40 seconds MAX. (at 200°C or higher.), Count: Twice or less VP15-00-2 Wave soldering Solder bath temperature: 260°C MAX., Time: 10 seconds MAX., Count: Once, Preheating temperature: 120°C MAX. (package surface temperature) WS60-00-1 Partial heating Pin temperature: 300°C MAX., Time: 3 seconds MAX. (per pin row) Caution Do not use different soldering methods together (except for partial heating). 352 Data Sheet U15722EJ1V1DS — µPD17704A, 17705A, 17707A, 17708A, 17709A APPENDIX A. CAUTIONS ON CONNECTING CRYSTAL RESONATOR When using the system clock oscillator, wire the portion enclosed by the dotted lines in the figure below as follows to prevent adverse influence from wiring capacity. • Keep the wiring length as short as possible. • If capacitances C1 and C2 are too high, the oscillation start characteristics may be degraded or current consumption may increase. • Generally, connect a trimmer capacitor for adjusting the oscillation frequency to the XIN pin. Depending on the crystal resonator to be used, however, the oscillation stability differs. Therefore, evaluate the crystal resonator actually used. • The crystal oscillation frequency cannot be accurately adjusted when an emulation probe is connected to the XOUT and XIN pin, because of the capacitance of the probe. Adjust the frequency while measuring the VCO oscillation frequency. µPD17709A XOUT XIN 4.5 MHz crystal resonator C1 C2 Data Sheet U15722EJ1V1DS 353 µPD17704A, 17705A, 17707A, 17708A, 17709A APPENDIX B. DEVELOPMENT TOOLS The following development tools are available for development of programs for the µPD17709A. Hardware Name Outline In-circuit emulator (IE-17K-ETNote 1) IE-17K-ET is an in-circuit emulator that can be used with any model in the 17K Series. IE-17K-ET is connected to a host machine, which is PC-9800 series or IBM PC/ATTM, with RS-232C. By using these in-circuit emulators with a system evaluation board (SE board) corresponding to each model, these emulators operate as emulators specific to a model. When man-machine interface software SIMPLEHOSTTM is used, a more sophisticated debugging environment can be created. SE board (SE-17709) SE-17709 is an SE board for the µPD17709A Subseries. This board can be used alone to evaluate a system, or in combination with an in-circuit emulator for debugging. Emulation probe (EP-17K80GC) EP-17K80GC is an emulation probe for the µPD17709A Subseries. By using this probe with EV9200GC-80Note 2, the SE board and target system are connected. Conversion socket (EV-9200GC-80Note 2) EV-9200GC-80 is a conversion socket for 80-pin plastic QFP (14 × 14). It is used to connect the EP17K80GC and target system. PROM programmer (PG-1500) PG-1500 is a PROM programmer supporting µPD17P709A. It can program the µPD17P709A when connected with the PG-1500 adapter PA-17KDZ and programmer adapter PA-17P709GC. Programmer adapter (PA-17P709GC) PA-17P709GC is an adapter to program the µPD17P709A. It is used with PG-1500. Notes 1. External power supply type 2. One EV-9200GC-80 is supplied with the EP-17K80GC. Five EV-9200GC-80 are also available as a set. Remark Third-party PROM programmers AF-9703, AF-9704, AF-9705, and AF-9706 are available from Ando Electric Co., Ltd. Use these programmers with programmer adapter PA-17P709GC. For details, consult Ando Electric Co., Ltd. (TEL: +8-44-549-7300). 354 Data Sheet U15722EJ1V1DS µPD17704A, 17705A, 17707A, 17708A, 17709A Software Name 17K Series assembler (RA17K) Device file (AS17707) Support Outline Host Machine RA17K is an assembler that can be commonly used with 17K Series. To develop programs for the µPD17709A, this RA17K and a device file (AS17707) are used in combination. AS17707 is a device file for the µPD17709A Subseries. It is used with the assembler common to the 17K Series (RA17K). SIMPLEHOST is man-machine interface software that runs on software Windows when a program is (SIMPLEHOST) developed by using an in-circuit emulator and personal computer. OS Media Parts Number WindowsTM 3.5” 2HD µSAA13RA17K IBM PC/AT Japanese Windows 3.5” 2HC µSAB13RA17K compatibles English Windows PC-9800 series Japanese µSBB13RA17K PC-9800 series Japanese Windows 3.5” 2HD µSAA13AS17707 IBM PC/AT Japanese Windows 3.5” 2HC µSAB13AS17707 compatibles English Windows µSBB13AS17707 PC-9800 series Japanese Windows 3.5” 2HD µSAA13ID17K IBM PC/AT Japanese Windows 3.5” 2HC µSAB13ID17K compatibles English Windows Data Sheet U15722EJ1V1DS µSBB13ID17K 355 µPD17704A, 17705A, 17707A, 17708A, 17709A NOTES FOR CMOS DEVICES 1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to V DD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function. 356 Data Sheet U15722EJ1V1DS µPD17704A, 17705A, 17707A, 17708A, 17709A Regional Information Some information contained in this document may vary from country to country. Before using any NEC product in your application, pIease contact the NEC office in your country to obtain a list of authorized representatives and distributors. They will verify: • Device availability • Ordering information • Product release schedule • Availability of related technical literature • Development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, AC supply voltages, and so forth) • Network requirements In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country. NEC Electronics Inc. (U.S.) NEC Electronics (Germany) GmbH NEC Electronics Hong Kong Ltd. Santa Clara, California Tel: 408-588-6000 800-366-9782 Fax: 408-588-6130 800-729-9288 Benelux Office Eindhoven, The Netherlands Tel: 040-2445845 Fax: 040-2444580 Hong Kong Tel: 2886-9318 Fax: 2886-9022/9044 NEC Electronics Hong Kong Ltd. Velizy-Villacoublay, France Tel: 01-3067-5800 Fax: 01-3067-5899 Seoul Branch Seoul, Korea Tel: 02-528-0303 Fax: 02-528-4411 NEC Electronics (France) S.A. NEC Electronics Singapore Pte. Ltd. Milton Keynes, UK Tel: 01908-691-133 Fax: 01908-670-290 Madrid Office Madrid, Spain Tel: 091-504-2787 Fax: 091-504-2860 Novena Square, Singapore Tel: 253-8311 Fax: 250-3583 NEC Electronics Italiana s.r.l. NEC Electronics (Germany) GmbH Milano, Italy Tel: 02-66 75 41 Fax: 02-66 75 42 99 Scandinavia Office Taeby, Sweden Tel: 08-63 80 820 Fax: 08-63 80 388 NEC Electronics (France) S.A. NEC Electronics (Germany) GmbH Duesseldorf, Germany Tel: 0211-65 03 02 Fax: 0211-65 03 490 NEC Electronics (UK) Ltd. NEC Electronics Taiwan Ltd. Taipei, Taiwan Tel: 02-2719-2377 Fax: 02-2719-5951 NEC do Brasil S.A. Electron Devices Division Guarulhos-SP, Brasil Tel: 11-6462-6810 Fax: 11-6462-6829 J01.2 Data Sheet U15722EJ1V1DS 357 µPD17704A, 17705A, 17707A, 17708A, 17709A Purchase of NEC I2C components conveys a license under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips. SIMPLEHOST is a trademark of NEC Corporation. Windows is either a registered trademark or trademark of Microsoft Corporation in the United States and/ or other countries. PC/AT is a trademark of International Business Machines Corporation. The export of this product from Japan is regulated by the Japanese government. To export this product may be prohibited without governmental license, the need for which must be judged by the customer. The export or re-export of this product from a country other than Japan may also be prohibited without a license from that country. Please call an NEC sales representative. • The information in this document is current as of October, 2001. The information is subject to change without notice. For actual design-in, refer to the latest publications of NEC's data sheets or data books, etc., for the most up-to-date specifications of NEC semiconductor products. Not all products and/or types are available in every country. Please check with an NEC sales representative for availability and additional information. • No part of this document may be copied or reproduced in any form or by any means without prior written consent of NEC. NEC assumes no responsibility for any errors that may appear in this document. • NEC does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of NEC semiconductor products listed in this document or any other liability arising from the use of such products. No license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC or others. • Descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. The incorporation of these circuits, software and information in the design of customer's equipment shall be done under the full responsibility of customer. NEC assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. • While NEC endeavours to enhance the quality, reliability and safety of NEC semiconductor products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To minimize risks of damage to property or injury (including death) to persons arising from defects in NEC semiconductor products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment, and anti-failure features. • NEC semiconductor products are classified into the following three quality grades: "Standard", "Special" and "Specific". The "Specific" quality grade applies only to semiconductor products developed based on a customer-designated "quality assurance program" for a specific application. The recommended applications of a semiconductor product depend on its quality grade, as indicated below. Customers must check the quality grade of each semiconductor product before using it in a particular application. "Standard": Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots "Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) "Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc. The quality grade of NEC semiconductor products is "Standard" unless otherwise expressly specified in NEC's data sheets or data books, etc. If customers wish to use NEC semiconductor products in applications not intended by NEC, they must contact an NEC sales representative in advance to determine NEC's willingness to support a given application. (Note) (1) "NEC" as used in this statement means NEC Corporation and also includes its majority-owned subsidiaries. (2) "NEC semiconductor products" means any semiconductor product developed or manufactured by or for NEC (as defined above). M8E 00. 4