Features • Serial Peripheral Interface (SPI) Compatible • Supports SPI Modes 0 (0,0) and 3 (1,1) • Low-voltage and Standard-voltage Operation • • • • • • • • – 5.0 (VCC = 4.5V to 5.5V) – 2.7 (VCC = 2.7V to 5.5V) – 1.8 (VCC = 1.8V to 3.6V) 3 MHz Clock Rate 64-byte Page Mode and Byte Write Operation Block Write Protection – Protect 1/4, 1/2, or Entire Array Write Protect (WP) Pin and Write Disable Instructions for Both Hardware and Software Data Protection Self-timed Write Cycle (5 ms Typical) High-reliability – Endurance: 100,000 Write Cycles – Data Retention: >200 Years – ESD Protection: >4000V Automotive Grade and Extended Temperature Devices Available 8-pin PDIP, 8-pin EIAJ SOIC, 8-pin and 16-pin JEDEC SOIC, 14-pin and 20-pin TSSOP, 8-pin Leadless Array, and 8-ball dBGA™ Packages Description SPI Serial EEPROMs 128K (16,384 x 8) 256K (32,768 x 8) AT25128 AT25256 The AT25128/256 provides 131,072/262,144 bits of serial electrically-erasable programmable read only memory (EEPROM) organized as 16,384/32,768 words of 8 bits each. The device is optimized for use in many industrial and commercial applications (continued) Pin Configurations Pin Name Function CS Chip Select SCK Serial Data Clock SI Serial Data Input SO Serial Data Output GND Ground VCC Power Supply WP Write Protect HOLD Suspends Serial Input NC No Connect DC Don't Connect 14-lead TSSOP CS SO NC NC NC WP GND 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 14 13 12 11 10 9 8 VCC HOLD NC NC NC SCK SI 8-ball dBGA VCC HOLD SCK SI 16-pin SOIC CS SO NC NC NC NC WP GND 1 2 3 4 5 6 7 8 1 7 2 6 3 5 4 20-lead TSSOP* CS SO WP GND NC CS SO SO NC NC WP GND DC NC 1 2 3 4 5 6 7 8 9 10 8-pin Leadless Array VCC HOLD SCK SI Bottom View VCC HOLD NC NC NC NC SCK SI 1 2 3 4 8 7 6 5 8 7 6 5 1 2 3 4 CS SO WP GND Bottom View 8-pin PDIP CS SO WP GND NC VCC HOLD HOLD NC NC SCK SI DC NC 20 19 18 17 16 15 14 13 12 11 8-pin SOIC VCC HOLD SCK SI CS SO WP GND 1 2 3 4 *Note: Pins 3, 4 and 17, 18 are internally connected for 14-lead TSSOP socket compatibility. 8 7 6 5 VCC HOLD SCK SI Rev. 0872G–01/01 1 where low-power and low-voltage operation are essential. The devices are available in space saving 8-pin PDIP (AT25128/256), 8-pin EIAJ SOIC (AT25128/256), 8-pin and 16-pin JEDEC SOIC (AT25128), 14-pin TSSOP (AT25128), 20-pin TSSOP (AT25128/256), 8-pin Leadless Array (AT25128/256), and 8-ball dBGA packages. In addition, the entire family is available in 5.0V (4.5V to 5.5V), 2.7V (2.7V to 5.5V) and 1.8V (1.8V to 3.6V) versions. The AT25128/256 is enabled through the Chip Select pin (CS) and accessed via a 3wire interface consisting of Serial Data Input (SI), Serial Data Output (SO), and Serial Clock (SCK). All programming cycles are completely self-timed, and no separate ERASE cycle is required before WRITE. BLOCK WRITE protection is enabled by programming the status register with top ¼, top ½ or entire array of write protection. Separate program enable and program disable instructions are provided for additional data protection. Hardware data protection is provided via the WP pin to protect against inadvertent write attempts to the status register. The HOLD pin may be used to suspend any serial communication without resetting the serial sequence. Absolute Maximum Ratings* Operating Temperature.................................. -55°C to +125°C *NOTICE: Storage Temperature ..................................... -65°C to +150°C Voltage on Any Pin with Respect to Ground .....................................-1.0V to +7.0V Maximum Operating Voltage .......................................... 6.25V Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. DC Output Current........................................................ 5.0 mA Block Diagram 16384/32768 x 8 2 AT25128/256 0872G–01/01 AT25128/256 Pin Capacitance(1) Applicable over recommended operating range from TA = 25°C, f = 1.0 MHz, VCC = +5.0V (unless otherwise noted). Symbol Test Conditions COUT CIN Note: Max Units Conditions Output Capacitance (SO) 8 pF VOUT = 0V Input Capacitance (CS, SCK, SI, WP, HOLD) 6 pF VIN = 0V 1. This parameter is characterized and is not 100% tested. DC Characteristics Applicable over recommended operating range from TAI = -40°C to +85°C, VCC = +1.8V to +5.5V, TAC = 0°C to +70°C, VCC = +1.8V to +5.5V(unless otherwise noted). Symbol Parameter VCC1 Supply Voltage VCC2 Max Units 1.8 3.6 V Supply Voltage 2.7 5.5 V VCC3 Supply Voltage 4.5 5.5 V ICC1 Supply Current VCC = 5.0V at 1 MHz, SO = Open, Read 2.0 3.0 mA ICC2 Supply Current VCC = 5.0V at 2 MHz, SO = Open, Read, Write 3.0 5.0 mA ISB1 Standby Current VCC = 1.8V, CS = VCC 0.1 2.0 µA ISB2 Standby Current VCC = 2.7V, CS = VCC 0.2 2.0 µA ISB3 Standby Current VCC = 5.0V, CS = VCC 2.0 5.0 µA IIL Input Leakage VIN = 0V to VCC -3.0 3.0 µA Output Leakage VIN = 0V to VCC, TAC = 0°C to 70°C -3.0 3.0 µA IOL VIL Test Condition Min Typ (1) Input Low-voltage -1.0 VCC x 0.3 V (1) Input High-voltage VCC x 0.7 VCC + 0.5 V 0.4 V VIH VOL1 Output Low-voltage VOH1 Output High-voltage VOL2 Output Low-voltage VOH2 Output High-voltage Note: 4.5 ≤ VCC ≤ 5.5V 1.8V ≤ VCC ≤ 3.6V IOL = 3.0 mA IOH = -1.6 mA VCC - 0.8 IOL = 0.15 mA IOH = -100 µA V 0.2 VCC - 0.2 V V 1. VIL and VIH max are reference only and are not tested. 3 0872G–01/01 AC Characteristics Applicable over recommended operating range from TA = -40°C to + 85°C, VCC = As Specified, CL = 1 TTL Gate and 100 pF (unless otherwise noted). Symbol Parameter Voltage Min Max Units fSCK SCK Clock Frequency 4.5 - 5.5 2.7 - 5.5 1.8 - 3.6 0 0 0 3.0 2.1 0.5 MHz tRI Input Rise Time 4.5 - 5.5 2.7 - 5.5 1.8 - 3.6 2 2 2 µs tFI Input Fall Time 4.5 - 5.5 2.7 - 5.5 1.8 - 3.6 2 2 2 µs tWH SCK High Time 4.5 - 5.5 2.7 - 5.5 1.8 - 3.6 150 200 800 ns tWL SCK Low Time 4.5 - 5.5 2.7 - 5.5 1.8 - 3.6 150 200 800 ns tCS CS High Time 4.5 - 5.5 2.7 - 5.5 1.8 - 3.6 250 250 1000 ns tCSS CS Setup Time 4.5 - 5.5 2.7 - 5.5 1.8 - 3.6 100 250 1000 ns tCSH CS Hold Time 4.5 - 5.5 2.7 - 5.5 1.8 - 3.6 150 250 1000 ns tSU Data In Setup Time 4.5 - 5.5 2.7 - 5.5 1.8 - 3.6 30 50 100 ns tH Data In Hold Time 4.5 - 5.5 2.7 - 5.5 1.8 - 3.6 50 50 100 ns tHD Hold Setup Time 4.5 - 5.5 2.7 - 5.5 1.8 - 3.6 100 100 400 ns tCD Hold Hold Time 4.5 - 5.5 2.7 - 5.5 1.8 - 3.6 200 300 400 ns tV Output Valid 4.5 - 5.5 2.7 - 5.5 1.8 - 3.6 0 0 0 tHO Output Hold Time 4.5 - 5.5 2.7 - 5.5 1.8 - 3.6 0 0 0 tLZ Hold to Output Low Z 4.5 - 5.5 2.7 - 5.5 1.8 - 3.6 0 0 0 4 150 200 800 ns ns 100 200 300 ns AT25128/256 0872G–01/01 AT25128/256 AC Characteristics (Continued) Applicable over recommended operating range from TA = -40°C to + 85°C, VCC = As Specified, CL = 1 TTL Gate and 100 pF (unless otherwise noted). Symbol Parameter Voltage tHZ Hold to Output High Z tDIS tWC Endurance(1) Note: Max Units 4.5 - 5.5 2.7 - 5.5 1.8 - 3.6 100 200 300 ns Output Disable Time 4.5 - 5.5 2.7 - 5.5 1.8 - 3.6 200 250 1000 ns Write Cycle Time 4.5 - 5.5 2.7 - 5.5 1.8 - 3.6 5 10 10 ms 5.0V, 25°C, Page Mode Min 100K Write Cycles 1. This parameter is characterized and is not 100% tested. Contact Atmel for further information. Serial Interface Description MASTER: The device that generates the serial clock. SLAVE: Because the Serial Clock pin (SCK) is always an input, the AT25128/256 always operates as a slave. TRANSMITTER/RECEIVER: The AT25128/256 has separate pins designated for data transmission (SO) and reception (SI). MSB: The Most Significant Bit (MSB) is the first bit transmitted and received. SERIAL OP-CODE: After the device is selected with CS going low, the first byte will be received. This byte contains the op-code that defines the operations to be performed. INVALID OP-CODE: If an invalid op-code is received, no data will be shifted into the AT25128/256, and the serial output pin (SO) will remain in a high impedance state until the falling edge of CS is detected again. This will reinitialize the serial communication. CHIP SELECT: The AT25128/256 is selected when the CS pin is low. When the device is not selected, data will not be accepted via the SI pin, and the serial output pin (SO) will remain in a high impedance state. HOLD: The HOLD pin is used in conjunction with the CS pin to select the AT25128/256. When the device is selected and a serial sequence is underway, HOLD can be used to pause the serial communication with the master device without resetting the serial sequence. To pause, the HOLD pin must be brought low while the SCK pin is low. To resume serial communication, the HOLD pin is brought high while the SCK pin is low (SCK may still toggle during HOLD). Inputs to the SI pin will be ignored while the SO pin is in the high impedance state. WRITE PROTECT: The write protect pin (WP) will allow normal read/write operations when held high. When the WP pin is brought low and WPEN bit is “1”, all write operations to the status register are inhibited. WP going low while CS is still low will interrupt a write to the status register. If the internal write cycle has already been initiated, WP going low will have no effect on any write operation to the status register. The WP pin function is blocked when the WPEN bit in the status register is “0”. This will allow the user to install the AT25128/256 in a system with the WP pin tied to ground and still be able to write to the status register. All WP pin functions are enabled when the WPEN bit is set to “1”. 5 0872G–01/01 SPI Serial Interface AT25128/256 Functional Description The AT25128/256 is designed to interface directly with the synchronous serial peripheral interface (SPI) of the 6800 type series of microcontrollers. The AT25128/256 utilizes an 8-bit instruction register. The list of instructions and their operation codes are contained in Table 1. All instructions, addresses, and data are transferred with the MSB first and start with a high-to-low CS transition.. Table 1. Instruction Set for the AT25128/256 6 Instruction Name Instruction Format Operation WREN 0000 X110 Set Write Enable Latch WRDI 0000 X100 Reset Write Enable Latch RDSR 0000 X101 Read Status Register WRSR 0000 X001 Write Status Register READ 0000 X011 Read Data from Memory Array WRITE 0000 X010 Write Data to Memory Array AT25128/256 0872G–01/01 AT25128/256 WRITE ENABLE (WREN): The device will power-up in the write disable state when VCC is applied. All programming instructions must therefore be preceded by a Write Enable instruction. WRITE DISABLE (WRDI): To protect the device against inadvertent writes, the Write Disable instruction disables all programming modes. The WRDI instruction is independent of the status of the WP pin. READ STATUS REGISTER (RDSR): The Read Status Register instruction provides access to the status register. The READY/BUSY and Write Enable status of the device can be determined by the RDSR instruction. Similarly, the Block Write Protection bits indicate the extent of protection employed. These bits are set by using the WRSR instruction. Table 2. Status Register Format Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 WPEN X X X BP1 BP0 WEN RDY Table 3. Read Status Register Bit Definition Bit Definition Bit 0 (RDY) Bit 0 = 0 (RDY) indicates the device is READY. Bit 0 = 1 indicates the write cycle is in progress. Bit 1 (WEN) Bit 1 = 0 indicates the device is not WRITE ENABLED. Bit 1 = 1 indicates the device is WRITE ENABLED. Bit 2 (BP0) See Table 4. Bit 3 (BP1) See Table 4. Bits 4 - 6 are 0s when device is not in an internal write cycle. Bit 7 (WPEN) See Table 5. Bits 0 - 7 are 1s during an internal write cycle. WRITE STATUS REGISTER (WRSR): The WRSR instruction allows the user to select one of four levels of protection. The AT25128/256 is divided into four array segments. Top quarter (1/4), top half (1/2), or all of the memory segments can be protected. Any of the data within any selected segment will therefore be READ only. The block write protection levels and corresponding status register control bits are shown in Table 4. The three bits, BP0, BP1, and WPEN are nonvolatile cells that have the same properties and functions as the regular memory cells (e.g. WREN, tWC, RDSR). Table 4. Block Write Protect Bits Status Register Bits Array Addresses Protected Level BP1 BP0 AT25128 AT25256 0 0 0 None None 1(1/4) 0 1 3000 - 3FFF 6000 - 7FFF 2(1/2) 1 0 2000 - 3FFF 4000 - 7FFF 3(All) 1 1 0000 - 3FFF 0000 - 7FFF 7 0872G–01/01 The WRSR instruction also allows the user to enable or disable the write protect (WP) pin through the use of the Write Protect Enable (WPEN) bit. Hardware write protection is enabled when the WP pin is low and the WPEN bit is “1”. Hardware write protection is disabled when either the WP pin is high or the WPEN bit is “0.” When the device is hardware write protected, writes to the Status Register, including the Block Protect bits and the WPEN bit, and the block-protected sections in the memory array are disabled. Writes are only allowed to sections of the memory which are not block-protected. NOTE: When the WPEN bit is hardware write protected, it cannot be changed back to “0”, as long as the WP pin is held low. Table 5. WPEN Operation WPEN WP WEN Protected Blocks Unprotected Blocks Status Register 0 X 0 Protected Protected Protected 0 X 1 Protected Writable Writable 1 Low 0 Protected Protected Protected 1 Low 1 Protected Writable Protected X High 0 Protected Protected Protected X High 1 Protected Writable Writable READ SEQUENCE (READ): Reading the AT25128/256 via the SO (Serial Output) pin requires the following sequence. After the CS line is pulled low to select a device, the READ op-code is transmitted via the SI line followed by the byte address to be read (Refer to Table 6). Upon completion, any data on the SI line will be ignored. The data (D7 - D0) at the specified address is then shifted out onto the SO line. If only one byte is to be read, the CS line should be driven high after the data comes out. The READ sequence can be continued since the byte address is automatically incremented and data will continue to be shifted out. When the highest address is reached, the address counter will roll over to the lowest address allowing the entire memory to be read in one continuous READ cycle. WRITE SEQUENCE (WRITE): In order to program the AT25128/256, two separate instructions must be executed. First, the device must be write enabled via the Write Enable (WREN) Instruction. Then a Write (WRITE) Instruction may be executed. Also, the address of the memory location(s) to be programmed must be outside the protected address field location selected by the Block Write Protection Level. During an internal write cycle, all commands will be ignored except the RDSR instruction. A Write Instruction requires the following sequence. After the CS line is pulled low to select the device, the WRITE op-code is transmitted via the SI line followed by the byte address and the data (D7 - D0) to be programmed (Refer to Table 6). Programming will start after the CS pin is brought high. (The LOW-to-High transition of the CS pin must occur during the SCK low time immediately after clocking in the D0 (LSB) data bit. The READY/BUSY status of the device can be determined by initiating a READ STATUS REGISTER (RDSR) Instruction. If Bit 0 = 1, the WRITE cycle is still in progress. If Bit 0 = 0, the WRITE cycle has ended. Only the READ STATUS REGISTER instruction is enabled during the WRITE programming cycle. 8 AT25128/256 0872G–01/01 AT25128/256 The AT25128/256 is capable of a 64-byte PAGE WRITE operation. After each byte of data is received, the six low order address bits are internally incremented by one; the high order bits of the address will remain constant. If more than 64 bytes of data are transmitted, the address counter will roll over and the previously written data will be overwritten. The AT25128/256 is automatically returned to the write disable state at the completion of a WRITE cycle. NOTE: If the device is not Write enabled (WREN), the device will ignore the Write instruction and will return to the standby state, when CS is brought high. A new CS falling edge is required to re-initiate the serial communication. Table 6. Address Key Address AT25128 AT25256 AN A13 - A0 A14 - A0 Don’t Care Bits A15 - A14 A15 9 0872G–01/01 Timing Diagrams (for SPI Mode 0 (0, 0)) Synchronous Data Timing t CS VIH CS VIL t CSH t CSS VIH t WH SCK t WL VIL tH t SU VIH SI VALID IN VIL tV VOH SO HI-Z t HO t DIS HI-Z VOL WREN Timing WRDI Timing 10 AT25128/256 0872G–01/01 AT25128/256 RDSR Timing CS 0 1 2 3 4 5 6 7 8 9 10 7 6 5 11 12 13 14 2 1 SCK SI SO INSTRUCTION HIGH IMPEDANCE DATA OUT 4 3 0 MSB WRSR Timing READ Timing 11 0872G–01/01 WRITE Timing HOLD Timing CS tCD tCD SCK tHD tHD HOLD tHZ SO tLZ 12 AT25128/256 0872G–01/01 AT25128/256 AT25128 Ordering Information tWC (max) (ms) ICC (max) (µA) ISB (max) (µA) fMAX (kHz) 5 5000 5.0 5000 5.0 Ordering Code Package Operation Range 3000 AT25128-10CC AT25128C1-10CC AT25128-10PC AT25128N-10SC AT25128W-10SC AT25128-10UC AT25128N1-10SC AT25128T1-10TC AT25128T2-10TC 8C 8C1 8P3 8S1 8S2 8U1 16S1 14T 20T Commercial (0°C to 70°C) 3000 AT25128-10CI AT25128C1-10CI AT25128-10PI AT25128N-10SI AT25128W-10SI AT25128-10UI AT25128N1-10SI AT25128T1-10TI AT25128T2-10TI 8C 8C1 8P3 8S1 8S2 8U1 16S1 14T 20T Industrial (-40°C to 85°C) Package Type 8C 8-lead, 0.230" Wide, Leadless Array Package (LAP) 8C1 8-lead, 0.300" Wide, Leadless Array Package (LAP) 8P3 8-lead, 0.300" Wide, Plastic Dual In-line Package (PDIP) 8S1 8-lead, 0.150" Wide, Plastic Gull Wing Small Outline Package (JEDEC SOIC) 8S2 8-lead, 0.200" Wide, Plastic Gull Wing Small Outline Package (EIAJ SOIC) 8U1 8-ball, die Ball Grid Array Package (dBGA) 16S1 16-lead, 0.150" Wide, Plastic Gull Wing Small Outline Package (JEDEC SOIC) 14T 14-lead, 0.170" Wide, Thin Shrink Small Outline Package (TSSOP) 20T 20-lead, 0.170" Wide, Thin Shrink Small Outline Package (TSSOP) Options Blank Standard Device (4.5V to 5.5V) -2.7 Low-voltage (2.7V to 5.5V) -1.8 Low-voltage (1.8V to 3.6V) 13 0872G–01/01 AT25128 Ordering Information (Continued) tWC (max) (ms) ICC (max) (µA) ISB (max) (µA) fMAX (kHz) Ordering Code Package 10 2000 2.0 2100 AT25128-10CC-2.7 AT25128C1-10CC-2.7 AT25128-10PC-2.7 AT25128N-10SC-2.7 AT25128W-10SC-2.7 AT25128-10UC-2.7 AT25128N1-10SC-2.7 AT25128T1-10TC-2.7 AT25128T2-10TC-2.7 8C 8C1 8P3 8S1 8S2 8U1 16S1 14T 20T Commercial (0°C to 70°C) 2000 2.0 2100 AT25128-10CI-2.7 AT25128C1-10CI-2.7 AT25128-10PI-2.7 AT25128N-10SI-2.7 AT25128W-10SI-2.7 AT25128-10UI-2.7 AT25128N1-10SI-2.7 AT25128T1-10TI-2.7 AT25128T2-10TI-2.7 8C 8C1 8P3 8S1 8S2 8U1 16S1 14T 20T Industrial (-40°C to 85°C) Operation Range Package Type 8C 8-lead, 0.230" Wide, Leadless Array Package (LAP) 8C1 8-lead, 0.300" Wide, Leadless Array Package (LAP) 8P3 8-lead, 0.300" Wide, Plastic Dual In-line Package (PDIP) 8S1 8-lead, 0.150" Wide, Plastic Gull Wing Small Outline Package (JEDEC SOIC) 8S2 8-lead, 0.200" Wide, Plastic Gull Wing Small Outline Package (EIAJ SOIC) 8U1 8-ball, die Ball Grid Array Package (dBGA) 16S1 16-lead, 0.150" Wide, Plastic Gull Wing Small Outline Package (JEDEC SOIC) 14T 14-lead, 0.170" Wide, Thin Shrink Small Outline Package (TSSOP) 20T 20-lead, 0.170" Wide, Thin Shrink Small Outline Package (TSSOP) Options Blank Standard Device (4.5V to 5.5V) -2.7 Low-voltage (2.7V to 5.5V) -1.8 Low-voltage (1.8V to 3.6V) 14 AT25128/256 0872G–01/01 AT25128/256 AT25128 Ordering Information (Continued) tWC (max) (ms) ICC (max) (µA) ISB (max) (µA) fMAX (kHz) Ordering Code Package 10 1000 2.0 500 AT25128-10CC-1.8 AT25128C1-10CC-1.8 AT25128-10PC-1.8 AT25128N-10SC-1.8 AT25128W-10SC-1.8 AT25128-10UC-1.8 AT25128N1-10SC-1.8 AT25128T1-10TC-1.8 AT25128T2-10TC-1.8 8C 8C1 8P3 8S1 8S2 8U1 16S1 14T 20T Commercial (0°C to 70°C) 1000 2.0 500 AT25128-10CI-1.8 AT25128C1-10CI-1.8 AT25128-10PI-1.8 AT25128N-10SI-1.8 AT25128W-10SI-1.8 AT25128-10UI-1.8 AT25128N1-10SI-1.8 AT25128T1-10TI-1.8 AT25128T2-10TI-1.8 8C 8C1 8P3 8S1 8S2 8U1 16S1 14T 20T Industrial (-40°C to 85°C) Operation Range Package Type 8C 8-lead, 0.230" Wide, Leadless Array Package (LAP) 8C1 8-lead, 0.300" Wide, Leadless Array Package (LAP) 8P3 8-lead, 0.300" Wide, Plastic Dual In-line Package (PDIP) 8S1 8-lead, 0.150" Wide, Plastic Gull Wing Small Outline Package (JEDEC SOIC) 8S2 8-lead, 0.200" Wide, Plastic Gull Wing Small Outline Package (EIAJ SOIC) 8U1 8-ball, die Ball Grid Array Package (dBGA) 16S1 16-lead, 0.150" Wide, Plastic Gull Wing Small Outline Package (JEDEC SOIC) 14T 14-lead, 0.170" Wide, Thin Shrink Small Outline Package (TSSOP) 20T 20-lead, 0.170" Wide, Thin Shrink Small Outline Package (TSSOP) Options Blank Standard Device (4.5V to 5.5V) -2.7 Low-voltage (2.7V to 5.5V) -1.8 Low-voltage (1.8V to 3.6V) 15 0872G–01/01 AT25256 Ordering Information tWC (max) (ms) ICC (max) (µA) ISB (max) (µA) fMAX (kHz) Ordering Code Package 5 5000 5.0 3000 AT25256-10CC AT25256C1-10CC AT25256-10PC AT25256W-10SC AT25256-10UC AT25256T2-10TC 8C 8C1 8P3 8S2 8U4 20T Commercial (0°C to 70°C) 5000 5.0 3000 AT25256-10CI AT25256C1-10CI AT25256-10PI AT25256W-10SI AT25256-10UI AT25256T2-10TI 8C 8C1 8P3 8S2 8U4 20T Industrial (-40°C to 85°C) 2000 2.0 2100 AT25256-10CC-2.7 AT25256C1-10CC-2.7 AT25256-10PC-2.7 AT25256W-10SC-2.7 AT25256-10UC-2.7 AT25256T2-10TC-2.7 8C 8C1 8P3 8S2 8U4 20T Commercial (0°C to 70°C) 2000 2.0 2100 AT25256-10CI-2.7 AT25256C1-10CI-2.7 AT25256-10PI-2.7 AT25256W-10SI-2.7 AT25256-10UI-2.7 AT25256T2-10TI-2.7 8C 8C1 8P3 8S2 8U4 20T Industrial (-40°C to 85°C) 10 Operation Range Package Type 8C 8-lead, 0.230" Wide, Leadless Array Package (LAP) 8C1 8-lead, 0.300" Wide, Leadless Array Package (LAP) 8P3 8-lead, 0.300" Wide, Plastic Dual In-line Package (PDIP) 8S2 8-lead, 0.200" Wide, Plastic Gull Wing Small Outline Package (EIAJ SOIC) 8U4 8-ball, die Ball Grid Array Package (dBGA) 20T 20-lead, 0.170" Wide, Thin Shrink Small Outline Package (TSSOP) Options Blank Standard Device (4.5V to 5.5V) -2.7 Low-voltage (2.7V to 5.5V) -1.8 Low-voltage (1.8V to 3.6V) 16 AT25128/256 0872G–01/01 AT25128/256 AT25256 Ordering Information (Continued) tWC (max) (ms) ICC (max) (µA) ISB (max) (µA) fMAX (kHz) Ordering Code Package 10 1000 2.0 500 AT25256-10CC-1.8 AT25256C1-10CC-1.8 AT25256-10PC-1.8 AT25256W-10SC-1.8 AT25256-10UC-1.8 AT25256T2-10TC-1.8 8C 8C1 8P3 8S2 8U4 20T Commercial (0°C to 70°C) 1000 2.0 500 AT25256-10CI-1.8 AT25256C1-10CI-1.8 AT25256-10PI-1.8 AT25256W-10SI-1.8 AT25256-10UI-1.8 AT25256T2-10TI-1.8 8C 8C1 8P3 8S2 8U4 20T Industrial (-40°C to 85°C) Operation Range Package Type 8C 8-lead, 0.230" Wide, Leadless Array Package (LAP) 8C1 8-lead, 0.300" Wide, Leadless Array Package (LAP) 8P3 8-lead, 0.300" Wide, Plastic Dual In-line Package (PDIP) 8S2 8-lead, 0.200" Wide, Plastic Gull Wing Small Outline Package (EIAJ SOIC) 8U4 8-ball, die Ball Grid Array Package (dBGA) 20T 20-lead, 0.170" Wide, Thin Shrink Small Outline Package (TSSOP) Options Blank Standard Device (4.5V to 5.5V) -2.7 Low-voltage (2.7V to 5.5V) -1.8 Low-voltage (1.8V to 3.6V) 17 0872G–01/01 Packaging Information 8C, 8-lead, 0.230" Wide, Leadless Array Package (LAP) Dimensions in Inches and (Millimeters) 8C1, 8-lead, 0.300" Wide, Leadless Array Package (LAP) Dimensions in Inches and (Millimeters) SIDE VIEW TOP VIEW SIDE VIEW TOP VIEW 5.10 (0.201) 4.90 (0.193) 5.03 (0.198) 4.83 (0.190) 1.32 (0.052) 1.22 (0.048) 6.09 (0.240) 5.89 (0.232) 1.14 (0.045) 0.94 (0.037) 8.10 (0.319) 7.90 (0.311) 1.14 (0.045) 0.94 (0.037) BOTTOM VIEW 0.38 (0.015) 0.30 (0.012) BOTTOM VIEW 0.38 (0.015) 0.30 (0.012) 8 1.19 (0.047) 1.09 (0.043) 1.32 (0.052) 1.22 (0.048) 1.22 (0.048) 1.12 (0.044) 1 8 7 2 6 3 5 4 0.61 (0.024) 0.51 (0.020) 0.89 (0.035) 0.79 (0.031) 0.61 (0.024) 0.51 (0.020) 8P3, 8-lead, 0.300" Wide, Plastic Dual In-line Package (PDIP) Dimensions in Inches and (Millimeters) 4.76 (0.187) 4.66 (0.183) 1 7 2 6 3 5 4 0.95 (0.037) 0.85 (0.033) 0.92 (0.036) 0.82 (0.032) 0.34 (0.013) 0.24 (0.009) 8S1, 8-lead, 0.150" Wide, Plastic Gull Wing Small Outline (JEDEC SOIC) Dimensions in Inches and (Millimeters) JEDEC STANDARD MS-001 BA .400 (10.16) .355 (9.02) .020 (.508) .013 (.330) PIN 1 .280 (7.11) .240 (6.10) .157 (3.99) .150 (3.81) PIN 1 .244 (6.20) .228 (5.79) .037 (.940) .027 (.690) .300 (7.62) REF .050 (1.27) BSC .210 (5.33) MAX .100 (2.54) BSC SEATING PLANE .196 (4.98) .189 (4.80) .068 (1.73) .053 (1.35) .015 (.380) MIN .150 (3.81) .115 (2.92) .070 (1.78) .045 (1.14) .022 (.559) .014 (.356) .010 (.254) .004 (.102) .325 (8.26) .300 (7.62) .012 (.305) .008 (.203) 0 REF 15 .430 (10.9) MAX 18 0 REF 8 .010 (.254) .007 (.203) .050 (1.27) .016 (.406) AT25128/256 0872G–01/01 AT25128/256 Packaging Information 8S2, 8-lead, 0.200" Wide, Plastic Gull Wing Small Outline (EIAJ SOIC) Dimensions in Inches and (Millimeters) 8U1, 8-ball, die Ball Grid Array Package (dBGA) Dimensions in Millimeters and (Inches)* TOP VIEW .020 (.508) .012 (.305) 2.21 (0.087) .213 (5.41) .205 (5.21) PIN 1 .330 (8.38) .300 (7.62) 3.73 (0.147) .050 (1.27) BSC SIDE VIEW .212 (5.38) .203 (5.16) 0.38 (0.015) BOTTOM VIEW .080 (2.03) .070 (1.78) .013 (.330) .004 (.102) 8 1 7 2 6 3 5 4 0.75 (0.029) 0 REF 8 .010 (.254) .007 (.178) 0.74 (0.029) .035 (.889) .020 (.508) 0.75 (0.029) 0.52 (0.020) 0.73 (0.028) *Controlling dimension: millimeters 8U4, 8-ball, die Ball Grid Array Package (dBGA) Dimensions in Millimeters and (Inches)* 16S1, 16-lead, 0.150" Wide, Plastic Gull Wing Small Outline (JEDEC SOIC) Dimensions in Inches and (Millimeters) TOP VIEW 0.020 (0.51) 0.013 (0.33) 2.95 (0.116) 0.158 (4.00) 0.150 (3.80) PIN 1 0.244 (6.20) 0.228 (5.80) 3.86 (0.152) .050 (1.27) BSC SIDE VIEW 8 1 7 2 6 3 5 4 0.394 (10.00) 0.386 (09.80) 0.38 (0.015) BOTTOM VIEW 0.069 (1.75) 0.053 (1.35) 0.010 (0.25) 0.004 (0.10) 0.75 (0.029) 0 REF 8 0.010 (0.25) 0.008 (0.19) 0.81 (0.032) 0.75 (0.029) 1.10 (0.043) 0.52 (0.020) 0.050 (1.27) 0.016 (0.40) *Controlling dimension: millimeters 19 0872G–01/01 AT25128/256 Packaging Information 14T, 14-lead, 0.170" Wide, Thin Shrink Small Outline Package (TSSOP) Dimensions in Millimeters and (Inches)* 20T, 20-lead, 0.170" Wide, Thin Shrink Small Outline Package (TSSOP) Dimensions in Millimeters and (Inches)* INDEX MARK INDEX MARK PIN 1 PIN 1 4.50 (.177) 4.30 (.169) 5.10 (.201) 4.90 (.193) .650 (.026) BSC 0.20 (.008) 0.09 (.004) 0 REF 8 4.50 (.177) 4.30 (.169) 6.60 (.260) 6.40 (.252) 1.20 (.047) MAX 0.15 (.006) 0.05 (.002) 0.30 (.012) 0.19 (.007) 6.50 (.256) 6.25 (.246) 0.75 (.030) 0.45 (.018) *Controlling dimension: millimeters SEATING PLANE .650 (.026) BSC 1.20 (.047) MAX 0.15 (.006) 0.05 (.002) 0.30 (.012) 0.19 (.007) 6.50 (.256) 6.25 (.246) SEATING PLANE 0.20 (.008) 0.09 (.004) 0 REF 8 0.75 (.030) 0.45 (.018) *Controlling dimension: millimeters 20 0872G–01/01 Atmel Headquarters Atmel Operations Corporate Headquarters Atmel Colorado Springs 2325 Orchard Parkway San Jose, CA 95131 TEL (408) 441-0311 FAX (408) 487-2600 Europe Atmel SarL Route des Arsenaux 41 Casa Postale 80 CH-1705 Fribourg Switzerland TEL (41) 26-426-5555 FAX (41) 26-426-5500 Asia Atmel Asia, Ltd. Room 1219 Chinachem Golden Plaza 77 Mody Road Tsimhatsui East Kowloon Hong Kong TEL (852) 2721-9778 FAX (852) 2722-1369 Japan 1150 E. Cheyenne Mtn. Blvd. Colorado Springs, CO 80906 TEL (719) 576-3300 FAX (719) 540-1759 Atmel Rousset Zone Industrielle 13106 Rousset Cedex France TEL (33) 4-4253-6000 FAX (33) 4-4253-6001 Atmel Smart Card ICs Scottish Enterprise Technology Park East Kilbride, Scotland G75 0QR TEL (44) 1355-357-000 FAX (44) 1355-242-743 Atmel Grenoble Avenue de Rochepleine BP 123 38521 Saint-Egreve Cedex France TEL (33) 4-7658-3000 FAX (33) 4-7658-3480 Atmel Japan K.K. 9F, Tonetsu Shinkawa Bldg. 1-24-8 Shinkawa Chuo-ku, Tokyo 104-0033 Japan TEL (81) 3-3523-3551 FAX (81) 3-3523-7581 Fax-on-Demand e-mail North America: 1-(800) 292-8635 [email protected] International: 1-(408) 441-0732 http://www.atmel.com Web Site BBS 1-(408) 436-4309 © Atmel Corporation 2001. Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company’s standard warranty which is detailed in Atmel’s Terms and Conditions located on the Company’s web site. The Company assumes no responsibility for any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does not make any commitment to update the information contained herein. No licenses to patents or other intellectual property of Atmel are granted by the Company in connection with the sale of Atmel products, expressly or by implication. Atmel’s products are not authorized for use as critical components in life support devices or systems. dBGA is a rademark of Atmel Corporation. Terms and product names in this document may be trademarks of others. Printed on recycled paper. 0872G–01/01/xM