ETC AT25010N-10SI-2.7

Features
• Serial Peripheral Interface (SPI) Compatible
• Supports SPI Modes 0 (0,0) and 3 (1,1)
• Low-voltage and Standard-voltage Operation
– 2.7 (VCC = 2.7V to 5.5V)
• 3.0 MHz Clock Rate (5V)
• 8-byte Page Mode
• Block Write Protection
– Protect 1/4, 1/2, or Entire Array
• Write Protect (WP) Pin and Write Disable Instructions for
SPI Serial
EEPROMs
Both Hardware and Software Data Protection
• Self-timed Write Cycle (10 ms max)
• High Reliability
– Endurance: One Million Write Cycles
– Data Retention: 100 Years
• Automotive Grade and Extended Temperature Devices Available
• 8-pin PDIP and 8-lead JEDEC SOIC Package
1K (128 x 8)
2K (256 x 8)
Description
4K (512 x 8)
The AT25010/020/040 provides 1024/2048/4096 bits of serial electrically erasable
programmable read only memory (EEPROM) organized as 128/256/512 words of 8
bits each. The device is optimized for use in many industrial and commercial applications where low-power and low voltage operation are essential. The AT25010/020/040
is available in space saving 8-pin PDIP and 8-lead JEDEC (SOIC) packages.
The AT25010/020/040 is enabled through the Chip Select pin (CS) and accessed via a
3-wire interface consisting of Serial Data Input (SI), Serial Data Output (SO), and
Serial Clock (SCK). All programming cycles are completely self-timed, and no separate ERASE cycle is required before WRITE.
AT25010
AT25020
AT25040
BLOCK WRITE protection is enabled by programming the status register with one of
four blocks of write protection. Separate program enable and program disable instructions are provided for additional data protection. Hardware data protection is provided
via the WP pin to protect against inadvertent write attempts. The HOLD pin may be
used to suspend any serial communication without resetting the serial sequence.
Pin Configurations
Pin Name
Function
CS
Chip Select
SCK
Serial Data Clock
SI
Serial Data Input
SO
Serial Data Output
GND
Ground
VCC
Power Supply
WP
Write Protect
HOLD
Suspends Serial Input
8-pin PDIP
CS
SO
WP
GND
1
2
3
4
8
7
6
5
VCC
HOLD
SCK
SI
8-lead SOIC
CS
SO
WP
GND
1
2
3
4
8
7
6
5
VCC
HOLD
SCK
SI
Rev. 0606G–SEEPR–02/02
1
Absolute Maximum Ratings*
Operating Temperature................................. -55°C to + 125°C
Storage Temperature .................................... -65°C to + 150°C
Voltage on Any Pin
with Respect to Ground ....................................-1.0V to + 7.0V
Maximum Operating Voltage .......................................... 6.25V
*NOTICE:
Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect
device reliability.
DC Output Current........................................................ 5.0 mA
Block Diagram
2
AT25010/020/040
0606G–SEEPR–02/02
AT25010/020/040
Pin Capacitance (1)
Applicable over recommended operating range from TA = 25°C, f = 1.0 MHz, VCC = +5.0V (unless otherwise noted).
Symbol
Test Conditions
COUT
CIN
Note:
Max
Units
Conditions
Output Capacitance (SO)
8
pF
VOUT = 0V
Input Capacitance (CS, SCK, SI, WP, HOLD)
6
pF
VIN = 0V
1. This parameter is characterized and is not 100% tested.
DC Characteristics
Applicable over recommended operating range from: TAI = -40°C to +85°C, VCC = +2.7V to +5.5V, TAC = 0°C to +70°C,
VCC = +1.8V to +5.5V (unless otherwise noted).
Symbol
Parameter
VCC1
Min
Max
Units
Supply Voltage
2.7
5.5
V
VCC2
Supply Voltage
4.5
5.5
V
ICC1
Supply Current
VCC = 5.0V at 1 MHz, SO = Open, Read
3.0
mA
ICC2
Supply Current
VCC = 5.0V at 2 MHz, SO = Open,
Read, Write
6.0
mA
ISB1
Standby Current
VCC = 2.7V
CS = VCC
5
µA
ISB2
Standby Current
VCC = 5.0V
CS = VCC
10
µA
IIL
Input Leakage
VIN = 0V to VCC
-0.6
3.0
µA
IOL
Output Leakage
VIN = 0V to VCC, TAC = 0°C to 70°C
-0.6
3.0
µA
Input Low Voltage
-0.6
VCC x 0.3
V
Input High Voltage
VCC x 0.7
VCC + 0.5
V
0.4
V
VIL(2)
VIH
(2)
VOL1
Output Low Voltage
VOH1
Output High Voltage
VOL2
Output Low Voltage
VOH2
Output High Voltage
Note:
Test Condition
4.5V ≤ VCC ≤ 5.5V
2.7V ≤ VCC ≤ 5.5V
IOL = 2.0 mA
IOH = -1.0 mA
VCC - 0.8
IOL = 0.15 mA
IOH = -100 µA
V
0.2
VCC - 0.2
V
V
1. This parameter is preliminary and Atmel may change the specifications upon further characterization.
2. VIL min and VIH max are reference only and are not tested.
3
0606G–SEEPR–02/02
AC Characteristics
Applicable over recommended operating range from TA = -40°C to +85°C, VCC = As Specified,
CL = 1 TTL Gate and 100 pF (unless otherwise noted).
Symbol
Parameter
Voltage
Min
Max
Units
fSCK
SCK Clock Frequency
4.5 - 5.5
2.7 - 5.5
0
0
3.0
2.1
MHz
tRI
Input Rise Time
4.5 - 5.5
2.7 - 5.5
2
2
µs
tFI
Input Fall Time
4.5 - 5.5
2.7 - 5.5
2
2
µs
tWH
SCK High Time
4.5 - 5.5
2.7 - 5.5
133
200
ns
tWL
SCK Low Time
4.5 - 5.5
2.7 - 5.5
133
200
ns
tCS
CS High Time
4.5 - 5.5
2.7 - 5.5
250
250
ns
tCSS
CS Setup Time
4.5 - 5.5
2.7 - 5.5
250
250
ns
tCSH
CS Hold Time
4.5 - 5.5
2.7 - 5.5
250
250
ns
tSU
Data In Setup Time
4.5 - 5.5
2.7 - 5.5
50
50
ns
tH
Data In Hold Time
4.5 - 5.5
2.7 - 5.5
50
100
ns
tHD
Hold Setup Time
4.5 - 5.5
2.7 - 5.5
100
100
ns
tCD
Hold Hold Time
4.5 - 5.5
2.7 - 5.5
200
200
ns
tV
Output Valid
4.5 - 5.5
2.7 - 5.5
0
0
tHO
Output Hold Time
4.5 - 5.5
2.7 - 5.5
0
0
tLZ
Hold to Output Low Z
4.5 - 5.5
2.7 - 5.5
0
0
tHZ
Hold to Output High Z
tDIS
tWC
Endurance(1)
Note:
4
133
200
ns
ns
100
100
ns
4.5 - 5.5
2.7 - 5.5
100
100
ns
Output Disable Time
4.5 - 5.5
2.7 - 5.5
250
500
ns
Write Cycle Time
4.5 - 5.5
2.7 - 5.5
5
10
ms
5.0V, 25°C, Page Mode
1M
Write Cycles
1. This parameter is characterized and is not 100% tested.
AT25010/020/040
0606G–SEEPR–02/02
AT25010/020/040
Serial Interface
Description
MASTER:
The device that generates the serial clock.
SLAVE: Because the Serial Clock pin (SCK) is always an input, the AT25010/020/040
always operates as a slave.
TRANSMITTER/RECEIVER: The AT25010/020/040 has separate pins designated for
data transmission (SO) and reception (SI).
MSB:
The Most Significant Bit (MSB) is the first bit transmitted and received.
SERIAL OP-CODE: After the device is selected with CS going low, the first byte will
be received. This byte contains the op-code that defines the operations to be performed.
The op-code also contains address bit A8 in both the READ and WRITE instructions.
INVALID OP-CODE: If an invalid op-code is received, no data will be shifted into the
AT25010/020/040, and the serial output pin (SO) will remain in a high impedance state
un til the falling edge of CS is de tected a gain. This will reinitialize the serial
communication.
CHIP SELECT: The AT25010/020/040 is selected when the CS pin is low. When the
device is not selected, data will not be accepted via the SI pin, and the serial output pin
(SO) will remain in a high impedance state.
H OLD: Th e HOLD p in is use d in conjunction w ith the C S pin to select th e
AT25010/020/040. When the device is selected and a serial sequence is underway,
HOLD can be used to pause the serial communication with the master device without
resetting the serial sequence. To pause, the HOLD pin must be brought low while the
SCK pin is low. To resume serial communication, the HOLD pin is brought high while the
SCK pin is low (SCK may still toggle during HOLD). Inputs to the SI pin will be ignored
while the SO pin is in the high impedance state.
WRITE PROTECT: The write protect pin (WP) will allow normal read/write operations
when held high. When the WP pin is brought low, all write operations are inhibited.
WP going low while CS is still low will interrupt a write to the AT25010/020/040. If the
internal write cycle has already been initiated, WP going low will have no effect on any
write operation.
5
0606G–SEEPR–02/02
SPI Serial Interface
Functional
Description
The AT25010/020/040 is designed to interface directly with the synchronous serial
peripheral interface (SPI) of the 6805 and 68HC11 series of microcontrollers.
The AT25010/020/040 utilizes an 8-bit instruction register. The list of instructions and
their operation codes are contained in Table 1. All instructions, addresses, and data are
transferred with the MSB first and start with a high-to-low CS transition.
Table 1. Instruction Set for the AT25010/020/040
Instruction Name
Instruction Format
Operation
WREN
0000 X110
Set Write Enable Latch
WRDI
0000 X100
Reset Write Enable Latch
RDSR
0000 X101
Read Status Register
WRSR
0000 X001
Write Status Register
READ
0000 A011
Read Data from Memory Array
WRITE
0000 A010
Write Data to Memory Array
Note:
6
“A” represents MSB address bit A8.
AT25010/020/040
0606G–SEEPR–02/02
AT25010/020/040
WRITE ENABLE (WREN): The device will power up in the write disable state when
VCC is applied. All programming instructions must therefore be preceded by a Write
Enable instruction. The WP pin must be held high during a WREN instruction.
WRITE DISABLE (WRDI): To protect the device against inadvertent writes, the Write
Disable instruction disables all programming modes. The WRDI instruction is independent of the status of the WP pin.
READ STATUS REGISTER (RDSR): The Read Status Register instruction provides
access to the status register. The READY/BUSY and Write Enable status of the device
can be determined by the RDSR instruction. Similarly, the Block Write Protection bits
indicate the extent of protection employed. These bits are set by using the WRSR
instruction.
Table 2. Status Register Format
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
X
X
X
X
BP1
BP0
WEN
RDY
Table 3. Read Status Register Bit Definition
Bit
Definition
Bit 0 (RDY)
Bit 0 = 0 (RDY) indicates the device is READY. Bit 0 = 1 indicates the
write cycle is in progress.
Bit 1 (WEN)
Bit 1 = 0 indicates the device is not WRITE ENABLED. Bit 1 = 1 indicates
the device is WRITE ENABLED.
Bit 2 (BP0)
See Table 4.
Bit 3 (BP1)
See Table 4.
Bits 4-7 are 0s when device is not in an internal write cycle.
Bits 0-7 are 1s during an internal write cycle.
WRITE STATUS REGISTER (WRSR): The WRSR instruction allows the user to
select one of four levels of protection. The AT25010/020/040 is divided into four array
segments. Top quarter (1/4), Top half (1/2), or all of the memory segments can be protected. Any of the data within any selected segment will therefore be READ only. The
block write protection levels and corresponding status register control bits are shown in
Table 4.
The two bits, BP1 and BP0 are nonvolatile cells that have the same properties and functions as the regular memory cells (e.g. WREN, tWC, RDSR).
Table 4. Block Write Protect Bits
Status Register Bits
Array Addresses Protected
Level
BP1
BP0
AT25010
AT25020
AT25040
0
0
0
None
None
None
1 (1/4)
0
1
60-7F
C0-FF
180-1FF
2 (1/2)
1
0
40-7F
80-FF
100-1FF
3 (All)
1
1
00-7F
00-FF
000-1FF
7
0606G–SEEPR–02/02
READ SEQUENCE (READ): Reading the AT25010/020/040 via the SO (Serial Output) pin requires the following sequence. After the CS line is pulled low to select a
device, the READ op-code (including A8) is transmitted via the SI line followed by the
byte address to be read (A7-A0). Upon completion, any data on the SI line will be
ignored. The data (D7-D0) at the specified address is then shifted out onto the SO line.
If only one byte is to be read, the CS line should be driven high after the data comes out.
The READ sequence can be continued since the byte address is automatically incremented and data will continue to be shifted out. When the highest address is reached,
the address counter will roll over to the lowest address allowing the entire memory to be
read in one continuous READ cycle.
WRITE SEQUENCE (WRITE): In order to program the AT25010/020/040, the Write
Protect pin (WP) must be held high and two separate instructions must be executed.
First, the device must be write enabled via the Write Enable (WREN) Instruction. Then
a Write (WRITE) Instruction may be executed. Also, the address of the memory location(s) to be programmed must be outside the protected address field location selected
by the Block Write Protection Level. During an internal write cycle, all commands will be
ignored except the RDSR instruction.
A Write Instruction requires the following sequence. After the CS line is pulled low to
select the device, the WRITE op-code (including A8) is transmitted via the SI line followed by the byte address (A7-A0) and the data (D7-D0) to be programmed.
Programming will start after the CS pin is brought high. (The LOW to High transition of
the CS pin must occur during the SCK low time immediately after clocking in the D0
(LSB) data bit.
The READY/BUSY status of the device can be determined by initiating a READ STATUS REGISTER (RDSR) Instruction. If Bit 0 = 1, the WRITE cycle is still in progress. If
Bit 0 = 0, the WRITE cycle has ended. Only the READ STATUS REGISTER instruction
is enabled during the WRITE programming cycle.
The AT25010/020/040 is capable of an 8-byte PAGE WRITE operation. After each byte
of data is received, the three low order address bits are internally incremented by one;
the six high order bits of the address will remain constant. If more than 8 bytes of data
are transmitted, the address counter will roll over and the previously written data will be
overwritten. The AT25010/020/040 is automatically returned to the write disable state at
the completion of a WRITE cycle.
NOTE: If the WP pin is brought low or if the device is not Write enabled (WREN), the
device will ignore the Write instruction and will return to the standby state, when CS is
brought high. A new CS falling edge is required to re-initiate the serial communication.
8
AT25010/020/040
0606G–SEEPR–02/02
AT25010/020/040
Timing Diagrams
Synchronous Data Timing (for mode 0)
t CS
VIH
CS
VIL
t CSH
t CSS
VIH
t WH
SCK
t WL
VIL
tH
t SU
VIH
SI
VALID IN
VIL
tV
VOH
SO
HI-Z
t HO
t DIS
HI-Z
VOL
WREN Timing
WRDI Timing
9
0606G–SEEPR–02/02
RDSR Timing
CS
0
1
2
3
4
5
6
7
8
9
10
7
6
5
11
12
13
14
2
1
SCK
INSTRUCTION
SI
SO
DATA OUT
HIGH IMPEDANCE
4
3
0
MSB
WRSR Timing
CS
0
1
2
3
4
5
6
7
8
9
10
11
7
6
5
4
12
13
14
15
2
1
0
SCK
INSTRUCTION
SI
SO
DATA IN
3
HIGH IMPEDANCE
READ Timing
10
AT25010/020/040
0606G–SEEPR–02/02
AT25010/020/040
WRITE Timing
CS
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
7
6
SCK
INSTRUCTION
SI
BYTE ADDRESS
8
5
4
3
2
1
DATA IN
0
7
6
5
4
3
2
1
0
9TH BIT OF ADDRESS
SO
HIGH IMPEDANCE
HOLD Timing
CS
tCD
tCD
SCK
tHD
tHD
HOLD
tHZ
SO
tLZ
11
0606G–SEEPR–02/02
AT25010 Ordering Information
tWC (max)
(ms)
ICC (max)
(µA)
ISB (max)
(µA)
fMAX
(kHz)
10
3000
100
2100
Ordering Code
Package
AT25010-10PI-2.7
AT25010N-10SI-2.7
8P3
8S1
Operation Range
Industrial
(-40°C to 85°C)
Package Type
8P3
8-pin, 0.300" Wide, Plastic Dual Inline Package (PDIP)
8S1
8-lead, 0.150" Wide, Plastic Gull Wing Small Outline Package (JEDEC SOIC)
Options
-2.7
12
Low Voltage (2.7V to 5.5V)
AT25010/020/040
0606G–SEEPR–02/02
AT25010/020/040
AT25020 Ordering Information
tWC (max)
(ms)
ICC (max)
(µA)
ISB (max)
(µA)
fMAX
(kHz)
10
3000
100
2100
Ordering Code
Package
AT25020-10PI-2.7
AT25020N-10SI-2.7
8P3
8S1
Operation Range
Industrial
(-40°C to 85°C)
Package Type
8P3
8-pin, 0.300" Wide, Plastic Dual Inline Package (PDIP)
8S1
8-lead, 0.150" Wide, Plastic Gull Wing Small Outline Package (JEDEC SOIC)
Options
-2.7
Low Voltage (2.7V to 5.5V)
13
0606G–SEEPR–02/02
AT25040 Ordering Information
tWC (max)
(ms)
ICC (max)
(µA)
ISB (max)
(µA)
fMAX
(kHz)
10
3000
100
2100
Ordering Code
Package
AT25040-10PI-2.7
AT25040N-10SI-2.7
8P3
8S1
Operation Range
Industrial
(-40°C to 85°C)
Package Type
8P3
8-pin, 0.300" Wide, Plastic Dual Inline Package (PDIP)
8S1
8-lead, 0.150" Wide, Plastic Gull Wing Small Outline Package (JEDEC SOIC)
Options
-2.7
14
Low Voltage (2.7V to 5.5V)
AT25010/020/040
0606G–SEEPR–02/02
AT25010/020/040
Packaging Information
8P3 – PDIP
E
1
E1
N
Top View
c
eA
End View
COMMON DIMENSIONS
(Unit of Measure = inches)
D
e
D1
A2 A
MIN
NOM
A2
0.115
0.130
0.195
b
0.014
0.018
0.022
5
b2
0.045
0.060
0.070
6
b3
0.030
0.039
0.045
6
c
0.008
0.010
0.014
D
0.355
0.365
0.400
D1
0.005
E
0.300
0.310
0.325
4
E1
0.240
0.250
0.280
3
SYMBOL
A
b2
b3
b
4 PLCS
Side View
L
Notes:
0.210
0.100 BSC
eA
0.300 BSC
0.115
NOTE
2
3
3
e
L
MAX
0.130
4
0.150
2
1. This drawing is for general information only; refer to JEDEC Drawing MS-001, Variation BA for additional information.
2. Dimensions A and L are measured with the package seated in JEDEC seating plane Gauge GS-3.
3. D, D1 and E1 dimensions do not include mold Flash or protrusions. Mold Flash or protrusions shall not exceed 0.010 inch.
4. E and eA measured with the leads constrained to be perpendicular to datum.
5. Pointed or rounded lead tips are preferred to ease insertion.
6. b2 and b3 maximum dimensions do not include Dambar protrusions. Dambar protrusions shall not exceed 0.010 (0.25 mm).
01/09/02
R
2325 Orchard Parkway
San Jose, CA 95131
TITLE
8P3, 8-lead, 0.300" Wide Body, Plastic Dual
In-line Package (PDIP)
DRAWING NO.
REV.
8P3
B
15
0606G–SEEPR–02/02
8S1 – JEDEC SOIC
3
2
1
H
N
Top View
e
B
A
D
COMMON DIMENSIONS
(Unit of Measure = mm)
Side View
A2
C
L
SYMBOL
MIN
NOM
MAX
A
–
–
1.75
B
–
–
0.51
C
–
–
0.25
D
–
–
5.00
E
–
–
4.00
e
E
End View
NOTE
1.27 BSC
H
–
–
6.20
L
–
–
1.27
Note: This drawing is for general information only. Refer to JEDEC Drawing MS-012 for proper dimensions, tolerances, datums, etc.
10/10/01
R
16
2325 Orchard Parkway
San Jose, CA 95131
TITLE
8S1, 8-lead (0.150" Wide Body), Plastic Gull Wing
Small Outline (JEDEC SOIC)
DRAWING NO.
REV.
8S1
A
AT25010/020/040
0606G–SEEPR–02/02
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© Atmel Corporation 2002.
Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company’s standard warranty
which is detailed in Atmel’s Terms and Conditions located on the Company’s web site. The Company assumes no responsibility for any errors
which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does
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