47V CY62146BV18 MoBL2TM 256K x 16 Static RAM Features • Low voltage range: — CY62146BV18: 1.65V–1.95V • Ultra-low active, standby power • Easy memory expansion with CE and OE features • TTL-compatible inputs and outputs • Automatic power-down when deselected • CMOS for optimum speed/power Functional Description The CY62146BV18 is a high-performance CMOS static RAM organized as 262,144 words by 16 bits. These devices feature advanced circuit design to provide ultra-low active current. This is ideal for providing More Battery Life™ (MoBL™) in portable applications such as cellular telephones. The devices also have an automatic power-down feature that significantly reduces power consumption by 99% when addresses are not toggling. The device can also be put into standby mode when deselected (CE HIGH). The input/output pins (I/O0 through I/O15) are placed in a high-impedance state when: deselected (CE HIGH), outputs are disabled (OE HIGH), BHE and BLE are disabled (BHE, BLE HIGH), or during a write operation (CE LOW, and WE LOW). Writing to the device is accomplished by taking Chip Enable (CE) and Write Enable (WE) inputs LOW. If Byte Low Enable (BLE) is LOW, then data from I/O pins (I/O0 through I/O7), is written into the location specified on the address pins (A0 through A17). If Byte High Enable (BHE) is LOW, then data from I/O pins (I/O8 through I/O15) is written into the location specified on the address pins (A0 through A17). Reading from the device is accomplished by taking Chip Enable (CE) and Output Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then data from the memory location specified by the address pins will appear on I/O0 to I/O7. If Byte High Enable (BHE) is LOW, then data from memory will appear on I/O8 to I/O15. See the truth table at the back of this data sheet for a complete description of read and write modes. The CY62146BV18 is available in 48-ball FBGA packaging. Logic Block Diagram SENSE AMPS A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 ROW DECODER DATA IN DRIVERS 256K x 16 RAM Array 2048 x 2048 I/O0 – I/O7 I/O8 – I/O15 COLUMN DECODER A10 A11 A12 A13 A14 A15 A16 A17 BHE WE CE OE BLE MoBL, MoBL2 and More Battery Life are trademarks of Cypress Semiconductor Corporation. Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600 May 2, 2001 CY62146BV18 MoBL2™ Pin Configuration FBGA Top View 4 3 1 2 BLE OE A0 I/O8 BHE I/O9 5 6 A1 A2 NC A A3 A4 CE I/O0 B I/O10 A5 A6 I/O1 I/O2 C VSS I/O11 A17 A7 I/O3 VCC D VCC I/O12 NC A16 I/O4 VSS E I/O14 I/O13 A14 A15 I/O5 I/O6 F I/O15 NC A12 A13 WE I/O7 G NC A8 A9 A10 A11 NC H Maximum Ratings DC Voltage Applied to Outputs in High Z State ................................... –0.5V to VCC + 0.5V (Above which the useful life may be impaired. For user guidelines, not tested.) DC Input Voltage .................................... −0.5V to VCC + 0.5V Output Current into Outputs (LOW)............................. 20 mA Storage Temperature ................................. –65°C to +150°C Static Discharge Voltage .......................................... >2001V (per MIL-STD-883, Method 3015) Ambient Temperature with Power Applied ............................................. –55°C to +125°C Latch-Up Current.................................................... >200 mA Supply Voltage to Ground Potential ............... –0.5V to +2.4V Operating Range Device CY62146BV18 Range Industrial Ambient Temperature –40°C to +85°C VCC 1.65V to 1.95V Product Portfolio Power Dissipation (Industrial) VCC Range Product CY62146BV18 Operating (ICC) VCC(min.) VCC(typ.) VCC(max.) 1.65V 1.80V 1.95V Standby (ISB2) Power Typ. Maximum Typ. Maximum Std. 3 mA 7 mA 5 µA 20 µA Notes: 1. VIL(min.) = –2.0V for pulse durations less than 20 ns. 2. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ.), TA = 25°C. 2 CY62146BV18 MoBL2™ Electrical Characteristics Over the Operating Range CY62146BV18 Parameter Description Test Conditions Min. Typ. Max. Unit VOH Output HIGH Voltage IOH = –0.1 mA VCC = 1.65V 1.5 VOL Output LOW Voltage IOL = 0.1 mA VCC = 1.65V VIH Input HIGH Voltage VCC = 1.95V 1.4 VCC + 0.2V V VIL Input LOW Voltage VCC = 1.65V –0.5 0.4 V IIX Input Load Current GND < VI < VCC –1 ±1 +1 µA IOZ Output Leakage Current GND < VO < VCC, Output Disabled –1 +1 +1 µA ICC VCC Operating Supply Current IOUT = 0 mA, f = fMAX = 1/tRC, CMOS Levels 3 7 mA 1 2 mA 5 20 µA 0.2 VCC = 1.95V IOUT = 0 mA, f = 1 MHz, CMOS Levels ISB2 Automatic CE Power-Down Current— CMOS Inputs VCC = 1.95V CE > VCC – 0.2V VIN > VCC – 0.2V or VIN < 0.2V, f = 0 V Std. V . Capacitance Parameter Description CIN Input Capacitance COUT Output Capacitance Test Conditions Max. Unit 6 pF 8 pF TA = 25°C, f = 1 MHz, VCC = VCC(typ.) Thermal Resistance Description Thermal Resistance (Junction to Ambient) Test Conditions Symbol BGA Units Still Air, soldered on a 4.25 x 1.125 inch, 4-layer printed circuit board ΘJA 55 °C/W ΘJC 16 °C/W Thermal Resistance (Junction to Case) Note: 3. Tested initially and after any design or process changes that may affect these parameters. 3 CY62146BV18 MoBL2™ AC Test Loads and Waveforms R1 R1 VCC ALL INPUT PULSES VCC OUTPUT VCC Typ OUTPUT INCLUDING JIG AND SCOPE Equivalent to: R2 5 pF R2 30 pF GND Rise TIme: 1 V/ns Fall Time: 1 V/ns INCLUDING JIG AND SCOPE (a) 90% 10% 90% 10% (C) (b) THÉVENIN EQUIVALENT RTH OUTPUT VTH Parameters 1.8V Unit R1 15294 Ohms R2 11300 Ohms RTH 6500 Ohms VTH 0.85V Volts . Data Retention Characteristics (Over the Operating Range) Parameter Description Conditions Min. Typ. 1.0 Max. Unit 1.95 V 10 µA VDR VCC for Data Retention ICCDR Data Retention Current tCDR Chip Deselect to Data Retention Time 0 ns tR Operation Recovery Time 70 ns VCC= 1.0V CE > VCC – 0.2V, VIN > VCC – 0.2V or VIN < 0.2V No input may exceed VCC + 0.2V Std. 3 Data Retention Waveform DATA RETENTION MODE VCC VCC(min.) VDR > 1.0 V VCC(min) tR tCDR CE Note: 4. Full Device AC operation requires linear VCC ramp from VDR to VCC(min.) > 10 µs or stable at VCC(min.) >10 µs. 4 CY62146BV18 MoBL2™ Switching Characteristics Over the Operating Range Parameter Description Min. Max. Unit READ CYCLE tRC Read Cycle Time 70 tAA Address to Data Valid tOHA Data Hold from Address Change tACE CE LOW to Data Valid 70 ns tDOE OE LOW to Data Valid 35 ns OE LOW to Low tHZOE OE HIGH to High Z tLZCE CE LOW to Low 70 Z[6, 7] tLZOE ns 10 ns 5 ns 25 Z 10 Z[6, 7] ns ns ns tHZCE CE HIGH to High 25 tPU CE LOW to Power-Up tPD CE HIGH to Power-Down 70 ns tDBE BHE / BLE LOW to Data Valid 70 ns tLZBE BHE / BLE LOW to Low Z tHZBE BHE / BLE HIGH to High Z 0 ns ns 5 ns 25 ns WRITE CYCLE[9, 10] tWC Write Cycle Time 70 ns tSCE CE LOW to Write End 60 ns tAW Address Set-Up to Write End 60 ns tHA Address Hold from Write End 0 ns tSA Address Set-Up to Write Start 0 ns tPWE WE Pulse Width 50 ns tBW BHE / BLE Pulse Width 60 ns tSD Data Set-Up to Write End 30 ns tHD Data Hold from Write End 0 ns tHZWE tLZWE WE LOW to High Z[6, 7] WE HIGH to Low Z 35 10 ns ns Notes: 5. Test conditions assume signal transition time of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to VCC(typ.), and output loading of the specified IOL/IOH and 30 pF load capacitance. 6. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device. 7. tHZOE, tHZCE, and tHZWE are specified with CL = 5 pF as in part (b) of AC Test Loads. Transition is measured ±500 mV from steady-state voltage. 8. If both byte enables are toggled together this value is 10ns 9. The internal write time of the memory is defined by the overlap of CE LOW and WE LOW. Both signals must be LOW to initiate a write and either signal can terminate a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write. 10. The minimum write cycle time for Write Cycle #3 (WE controlled, OE LOW) is the sum of tHZWE and tSD. 5 CY62146BV18 MoBL2™ Switching Waveforms Read Cycle No. 1 [11, 12] tRC ADDRESS tOHA DATA OUT tAA PREVIOUS DATA VALID DATA VALID Read Cycle No. 2 [12, 13] tRC CE tPD tHZCE tACE OE tHZOE tDOE BHE/BLE tLZOE tHZBE tDBE tLZBE DATA OUT HIGH IMPEDANCE HIGH IMPEDANCE DATA VALID tLZCE VCC SUPPLY CURRENT tPU ICC 50% 50% ISB Notes: 11. Device is continuously selected. OE, CE = VIL. 12. WE is HIGH for read cycle. 13. Address valid prior to or coincident with CE transition LOW. 6 CY62146BV18 MoBL2™ Switching Waveforms (continued) [9, 14, 15] Write Cycle No. 1 (WE Controlled) tWC ADDRESS CE tAW tHA tSA WE tPWE tBW BHE/BLE OE tSD DATA I/O tHD DATAIN VALID NOTE 16 tHZOE Write Cycle No. 2 (CE Controlled) [8, 14, 15] tWC ADDRESS tSCE CE tSA tAW BHE/BLE WE tHA tBW tPWE tSD DATA I/O DATAIN VALID Notes: 14. Data I/O is high-impedance if OE = VIH. 15. If CE goes HIGH simultaneously with WE HIGH, the output remains in a high-impedance state. 16. During this period, the I/Os are in output state and input signals should not be applied. 7 tHD CY62146BV18 MoBL2™ Switching Waveforms (continued) Write Cycle No. 3 (WE Controlled, OE LOW) [10, 15] tWC ADDRESS CE tAW tBW BHE/BLE WE tHA tSA tHD tSD DATA I/O DATAIN VALID NOTE 16 tLZWE tHZWE  Write Cycle No. 4 (BHE/BLE Controlled, OE LOW) tWC ADDRESS CE tAW tHA tBW BHE/BLE tSA WE tSD DATA I/O tHD DATAIN VALID NOTE 16 tLZWE tHZWE 8 CY62146BV18 MoBL2™ Typical DC and AC Characteristics Normalized Operating Current 1.2 Standby Current vs. Supply Voltage 35 MoBL2 30 1.0 25 vs. Supply Voltage 1.4 ISB (µA) ICC MoBL2 0.8 0.6 20 15 0.4 10 0.2 5 0.0 1.65 1.8 SUPPLY VOLTAGE (V) 0 1.95 1.65 2.2 1.95 1.8 SUPPLY VOLTAGE (V) Access Time vs. Supply Voltage 90 80 70 MoBL2 TAA (ns) 60 50 40 30 20 1.65 2.2 1.95 1.8 SUPPLY VOLTAGE (V) Truth Table CE WE OE BHE BLE H X X X X High Z Inputs/Outputs Deselect/Power-Down Standby (ISB) L H L L L Data Out (I/OO–I/O15) Read Active (ICC) L H L H L Data Out (I/OO–I/O7); I/O8–I/O15 in High Z Read Active (ICC) L H L L H Data Out (I/O8–I/O15); I/O0–I/O7 in High Z Read Active (ICC) L H H L L High Z Deselect/Output Disabled Active (ICC) L H H H L High Z Deselect/Output Disabled Active (ICC) L H H L H High Z Deselect/Output Disabled Active (ICC) L L X L L Data In (I/OO–I/O15) Write Active (ICC) L L X H L Data In (I/OO–I/O7); I/O8–I/O15 in High Z Write Active (ICC) L L X L H Data In (I/O8–I/O15); I/O0–I/O7 in High Z Write Active (ICC) 9 Mode Power CY62146BV18 MoBL2TM Ordering Information Speed (ns) Ordering Code Package Name 70 CY62146BV18LL -70BAI BA49 Operating Range Package Type 48-Ball Fine Pitch BGA Industrial Document #: 38-01046-*A Package Diagrams 48-Ball (7.00 mm x 8.5 mm x 1.1 mm) Thin BGA BA49 51-85106-B © Cypress Semiconductor Corporation, 2001. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.