MoBL CY62148V MoBL™ 512K x 8 MoBL Static RAM The device can be put into standby mode when deselected (CE HIGH). Features • Low voltage range: — 2.7V–3.6V • Ultra low active power • Low standby power • TTL-compatible inputs and outputs • Automatic power-down when deselected • CMOS for optimum speed/power Writing to the device is accomplished by taking Chip Enable (CE) and Write Enable (WE) inputs LOW. Data on the eight I/O pins (I/O0 through I/O7) is then written into the location specified on the address pins (A0 through A18). Reading from the device is accomplished by taking Chip Enable (CE) and Output Enable (OE) LOW while forcing Write Enable (WE) HIGH. Under these conditions, the contents of the memory location specified by the address pins will appear on the I/O pins. Functional Description The CY62148V is a high-performance CMOS static RAM organized as 524,288 words by 8 bits. This device features advanced circuit design to provide ultra-low active current. This is ideal for providing More Battery Life™ (MoBL™) in portable applications such as cellular telephones. The device also has an automatic power-down feature that significantly reduces power consumption by 99% when addresses are not toggling. The eight input/output pins (I/O0 through I/O7) are placed in a high-impedance state when the device is deselected (CE HIGH), the outputs are disabled (OE HIGH), or during a write operation (CE LOW and WE LOW). The CY62148V is available in a 36-ball FBGA, 32 pin TSOPII, and a 32-pin SOIC package. Logic Block Diagram I/O0 Data in Drivers I/O1 512K x 8 ARRAY I/O2 SENSE AMPS ROW DECODER A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 I/O3 I/O4 I/O5 COLUMN DECODER CE I/O6 POWER DOWN I/O7 A10 A11 A12 A13 A14 A15 A16 A17 A18 WE OE Cypress Semiconductor Corporation • 3901 North First Street 62148V-1 • San Jose • CA 95134 • 408-943-2600 March 23, 2000 CY62148V MoBL™ Pin Configurations FBGA Top View TSOPII/SOIC Top View A17 A16 A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O0 I/O1 I/O2 VSS 1 2 3 4 32 31 30 29 5 6 28 27 7 8 9 10 26 25 11 12 22 21 20 19 18 17 13 14 15 16 24 23 VCC A15 A18 WE A13 A8 A9 A11 OE A10 CE I/O7 I/O6 I/O 5 I/O4 I/O3 1 2 3 4 5 6 A0 A1 NC A3 A6 A8 A I/O4 A2 WE A4 A7 I/O0 B NC A5 I/O1 C VSS VCC D VCC VSS E I/O2 F I/O5 I/O6 A18 A17 I/O7 OE CE A16 A15 I/O3 G A9 A10 A11 A12 A13 A14 H 62148V–2 DC Input Voltage ................................ –0.5V to V CC + 0.5V Maximum Ratings Output Current into Outputs (LOW)............................. 20 mA (Above which the useful life may be impaired. For user guidelines, not tested.) Static Discharge Voltage .......................................... >2001V (per MIL-STD-883, Method 3015) Storage Temperature ................................. –65°C to +150°C Latch-Up Current .................................................... >200 mA Ambient Temperature with Power Applied ............................................... 55°C to +125°C Operating Range Supply Voltage to Ground Potential ............... –0.5V to +4.6V Range DC Voltage Applied to Outputs in High Z State ....................................–0.5V to VCC + 0.5V Ambient Temperature VCC –40°C to +85°C 2.7V to 3.6V Industrial Product Portfolio Power Dissipation (Industrial) Product CY62148V VCC Range Operating (ICC) Min. Typ. Max. 2.7V 3.0V 3.6V Speed Typ. 70 ns 7 Standby (ISB2) Maximum Ty.p Maximum 15 mA 2 µA 20 µA Notes: 1. VIL(min.) = –2.0V for pulse durations less than 20 ns. 2. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ.), TA = 25°C. 2 CY62148V MoBL™ Electrical Characteristics Over the Operating Range CY62148V Parameter Description Test Conditions Min. Typ. Max. Unit VOH Output HIGH Voltage IOH = –1.0 mA VCC = 2.7V 2.4 VOL Output LOW Voltage IOL = 2.1 mA VCC = 2.7V VIH Input HIGH Voltage VIL Input LOW Voltage 0.8 V IIX Input Load Current GND < VI < VCC –1 +1 +1 µA IOZ Output Leakage Current GND < VO < VCC, Output Disabled –1 +1 +1 µA ICC VCC Operating Supply Current IOUT = 0 mA, (f = fMAX = 1/tRC) CMOS Levels VCC = 3.6V 7 15 mA IOUT = 0 mA, f = 1 MHz CMOS Levels 1 ISB1 Automatic CE Power-Down Current— CMOS Inputs CE > V CC − 0.3V, VIN > VCC − 0.3V or VIN < 0.3V, f = fMAX ISB2 Automatic CE Power-Down Current— CMOS Inputs CE > VCC − 0.3V VIN > VCC − 0.3V or VIN < 0.3V, f = 0 VCC = 3.6V 2.2 VCC = 2.7V –0.5 VCC = 3.6V V 0.4 V VCC + 0.5V V 2 mA 100 µA L 1 50 µA LL 2 20 µA Capacitance Parameter Description CIN Input Capacitance COUT Output Capacitance Test Conditions Max. Unit 6 pF 8 pF TA = 25°C, f = 1 MHz, VCC = 3.0V Thermal Resistance Description  Thermal Resistance (Junction to Ambient) Test Conditions Symbol Others BGA Units Still Air, soldered on a 4.25 x 1.125 inch, 4-layer printed circuit board ΘJA TBD TBD °C/W ΘJC TBD TBD °C/W Thermal Resistance (Junction to Case) Note: 3. Tested initially and after any design or process changes that may affect these parameters. 3 CY62148V MoBL™ AC Test Loads and Waveforms R1 VCC ALL INPUT PULSES OUTPUT VCC Typ R2 30 pF 90% 10% 90% 10% GND Fall time: 1 V/ns Rise Time: 1 V/ns INCLUDING JIG AND SCOPE 62148V–4 62148V–3 Equivalent to: THÉVENIN EQUIVALENT R TH OUTPUT V TH Parameters 3.0V Unit R1 1105 Ohms R2 1550 Ohms RTH 645 Ohms VTH 1.75V Volts Data Retention Characteristics (Over the Operating Range) Parameter Description Conditions VDR VCC for Data Retention ICCDR Data Retention Current tCDR Chip Deselect to Data Retention Time tR Operation Recovery Time Min. Typ. 1.0 VCC = 1.0V CE > VCC − 0.3V, VIN > VCC − 0.3V or VIN < 0.3V No input may exceed VCC+0.3V L/ LL 0.2 Max. Unit 3.6 V 5.5 µA µA 0 ns tRC ns Note: 4. Full Device AC operation requires linear VCC ramp from VDR to VCC(min.) > 10 µs or stable at VCC(min.) > 10 µs. Data Retention Waveform DATA RETENTION MODE VCC 1.0V VDR > 1.0 V 1.0V tR tCDR CE 62148V–5 4 CY62148V MoBL™ Switching Characteristics Over the Operating Range (2.7V–3.6V Operation) Parameter Description Min. Max. Unit READ CYCLE tRC Read Cycle Time 70 tAA Address to Data Valid tOHA Data Hold from Address Change tACE CE LOW to Data Valid 70 ns tDOE OE LOW to Data Valid 35 ns OE LOW to Low Z tHZOE OE HIGH to High Z[7 ] tLZCE CE LOW to Low Z 10 CE HIGH to High Z tPU CE LOW to Power-Up tPD CE HIGH to Power-Down ns 25 10 [6, 7] ns ns 5  tHZCE WRITE 70  tLZOE ns ns ns 25 0 ns ns 70 ns CYCLE[8, 9] tWC Write Cycle Time 70 ns tSCE CE LOW to Write End 60 ns tAW Address Set-Up to Write End 60 ns tHA Address Hold from Write End 0 ns tSA Address Set-Up to Write Start 0 ns tPWE WE Pulse Width 50 ns tSD Data Set-Up to Write End 30 ns tHD Data Hold from Write End 0 ns tHZWE tLZWE WE LOW to High Z [6, 7] WE HIGH to Low Z 25  10 ns ns Notes: 5. Test conditions assume signal transition time of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to VCC(typ.), and output loading of the specified I OL/IOH and 30 pF load capacitance. 6. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device. 7. t HZOE, tHZCE, and t HZWE are specified with CL = 5 pF as in part (b) of AC Test Loads. Transition is measured ±200 mV from steady-state voltage. 8. The internal write time of the memory is defined by the overlap of CE LOW and WE LOW. Both signals must be LOW to initiate a write and either signal can terminate a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write. 9. The minimum write cycle time for Write Cycle #3 (WE controlled, OE LOW) is the sum of tHZWE and tSD. 5 CY62148V MoBL™ Switching Waveforms Read Cycle No. 1 [10, 11] tRC ADDRESS tOHA DATA OUT tAA DATA VALID PREVIOUS DATA VALID 62148V–6 Read Cycle No. 2 [11, 12] tRC CE tACE OE DATA OUT tHZOE tHZCE tDOE tLZOE HIGH IMPEDANCE HIGH IMPEDANCE DATA VALID tLZCE VCC SUPPLY CURRENT tPD tPU ICC 50% 50% ISB 62148V–7 [8, 13, 14] Write Cycle No. 1 (WE Controlled) tWC ADDRESS CE tAW tHA tSA WE tPWE OE tSD DATA I/O NOTE 15 tHD DATAIN VALID tHZOE 62148V–8 Notes: 10. Device is continuously selected. OE, CE = VIL. 11. WE is HIGH for read cycle. 12. Address valid prior to or coincident with CE transition LOW. 13. Data I/O is high impedance if OE = VIH. 14. If CE goes HIGH simultaneously with WE HIGH, the output remains in a high-impedance state. 15. During this period, the I/Os are in output state and input signals should not be applied. 6 CY62148V MoBL™ Switching Waveforms (continued) Write Cycle No. 2 (CE Controlled) [8, 13, 14] tWC ADDRESS tSCE CE tSA tAW tHA WE tSD DATA I/O tHD DATAIN VALID 62148V–9 Write Cycle No. 3 (WE Controlled, OE LOW) [9, 14] tWC ADDRESS CE tAW WE tHA tSA tSD DATA I/O tHD DATAIN VALID NOTE 15 tLZWE tHZWE 62148–10 7 CY62148V MoBL™ Typical DC and AC Characteristics 1.4 Standby Current vs. Supply Voltage 45 Normalized Operating Current vs. Supply Voltage 40 1.2 35 ISB (µA) ICC 1.0 0.8 0.6 25 20 0.4 15 0.2 0.0 1.7 30 2.2 2.7 3.2 SUPPLY VOLTAGE (V) 10 1.0 3.7 3.7 2.8 1.9 SUPPLY VOLTAGE (V) Access Time vs. Supply Voltage 80 70 60 TAA (ns) 50 40 30 20 10 1.0 2.8 1.9 3.7 SUPPLY VOLTAGE (V) Truth Table CE WE OE Inputs/Outputs Mode H X X High Z Deselect/Power-Down Standby (ISB) L H L Data Out Read Active (ICC) L L X Data In Write Active (ICC) L H H High Z Output Disabled Active (ICC) 8 Power CY62148V MoBL™ Ordering Information Speed (ns) 70 Ordering Code Package Name Operating Range Package Type CY62148VLL-70BAI BA37 36-Ball Fine Pitch BGA CY62148VLL-70ZI ZS32 32-Lead TSOPII CY62148VLL-70SI S34 Industrial 32-Lead 450 mil. molded SOIC Document #: 38-00646-C Package Diagrams 36-Ball (7.00 mm x 8.5 mm x 1.5 mm) Thin BGA BA37 51-85105-A 9 CY62148V MoBL™ Package Diagrams (continued) 32-Lead (450 MIL) Molded SOIC S34 10 CY62148V MoBL™ Package Diagrams (continued) 32-Lead TSOP II ZS32 51-85095 © Cypress Semiconductor Corporation, 1999. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.