24-Bit, 10mW, 125ksps Analog to Digital
Converter in 16 lead TSSOP
AD7766
Preliminary Technical Data
FEATURES
PRODUCT OVERVIEW
High performance 24-bit ADC
114dB SNR at 31.25 KHz output data rate
111dB SNR at 62.5 KHz output data rate
108dB SNR at 125 KHz output data rate
Max 20mW Power Consumption
10mW typ at 31.25 KHz output data rate
12mW typ at 62.5 KHz output data rate
15 mW typ at 125 KHz output data rate
High DC accuracy
24 Bits No Missing Codes (NMC)
Integral Non Linearity 15 ppm
Low temperature drift
Offset Drift ±25 nV/°C
On Chip Low pass FIR filter
Linear Phase Response
Passband Ripple: ±0.005dB
Stopband Attenuation: 100dB
2.5V Supply with 1.8V/2.5V/3V/3.6V logic interface
Flexible Interfacing options
Synchronization of multiple devices
Daisy Chain capability
Temp Range -40oC to 105oC
The AD7766 is high performance 24-bit over-sampled analog to
digital converter combining wide dynamic range and input
bandwidth with an on chip FIR filter while consuming only
20mW max power in a 16 pin TSSOP package.
Specifically designed for ultra low power data acquisition,
providing 24-bit resolution and high SNR makes the device
ideal for measuring small signal changes over a wide dynamic
range. This is particularly important in many data acquisition
applications where small changes are measured on larger AC or
DC signals. In addition the AD7766 provides excellent DC
accuracy and drift specifications making the device suitable
where DC data also needs to be acquired. The AD7766
improves SNR performance and simplifies anti aliasing
requirements through over-sampling which is important in
minimizing input signal distortion to the inputs of the ADC. A
high performance on-chip FIR filter subsequently filters the
over-sampled data and removes out of band noise. A SYNC/PD
(Synchronisation/Power down) pin is an added feature,
allowing for easy synchronization of multiple devices. The
device operates from -40oC to 105oC.
By combining wide dynamic range and high SNR at output data
rates up to 125ksps with ultra low power the AD7766 provides a
compact solution for low power data acquisition such as PCI or
USB based systems.
APPLICATIONS
Low-Power PCI/USB Data Acquisition Systems
Low-Power Wireless Acquisition Systems
Vibration Analysis
Instrumentation
RELATED DEVICES
Table 1. 24 bit Analog to Digital Converters
FUNCTIONAL BLOCK DIAGRAM
AVDD
AGND
MCLK
DVDD
VDRIVE
Part No
Speed
AD7760
2.5MSPs
AD7762/3
625KSPs
AD7764
312KSps
AD7765
156KSPs
AD7767
125KSPs
DGND
VREF+
DIGITAL
FIR FILTER
VIN+
CONVERTER
VIN-
REFGND
AD7766/
AD7766-1/
AD7766-2
SERIAL INTERFACE
&
CONTROL LOGIC
SCLK
DRDY SDO
SYNC/PD
CS
SDI
Figure 1.
1
Rev. PrD
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responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
Description
100dB Dynamic Range1
On-board Diff Amp & Ref Buffer
Parallel, Variable Decimation
109dB Dynamic Range1
On-Board Diff Amp & Ref buffer
Parallel/Serial, Variable Decimation
109dB Dynamic Range1
On-board Diff Amp & Ref Buffer
Serial, Variable Decimation (pin)
112dB Dynamic Range1
On-board Diff Amp & Ref Buffer
Serial,Variable Decimation (pin)
109dB Dynamic Range1
10mW power dissipation
Serial interface
Dynamic Range at max output data rate.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2006 Analog Devices, Inc. All rights reserved.
AD7766
Preliminary Technical Data
TABLE OF CONTENTS
PRODUCT OVERVIEW............................................................. 1
Initial Power-Up ......................................................................... 13
Revision History ............................................................................... 2
Reading Data............................................................................... 13
AD7766/AD7766-1/AD7766-2—Specifications .......................... 3
Power Down, Reset & Synchronization .................................. 13
Timimg Diagrams............................................................................. 5
Daisy Chaining ............................................................................... 14
Timing Specifications....................................................................... 7
Reading Data in Daisy chain Mode ......................................... 14
Absolute Maximum Ratings............................................................ 8
Choosing the SCLK frequency ................................................. 14
ESD Caution.................................................................................. 8
Daisy Chain Mode Configuration & Timing Diagrams ....... 15
Pin Configuration and Function Descriptions............................. 9
Driving the AD7766....................................................................... 16
Typical Performance Characteristics ........................................... 10
Differential Signal Source ......................................................... 16
Terminology .................................................................................... 11
Single-Ended signal source ....................................................... 16
Theory of Operation ...................................................................... 12
Digital Filtering............................................................................... 17
AD7766 Transfer Function ....................................................... 12
Outline Dimensions ....................................................................... 18
AD7766 Interface............................................................................ 13
Ordering Guide............................................................................... 18
REVISION HISTORY
Rev. PrD | Page 2 of 18
Preliminary Technical Data
AD7766
AD7766/AD7766-1/AD7766-2—SPECIFICATIONS
Table 2. AVDD = DVDD = 2.5 V ± 5%, VDRIVE = 1.8 V to 3.6 V, VREF = 5 V, MCLK = 1MHz, TA = -40°C to +105°C, unless otherwise
noted
Parameter
OUTPUT DATA RATE
AD7766
AD7766-1
AD7766-2
ANALOG INPUT1
Differential Input Voltage
Absolute Input Voltage
Common mode Input Voltage
Input Capacitance
Differential Input Impedance
DYNAMIC PERFORMANCE
AD7766
Dynamic Range2
Signal to Noise Ratio (SNR)2
Spurious Free Dynamic Range (SFDR)2
Total Harmonic Distortion (THD) 2
Intermodulation Distortion (IMD) 2
AD7766-1
Dynamic Range2
Signal to Noise Ratio (SNR)2
Spurious Free Dynamic Range2 (SFDR)
Total Harmonic Distortion (THD) 2
Intermodulation Distortion (IMD) 2
AD7766-2
Dynamic Range2
Signal to Noise Ratio (SNR) 2
Spurious Free Dynamic Range (SFDR)2
Total Harmonic Distortion (THD) 2
Intermodulation Distortion (IMD) 2
DC ACCURACY1
Resolution
Differential Nonlinearity2
Integral Nonlinearity2
Zero Error2
Gain Error2
Zero Error Drift2
Gain Error Drift2
Power Supply Rejection2
Common mode rejection2
DIGITAL FILTER RESPONSE1
Group Delay
Settling time (latency)
Passband ripple
Passband
-3dB bandwidth
Stopband
Stopband Attenuation
Test Conditions/Comments
Specifcation
Unit
Decimate × 8
Decimate × 16
Decimate × 32
125
62.5
31.25
KHz max
KHz max
KHz max
Vin(+) – Vin(-)
Vin(+)
Vin(-)
±VREF
-0.1 | +VREF + 0.1
-0.1 | +VREF + 0.1
VREF/2 ± 0.1
V pk-pk
V min | max
Decimate by 8, ODR = 125 ksps
Shorted inputs
108
TBD
-96
TBD
dB typ
dB typ
dBFS typ
dB max
dB typ
111
TBD
-96
TBD
dB typ
dB typ
dBFS typ
dB max
dB typ
114
TBD
-96
TBD
dB typ
dB typ
dBFS typ
dB max
dB typ
24
Bits
15
TBD
TBD
±25
±0.3
TBD
TBD
ppm
% typ
% typ
nV/°C typ
ppm/°C typ
dB typ
dB
37/ODR
74/ODR
±0.005
TBD
TBD
TBD
100
µs typ
µs typ
dB max
Hz
Hz
Hz
dB min
Decimate by 16, ODR = 62.5 ksps
Shorted inputs
Decimate by 32, ODR = 31.25 ksps
Shorted inputs
No Missing Codes
Guaranteed monotonic to 24 bits
16 bit linearity
f = 50Hz, 60Hz
Complete Settling
Rev. PrD | Page 3 of 18
V
pF typ
Ohms
AD7766
Parameter
REFERENCE INPUT1
VREF+ Input Voltage
Preliminary Technical Data
Test Conditions/Comments
Specifcation
Unit
+2.4
2 x AVDD
TBD
V min
V max
Ohms
-0.3
0.3 x VDRIVE
0.7 x VDRIVE
VDRIVE + 0.3
TBD
TBD
TBD
1
30
Vmin
Vmax
Vmin
Vmax
uA max
uA/pin max
pF max
MHz typ
MHz max
0.4
VDRIVE – 0.3
V max
V min
+2.375/+2.625
+2.375/+2.625
+1.7/+3.6
V min/max
V min/max
V min/max
1.4
3.2
0.7
0.8
mA typ
mA typ
mA typ
mA typ
1.4
1.8
0.7
0.8
mA typ
mA typ
mA typ
mA typ
VDRIVE = 3.6V Full-scale code output, TBD pF load.
1.4
1.1
0.7
0.8
mA typ
mA typ
mA typ
mA typ
125 KHz Output Data Rate (Dec × 8)
62.5 KHz Output Data Rate (Dec × 16)
31.25 KHz Output Data Rate (Dec × 32)
(All decimation rates)
15
12
10
TBD
mW typ
mW typ
mW typ
mW typ
Reference Input Impedance
DIGITAL INPUTS (Logic Levels)1
VIL
VIH
VIH
Input Current
Input leakage
Input Capacitance
Master Clock rate
Serial Clock rate
DIGITAL OUTPUTS1
Data Format
VOL
VOH
POWER REQUIREMENTS1
AVDD
DVDD
VDRIVE
AD7766 Current Specifications
AIDD
DIDD
IREF
IDRIVE
AD7766-1 Current Specifications
AIDD
DIDD
IREF
IDRIVE
AD7766-2 Current Specifications
AIDD
DIDD
IREF
IDRIVE
Power Dissapation
AD7766
AD7766-1
AD7766-2
Power Down 1
1
2
Serial 24 bits Two’s Complement (MSB 1st)
ISINK = +500 µA
ISOURCE = -500 µA
125 Khz Output Data Rate
VDRIVE = 3.6V, Full-scale code output, TBD pF load.
62.5 Khz Output Data Rate
VDRIVE = 3.6V, Full-scale code output, TBD pF load.
31.25 Khz Output Data Rate
Specifications for all devices, AD7766, AD7766-1 and AD7766-2.
See Terminology
Rev. PrD | Page 4 of 18
Preliminary Technical Data
AD7766
TIMIMG DIAGRAMS
t2
1
MCLK
1
8*n
t3
8*n
t4
t5
t1
DRDY
t5
tREAD
tDRDY
Figure 2.DRDY versus MCLK TimingDiagram. For AD7766 n=1(Decimate by8), AD7766-1 n=2(Decimate by 16), AD7766-2 n = 4(Decimate by 32).
tDRDY
DRDY
tREAD
t13
t6
CS
t10
23
1
SCLK
t11
t8
t7
t12
t9
SDO
MSB
D22
D20
D21
LSB
D1
Figure 3.Serial timing diagram, reading data using CS
CS = 0
tDRDY
DRDY
tREAD
t14
t10
23
1
SCLK
24
t11
t8
SDO
DATA
INVALID
MSB
D22
t15
t9
D21
D20
D1
Figure 4.Serial timing diagram, reading data setting CS logic low.
Rev. PrD | Page 5 of 18
LSB
DATA
INVALID
AD7766
Preliminary Technical Data
Part out of Power down
Filter Reset
Part in Power down
B
A
MCLK (I)
Begins Sampling
C
D
t20
t18
SYNC/PD (I)
t21
t19
DRDY (O)
DOUT (O)
tSETTLING
VALID DATA
INVALID DATA
Figure 5.Reset and Synchronization and Power down timing diagram.
Rev. PrD | Page 6 of 18
VALID DATA
Preliminary Technical Data
AD7766
TIMING SPECIFICATIONS
Table 3. AVDD = DVDD = 2.5 V ± 5%, VDRIVE = 1.7 V to 3.6 V, VREF = 5 V, TA = -40°C to +105°C, unless otherwise noted1
Parameter
DRDY Operation
t1
t2
t3
t4
t5
tREAD 2
tDRDY2
Read Operation
t6
t7
t8
t9
t10
t11
t12
t13
Read Operation with CS low
t14
t15
Daisy Chain Operation
t16
t17
Synchronise Operation
t18
t19
t20
t21
tSETTLING2
Min
Typ
Unit
Test Conditions/Comments
TBD
TBD
TBD
TBD
TBD
tDRDY - t5
ns
ns
ns
ns
ns
ns
DRDY Falling edge to MCLK rising edge
MCLK High Pulsewidth
MCLK Low Pulsewidth
MCLK Rising edge to DRDYRising edge
DRDY Pulse width
DRDY low period. Read data during this period.
n×8×tMCLK
ns
DRDY Period.
0
TBD
TBD
TBD
TBD
TBD
TBD
0
ns
ns
ns
ns
ns
ns
ns
ns
DRDY Falling Edge to CS Setup Time
CS Falling Edge to SDO three-state disabled
Data access time after SCLK falling edge
SCLK Falling Edge to Data Valid hold time
SCLK High Pulsewidth
SCLK Low Pulsewidth
Bus Relinquish Time after CS Rising Edge
CS Rising Edge to DRDY Rising Edge
TBD
0
ns
ns
DRDY Falling Edge to Data valid Setup Time
DRDY Rising Edge to Data Valid hold time
TBD
TBD
ns
ns
SDI Valid to SCLK Falling Edge Setup Time
SCLK Falling Edge to SDI Valid Hold Time
ns
ns
ns
ns
tMCLK
SYNC/PD Falling edge to MCLK Rising Edge
MCLK Rising edge to DRDY Rising Edge
SYNC/PD Rising edge to MCLK Rising Edge
MCLK Rising edge to DRDY Falling edge coming out of SYNC/PD
Filter Settling Time after a Reset or power down.
TBD
TBD
TBD
TBD
592×n +2
Max
1
Sample tested during initial release to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of DVDD) and timed from a voltage level of
1.6 V
2
n = 1 for AD7766, n= 2 for the AD7766-1, n=4 for the AD7766-2.
Rev. PrD | Page 7 of 18
AD7766
Preliminary Technical Data
ABSOLUTE MAXIMUM RATINGS
Table 4. TA = 25°C, unless otherwise noted.
Parameters
AVDD to AGND
DVDD to DGND
AVDD to DVDD
VREF+ to VREFVREF- to AGND
VDRIVE to DGND
VIN+, VIN– to AGND
Digital inputs to DGND
Digital Outputs to DGND
AGND to DGND
Input current to any pin except
supplies1
Operating temperature range
Storage temperature range
Junction temperature
TSSOP Package
θJA Thermal Impedance
θJC Thermal Impedance
Lead temperature, soldering
Vapor phase (60 secs)
Infrared (15 secs)
ESD
Rating
-0.3V to +3V
-0.3V to +3V
-0.3V to + 0.3V
-0.3V to +7V
-0.3V to + 0.3V
-0.3V to +6V
-0.3V to VREF +0.3V
-0.3V to VDRIVE + 0.3V
-0.3V to VDRIVE + 0.3V
-0.3V to + 0.3V
±10mA
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those listed in the operational sections
of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
−40°C to +105°
−65°C to +150°C
150°C
150.4°C/W
27.6°C/W
215°C
220°C
TBD kV
1
Transient currents of up to TBD mA do not cause SCR latch-up.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the
human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Rev. PrD | Page 8 of 18
Preliminary Technical Data
AD7766
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
AVDD 1
VREF+ 2
REFGND
3
16 CS
AD7766/
AD7766-1/
AD7766-2
15 SDI
14 MCLK
13 SCLK
TOP VIEW
VIN- 5 (Not to Scale) 12 DRDY
11 DGND
AGND 6
VIN+ 4
SYNC/PD 7
DVDD 8
10 SDO
9
VDRIVE
Figure 6.16-Lead TSSOP Pin Configuration
Table 5. Pin Function Descriptions
Pin
Number
1
2
Pin Mnemonic
Description
AVDD
VREF+
3
REFGND
4
5
6
7
VIN+
VINAGND
SYNC/PD
8
9
DVDD
VDRIVE
+2.5V Analog power supply.
Reference Input for the AD7766. An external reference must be applied to this input pin. The
VREF+ input can range from 2.4V to 5V. The reference voltage input is independent of the
voltage magnitude applied to the AVDD pin.
Reference Ground. Ground Connection for the reference voltage. The input reference voltage
(VREF+) should be decoupled to this pin.
Positive input of the Differential Analog input.
Negative input of the Differential Analog input.
Power supply ground for Analog circuitry.
Synchronisation and Power Down Input pin. This pin has dual functionality. It can be used to
synchronise multiple AD7766 devices and/or put the AD7766 device into power down mode.
See the Power Down, Reset & Synchronization section for further details.
Digital Power Supply input. This pin can be connected directly to VDRIVE.
Logic power supply input, +1.8V to +3.6V. The voltage supplied at this pin will determine the
operating voltage of the digital logic interface.
10
SDO
11
12
DGND
DRDY
13
SCLK
14
MCLK
15
SDI
16
CS
Serial Data Output (SDO). The conversion result from the AD7766 is output on the SDO pin as a
24 bit, two’s complement, MSB first, serial data stream.
Digital logic power supply ground
Data Ready Output. A falling edge on the DRDY signal indicates that a new conversion data
result is available in the output register of the AD7766. See the AD7766 Interface section for
further details.
Serial Clock Input. The SCLK input provides the serial clock for all serial data transfers with the
AD7766 device. See the AD7766 Interface Section for further details.
Master Clock Input. The AD7766 sampling frequency is directly proportional to the MCLK
frequency.
Serial Data Input. This is the Daisy-Chain input of the AD7766. See the
Daisy Chaining section for further details.
Chip Select Input. The CS input selects the AD7766 device, and acts as an enable on the SDO
pin. In cases where CS is used, the MSB of the conversion result is clocked onto the SDO line on
the CS falling edge. The CS input allows multiple AD7766 devices to share the same SDO line.
This allows the user to select the appropriate device by supplying it with a logic low CS signal,
which enables the SDO pin of the device concerned. See the AD7766 Interface section for
further details.
Rev. PrD | Page 9 of 18
AD7766
Preliminary Technical Data
TYPICAL PERFORMANCE CHARACTERISTICS
Figure 7
Figure 10
Figure 8
Figure 11
Figure 9
Rev. PrD | Page 10 of 18
Preliminary Technical Data
AD7766
TERMINOLOGY
Signal-to-Noise Ratio (SNR)
SNR is the ratio of the rms value of the actual input signal to the
ms sum of all other spectral components below the Nyquist
frequency, excluding harmonics and dc. The value for SNR is
expressed in decibels.
Total Harmonic Distortion (THD)
THD is the ratio of the rms sum of harmonics to the fundamental.
For the AD7766, it is defined as
THD (dB ) = 20 log
V 22 + V32 + V 42 + V 52 + V62
V1
Integral Nonlinearity (INL)
INL is the maximum deviation from a straight line passing
through the endpoints of the ADC transfer function.
Differential Nonlinearity (DNL)
DNL is the difference between the measured and the ideal
1 LSB change between any two adjacent codes in the ADC.
Zero Error
Zero error is the difference between the ideal midscale input
voltage (when both inputs are shorted together) and the actual
voltage producing the midscale output code.
where:
V1 is the rms amplitude of the fundamental.
V2, V3, V4, V5, and V6 are the rms amplitudes of the second to
the sixth harmonics.
Zero Error Drift
Zero error drift is the change in the actual zero error value due
to a temperature change of 1°C. It is expressed as a percentage
of full scale at room temperature.
Nonharmonic Spurious-Free Dynamic Range (SFDR)
SFDR is the ratio of the rms signal amplitude to the rms value
of the peak spurious spectral component, excluding harmonics.
Gain Error
The first transition (from 100 … 000 to 100 … 001) should
occur for an analog voltage ½ LSB above the nominal negative
full scale. The last transition (from 011 … 110 to 011 … 111)
should occur for an analog voltage 1½ LSB below the nominal
full scale. The gain error is the deviation of the difference
between the actual level of the last transition and the actual
level of the first transition, from the difference between the
ideal levels.
Dynamic Range
Dynamic range is the ratio of the rms value of the full scale to
the rms noise measured with the inputs shorted together. The
value for the dynamic range is expressed in decibels.
Intermodulation Distortion
With inputs consisting of sine waves at two frequencies, fa and
fb, any active device with nonlinearities creates distortion products
at sum and difference frequencies of mfa ± nfb, where m, n = 0,
1, 2, 3, and so on. Intermodulation distortion terms are those
for which neither m nor n are equal to 0. For example, the secondorder terms include (fa + fb) and (fa − fb), and the third-order
terms include (2fa + fb), (2fa − fb), (fa + 2fb), and (fa − 2fb).
Gain Error Drift
Gain error drift is the change in the actual gain error value due
to a temperature change of 1°C. It is expressed as a percentage
of full scale at room temperature.
The AD7766 is tested using the CCIF standard, where two input
frequencies near the top end of the input bandwidth are used.
In this case, the second-order terms are usually distanced in
frequency from the original sine waves, and the third-order
terms are usually at a frequency close to the input frequencies.
As a result, the second- and third-order terms are specified
separately. The calculation of the intermodulation distortion is
as per the THD specification, where it is the ratio of the rms
sum of the individual distortion products to the rms amplitude
of the sum of the fundamentals expressed in decibels.
Rev. PrD | Page 11 of 18
AD7766
Preliminary Technical Data
THEORY OF OPERATION
AD7766 TRANSFER FUNCTION
The AD7766 is high performance 24-bit over-sampled analog to
digital converter combining wide dynamic range and input
bandwidth with an on chip FIR filter while consuming only
20mW max power in a 16 pin TSSOP package. The AD7766 is
available with 3 preset decimation rates, 8, 16 and 32. Table 6
shows the three available models of the AD7766. The three
models differ in the preset decimation rate employed. The
output data rates of the AD7766, AD7766-1 and the AD7766-2
are relative to each of their preset decimation rates.
The AD7766 outputs its conversion results in a 2’s complement,
24-bit serial format. The fully differential inputs VIN+ and
VIN- are scaled by the AD7766 relative to the reference voltage
input (VREF+) as shown in Figure 12.
24-Bits
2’s Complement
011…111
011…110
000…010
Table 6. AD7766 Models.
Decimation Rate
Output Data Rate (ODR)
AD7766
8
125 KHz
AD7766-1
16
62.5 KHz
AD7766-2
32
31.25 KHz
000…001
AD7766
24-Bit 000…000
Output
111…111
111…110
100…001
In decimate × 8 mode the output will be updated every 8 MCLK
periods, offering a maximum output data rate of 125KHz for
the AD7766 device. The AD7766-1 model is set in decimate ×
16 mode, and the AD7766-2 is preset to decimate × 32. The
decimation ratio of each model indicates the level of filtering
employed in the on-board digital FIR filter. The higher filter
decimation rates provide the user with increased dynamic
specifications; however, there is a trade-off on throughput as the
filter delay increases as higher decimation rates are introduced.
100…000
VIN + = 0V
VIN - = VREF -1LSB
VIN + = VREF
2
VIN - = VREF
2
Figure 12.AD7766 TransferFunction
.
Rev. PrD | Page 12 of 18
VIN + = VREF - 1LSB
VIN - = 0V
Preliminary Technical Data
AD7766
AD7766 INTERFACE
devices indicating permission to use the bus. When CS logic
high, the SDO line of the AD7766 is is tri-stated.
The AD7766 provides the user with a flexible serial interface
enabling the user to implement the most desireable interfacing
scheme for their application. The AD7766 interface is
comprised of seven different signals. Five of these signals are
inputs : MCLK CS, SYNC/PD, SCLK, and SDI. There are two
output signals, DRDY and SDO.
There are two distinct patterns that can be initiated to read data
from the AD7766 device, these are for the cases when CS falling
edge occurs after the DRDY falling edge and for the case when
the CS falling edge occurs before the DRDY falling edge (when
CS is set to logic low.
INITIAL POWER-UP
On initial power up, apply a continuous MCLK signal. Iit is
recommended that the user reset the AD7766 to clear the filters
and ensure correct operation. The reset is completed as
described in Figure 5, with all events occurring relative to the
rising edge of MCLK. A negative pulse on the SYNC/PD input
initiates the reset and the DRDY output will switch to logic high
and will remain high until valid data is available.. Following the
power up of the AD7766 by transitioning the SYNC/PD pin to
logic high, a settling time is required before valid data is output
by the device. This settling time, tSETTLING, is a function of the
MCLK frequency and the decimation rate. Table 7 lists the
settling time of each of the AD7766 models, and should be
referenced to Figure 5..
When CS is tied low the AD7766 serial interface can operate in
3-wire mode as shown in Figure 4. In this case the MSB of the
conversion result is available on the SDO line on the falling
edge of DRDY. The remaining bits of the data conversion result
(MSB-1, MSB-2 etc..) are clocked onto the SDO line by the
subsequent SCLK falling edges.
POWER DOWN, RESET & SYNCHRONIZATION
Table 7. Filter settling time after SYNC/PD
1
When the CS falling edge occurs after DRDY falling edge the
MSB of the conversion result is becomes available on the SDO
line on this CS falling edge. The remaining bits of the
conversion result (MSB-1, MSB-2 ..etc) are clocked onto the
SDO line by the falling edges of SCLK which follow the CS
falling edge. Figure 3 details this interfacing scheme.
1
Decimation Rate
tSETTLING
AD7766
8
594 × tMCLK + t21
AD7766-1
16
1,186 × tMCLK + t21
AD7766-2
32
2,370 × tMCLK + t21
tSETTLING is measured from the first MCLK rising edge after the rising edge of
SYNC/PDto the falling edge of DRDY.
READING DATA
The AD7766 outputs its data conversion results in an MSB first,
2’s complement 24-bit format on the Serial Data Output Pin
(SDO). MCLK is the master clock, which controls all the
AD7766 conversions. The SCLK is the serial clock input for the
device. All data transfers take place with respect to the SCLK
signal
The DRDY line is used as a status signal to indicate when the
data is available to be read from the AD7766. The falling edge of
DRDY indicates that a new data word is available in the output
register of the device. DRDY stays low during the period that
output data is permitted to be read from the SDO pin. The
DRDY signal returns to logic high to indicate when not to read
from the device. Ensure that a data read is not attempted during
this period as the output register is being updated
The AD7766 offers the user the option of using a chip select
input signal (CS) in its data read cycle. The CS signal is a gate
for the SDO pin and allows many AD7766 devices to share the
same serial bus acting as an instruction signal to each of these
The AD7766’s SYNC/PD pin allows the user to synchronise
multiple AD7766 devices. This pin also allows the user to reset
and power down the AD7766 device. These features are
implemented relative to the rising edges of MCLK and are
shown in Figure 5
To power down, reset or synchronise a device the AD7766
SYNC/PD pin should be taken low. On the first rising edge of
MCLK the AD7766 is powered down. The DRDY pin
transitions to logic high indicating that the data in the output
register is no longer valid. The status of the SYNC/PD pin is
checked on each subsequent rising edge of MCLK. On the first
rising edge of MCLK after the SYNC/PD pin is taken high the
AD7766 is taken out of power down. On the next rising edge,
the filter of the AD7766 is reset. On the following rising edge,
the first new sample is taken.
A settling time, tSETTLING, from the filter reset, must pass before
valid data is output by the device (as listed in Table 7). The
DRDY output goes logic low after tSETTLING to indicate when
valid data is available on SDO for readback.
AD7766
Preliminary Technical Data
DAISY CHAINING
Daisy chaining devices allows numerous devices to use the same
digital interface lines by cascading the outputs of multiple
ADC’s on a single data line. This feature is especially useful for
reducing component count and wiring connections, e.g. in
isolated multi-converter applications or for systems with a
limited interfacing capacity. Data read-back is analogous to
clocking a shift register where data is clocked on the falling edge
of SCLK.
The period of SCLK (tSCLK) required for a known daisy chain
length using a known common MCLK frequency must
therefore be established in advance. In the case where CS is tied
logic low:
Equation 1
tSCLK
The block diagram in Figure 13 shows the way in which devices
must be connected in order to achieve daisy chain functionality.
This scheme operates by passing the output data of the SDO pin
of an AD7766 device to the SDI input of the next AD7766
device in the chain. The data then continues through the chain
until it is clocked onto the SDO pin of the first device on the
chain.
READING DATA IN DAISY CHAIN MODE
=
]
{n x 8 x tMCLK } - {tDRDY Hi }
24 x K
]
Where K = Number of AD7766 devices in the chain
n is the AD7766 model number being used, where for
AD7766 n= 1, AD7766-1 n= 2, AD7766-2 n= 4.
tMCLK is the period of the MCLK.
tDRDY Hi ~ Where DRDY is logic high between conversion
results.
In the case where CS is used in the daisy chain interface:
An example of a daisy chain of four AD7766 devices is shown in
Figure 13 and Figure 14. In the case illustrated in Figure 13 the
output of AD7766 (A) is the output of the full daisy chain. The
last device in the chain (AD7764(D)) will have its Serial Data In
(SDI) pin connected to ground. All the devices in the chain
must use common MCLK, SCLK, CS and SYNC/PD signals.
Equation 2
tSCLK
CHOOSING THE SCLK FREQUENCY
]
{n x 8 x tMCLK } - { t6 + t7 + t13 + tDRDY Hi }
24 x K
]
K = Number of AD7766 devices in the chain
n = AD7766 model number being used,
{AD7766 n= 1, AD7766-1 n= 2, AD7766-2 n= 4}
tMCLK is the period of the MCLK.
tCS = Time when CS is logic low (SDO is active).
To enable the daisy chain conversion process, apply a common
SYNC/PD pulse to all devices synchronizing all the devices in
the chain (see Power Down, Reset & Synchronization section).
After applying a SYNC/PD pulse to all the devices there is a
delay (as listed in Table 7) before valid conversion data appears
at the output of the chain of devices. As shown in Figure 14 the
first conversion result is output from the device labeled
AD7766(A). This 24-bit conversion result is then followed by
the conversion results from the devices B, C and D respectively
with all conversion results output in an MSB first sequence. The
stream of conversion results are clocked through each device in
the chain and are eventually clocked onto the SDO pin of the
AD7766 (A) device. The conversion results of the all the devices
in the chain must be clocked onto the SDO pin of the final
device in the chain while its DRDY signal is active low. This is
illustrated in the example shown where the conversion results
from devices A, B, C, & D are be clocked onto SDO (A) in the
time between the falling edge of DRDY (A) and the rising edge
of DRDY (A).
=
If it is the case that the SCLK frequency is chosen firstly then it
is the SCLK for any given MCLK, which determines the limit of
the number of AD7766 devices that can be successfully daisychained.
Table 8 SCLK Frequency required for a given number of
daisy-chained devices using a 1MCLK frequency.
No. Of Devices
MCLK (MHz)
SCLK Frequency
(MHz)1
2
1
TBD/(n)
4
1
TBD/(n)
8
1
TBD/(n)
16
1
TBD/(n)
1
n = 1 for AD7766, n= 2 for the AD7766-1, n=4 for the AD7766-2.
As shown in Figure 13 the number of SCLK falling edges that
occur during the period when DRDY (A) is active low must
match the number of devices in the chain multiplied by 24 (the
number of bits that must be clocked through onto SDO (A) for
each device).
Rev. PrD | Page 14 of 18
Preliminary Technical Data
AD7766
DAISY CHAIN MODE CONFIGURATION & TIMING DIAGRAMS
SYNC/PD
CS
SYNC/PD
SYNC/PD
SDI
SYNC/PD
CS
CS
SDI
AD7766
(D)
SDO
SDI
SCLK
AD7766
(C)
SDI
SDO
CS
AD7766
(B)
SDO
DRDY
AD7766
(A)
SDI
SCLK
SCLK
MCLK
SYNC/PD
CS
SCLK
MCLK
MCLK
MCLK
SCLK
MCLK
Figure 13 AD7766 Daisy chain configuration with 4 ×AD7766 devices..
MCLK
8*n
1
DRDY(A)
CS
24 x tSCLK
24 x tSCLK
24 x tSCLK
24 x tSCLK
SDO (A)
AD7766 (A)
AD7766 (B)
AD7766 (C)
AD7766 (D)
SDI (A) = SDO (B)
AD7766 (B)
AD7766 (C)
AD7766 (D)
SDI (B) = SDO (C)
AD7766 (C)
AD7766 (D)
SDI (C) = SDO (D)
AD7766 (D)
SCLK
AD7766 (A)
AD7766 (B)
AD7766 (C)
AD7766 (D)
Figure 14 AD7766 Daisy chain Timing diagram. For AD7766 n=1, AD7766-1 n =2, AD7766-2 n= 4. Driving the AD7766
1
MCLK
DRDY(A)
CS
SDO (A)
MSB (A)
t16
SDI (A) = SDO (B)
MSB (B)
LSB (A)
MSB (B)
LSB (B)
MSB (C)
LSB (C)
LSB (B)
MSB (C)
LSB (C)
MSB (D)
LSB (D)
t17
Figure 15 AD7766 Daisychain SDI Set-up and hold timing .
SDO
AD7766
Preliminary Technical Data
DRIVING THE AD7766
The AD7766 must be driven with fully differential inputs. The
common mode voltage of the differential inputs to the AD7766
device and thus the limits on the differential inputs are set by
the reference voltage VREF applied to the device. The common
mode voltage of the AD7766 is VREF/2. Where the AD7766 VREF
pin is supplied with a 5V supply (the ADR435 is
reccommended) the common mode is at 2.5V. This means that
the max inputs that can be applied on the AD7766 differential
inputs are a 5V pk-pk input around 2.5V.
DIFFERENTIAL SIGNAL SOURCE
An example of some recommended driving circuitry that can be
employed in conjunction with the AD7766 is shown in Figure
17. Figure 17 shows how the ADA4841 device can be used to
drive an input to the AD7766 from a differential source. Each of
the differential is driven by an ADA4841 device.
499R
3.3nF
499R
AIN+
VREF
2.5V
3R3
ADA4841
VREF
1
V IN +
2
AVDD
4 VIN+
499R
10nF
3.3nF
AD7766
5 VIN-
0V
VREF+
499R
AIN-
2
3R3
VREF
ADA4841
2x VCM
1K
VREF
ADR425
1K
V IN –
2
Figure 17. Driving the AD7766 from a fully differential source
0V
Figure 16 Maximum differential inputs to the AD7766
An analog voltage of 2.5V supplies the AD7766 AVDD pin.
However, the AD7766 allows the user to apply a reference
voltage of up to 5V. This provides the user with an increased
full-scale range, offering the user the option of using the
AD7766 with a larger LSB voltage size Figure 16 shows the
maximum and minimum inputs to the AD7766.
SINGLE-ENDED SIGNAL SOURCE
In the case where the AD7766 is being supplied from a singleended source the following application circuit can be used to
drive the AD7766 device. Figure 18 shows how the ADA4941
single to differential amplifier can be used to create a fully
differential input to the AD7766. The single-ended signal input
is applied to the positive input of the ADA4941 device
Vss R1
2.5V
IN
DIS
V-
5
6
C1
7
R1
8
Ain +
OUT-
R3
1
4 V
IN+
C2
ADA4941
AD7766
5 VIN-
R3
2
2
OUT+
R4
ADR425
R2
Voffset
C3
R5
2 xVCM
R2
Vss +
RFB
CFB
Figure 18. Driving the AD7766 from a single- ended source.
Rev. PrD | Page 16 of 18
VREF+
4
V+
3
REF
1
FB
AVDD
Preliminary Technical Data
AD7766
DIGITAL FILTERING
The AD7766 has an on-board digital FIR filter. The FIR filter’s
decimation rate is preset for each AD7766 model (See Table 6
for details). The digital filter consists of three separate filter
blocks. Figure 19 shows the three constituent blocks of the filter.
The order of decimation of the first filter block is either set as
either 2, 4 or 8. The remaining sections have a decimation rate
of 2. The settling time of the filter implemented on the AD7766,
AD7766-1 and AD7766-2 is related to the amount of
decimation employed, the filter settling time of each device is
shown in Table 7.
0
-20
-40
( dB )
-60
-80
Digital Filter
Data
Stream
The response of the digital filter on board the AD7766 is shown
in Figure 20.. The filter provides stop-band attenuation of
100dB and passband ripple of ± 0.005dB.
Stage 1
Stage 2
Stage 3
7th Order
Sinc Filter
FIR Filter
FIR Filter
Dec x (2 x n)
Dec x 2
Dec x 2
-100
SDO
103
104
105
(Hz)
Figure 20.AD7766 Filter Response for AD7766 (MCLK =1Mhz, ODR = 125Khz)
Figure 19.FIR filter stages
(n = 1 for AD7766, n= 2 for AD7766-1, n = 4 for AD7766-2)
AD7766
Preliminary Technical Data
OUTLINE DIMENSIONS
5.10
5.00
4.90
16
9
4.50
4.40
4.30
6.40
BSC
1
8
PIN 1
1.20
MAX
0.15
0.05
0.20
0.09
0.30
0.19
0.65
BSC
COPLANARITY
0.10
SEATING
PLANE
8°
0°
0.75
0.60
0.45
COMPLIANT TO JEDEC STANDARDS MO-153-AB
Figure 21 16-Lead Thin Shrink Small Outline Package
ORDERING GUIDE
Model
AD7766BRUZ1
AD7766BRUZ-11
AD7766BRUZ-21
1
Temperature Range
−40°C to +105°
−40°C to +105°
−40°C to +105°
Package Description
16-Lead Thin Shrink Small Outline Package
16-Lead Thin Shrink Small Outline Package
16-Lead Thin Shrink Small Outline Package
Z = Pb-free part.
©2006 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
PR06449-0-11/06(PrD)
Rev. PrD | Page 18 of 18
Package Option
RU-16
RU-16
RU-16