2002•February Inverter-type air conditioners The V850 SeriesTM of embedded microcontrollers answers diversified needs in all kinds of application systems. It realizes lower power consumption and noise while achieving higher performance and multiple functions. Consisting of a rich lineup, the V850 Series offers optimum solutions for nextgeneration embedded systems. Digital video cameras 2 Automotive electronics DVD players Digital still cameras Cellular phones Storage devices Fax machines Pamphlet U15412EJ1V0PF Single-lens reflex cameras Network modems Microwave ranges PDA Washing machines Digital video recorders Printers Home audio Vending machines Electronic music instruments Car audio Car AV centers Pamphlet U15412EJ1V0PF 3 V850 POSITION Performance NEC Microcontroller Lineup VR SeriesTM VR4x00 / 5x00 VR1x000 64-bit MIPS RISC Microprocessors V850E/Mxx high-end lineup V850 Series 32-bit RISC microcontrollers V850, V850ES, V850E ASSP lineup V850ES, V850/Sxx low-end lineup 78K Series 8/16-bit microcontrollers Sys 78K4 Low-End Da rol ta ess ing Mid-range 16-bit microcontrollers 78K0 78K0S tem t con c pro High-End 8-bit microcontrollers 75X/XL 17K 8-bit 16-bit 32-bit Price ROADMAP External 32-bit bus 80 to 100 MHz High-end lineup V850E1 core 124 MIPS /100 MHz @ 0.35 µm or lower V850E2/xxx Enhanced MEMC 33 to 40 MHz SDRAM compatible 40 to 50 MHz V850E/Mxx V850E/MAx V850E/MSx 33 MHz with on-chip flash memory V853TM V850 core 38 MIPS /33 MHz @ 0.8 µm or lower V850 ASSP lineup V850E ASSP lineup V850/Sxx low-power lineup V850ES low-power lineup Low-end lineup : Under development 4 Pamphlet U15412EJ1V0PF High-end applications Instruction set upward compatible V850E2 core 200 to 266 MHz @ 0.13 µm or lower Low-end applications V850 INDEX 5KEYS V850 06 Architecture 1 8 Variety of Peripheral Functions 27 Low Power & Low Noise 32 Middleware 36 Flash Memory Microcontrollers 38 Functional Outline 42 Comfortable Development Environment 53 Information Pamphlet U15412EJ1V0PF 61 5 5KEYS V850 Processor products Data processing V850E2 High Performance Scalable coverage of 20 MHz to over 100 MHz 3 to 4 times higher performance at same frequency compared to 16-bit microcontrollers V850, V850ES, and V850E1 cores are upward compatible at object level. V850 Series covers a broad range from middle to high-end market with a single instruction set 100MHz Applicable down to middle-range models 32-bit microcontrollers of other companies V850E1 50MHz 33MHz V850 3-4 times higher performance Applicable up to high-end models 16-bit microcontrollers of other companies 20MHz V850ES V850 System control : Under development V850E/Mxx Extensive Product Lineup From low-end/high-end general-purpose products all the way to ASSP lineup Low-end lineup designed for 8/16-bit market (V850ES, V850/Sxx) High-end lineup with on-chip MEMC, DMA, that pursues high performance (V850E) ASSP lineup with on-chip dedicated hardware optimized for various fields (V850E, V850ES, V850/Sxx) Automotive High-end lineup Sophisticated memory I/F OA V850E/xxx V850E1 core V850ES/xxx V850ES core On-chip dedicated hardware V850 core Industrial V850/xxx ASSP lineup Communications Low power, low noise, expanded internal memory Information appliances V850ES/xxx V850/Sxx Low-end lineup Consumer electronics Amusement machines FAX Additional Functions DSC JBIG 6 ADPCM TTS Video processing Enriched middleware lineup JPEG Electronic dictionaries Handwriting recognition MH/MR/MMR Toys Rich lineup of middleware related to video, audio, networks, etc., optimized for the V850 Realization of peripheral functions through V850 + middleware combination Shorter development time, lower system cost Portable terminals Human interface Middleware Home appliances AV equipment Phones Car audio Speech recognition Browser Network Java Pamphlet U15412EJ1V0PF TCP/IP System System Integration Process Design environment Analog P C I /F CPU DSP IP Memory Flash High-performance CPU cores Logic DRAM By meeting the five conditions consisting of leading-edge process technology, high-performance CPU cores, a rich lineup of IP cores, a top-down design environment, and a flexible application environment, the V850 Series offers optimum system-on-chip solutions. middleware Middleware IP cores CPU Core Lineup 700 500 V850E3 0.1µm process [MIPS] 200 V850E3/xxx Nx85E3 350MHz V850E2 300 0.13µm process Nx85E2 260MHz Nx85E2 200MHz V850E1 V850E2/xxx xxx V850E2/xxx Nx85E 100MHz 100 0.25µm process xxx V850E3/xxx V850E/MAx Nx85E 66MHz 66 0.35µm process 33 V850E/MA1TM V850E/IA1 TM MA2TM IA2TM V850 2000 2005 Utilization of existing functions Improved operability Accessible Development Enviroment Rich lineup and high operability Inherits operability of 78K Series. Shorter software development TAT through superior operability and sophisticated development environment Easy C-language support through high-performance CPUs and real-time OS embedding possible 78K Development Environment V850 Development Environment PM PM Project Manager Project Manager CC (Compiler) Higher versatility CA (Compiler) RX (Real-time OS) Higher performance RX (Real-time OS) Debugging support + RD (Task debugger) + AZ (Analyzer) SM (Simulator) Debugging support SM (Simulator) ID (Debugger) Improved operability ID (Debugger) IE (In-circuit emulator) Support of high speed IE (In-circuit emulator) Pamphlet U15412EJ1V0PF V850 products Realize a sophisticated and powerful development environment through: •High performance •General-purpose registers •Large-capacity memory 7 V850E Product Development Concept Pursuit of high performance High-performance CPU using V850E core 10% higher performance than V850 CPU at same frequency 10% to 20% higher code efficiency than V850 CPU through addition of C-compatible instructions Upward compatibility at object level with V850 CPU cores Enhanced external bus performance On-chip direct interface for various memories SRAM, page ROM, EDO DRAM, synchronous DRAM, etc. On-chip DMA controller Realization of voluminous data processing and high-performance control on one chip [Low Voltage] In mass production External 32-bit bus Under development Higher performance 144-pin LQFP/161-pin FBGA In planning V850E/MA1 On-chip SDRAM controller ROMless/4 KB to 256 KB/10 KB On-chip 256 KB flash memory 50 MHz @ 3.0 to 3.6 V (5 V tolerance) Higher performance 144-pin LQFP/157-pin FBGA (3.3 V only) More compact 100-pin LQFP V850E/MA2 On-chip SDRAM controller ROMless/4 KB 40 MHz @ 3.0 to 3.6 V V850E/MS1TM(3.3V) V850E/MS1(5V) On-chip DRAM controller ROMless/4 KB to 128 KB/4 KB On-chip 128 KB flash memory 33 MHz @ 3.0 to 3.6 V 33 MHz @ 3.0 to 3.6 V/ 4.5 to 5.5 V (external) Higher performance Enhanced peripheral functions 100-pin LQFP 16-bit V SeriesTM 8 Higher performance 100-pin LQFP V850E/IA1 More compact On-chip inverter and timer 256 KB/10 KB On-chip 256 KB flash memory 50 MHz @ 3.0 to 3.6 V/ 4.5 to 5.5 V (external) V850E/MS2TM Higher performance [5 V ] 144-pin LQFP ROMless/4 KB 33 MHz @ 3.0 to 3.6 V/ 4.5 to 5.5 V (external) V850E/Mxx 80 to 100MHz 100-pin LQFP Higher performance Enhanced peripheral functions V853 96KB/4KB to 256KB/8KB On-chip 128 KB, 256 KB flash memory 33 MHz @4.5 to 5.5V 78K/III Pamphlet U15412EJ1V0PF V850E/IA2 On-chip inverter and timer 128KB/6KB On-chip 128 KB flash memory 40 MHz @4.5 to 5.5V V850E Product Features V850E/MS1 Performance of 43 MIPS @ 33 MHz On-chip memory controllers for EDO DRAM, etc. Lineup of products for 5 V systems and 3.3 V systems V850E/MS2 Support of 5 V interface enables connection of existing external I/Os Contributes to higher cost performance of sets through use of V850E CPU architecture V850E/MA1 High performance of 62 MIPS @ 50 MHz On-chip memory controllers for SDRAM, etc. Various peripheral functions such as timer, serial interface, and A/D converter V850E/MA2 On-chip SDRAM controller Contributes to smaller applications, lighter weight, and higher cost performance through use of 14 × 14 mm, 100-pin package V850E/IA1 On-chip 3-phase sine wave PWM timer, 2-phase encoder input up/down counter, A/D converter, 2-system motor driving enabled through inverter control 6-system serial I/F including FCAN for automotive LAN (Ver. 2.0 Part B compliant) V850E/IA2 2-system motor driving enabled through on-chip peripheral functions almost the same as those of V850E/IA1 System can be configured with single 5 V power supply thanks to on-chip regulator Pamphlet U15412EJ1V0PF 9 V850E Product Application Examples System bus Optical system Document Image processing Shading Compensation/ binarization S/H CCD A/D V850E/MS1 ROM: 128 KB MH/MR/MMR JBIG PORT Memory Motor INTC SDRM CPU Operation panel DMA SIO ROM FAX Motor driver RPU RAM 4 KB RAM For storing image data Communication system AFE Telephone network NCU Application example using V850E/MS1 Printing system Watch Image processing Real-time clock Program ROM Font ROM Paper Printer engine DRAM ASIC SRAM ASIC CR motor IEEE1284 PF motor Printer Color head Engine controller Interface controller V850E/MA1 IEEE1394 USB Application example using V850E/MA1 Black head LAN Operation panel AC-3 decoder Pick up Driver DRAM DRAM RF-Amp 2ch DAC Speech output ADC NTSC/PAL Servo processor DVDPlayer Error correction Stream management A/V separation MPEG2 decoder 3ch DAC GUI Image output CPUI/F Mechanical control microcontroller Application example using V850E/MA2 System control microcontroller 10 Video encoder Pamphlet U15412EJ1V0PF V850E/MA2 Display Key input V850ES, V850/Sxx Product Development Concept High Performance 3 to 4 times higher performance compared to 16-bit CISC microcontrollers Middleware support (JPEG, speech recognition, etc.) Low noise & low power Optimum design for maximum operating frequency of 20 MHz Thorough EMI noise countermeasures Low-voltage support Realization of 2.2 V low voltage operation (V850ES/SA2, SA3) Variation in memory and I/O Various memory capacities (ROM: 64 KB to 512 KB, RAM: 4 KB to 24 KB) Various packages (100-pin to 180-pin) Various ASSPs (automotive bus support (IEBusTM, CAN), servo timer, etc.) Peripheral functions inherited from 78K Series Standard peripheral functions of 78K Series (timer, serial interface, etc.) Designed for 8/16-bit application market Pursuit of high cost performance [Low Voltage] In mass production [5 V] 176-pin LQFP/180-pin FBGA 144-pin LQFP V850/SV1TM Under development Enhanced peripheral functions On-chip servo timer 192 KB/8 KB to 384 KB/16 KB On-chip 256 KB, 384 KB flash memory 16 MHz @2.7 to 3.6 V 20 MHz @3.1 to 3.6 V Enhanced peripheral functions 100-pin QFP/LQFP V850/SC1,2,3TM On-chip IEBus (SC2), on-chip FCAN (SC3) 256 KB/20 KB to 512 KB/24 KB On-chip 512 KB flash memory 20 [email protected] to 5.5V 100-pin LQFP/121-pin FBGA V850/SB1,2TM V850/SA1TM 64 KB/4 KB to 256 KB/8 KB On-chip 128 KB, 256 KB flash memory 17 MHz @2.7 to 3.6 V 20 MHz @3.0 to 3.6 V On-chip IEBus (SB2) 128 KB/12 KB to 512 KB/24 KB On-chip 256 KB, 512 KB flash memory 20 [email protected] to 5.5V V850ES/SA2,3TM 256 KB/16 KB On-chip 256 KB flash memory 13.5 MHz @2.2 to 2.7 V 17 MHz @2.3 to 2.7 V Higher 3 V performance 78K/IV 78K/0 Support of low voltage 100-pin LQFP/121-pin FBGA Enhanced peripheral functions 100-pin LQFP V850/SF1TM On-chip FCAN 256 KB/16 KB On-chip 256 KB flash memory 16 [email protected] to 5.5V 5 V higher performance Pamphlet U15412EJ1V0PF 11 V850ES, V850/Sxx Product Features V850ES/SA2, SA3 Ultra-low power consumption/high-speed operation (30 mW @ 2.5 V, 17 MHz) Low-voltage operation of 2.2 V Min. (1.8 V under planning) On-chip single power supply flash memory On-chip V850ES core V850/SA1 Ultra-low power consumption (66 mW (20 MHz @ 3.3 V, mask ROM version, Typ.)) Rich memory lineup (ROM 64 KB to 256 KB/RAM 4 KB to 8 KB) Support of CSP package (121-pin FBGA) V850/SV1 Various on-chip peripheral functions including servo timer Rich memory lineup (ROM 192 KB to 384 KB/RAM 8 KB to 16 KB) Support of high-pin-count CSP package (180-pin FBGA) ASSP lineup for DVC V850/SB1, SB2 Low EMI noise On-chip large-capacity memory (512 KB/24 KB Max.) Rich memory lineup (ROM 128 KB to 512 KB/RAM 12 KB to 24 KB) Automotive bus support (V850/SB2 only) V850/SF1 Low EMI noise On-chip FCAN controller (2 ch Max.) ASSP lineup for car audio V850/SC1, SC2, SC3 Low EMI noise Enhanced peripheral functions for V850/SB1, SB2 (100-pin Automotive bus support (IEBus, FCAN) 12 Pamphlet U15412EJ1V0PF 144-pin) V850ES, V850/Sxx Product Features V850ES, V850/Sxx Series power performance Current consumption/performance mA/MIPS 10 8-bit CISC 9.2mA/MIPS 16-bit CISC Low current consumption: 1/5th that of 16-bit CISC with equivalent performance 7.3mA/MIPS 5 1.1mA/MIPS V850/SV1 1.1mA/MIPS V850/SB1 0.9mA/MIPS V850/SA1 0.7mA/MIPS V850ES/SA2, 3* 0 ∗:Under development Smooth transition from CISC to RISC CISC-like use enabled On-chip standard peripheral functions of 78K Series • Bit manipulation instructions (SET1, CLR1, NOT1, TST1) • Multi-status flags • 32-bit barrel shifter • Timers (8-bit, 16-bit) • Serial interface (3-wire CSI, UART) • Watchdog timer, etc. High code efficiency • Equals CISC code efficiency (1.0 to 1.2) • High-level language (C language) programming supported Comparison of peripheral functions of 78K Series and V850/Sxx products 78K/0 Series 78K/IV Series µPD78003x µ PD78421x 16-bit timer TM0 8-bit timer TM5 Serial interface (CSI) SIO3 Serial interface (UART) UART0 I2C interface IIC0 AD converter ADCTL0 V850/SB1,2 V850/SV1 V850/SF1 V850/SC1,2,3 UART3 RT00 Real-time output Watchdog timer WDT Watch timer WT Key return function V850 Series V850/SA1 Separate specifications WDT WTN0 Separate specifications KR0 :Listed on left :Not provided Pamphlet U15412EJ1V0PF 13 V850 ASSP Lineup Inverter Control V850E/IA1 High performance DVC V850E/IA2 For general use V850/SAx For camera control Car Audio V850/Sxx Standard product V850/SB2, SC2 IEBus Automotive Electronics V850/SF1, SC3 CAN bus V850E/IA2 inverter air conditioner application example Power supply block Indoor unit V850/xxx ABS V850/xxx Air bag V850/xxx Dashboard V850/SV1 System Block Diagram (DVC) Sensors 3CCD CDS +AGC 10-bit ADC Camera signal control V850E/IA2 Vertical drive Power module V850/SV1 For servo control Drive SG Field memory DRAM Memory control Video compression/ decompression LCD signal processing Error correction (modem) Finder Head amp Head OSD Sync SG Power module Motor drive Motor drive V850/SV1 Display key operation Microphone Compressor motor Fan motor V850/SB2 System Block Diagram (Car Audio) FM/AM tuner block MD deck block CD deck block Changer connector AUX connector IEBus Audio switch PLL DSP Power supply block FLT driver Front panel block AMP V850/SB2 FCAN driver Key microcontroller Display block VFD Key matrix Remote control receiver 14 Pamphlet U15412EJ1V0PF Mic/amp ADC Error correction Memory Lineup Mask products ROM Size (Bytes) Flash memory products V850/SC3 V850/SC3 V850/SC2 V850/SC2 V850/SC1 512K V850/SC1 V850/SB2 V850/SB2 V850/SB1 V850/SB1 384K V850/SV1 V850/SB2* V850/SB2* V850/SV1 V850/SB1* V850/SB1* V850ES/SA3* V850ES/SA3* V850ES/SA2* V850ES/SA2* V850/SV1 V850/SV1 256K V850/SF1 V853 V853 V850/SF1 V850E/IA1 V850/SB2 V850/SV1 V850E/IA1 V850/SB2 V850/SA1 V850E/MA1 V850/SB1 V850/SA1 V850E/MA1 V850/SB1 V850/SV1 192K V853 V853 V850/SA1 128K V850/SA1 V850E/MA1 V850E/MS1 V850E/IA2 V850/SB2* V850E/MS1 V850E/IA2 V850/SB1* V850E/MA1 V850/SB1* 8K 10K 12K V850/SB2* V853 96K 64K V850E/MS1 V850/SA1 V850E/MS1 ROMless V850E/MS2 V850E/MA1 V850E/MA2 4K 6K RAM Size (Bytes) Pamphlet U15412EJ1V0PF 16K 20K 24K *: Under development 15 Package Lineup Package Name Applicable Products 100-pin plastic QFP (14 × 20 mm) V850/SB1, SB2, SF1 100-pin plastic LQFP (14 × 14 mm) V850E/MA2, MS2, IA2, V850ES/SA2, V850/SA1, SB1, SB2, SF1, V853 144-pin plastic LQFP (20 × 20 mm) V850E/MA1, IA1, MS1, V850/SC1, SC2, SC3 176-pin plastic LQFP (24 × 24 mm) V850/SV1 121-pin plastic FBGA (12 × 12 mm) V850ES/SA3, V850/SA1 157-pin plastic FBGA (14 × 14 mm) V850E/MS1 161-pin plastic FBGA (13 × 13 mm) V850E/MA1 180-pin plastic FBGA (13 × 13 mm) V850/SV1 QFP package photos 100-pin plastic QFP 0.65 mm pitch, 14 × 20 mm, 3.0 mm thick 100-pin plastic LQFP 0.5 mm pitch, 14 × 14 mm, 1.4 mm thick 144-pin plastic LQFP 0.5 mm pitch, 20 × 20 mm, 1.4 mm thick 176-pin plastic LQFP 0.5 mm pitch, 24 × 24 mm, 1.4 mm thick 157-pin plastic FBGA 0.8 mm pitch, 14 × 14 mm, 1.31 mm thick 161-pin plastic FBGA 0.8 mm pitch, 13 × 13 mm, 1.48 mm thick 180-pin plastic FBGA 0.8 mm pitch, 13 × 13 mm, 1.48 mm thick FBGA package photos 121-pin plastic FBGA 0.8 mm pitch, 12 × 12 mm, 1.48 mm thick The Eco Symbol mark is applied to products that comply with NEC’s environmental standard, which is one of the world’s toughest. Such products are antimony-free and use smaller amounts of halogen, and are subject to product assessment and green procurement. 16 Pamphlet U15412EJ1V0PF Pamphlet U15412EJ1V0PF 17 Architecture V850 Common Architecture The V850 Series, which consists of single-chip RISC microcontrollers that use an architecture optimized for embedding, has the following features. 5-stage pipeline processing Harvard architecture 32 general-purpose registers Simple addressing Support of CISC-like instructions Multi-status flags DSP function 32-bit barrel shifter 2-byte basic instruction set 5-stage pipeline processing The V850 Series uses a 5-stage pipeline structure (5 stages from instruction fetch to writeback) that supports simultaneous processing of 5 instructions, thus enabling the execution of almost all instructions in just one clock. Internal system clock Instruction 1 IF Instruction 2 ID EX MEM WB IF ID EX MEM WB IF ID EX MEM WB IF ID EX MEM WB IF ID EX MEM WB IF ID EX MEM Instruction 3 Instruction 4 Instruction 5 Instruction 6 IF ID EX MEM WB : Instruction fetch : Instruction decode : Instruction execution : Memory access to target address : Write execution result to register Instruction 1 end Instruction 2 end Instruction 3 end Instruction 4 end WB Instruction 5 end Instruction 6 end An instruction is executed each clock Harvard architecture The V850 Series uses the Harvard architecture, which is designed so that the instruction bus and data bus can operate completely independently from each other, thereby preventing pipeline operation problems and ensuring efficient instruction execution. In the case of an architecture other than the Harvard architecture, the MEM stage of CPU Instruction fetch instruction 1 and the IF stage of instruction 4, and the MEM stage of instruction 2 BCU and the IF stage of instruction 5 conflict, causing bus waits. This in turn causes the Instruction bus pipeline operation to become disordered and lowers the instruction execution speed. Pipeline Operation of Non-Harvard Architecture Internal ROM Instruction1 External memory Operand data access ID EX IF ID EX IF ID EX MEM WB IF ID EX MEM WB IF ID EX MEM Instruction 3 Data bus On-chip peripheral I/O Internal RAM Instruction2 IF MEM Instruction 4 Instruction 5 : Idles inserted due to bus wait 18 Pamphlet U15412EJ1V0PF WB MEM WB WB 32 general-purpose registers The V850 Series provides 32 general-purpose registers. Along with a hardware environment that is ideal for program execution, the development environment, including compilers, exploits these 32 registers to achieve program generation with superior code efficiency and execution performance. Comparison of Performance/Object Efficiency According to Number of Registers Execution time (s) 12 Byte count (bytes) 4000 For example, looking at the program execution time and code size changes when the number of registers used 3000 9 by the compiler is changed using the servo control module, we can see that the larger the number of 2000 6 registers, the better the program execution speed and the smaller the code size. However, from about 26 1000 0 registers, the improvement in terms of execution speed and code size becomes smaller, and in the 3 16 18 20 22 24 26 Byte count Used C program: Servo control module 28 30 Execution time neighborhood of 32 registers, there are no more changes. This is why the V850 Series has been provided 0 32 with 32 registers as the strict minimum requirement. Number of registers Software register bank The number of registers can be selected from among 22, 26, and 32 as a compiler option to efficiently execute application programs. Unused registers can be used as a software register bank for which save and restore processing is not required during interrupt servicing or task switching, which increases the processing speed. Register bank interrupt Program execution Interrupt servicing instruction execution Save the program counter, etc., to a save register. Execute the interrupt restore instruction. Restore the program counter value, etc., from the save Program execution Actual interrupt servicing time Normal interrupt Program execution Interrupt servicing instruction execution register. Save general-purpose registers to stacks. Program execution Restore general-purpose registers from stacks. Actual interrupt servicing time User interrupt servicing routine execution time Total interrupt servicing time General-purpose register configuration 31 r0 r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 r12 r13 r14 r15 r16 r17 r18 r19 r20 r21 r22 r23 r24 r25 r26 r27 r28 r29 r30 r31 31 PC System register configuration 0 Zero Register Reserved for Address Generation Name Stack Pointer(SP) Global Pointer(GP) Text Pointer(TP) Element Pointer(EP) Link Pointer(LP) Application Operation No. r0 Zero register Always holds "0" r1 Assembler reservation Used as working register for address generation r2 Address/data variable register (If real-time OS being used does not use r2) r3 Stack pointer Used for stack frame generation during function call r4 Global pointer Used when accessing global variables in the data area r5 Text pointer Used as register for specifying the beginning of the text area (program code allocation) r6-r29 Address/data variable register r30 Element pointer 0 Program Counter Only supported by V850E1 CPU core products supported Used as base pointer for address generation during memory access r31 Link pointer Used during function call by compiler PC Program counter Holds instruction addresses during program execution System Register Name LDSR Application STSR Register for saving status during interrupt 0 EIPC 1 EIPSW 2 FEPC 3 FEPSW 4 ECR 5 PSW Program status word 16 CTPC 17 CTPSW Register for saving status during CALLT execution 18 DBPC 19 DBPSW 20 CTBP 6-15, 21-31 Register for saving status during NMI × × : Access prohibited Interrupt source register Register for saving status during exception/debug trap CALLT base pointer Reserved : Access enabled Pamphlet U15412EJ1V0PF Operand Specification × × LDSR: Instruction to load general-purpose register contents to system register STSR: Instruction to store system register contents to general-purpose register 19 Simple addressing The increased amount of address calculations in the CPU in the case of complex addressing causes disturbances in the pipeline operation. As a result, address calculation becomes a bottleneck for pipeline processing and raising the frequency to increase the performance becomes difficult. The V850 Series avoids this problem by supporting only simple addressing. Pipeline Processing Time and CPU Operating Frequency In case of excessive addressing In case of simple addressing Pipeline processing sequence Instruction fetch All processing is standardized and efficient Address calculation Operating frequency held back by slow processing Execution Memory access Writeback Processing time Processing time Addressing mode Instruction addresses Operand addresses •Relative addressing (PC dependent) •Register addressing Add 9 signed bits or 22 signed bits of data of the instruction code to the program counter. Example: 22-bit data 31 Addressing that accesses the general-purpose register specified by the general-purpose specification field or a system register as an operand. 0 26 25 0 •Immediate addressing PC Addressing of 5-bit data or 16-bit data for manipulation in the instruction code. 31 22 21 0 Signed extension 31 disp22 •Based addressing 26 25 0 0 31 0 Addressing that accesses memory, with the sum of the PC contents of the generalpurpose register (reg1) and Memory subject to manipulation reg1 31 16 15 0 disp16 Signed extension Memory subject to manipulation 16-bit displacement (disp16) as the operand address. •Register addressing (register indirect) Transfer the contents of the general-purpose register specified by the instruction (reg1) to the program counter (PC). 31 26 25 26 25 0 31 0 reg1 bit of 1 byte of the memory space, with the sum of the reg1 31 •Bit addressing Addressing that accesses 1 0 contents of the generalpurpose register (reg1) and 0 16 15 31 Signed extension 0 disp16 Memory subject to manipulation 16-bit displacement (disp16) that has been sign extended PC Memory subject to manipulation to word length as the operand address. 2-byte basic instruction set The V850 Series employs a 2-byte instruction code to perform basic processing to enable compact program development equivalent to 16-bit CISC microcontrollers. •Improved object efficiency through ROMization programming Object Code Size Comparison (Dhrystone 1.1/Large model) Application of 2-byte instructions to all basic processing, consisting of load, store, arithmetic/ logic operations, and branching. •To realize ease of use, restrictions on 16-bit fixed-length instructions are partially removed through incorporation of 32-bit instructions. •Bit manipulation instructions, etc. 16-bitV(CISC) 1.00 78K/IV(CISC) 1.03 V850(RISC) 1.02 1.48 VR/MIPS32(RISC) 20 Pamphlet U15412EJ1V0PF CISC-like instructions for embedding (bit manipulation instructions) The V850 Series supports bit manipulation instructions suitable for flag manipulation on I/O registers, which play a large role in embedding control. • Improvement of operability of memory mapped I/ Os for control purposes • Manipulation of any 1 bit of byte data in the memory space • Provision of test (tst1)/set (set1)/clear (clr1)/invert Example: Setting (1) bit 6 of ASIM00 register Bit Manipulation Instruction Item When Used When Used 6, ASIM00[r0] ld.b ori st.b ASIM00[r0], r20 0x0040, r20, r20 r20, ASIM00[r0] -4, sp Save r20 r20, 0[sp] ASIM00[r0], r20 0x0040, r20, r20 r20, ASIM00[r0] 0[sp], r20 Restore r20 4, sp set1 Object size 4 bytes 12 bytes 24 bytes Execution time 4 clocks 4 clocks 8 clocks (not1) • Effective for reducing object size and execution time since flags can be manipulated in 1-bit units with 1 instruction add st.w ld.b ori st.b ld.w add Coding example Multi-status flags In the V850 Series, calculation results are reflected in registers as status flags. As a result, delay branching such as can be seen in the RISC microcontrollers of other manufacturers does not occur and programs can be coded with the same feel as CISC microcontrollers. Example: Program that branches to positive/negative/zero according to register contents • Easy recording with assembler • Improved object efficiency and execution speed CISC Microcontroller ZERO : Zero processing PLUS : Positive processing MINUS : Negative processing cmp jz jgt jmp V850 cmp bz bgt br ax, 0 ZERO PLUS MINUS Other Manufacturer's RISC Microcontroller 0, r10 ZERO PLUS MINUS cmp/eq bt cmp/pl bt bra nop #0, r10 ZERO r10 PLUS MINUS ;For delay branching DSP function The V850 Series provides a DSP function for executing high-speed calculations and product-sum operations indispensable for digital signal processing such as image and speech processing. • Direct data handling via general-purpose registers • Realization of digital signal processing through generalpurpose CPU • High-speed 16-bit (V850 CPU), 32-bit (V850E1 CPU) V850 CPU+DSP General-purpose register CPU DSP CPU SAT flag multiply/sum-of-products (Multiply: 1 to 2 clocks, sum-of-products: 3 clocks) MUL INT MUL ALU ALU • Effective for filter operations and matrix operations for feedback calculations in speed, position, and other servo control. Memory 32-bit barrel shifter V850 Series can realize bit manipulations frequently used during signed data and image data processing in 1 instruction per clock. • Shifting of any number of bits (0 to 31) executable in 1 instruction per clock Improved execution speed/object efficiency Effective for extracting arbitrary bit lengths of image data and signed data (extracting code during MH/MR/MMR encoding, etc.) Example: 27-bit logical right shift Other manufacturer's V850 RISC microcontroller Processing sequence SHR16 Rn SHR8 Rn SHR2 Rn SHR Rn 4 4 Pamphlet U15412EJ1V0PF SHR 27, Rn Number of instructions 1 Number of execution clocks 1 21 Strengths of V850E1 and V850ES Cores The V850E1 and V850ES cores are CPU cores that enhance the functions of the V850 core. V850E1 core Higher performance and improved operating frequency of 50 to 100 MHz Improved external memory access function Improved code efficiency (10 to 15% higher than V850 core) •Addition of C language compatible instructions (Switch instruction, CALLT instruction, etc.) High performance high-end lineup (V850E products), system-on-chip core lineup V850ES core Next-generation CPU core of low-end lineup Support of lower voltage for V850/Sxx products Improved code efficiency through use of same architecture as V850E1 (10 to 15% higher than V850 core) CPU Core V850 Function V850ES V850E1 Maximum operating frequency 20/33 MHz 20 MHz 50 Maximum program memory space 16 MB 16 MB 64 MB Maximum data memory space 16 MB 16 MB 256 MB Higher performance Use of 5-stage pipeline Use of Harvard architecture Higher code efficiency 100MHz Improvement of pipeline • Non-blocking load/store Parallel execution of instructions (during instruction execution in internal ROM) • Addition of branch/load pipes • Shift to 3-operand manipulations in 1 slot Use of 2-byte instructions Use of CISC instructions Addition of C language compatible instructions (Addition of Switch instruction, Callt instruction, data conversion instruction, Prepare/Dispose instruction) 22 Multiplier 16 × 16 bit Interrupt responsiveness 11 to 18 clocks 32 bit 16 × 16 bit 32 bit (32-bit multiply instruction support) 4 to 10 clocks Pamphlet U15412EJ1V0PF 32 × 32 bit 64 bit Employment as ASIC CPU Cores Smooth transition to ASIC microcontroller development using V850E1 CPU cores 1. Introduction to market with short TAT through use of standard V850E1 products 2. Optimization of system through switch to ASIC Easy securing of compatibility from traditional systems made into ASICs through use of same device development methods for both standard products and ASIC microcontrollers Development of CPU cores bearing in mind shift to ASIC Software debugging support Release of CPU core that supports on-chip debugging through full-function in-circuit emulator, JTAG method (N-Wire ICE) and on-chip debugging with trace function Internal system bus configuration Independent high-speed 32-bit synchronous system bus and 16-bit asynchronous bus for low-speed peripheral function macro connection, realizing both high-speed processing, low-power consumption and easy design Provision of large assortment of peripheral function macros Cache memory, memory controller, ROM/RAM, USB, etc. Covering required performance and power consumption through support of a large variety of processes Process Cell-based IC family 0.35µm CB-9VX 0.25µm CB-10VX 0.13µm CB-12 V850E1 core Realization of excellent performance/power ratio of 827 MIPS/W for 100 MHz Max. (at 2.5 V operation) Improved object efficiency A flexible and high-performance bus system can be configured through independent buses such as a high-speed system bus that enables 400 MB/s data transfer and a low-speed peripheral macro connection bus. Support of on-chip debugging function V850E/MA1 block configuration DBG I/F V850E1 core V850E1Core INT(64ch) INTC iROM I/F (32bit/1clk) CPU BBR 32x32 MUL iRAM I/F (32bit/1clk) TEST Ctrl System Bus (32bit/1clk) INT INTC ROM (256KB) CPU DMA Pamphlet U15412EJ1V0PF Timer UART CSI BBR Peripheral Bus 32 × 32 MUL PWM System Bus RAM (10KB) Test Bus iCACHE I/F BCU dCACHE I/F DMA Peripheral Bus (16bit/asynchronous) RCU BCU TEST Ctrl Test Bus RCU PORT A/D MEMC 23 V850E1, V850ES architecture The V850E1 and V850ES cores achieve high performance and higher code efficiency through the implementation of the following improvements to the V850 CPU core. Non-blocking load/store • Improved bus use efficiency • Shorter interrupt insensitivity period Addition of branch/load pipes Shift to 3-operand manipulations in 1 slot Addition of high-level language-compatible instructions • 2-clock branching • Parallel execution of instructions • Improved absolute performance • Example: Synchronous processing of mov + add • Improved code efficiency • 10 to 15% improvement in object efficiency mainly when C compiler used Pipeline configuration Non-blocking load/store Master Pipeline (V850 CPU compatible) ID Conventional (V850 CPU) Pipeline is stopped until MEM stage complete EX IF br/sld Pipeline ID Address calculation stage IF (instruction fetch) ID (Instruction decode) WB Load instruction Async WB Pipeline ADD instruction MEM Next instruction DF WB Load, store buffer (1 stage each) V850E1 CPU Addition of branch/load pipes Branch instruction ID EX MEM MEM (external memory) T1 T2 T3 WB IF ID EX (MEM) WB IF ID EX MEM IF ADD instruction IF ADD instruction (16-bit length) WB ID MEM EX EX IF ID EX DF WB IF ID EX MEM IF ID EX (MEM) WB ID EX MEM WB IF ID Next instruction V850E1 CPU 1-clock reduction ID MEM WB IF ID ADD instruction IF Branch instruction Branch destination instruction WB EX MEM WB EX 2-clock reduction V850E1 CPU IF WB WB Branch destination determined in ID stage Branch instruction WB Conventional (V850 CPU) Branch instruction (16-bit length) Branch destination instruction MEM (external memory) T1 T2 ID Next instruction Branch destination determined in EX stage IF EX •Parallel instruction execution (when executed by internal ROM) •Pipeline operation with branch instruction Conventional (V850 CPU) ID Effective pipeline processing that uses the Async WB Pipeline when appropriate, according to the instruction. Load instruction : Fetches instructions and increments the fetch pointer. : Decodes instructions, creates immediate data, and reads registers. : Executes decoded instructions. : Accesses memory of corresponding addresses. : Writes execution results to registers. : Transfers execution data to WB stage. EX (ALU, multiplier, barrel shifter execution) MEM (Memory access) WB (Writeback) DF (data fetch) IF Next instruction ID EX DF ID MEM WB IF ID WB EX MEM WB * The next branch instruction code is also fetched due to the internal 32-bit bus. Shift to 3-operand manipulations in 1 slot Conventional (V850 CPU) mov add r20(src2), r22(src2), r21(dst) r21(dst) • Sequence from mov to arithmetic instruction is detected in the ID stage, and if dst is the same, the next manipulation is performed. src1 src2 dst : Replace with src2 of mov : src2 of arithmetic instruction : As is • mov + add instructions executable in 1 clock V850E1 CPU add r22(src2), r20(src1), r21(dst) 24 Pamphlet U15412EJ1V0PF MEM Addition of high-level language compatible instructions The V850E1 and V850ES cores have enhanced the instruction set of the V850 core as follows. switch (2 bytes) unsigned Load • C language switch statement processing converted into instruction callt (2 bytes)/ctret (4 bytes) • Reduction of unsigned manipulation code mov imm32, reg (6 bytes/2 clocks) • Table-reference branching • Reduction of address setting code • Reducing size of call code that frequently appears mul/mulu (4 bytes) • Reduction of array address calculation Data conversion instructions (2 bytes) • Improvement of sum-of-products performance • char, short type cast executed with 1 instruction • sxh, sxb, zxb, and zxh instructions Other • Bit manipulation (register indirect bit specification) prepare/dispose (4 bytes) • cmov (Conditional Move), divide (div/divu/divhu) • Function start/end processing executed in 1 instruction • sasf, endian conversion callt N (Table-reference subroutine calling) PC 15 0 switch R PC+2 entry 0 entry 1 2n <1> Transfers the restored PC and PSW values to CTPC and CTPSW. <2> Adds the CTBP value and 2N to generate a 32-bit table entry address. <3> Loads the halfword of the address generated in <2> and adds the CTBP value to the value 0 extended to word length to generate the 32-bit target address. <4> Branches to the address generated in <3>. CTBP entry 2 V850E1 V850 switch r10 movhi movea shl add ld.h add jmp hi (L267), zero, r9 lo (L267), r9, r9 1, r10 r9, r10 0[r10], r10 r9, r10 [r10] Object size 2 bytes 22 bytes Execution time 5 clocks 9 clocks Bytes 600 entry N <3> <1> entry n PC+2+2y Coding example <2> PC • • • CPU Item CTPC CTBP+(unsigned(entry data)) <4> <1> <3> entry 1 CTBP+2N • • • <1> PC+2+2n 0 entry 0 2N entry 2 <2> 15 PSW Target • • • <1> Adds the table start address and double the register value. <2> Sign extends halfword entry data indicated by the address generated in <1> to word length, doubles it, and adds the table start address to generate a 32-bit address. <3> Branches to target address generated in <2>. • • • switch R (table-reference branching) Target CTPSW PC PSW CTPC : Program counter : Program status word : Register to save status during CALLT execution CTPSW : Register to save status during CALLT execution CTBP : CALLT base pointer N : 0 to 63 PC : Program counter R : General-purpose register n : General-purpose register (R) value y : signed(entry data) V850E1 Core and V850ES Core vs. V850 Core Code Size Comparison Interrupt Response Time Internal system clock Interrupt request 500 Instruction 1 IF ID EX IFx IDx MEM WB INT1 INT2 400 Instruction 2 300 Interrupt acknowledgement operation Interrupt servicing routine 100 0 INT3 INT4 IF ID 4 system clocks 200 A B C D V850 core E F G H V850E1 core, V850ES core I J K Measurement program EX MEM WB System registers for saving the PC and PSW are provided and high-speed branching to the interrupt program is performed, except under the following conditions. • In IDLE/STOP mode • In case of consecutive interrupt request non-sample instructions • During external bus access • During access to the interrupt control register Remark INT1 to INT4 : Interrupt acknowledgement processing IFx : Invalid instruction fetch IDx : Invalid instruction decode Pamphlet U15412EJ1V0PF 25 Middleware Performance Measurement conditions Common MH/MR/MMR CPU • Internal ROM : V850 core (33 MHz) Measurement results are frequency-converted values (50 MHz). Bus width : Program • External memory (SRAM) : Encoding/decoding table, change point table, : 16 bits stacks (including I/O parameters) JBIG Number of waits : 1 (The basic bus cycle is 3 clocks, so 1 bus cycle = 4 clocks.) • Internal ROM : Program (including probability assumption table (1 KB)) • External memory (SRAM) : Learning table, stacks (including I/O parameters) Compiler : CA850 Tool : V850 in-circuit emulator (IE) (product of NEC) V850 MH Method — A4 100 dpi Compression Decompression chart1 0.06s 0.06s chart2 0.06s 0.05s chart3 0.09s 0.08s chart4 0.14s 0.12s chart5 0.09s 0.08s V850 MR (K = 4) Method — A4 100 dpi chart6 0.08s 0.07s chart7 0.15s 0.11s chart8 0.10s 0.07s chart1 0.07s 0.07s Compression Decompression Decompression chart3 0.10s 0.10s chart4 0.17s 0.16s Compression Seconds Compression chart2 0.06s 0.06s chart5 0.11s 0.10s 0.20 Seconds 0.18 0.18 0.16 0.16 0.16 0.16 0.14 0.14 0.14 0.14 0.12 0.12 0.12 0.12 0.10 0.10 0.10 0.10 0.08 0.08 0.08 0.08 0.06 0.06 0.06 0.06 0.04 0.04 0.04 0.04 0.02 0.02 0.02 2 3 4 5 6 7 8 chart 1 2 3 4 5 6 7 8 0.00 1 chart 2 3 4 5 V850 MMR Method — A4 100 dpi Compression Decompression chart1 0.07s 0.07s chart2 0.06s 0.05s chart3 0.11s 0.10s chart4 0.18s 0.17s Compression Seconds chart5 0.11s 0.10s 0.20 0.18 0.18 0.16 0.16 0.14 0.14 0.12 0.12 0.10 0.10 0.08 0.08 0.06 0.06 0.04 0.04 0.02 0.02 0.00 chart7 0.18s 0.16s chart8 0.11s 0.08s 2 3 4 5 6 7 8 chart Decompression 2 3 8 1 chart 4 5 6 7 8 chart2 0.52s 0.48s 0.59s 0.57s chart3 0.63s 0.58s 0.73s 0.68s Compression Seconds chart4 0.84s 0.76s 0.96s 0.89s 2 3 1.00 0.80 0.80 0.60 0.60 0.40 0.40 0.20 0.20 1 2 3 4 5 6 chart5 0.62s 0.57s 0.72s 0.68s 4 5 6 7 7 8 chart 0.00 chart6 0.57s 0.52s 0.67s 0.63s chart7 0.85s 0.78s 1.02s 0.93s 1 LRLTWO=ON 2 3 4 LRLTWO=OFF 5 6 7 8 LRLTWO=ON JPEG Internal ROM : Program Internal RAM : Stack, work area (one part) V850 JPEG Method External memory (SRAM) : Data and remaining work area 26 chart chart8 0.90s 0.83s 1.04s 0.97s chart LRLTWO=OFF Data I/O 8 Decompression Seconds 1.00 0.00 1 7 chart1 0.41s 0.38s 0.46s 0.43s Compression LRLTWO=OFF LRLTWO=ON Decompression LRLTWO=OFF LRLTWO=ON 0.00 1 6 V850 JBIG Method — A4 100 dpi (Layer=Lowest, TPBON=ON, AT=default) chart6 0.09s 0.07s Seconds 0.20 chart8 0.11s 0.08s 0.02 0.00 0.00 1 chart7 0.18s 0.15s Decompression Seconds 0.20 Seconds 0.00 chart6 0.09s 0.08s Sample ratio : RGB Pamphlet U15412EJ1V0PF Processing Time QVGA(320×240×24) VGA(640×480×24) Compression Decompression Compression Decompression 4:1:1 (Quality75) 0.27s 0.21s 1.09s 0.85s 4:2:2 (Quality75) 0.33s 0.26s 1.33s 1.04s chart Variety of Peripheral Functions Memory Access Functions SDRAM controller DRAM controller Products: V850E/MA1, MA2 Products: V850E/MS1, MS2, MA1 SDRAM connectable without external circuit CAS latency: 2, 3 supported EDO DRAM directly connectable without external circuit 2CAS type DRAM supported CBR refresh, CBR self refresh supported CBR refresh, CBR self refresh supported A1 to A12 A0 to A11 A21, A22Note A12, A13 D0 to D15 DQ0 to DQ15 SDCLK CLK A1 to A12 A0 to A11 SDCKE CKE D0 to D15 I/O1 to I/O16 CS RASn RAS SDRAS RAS LCAS LCAS SDCAS CAS UCAS UCAS CSn LDQM LDQM WE WE UDQM UDQM OE OE WE V850E/MA1 WE V850E/MA1 64 Mb DRAM (4 Mword × 16 bits) 64 Mb SDRAM (1 Mword × 16 bits × 4 banks) Note The address signal used differs depending on the SDRAM product. DMA controller (provided in V850E products) DMA controller (provided in V850/Sxx products) Products: V850E/MA1, MA2, MS1, MS2, IA1, IA2 Products: V850/SA1, SB1, SB2, SV1, SF1, SC1, SC2, SC3 8-/16-bit data units Transfer type: 1-cycle transfer, 2-cycle transfer 8-/16-bit data units Transfer clock: 4 clocks Min. Number of transfers: 65,536 Max. Number of transfers: 256 Max. CPU core Internal RAM On-chip peripheral I/O External I/O External RAM 8-/16-bit bus External ROM Bus interface DMA Data control Address control On-chip peripheral I/O CPU core Internal RAM DMA Transfer source address Count control Transfer destination address Channel control Number of transfers Pamphlet U15412EJ1V0PF Internal bus Transfer targets: Internal RAM-on-chip peripheral I/O Single transfer On-chip peripheral bus Transfer targets: Memory-peripheral I/O, memory-memory Single, single step, block transfer 8/16bit-data 27 A/D Converters Multi-stage buffer type ;;; ; ;; ; ; ; ;;;;;; ; ;;; ; ;;; Scan mode Products: V853, V850/SV1, V850E/MA1, IA1, IA2, MS1 Conversion can be started by both software and hardware Eight conversion result registers are incorporated Select/scan modes can be switched ANI0 (Input) Data 1 Data 5 Tap selector Resistor string ANI1 (Input) Selector • • • • • • • • • • • ANI0 ANIn Data 7 Data 2 AVREF ANI2 (Input) AVSS Successive approximation register ADTRG Data 6 Data 3 ANI3 (Input) INTAD Conversion controller A/D conversion Conversion result register 0 Conversion result register 1 Conversion result register 2 Conversion result registers Conversion result register 3 Conversion result register 4 Conversion result register 5 ;; ; ; ; ; ;; ; ; ; ; ;; ;; ; ;; ; ;; ; ; Conversion result register 6 Data 4 Data 1 (ANI0) Data 2 (ANI1) Data 3 (ANI2) Data 4 (ANI3) Data 1 (ANI0) Data 2 (ANI1) Data 3 (ANI2) Conversion Conversion Conversion result result result register 0 register 1 register 2 Data 5 (ANI0) Data 6 (ANI0) Data 7 (ANI1) Data 4 (ANI3) Data 6 (ANI0) Conversion result register 3 Conversion result register 0 INTAD interrupt Conversion result register 7 Conversion start (Control register setting) Conversion start (Control register setting) Select mode operation Data 4 ANI1 (Input) Data 1 Data 2 A/D conversion Conversion result registers Data 1 (ANI1) Data 2 (ANI1) Data 1 (ANI1) Data 3 Data 3 (ANI1) Data 2 (ANI1) Data 4 (ANI1) Data 3 (ANI1) Data 5 Data 5 (ANI1) Data 6 Data 6 (ANI1) Data 4 (ANI1) Data 7 Data 7 (ANI1) Data 6 (ANI1) INTAD interrupt Analog input ANI0 Conversion result register 0 ANI1 Conversion result register 1 ANI2 Conversion result register 2 ANI3 ANI0 ANI5 Conversion result register 5 ANI6 Conversion result register 6 ANI7 Conversion result register 7 Conversion result register 0 Conversion result register 1 ANI2 Conversion result register 2 ANI3 A/D converter Conversion result register 3 ANI4 Conversion result register 4 ANI5 Conversion result register 5 ANI6 Conversion result register 6 ANI7 Conversion result register 7 28 Conversion result register 3 Conversion result register 4 Conversion result registers ANI1 A/D converter ANI4 Conversion start Control bit Control bit Control bit Control bit Conversion start Control bit (Conversion result set set set set (Conversion result set register setting) register setting) Analog input Conversion result registers Pamphlet U15412EJ1V0PF Timer/Counter Functions 24-bit servo timer PWM Product: V850/SV1 24-bit timer unit for servo control Product: V850/SV1 12- to 16-bit PWM output Main pulse + additional pulse configuration Main pulse: 4/5/6/7/8 bits External input detector with 1-64/1-128 divider Additional pulse: 8 bits Active level of PWM output pulse selectable Clear count control Tim Selector Count clock Selector Capture registers: 4 Compare registers: 2 INTOVm INTTIm 24-bit timer PWM module register PWM module register (higher 8 bits) (lower 8 bits) OVFn 1-64 division Selector Count clock m bit down counter (m = 4 to 8) PWM pulse generator Capture register 2 1-64 division INTCPn3 Capture register 1 Selector Selector INTCPn1 Vsync INTCPn2 Reload controller Capture register 0 INTCPn0 1-128 division 1/2 Capture register 3 Compare register 1 INTCMm0 RTP Compare register 2 INTCMm1 m Output controller PWMn 8-bit counter INTCPm0-9 3-phase inverter control timer Up/down counter Products: V850E/IA1, IA2 Products: V850E/IA1, IA2 3-phase PWM output function Symmetric triangular wave, asymmetric triangular wave, sawtooth wave 16-bit 2-phase encoder input supported Compare registers: 2 Interrupt culling function Culling rate: 1/1, 1/2, 1/3, 1/4, 1/8, 1/16 Capture/compare registers: 2 3-phase PWM forcible output stop function Real-time output function Count clock Compare buffer register Compare register 3 Compare capture register Output controller INTCC0 16-bit timer Compare capture register Deadtime timer TCLR Compare buffer register Compare register 0 Compare buffer register Compare register 1 Deadtime generator Deadtime generator TO0 TCUD TO1 Selector 16-bit up/down counter timer CLR circuit Output control TO Compare register TO2 TO3 Edge detector INTCC1 INTCM0 TIUD Compare register Compare buffer register Compare register 2 INTCM1 Deadtime generator TO4 TO5 Pamphlet U15412EJ1V0PF 29 Serial Interface Variable-length serial interface 8-/16-bit serial interface Products: V850/SB1, SB2, SV1, SF1, SC1, SC2, SC3 3-wire serial I/O Products: V850/SC1, SC2, SC3, V850E/IA1, IA2 3-wire serial I/O Data length switchable between 8 bits and 16 bits Start bit switchable between MSB and LSB Data length switchable between 8 bits and 16 bits Start bit switchable between MSB and LSB MSB/LSB controller Counter clock 8-/16-bit variable-length shift register SIn SCKn Serial clock controller Selector Interrupt controller INTCSIn BRG SCKn SOn Serial clock counter (8/16 counting switchable) Interrupt controller 8-bit shift register L SIn INTCSIn SCKn 8-bit shift register H SOn Selector Serial clock controller BRG IEBus controller CAN Products: V850/SB2, SC2 Products: V850E/IA1, V850/SF1, SC3 Supports communication mode 1 Maximum number of transfer bytes: 32 bytes/frame CAN protocol Ver. 2.0 Part B (Transmission/reception of standard and extended frames) Maximum transfer speed: Approx. 17 Kbps Maximum transfer rate: 1 Mbps 32 message buffers Register block IETX IERX CANTX1 CAN receiver 1 Transmission block CAN module 1 CANRX1 Reception block MAC (Memory Access Controller) CANTX2 CAN receiver 2 CAN module 2 CANRX2 Bit controller Field controller CAN RAM Message buffer 0 Message buffer 31 Control block Interrupt request Note The number of channels differs depending on the product. 30 Pamphlet U15412EJ1V0PF Controller Interrupt request Distinctive Peripheral Functions of V850 Watch timer Hsync/Vsync separator Products: V850/SB1, SB2, SV1, SC1, SC2, SC3 0.5-second interrupt generation using watch timer function Product: V850/SV1 Separation of Vsync (vertical) signal and Hsync (horizontal) signal from Interval timer supported decoding sync signal of VCR Odd/even field discrimination fxt (subclock) Selector Selector fxx (main clock) Selector Hsync mask signal 5-bit counter INTWTN CSYNCIN IHsync↑ detection Edge switching HSOUT0 (Detected Hsync) Hsync separator HSOUT1 (Compensated Hsync) 11-bit prescaler Vsync separator Selector Count clock Odd/even field discrimination flag Selector INTWTNI VSOUT(Vsync) Division by 2 ROM correction function ROM correction operation Products: V850/SB1, SB2, SV1, SF1, SC1, SC2, SC3 Substitutes JMP r0 instruction for instruction of address to be corrected and branches to 0000H Program can be modified following creation of mask ROM Correction addresses: 4 points RESET Internal ROM Normal flow no ROM correction request flag = 0? Instruction address bus ROM correction flow Clear ROM correction request flag Yes ROM correction address register Initialization Internal ROM (Max. 1 MB space) Comparator JMP r0 instruction generator Download correction program External ROM EEPROMTM, etc. Correction address enable setting information Output trigger controller Jump to correction program Download correction program Correction address = XXXX ROM correction enable flag = 1 Write correction program to RAM Setting correction address and enabling ROM correction Internal RAM Correction program execution Return to internal ROM Instruction replacement block Replace with JMP[r0] instruction Correction point Next processing... Instruction data bus Pamphlet U15412EJ1V0PF Main routine 31 Low Power & Low Noise Low Power Consumption Measures Low-power-consuming, high-speed microcontrollers are required for portable devices and battery-operated devices such as DVCs and cellular phones. The V850 Series incorporates various functions to lower the power consumption. Superior power performance The V850ES and V850/Sxx products feature a thorough power-saving design that realizes a superb power/performance ratio of 1.1 to 0.7 mA/MIPS. As a result, these products realize a low consumption current only one fifth that of a 16-bit CISC microcontroller of comparable performance. By featuring such extremely high power performance, these products enable the simultaneous realization of lower power consumption and more sophisticated functions in various systems. Consumption current/performance mA/MIPS 10 8-bit CISC 16-bit CISC ;; ;; Low power consumption 1/5 that of 16-bit CISC of comparable performance 9.2mA/MIPS 7.3mA/MIPS 5 1.1mA/MIPS V850/SV1 1.1mA/MIPS 0.9mA/MIPS V850/SB1 0.7mA/MIPS V850/SA1 0 V850ES/SA2, 3* *: Under development Clock gear function Standby mode The V850/Sxx products come with two oscillators: a main clock and a subclock. 1/1/, 1/2, 1/4, or 1/8 of the main clock or the subclockNote can be selected as the CPU operating clock, making it possible to minimize the power consumption according to the system’s operating status. Note Not selectable in V850/SV1 An efficient low-power-consumption system can be realized by using the three standby modes, STOP, IDLE, and HALT, according to the usage purpose. Operation modes Current consumption CPU Approx. 70% reduction through clock gear Current consumption reduced to 1/100 or lower! Operating clock fxx (20MHz) Peripheral Watch functions timer Normal operation mode Further reduction to 1/20 through subclock operation HALT mode fxt (32.768kHz) Oscillator Main Sub clock clock Approx. 1/2 Approx. 1/10 IDLE mode fxx/8 Operation status of each mode Approx. 1/100 STOP mode Current consumption Operating Function to cut voltage between A/D converter VREF and resistor string AVDD ON/OFF Selector Tap selector Resistor string ANI0 • • • • • • • • • • • Voltage application to the A/D converter’s resistor string can be switched on and off. The power consumption can be minimized by switching off voltage application to the resistor string when the A/D converter is not used. • Main products: V850/SB1, SB2, SC1, SC2, SC3, SF1 ANIn Successive approximation register ADTRG Conversion controller Conversion result register 32 Stopped Pamphlet U15412EJ1V0PF AVREF AVSS INTAD EMI Countermeasures Minimizing the influence of electromagnetic interference (EMI) from the microcontroller in AV equipment such as car audio systems is a major requirement, making the reduction of EMI one of the highest technological priorities for microcontroller manufacturers. Various EMI countermeasures are implemented in the V850 Series. EMI countermeasures for individual chip Example for V850/SB1, 2, SF1, SC1, 2, 3 Noise reduction measures focussing on the following three points are implemented as noise countermeasures in individual V850 Series chips. Phase 1 V850/SB1 1st Ver. Reduction of noise generation • Use of low-voltage internal logic power supply • Optimization of oscillator Reduction of noise propagation • Separation of internal logic sound source and power supply of pins Phase 2 V850/SB1 A products Phase 3 V850/SB2 A products Phase4 V850/SF1 Phase5 V850/SBx B products V850/SCx Decoupling capacitor Increased on-chip capacitance 600pF 6000pF Noise (dBm) Separation of power supply and GND for port controller 10 dBm reduction • Reduction of cross talk between different power supply wires Separation of power supply and GND for oscillator 5 dBm reduction Elimination of VDD protection element Optimization of output buffer Change of regulator voltage 10 dBm reduction (3.3V 3.0V) Confining of noise inside • On-chip decoupling capacitor between power supply Insertion of bypass capacitor and GND inside microcontroller • Separation of power supply and GND for oscillator Optimization of operating frequency Internal regulator operation Separation of power supply circuit Standardization of evaluation methods (1/2) There are no rules regarding the EMI measurement testing method for individual microcontrollers. NEC aims to standardize evaluation circuit constants through the use of a standalone EMI evaluation board and evaluate products in a measuring environment that uses a shielded room and power supply filters. This approach enables the evaluation of different products (8-bit and 16-bit NEC CISC microcontrollers, etc.) in the same environment. Standalone EMI evaluation board Standalone EMI evaluation board measurement environment Spectrum analyzer Shielded room Probe Power supply Evaluation points Evaluation board + - Filter + + - Pamphlet U15412EJ1V0PF 33 Standardization of evaluation methods (2/2) EMI evaluation results A comparison of the EMI evaluation results for Phase 2 products (V850/SB1 A products) and Phase 4 products (V850/SF1) is shown below. Phase 2 (V850/SB1 A Products) Product Name Measurement Point VDD Phase 4 (V850/SF1) Noise [dBm] 10dB Noise [dBm] 10dB 70 75 80 85 90 95 100 105 110 115 120 70 75 80 85 90 Frequency [MHz] Port 95 100 105 110 115 120 105 110 115 120 Frequency [MHz] Noise [dBm] 10dB Noise [dBm] 10dB 70 75 80 85 90 95 100 105 110 115 120 70 75 80 85 90 95 100 Frequency [MHz] Frequency [MHz] Remark Oscillation frequency = 16 MHz Evaluation of characteristics using radio system board (1/2) In addition to EMI measurement using a standalone EMI evaluation board, NEC has also established an evaluation method employing set evaluation criteria using a radio system board. Since the evaluation results obtained with the radio evaluation board match the evaluation method established by the customer, the influence of EMI can be judged directly. Radio system board Radio system board measurement environment Tuner pack Audio analyzer Power supply Signal generator Audio output Electronic volume Antenna - Audio amp + 12 V power supply CPU board Coaxial cable Output Antenna Dummy load (4Ω) LCD & key panel Audio output level : 0.5 W Radio system board 34 Pamphlet U15412EJ1V0PF Frequency to be modulated : 400 Hz Frequency deviation : 30% (22.5 kHz) RF signal output level : 60 dB µV Output impedance : 75Ω Evaluation of characteristics using radio system board (2/2) Radio system board block diagram Audio amp Electronic volume 0.1 µF× 4 + ---+ ---+ ---+ ---- Tuner pack L output LF RF LR RR R output Analog 9V Analog 12 V Analog GND 0.027µF×2 3-wire SIO I2C bus Tuner 9V PLL Tuner GND CE Analog GND Mute Digital 5V Microcontroller Digital GND LCD & keyboard LCD panel 3-wire SIO CPU board Strobe LCD driver Key matrix Tuner Pack Electrical Specifications KEY REQ Digital 5V Digital GND Parameter Audio S/N ratio Operational sensitivity MIN. 51 TYP. 58 6 MAX. Unit dB dB µV 10 CPU board block diagram Noise-reduction element insertion location DIP switches Digital 5V P40-47 AVDD Digital 5V 1 kΩ×2 P50-57 SCL0 SDA0 Electronic volume IC AVSS SIO4 P37(CE) BVDD BVSS V850/SBx EVDD EVSS PLL IC SIO3 P31 (Strobe) P01 (KEY REQ) LCD driver IC P35 (Mute) VDD REGC Audio amp IC RESET X2 VSS X1 Reset signal 1µF Digital GND 0.33 µH V850/SBx CPU board Results of characteristics evaluation using radio system board The EMI reduction efficiency can be ascertained with a radio system board in the same way as standalone microcontroller evaluation. 25 20 15 10 5 0 -5 85 90 105 110 25 20 15 10 5 0 -5 85 Operational Sensivity [dBuV] 30 25 20 15 10 5 0 -5 85 90 95 100 Frequency [MHz] 90 95 100 Frequency [MHz] 105 110 Phase 2 (V850/SB1 A Products) 105 110 Operational Sensivity [dBuV] Phase 4 (V850/SF1) Product Name fXX=16MHz 95 100 Frequency [MHz] 16-Bit Microcontroller from Other Company 30 25 20 15 10 5 0 90 95 100 Frequency [MHz] 30 25 20 15 10 5 0 -5 85 90 95 100 Frequency [MHz] 105 110 16-Bit Microcontroller from Other Company 30 -5 85 Operational Sensivity [dBuV] 30 105 110 Operational Sensivity [dBuV] Operational Sensivity [dBuV] fXX=12MHz Phase 3 (V850/SB2 A Products) Operational Sensivity [dBuV] Phase 5 (V850/SB1 B Products) Product Name 30 25 20 15 10 5 0 -5 85 90 95 100 105 110 Frequency [MHz] Remark fxx : Oscillation frequency Pamphlet U15412EJ1V0PF 35 Middleware Middleware Development System Middleware Development NEC is developing a range of middleware products suitable to processors for various systems. NEC middleware is realized by original NEC technology, superior thirdparty technology, and established standards. Communications Multimedia MPEG7 MPEG-4 Video JPEG2000 Standard specifications Original NEC technology Cooperation with third parties Development support system Planning Creation of middleware Accumulation of solutions USB 2001 System proposal Demonstration Performance evaluation WMA Internet ATRAC3 Music source for incoming-call melody V.90 Security MP3 XML AMR AAC IrDA Information search MPEG-4 CELP Echo canceller Processor lineup Feasibility study RISC V850 Series TrueSpeechTM 8.5 Separation of hardware/software WAP Browser JAVA G.723/729 MH/MR/MMR Next-generation processor Development Assembly support Customization Development completed Image recognition TM POP/SMTP ADPCM HTTP JBIG JPEG PPP Human interface Speech recognition (Japanese) TCP/IP Handwriting recognition (Japanese) Speech recognition (English (US)) Agent system Mass production Text To Speech (Japanese) 2001 Development completed JPEG V850 Series Speech Recognition Conforms to JPEG international standard Conforms to DCT baseline process (non-reverse coding) Versatile compression and decompression processing <Compression functions> • User-customizable VRAM input module • User-specified Huffman and quantization tables • APPn marker insertion • Compression suspend function <Decompressing processing> • User-customizable VRAM output module • Support of various JPEG markers (DRI, RSTn, DNL) • Decompressing suspend function The V850 Series uses internal memory and peripheral I/Os to realize speech recognition on one chip. This makes this series ideal for applications that require speech recognition in sets with large constraints, such as games and home appliances. Speech recognition realized using just the internal memory and peripheral I/Os of V850 Series Increased number of recognized words Number of recognized words: 30 (for V850/SA1, 20 MHz) V850 Series Speech recognition system configuration example V850/SA1 (internal 20 MHz) Internal ROM LPF Internal RAM Mic/amp A/D(1ch) JPEG Performance Processing Time CPU Sample Ratio V850E/MS1 (33MHz)Note 4:1:1 (Quality75) QVGA (320×240×24) Compression Decompression 0.32s 0.24s VGA (640×480×24) Compression Decompression 1.3s 0.97s Increased number of recognized words Note Programs are placed in internal ROM, and stack and work areas (one part) are placed in internal RAM. Data and the remaining work area are placed in external RAM. Memory Capacity Parent dictionary Child dictionary 1 ROM/RAM Thomas, Richard, Harriet... Friends Company Reservations • • • Memory ROM Compression Decompression 10KB 7.5KB RAM Compression Decompression 5KB Capacity Approx. 25 KB Child dictionary 2 Table Approx. 62 KB Ms. Smith, Ms. Jones, Mr. Wang... Recognition dictionary (in case of 20 words) Approx. 0.8 KB Note1 RAM Child dictionary 3 Work area (in case of 20 words) Approx. 4.0 KB Note2 Stack area ANA, JAL, ticket... 10KB Description Program ROM Approx. 0.4 KB Notes 1. Figure using average of 5 letters per word to calculate standard dictionary size. 2. The variable work area is proportional to the number of recognized words. Speech recognition evaluation system In introducing speech recognition, NEC has provided an environment that allows easy evaluation. For details about this system or how to purchase it, contact NEC. 36 Pamphlet U15412EJ1V0PF Handwriting Recognition (Japanese Only) Text to Speech (TTS) (For Japanese Text) Easy to use because of flexibility regarding stroke order and count Speech synthesized from Japanese Kana and Kanji texts (SJIS Pattern matching method based on “non-linear normalization matching method” Conversion of pen-drawn lines into image High recognition rate, high-speed recognition code) Versatile speech synthesis Synthesis of male and female voices (2 types) Recognition of 95% or higher in 0.1 s (V85x: 25 MHz) Various parameters such as intonation and reading speed can be adjusted. Support of up to JIS No. 2 standard JIS No. 1 Standard: Approx. 3,400 characters, JIS No. 2 Standard: Approx. 800 characters New characters can be added (pictographs, etc., can be freely added) A dictionary can be created from character data using a dictionary compilation TTS rhythm data (pitch, phoneme duration) can be designed (Support of Speech Designer) TTS using natural rhythm possible (synthesis of more natural sounding speech) Support of characters with special readings (character readings can be set using the user dictionary) Synthesis speed (V853: 25 MHz) Speech: Between 1.9 sNote and 3 s; Text analysis: 163 ms; speech generation: tool. 1,709 ms Note Varies depending on the input character string. ROM/RAM Description ROM RAM Capacity Program Approx. 60 KB Dictionary data (approx. 4,200 characters) Data Work area Approx. 32 KB Stack area Approx. 2 KB ROM/RAM Description ROM Capacity Program data Approx. 103 KB Approx. 450 KB Dictionary data (approx. 80,000 words) Approx. 1.2 MB Approx. 60 KB Phoneme data Approx. 670 KB to 1.4 MB Work area Approx. 160 KB RAM Stack area Approx. 256 KB Speech output buffer Approx. 8 KB × n blocks Middleware Product List Middleware list Category Middleware MH/MR/MMR JBIG JPEG Text To Speech Japanese Speech CODEC G.726 (ADPCM) Speech recognition Japanese (small vocabulary) Speech recognition English (US) (small vocabulary) Handwriting recognition Japanese (input frame required) Browser TCP/IP IrDA protocol stack USB IEEE1394 PCMCIA/CF card PC-compatible file system Font Image Speech Recognition Internet Drivers Other Remarks 1. 2. 3. V850 Series : Development completed; : Under development; : In planning Third-party products included. For details about middleware products, refer to the following http://www.ic.nec.co.jp/apsoft/english/middle_top.html Middleware performance Middleware MH/MR/MMR JBIG JPEG G.726(ADPCM) Speech recognition (small vocabulary) Performance MH Chart1 : Enc0.12s/Dec0.08s Chart1 : Enc0.73s/Dec0.83s QVGA × 24 : Enc0.32s/Dec0.24s 32Kbps, 16Kbps 0.4s ROM 64 KB 21 KB 17.5 KB 9 KB 82 KB 0.1s/character Power(MIPS) ---------Enc8/Dec8.2 19 (20 words) 63 (100 words) 14 570 KB RAM 200 bytes 2.6 KB 15 KB 80 bytes 3.5 KB (15 words) 34 KB Handwriting recognition (Japanese, input frame required) IrDA protocol stack ---- ---- 60 KB 16 KB Pamphlet U15412EJ1V0PF 37 Flash Memory Microcontrollers Features To answer the need for shorter development time and maintenance after shipping, NEC offers microcontrollers with on-chip flash memory available in a large range of capacities from 128 KB to 512 KB as part of the V850 Series. NEC’s flash memory microcontrollers offer the following features. Flash Memory Size (Bytes) RAM Size (Bytes) 128K 4K 256K 6K 8K 10K 384K 512K 16K 24K 16K V850E/MA1 V850E/IA1 V850E/IA2 Support of batch rewrite of entire memory and rewrite in area units Flash memory programming with self-rewrite in area units Support of on-board programming through serial communication using a flash memory programmer Erase/write voltage: 2.5 V, 7.8 V, 10.3 V V850E/MS1 V853 V850/SA1 V850/SV1 V850/SB1 V850/SB2 V850/SF1 V850/SC1 V850/SC2 V850/SC3 V850ES/SA2∗ V850ES/SA3∗ ∗ : Under development Rewrite Mode The V850 Series supports a programmer rewrite mode that uses serial communication supporting on-board programming, as well as a self-programming mode that rewrites flash memory with user programs, to enable continuous use from development to maintenance. Programmer rewrite mode CSI communication mode UART communication mode VPP VPP VPP VPP VPP VPP VDD VDD VDD VDD VDD VDD GND VSS GND VSS GND VSS RESET Dedicated flash programmer (PG-FP3, etc.) Handshake-compatible CSI communication mode RESET SO SI0 SI SO0 SCK SCK0 Example: V850/SA1 Dedicated flash programmer (PG-FP3, etc.) RESET RESET RESET SO SI0 SI SO0 Example: V850/SA1 Dedicated flash programmer (PG-FP3, etc.) SCK0 SCK RESET TXD RXD0 RXD TXD0 Example: V850/SA1 P15 HS Self-Programming Mode Flash memory can be erased and rewritten by calling a selfprogramming function (device-internal processing) using a selfprogramming interface, from a program placed in an area other than the flash memory. The self-programming function is called by switching from the normal operation mode to the selfprogramming mode using the flash programming mode control register (FLPMC). Normal operation mode Self programming mode Flash memory Flash memory 3FFFFH 3FFFFH FLPMC Self-programming function (on-chip erase/ write routine) 256 KB FLPMC 00000H Pamphlet U15412EJ1V0PF Erase areaNote (128 KB) 00H Note Erasure is performed in area units (128 KB). 38 Erase areaNote (128 KB) 02H 00000H Specifications Part No. V850E/MA1 Flash Memory Capacity 256 KB Power Supply Voltage 3.0 to 3.6 V Max. Operating Frequency 50 MHz Package Rewrite Voltage VDD 144-pin LQFP (20 × 20mm) Rewrite Mode W/E Count VPP 3.3 V 7.8 V CSI, HS-compatible CSI 100 161-pin FBGA (13 × 13mm) V850E/IA1 256 KB 3.0 to 3.6 V (Internal unit) 50 MHz 144-pin LQFP (20 × 20mm) 3.3 V 7.8 V CSI, UART, HS-compatible CSI 100 33 MHz 144-pin LQFP (20 × 20mm) 3.3 V 7.8 V CSI, UART, HS-compatible CSI 100 5V 10.3 V CSI, UART, HS-compatible CSI 20 3.3 V 7.8 V CSI, UART, HS-compatible CSI 100 3.3 V 7.8 V CSI, UART, HS-compatible CSI 100 3.3 V 7.8 V CSI, UART, HS-compatible CSI 100 3.3 V 7.8 V CSI, UART, HS-compatible CSI 100 3.3 V 7.8 V CSI, UART, HS-compatible CSI 100 4.5 to 5.5 V (External pin) V850E/MS1 128 KB 3.0 to 3.6 V 157-pin FBGA (14 × 14mm) 128 KB 144-pin LQFP (20 × 20mm) 3.0 to 3.6 V (Internal unit) 4.5 to 5.5 V (External pin) V853 128 KB 4.5 to 5.5 V 33 MHz 100-pin LQFP (14 × 14mm) 256 KB V850/SA1 128 KB 100-pin LQFP (14 × 14mm) 3.0 to 3.6 V 20 MHz 100-pin LQFP (14 × 14mm) 100-pin LQFP (14 × 14mm) 256 KB 121-pin FBGA (12 × 12mm) V850/SV1 256 KB 3.1 to 3.6 V 20 MHz 176-pin LQFP (24 × 24mm) 180-pin FBGA (13 × 13mm) 180-pin FBGA (13 × 13mm) 384 KB V850/SB1 256 KB 4.0 to 5.5 V 20 MHz 100-pin LQFP (14 × 14mm) 100-pin QFP (14 × 20mm) 100-pin QFP (14 × 20mm) 512 KB V850/SB2 256 KB 4.0 to 5.5 V 13 MHz 100-pin LQFP (14 × 14mm) 100-pin QFP (14 × 20mm) 100-pin QFP (14 × 20mm) 512 KB V850/SF1 256 KB 4.0 to 5.5 V 16 MHz 100-pin LQFP (14 × 14mm) 100-pin QFP (14 × 20mm) V850/SC1, SC2, SC3 512 KB 4.0 to 5.5 V 20 MHz 144-pin LQFP (20 × 20mm) 3.3 V 7.8 V CSI, UART, HS-compatible CSI 100 V850ES/SA2* 256 KB 2.3 to 2.7 V 17 MHz 100-pin LQFP (14 × 14mm) 2.5 V 2.5 V CSI, UART 100 V850ES/SA3* 256 KB 2.3 to 2.7 V 17 MHz 121-pin FBGA (12 × 12mm) 2.5 V 2.5 V CSI, UART 100 * : Under Development Pamphlet U15412EJ1V0PF 39 Flash Memory Programmers NEC flash memory programmer (PG-FP3) [Features] Supports write to all NEC microcontrollers with dual-power supply flash memory Device-specific information required for writing can be automatically set with parameter files. Supports both on-board writing and program adapter writing. Easy-to-carry A5 size Simple operation either on standalone basis or with a dedicated application (Flashpro III) on WindowsTM 95, 98, 2000, or Windows NTTM Ver. 4.0 <Standalone> Executed in one of the following modes: PROMLOAD, ERASE, PROGRAM, VERIFY, E.P.V. <On Windows> Operated via GUI screen. Third-party flash memory programmers (1/2) Programming system Y1000-8 [Manufacturer/Marketing] Wave Technology Co., Ltd. [Target Devices] V850E/MA1, V850/SV1 [Features] Gang programmer enabling simultaneous programming and verification of up to 8 devices Enables reading of master data directly from floppy disk to internal memory. Data dump display and editing functions Master data storable on internal hard disk Emphasizes simple and comfortable operation via touch panel and workability via PASS/FAIL display, check-sum display, and task count display supporting sockets [Additional information] TEL: +81-3-5304-1885 FAX: +81-3-5304-1886 E-mail: [email protected] Website: http://www.y1000.com/en/index.html Flashpro III FL-PR3 [Manufacturer/Marketing] Naito Densei Machida Mfg. Co., Ltd. [Target Devices] V850 Series [Features] Supports writing to all NEC microcontrollers with dual-power supply flash memory Device-specific information required for writing can be automatically set with parameter files. Supports both on-board writing and program adapter writing. Easy-to-carry A5 size Simple operation either on standalone basis or with a dedicated application (Flashpro III) on Windows 95, 98, 2000, or Windows NT Ver. 4.0 [Additional Information] FAX: +81-45-475-4091 E-mail: [email protected] Website: http://www.ndk-m.co.jp/eng/index.html 40 Pamphlet U15412EJ1V0PF Third-party flash memory programmers (2/2) NET IMPRESS [Manufacturer/Marketing] Yokogawa Digital Computer Corporation [Target Devices] V850E/IA1, V850/SB1 (µPD70F3033A) [Features] This in-circuit programmer for flash memory microcontrollers (NET IMPRESS) is used to program the microcontrollers with on-chip flash memory of each company, which have various writing specifications, while solder mounted on the user system board. This programmer comes in four models (AF220, AF210, AF120, AF110) to be used according to the intended application field. One control module is the key to this product’s versatility. Microcontrollers of the same family are supported by changing parameters, and microcontrollers of different families are supported by purchasing the license for the descriptor part. Can be used on standalone basis as well as via a host machine. Rich lineup of freeware [Additional Information] TEL : Japan +81-42-333-6224 U.S.A +408-244-1932 Europe +44-1256-811998 FAX : Japan +81-42-352-6109 U.S.A +408-244-1881 Europe +44-1256-811761 E-mail : [email protected] Website : http://www.ydc.co.jp/micom/index_E.htm Flash Memory Programmers NEC's flash memory programmer (PG-FP3) supports all NEC microcontrollers with dual-power-supply on-chip flash memory. The PG-FP3 stores the device-specific information required for rewriting in a parameter file and the rewriting environment for each microcontroller can be automatically set by downloading this file. After the parameter file is downloaded, the PG-FP3 can be used on a standalone basis. Combined with a program adapter (FA series (manufactured by Naito Densei Machida Mfg. Co., Ltd.)), this programmer can be used to write single microcontrollers. On-board writing is also possible using a target cable. An example of the rewriting environment when using the program adapter is described below. Example of rewriting environment Flash memory programmer (PG-FP3) Target system Power supply unit Host machine interface (RS-232-C) To host machine Cautions 1. Install the control software of the PG-FP3 and the parameter file of the target device in the host machine. • PG-FP3 control software: Provided with PG-FP3 • Parameter files: Distributed via online delivery 2. In addition to using the program adapter, rewriting can also be done on-board on the target system. Pamphlet U15412EJ1V0PF 41 Functional Outline (1/11) V850E/MA1 µ PD703103A Item µ PD703105A V850E1 CPU performance (Dhrystone) ---- 62MIPS (@ 50 MHz) Internal ROM None 128 KB (Mask ROM) µ PD70F3107A µ PD703108 ---256 KB (mask ROM) 10 KB 4 KB Internal RAM External bus interface µ PD703107A V850E1 CPU core 256 KB (flash memory) None 4 KB Address bus 26 bits 25 bits Data bus 16 bits 16 bits 0 to 7 0 to 7 External: 25 (17)Note Internal: 33 External: 8 (4) Internal: 23 0.02 to 0.04µs (@ 50 MHz) 0.025 to 0.05µs (@ 40 MHz) 0.06µs (@ 50 MHz) 0.075µs (@ 40 MHz) ---- ---- Programmable waits Interrupt sources DSP function µ PD703106A V850E/MA2 32×32 64 32×32+32 16×16 32 32 Note ---- ---- 16-bit timer/event counter × 4 ch 16-bit interval timer × 4 ch 16-bit timer/event counter × 2 ch 16-bit interval timer × 4 ch CSI 1 ch ---- CSI/I2C ---- ---- CSI/UART 2 ch 2 ch UART 1 ch ---- Dedicated BRG 3 ch 2 ch A/D converter 8 ch (10-bit resolution) 4 ch (10-bit resolution) DMA controller 4 ch 4 ch 16×16+32 32 Timer/counter (RPU) Serial interface (SIO) ---- ---- I/O 106 74 Input 9 5 Other peripheral I/O functions Memory access control function (SDRAM, SRAM, EDO DRAM, page ROM, etc., directly connectable) PWM: 2 ch (8/9/10/12-bit resolution) Memory access control function (SDRAM, SRAM, page ROM, etc., directly connectable) Power save function HALT, IDLE, STOP HALT, IDLE, STOP Operating frequency 4 to 50 MHz 4 to 40 MHz 3.0 to 3.6 V 3.0 to 3.6 V Power consumption (Typ.) 540mW (@ 3.3 V, 50 MHz) 376mW (@ 3.3 V, 40 MHz) Package 144-pin plastic LQFP (20 × 20 mm) Real-time output port Ports Power supply voltage 144-pin plastic LQFP (20 × 20 mm) 161-pin plastic FGBA (13 × 13 mm) Note Number of external interrupts that can be used to release STOP mode 42 Pamphlet U15412EJ1V0PF 100-pin plastic LQFP (14 × 14 mm) (2/11) V850E/IA1 µ PD703116 Item V850E/IA2 µ PD703114 µ PD70F3116 CPU core V850E1 V850E1 CPU performance (Dhrystone) 62MIPS (@ 50 MHz) 50MIPS (@ 40 MHz) Internal ROM 256 KB (mask ROM) 6 KB 24 bits 22 bits Data bus 16 bits 16 bits 0 to 7 0 to 7 External: 20 (14)Note Internal: 46 External: 16 (12) External: 42 0.02 to 0.04µs (@ 50 MHz) 0.025 to 0.05µs (@ 40 MHz) 0.06µs (@ 50 MHz) 0.075µs (@ 40 MHz) ---- ---- ---- ---- 16-bit 3-phase sine wave PWM timer × 2 ch 16-bit encoder counter/timer × 2 ch 16-bit timer/counter × 2 ch 16-bit timer/event counter × 1 ch 16-bit interval timer × 1 ch 16-bit 3-phase sine wave PWM timer × 2 ch 16-bit encoder counter/timer × 1 ch 16-bit timer/counter × 2 ch 16-bit timer/event counter × 1 ch 16-bit interval timer × 1 ch CSI 2 ch 1 ch CSI/I2C ---- ---- CSI/UART ---- 1 ch UART 3 ch 1 ch Dedicated BRG 4 ch 3 ch Interrupt sources 32×32 64 32×32+32 16×16 32 32 16×16+32 32 Timer/counter (RPU) Serial interface (SIO) 128 KB (flash memory) 10 KB Programmable waits DSP function 128 KB (mask ROM) Address bus Internal RAM External bus interface 256 KB (flash memory) µ PD70F3114 Note A/D converter 8 ch (10-bit resolution), 2 units 6 ch (10-bit resolution): A/D converter 0, 8 ch (10-bit resolution): A/D converter 1 DMA controller 4 ch 4 ch ---- ---- I/O 75 47 Input 8 6 Other peripheral I/O functions Memory access control function (SRAM, ROM connectable) Memory access control function (SRAM, ROM connectable) Power save function HALT, IDLE, STOP HALT, IDLE, STOP Operating frequency 4 to 50 MHz 4 to 40 MHz Internal unit: 3.3 V, A/D converter: 5 V, external pin: 5 V 5 V (Internal unit: 3.3 V, A/D converter: 5 V, external pin: 5 V) (On-chip regulator) Power consumption (Typ.) 630 mW (For internal unit: 3.3 V, external pin: 5 V, 50 MHz) 440mW Package 144-pin plastic LQFP (20 × 20 mm) 100-pin plastic LQFP (14 × 14 mm) Real-time output port Ports Power supply voltage Note Number of external interrupts that can be used to release STOP mode Pamphlet U15412EJ1V0PF 43 (3/11) V850E/MS1 µ PD703100-40 Item µ PD703100-33 µ PD703101-33 CPU core V850E CPU performance (Dhrystone) ---- 43 MIPS (@ 33 MHz) Internal ROM None 96 KB (mask ROM) 4 KB Internal RAM External bus interface Address bus 24 bits Data bus 16 bits Programmable waits Note External: 25 (1) Internal: 47 Interrupt sources DSP function 0 to 7 32×32 64 32×32+32 16×16 32 32 0.075µs (@ 40 MHz) 0.09µs (@ 33 MHz) ---16-bit timer/event counter × 6 ch 16-bit interval timer × 2 ch Timer/counter (RPU) Serial interface (SIO) 0.03 to 0.06µs (@ 33 MHz) ---- 32 16×16+32 0.025 to 0.05µs (@ 40 MHz) CSI 2 ch CSI/I2C ---- CSI/UART 2 ch UART ---- Dedicated BRG 3 ch A/D converter 8 ch (10-bit resolution) DMA controller 4 ch ---- Real-time output port Ports I/O 114 Input 9 Other peripheral I/O functions Memory access control function (EDO DRAM, SRAM, page ROM, etc., directly connectable) Power save function HALT, IDLE, STOP Operating frequency 2 to 40 MHz Power supply voltage Internal unit: 3.3 V, A/D converter: 5 V External pin: 5 V Power consumption (Typ.) 540mW (@ 40 MHz) Package 144-pin plastic LQFP (20 × 20 mm) 2 to 33 MHz 430mW (@ 33 MHz) Note Number of external interrupts that can be used to release STOP mode 44 Pamphlet U15412EJ1V0PF µPD703102-33 128 KB (mask ROM) µ PD70F3102-33 128 KB (flash memory) (4/11) V850E/MS1 µ PD703100A-40 Item µ PD703100A-33 µPD703101A-33 V850E CPU performance (Dhrystone) ---- 43MIPS (@ 33 MHz) Internal ROM None 96 KB (mask ROM) µ PD703130 ---128 KB (mask ROM) 128 KB (flash memory) None 4 KB 4 KB 24 bits 24 bits Data bus 16 bits 16 bits 0 to 7 0 to 7 Programmable waits Note External: 10 (1)Note Internal: 35 External: 25 (1) Internal: 47 Interrupt sources 32×32 64 32×32+32 16×16 32 0.025 to 0.05µs (@ 40 MHz) 0.03 to 0.06µs (@ 33 MHz) 0.03 to 0.06µs (@ 33 MHz) 0.075µs (@ 40 MHz) 0.09µs (@ 33 MHz) 0.09µs (@ 33 MHz) ---- 32 ---- ---- ---- 16-bit timer/event counter × 6 ch 16-bit interval timer × 2 ch 16-bit timer/ event counter × 4 ch 16-bit interval timer × 2 ch CSI 2 ch ---- CSI/I2C ---- ---- CSI/UART 2 ch 2 ch UART ---- ---- Dedicated BRG 3 ch 2 ch 16×16+32 32 Timer/counter (RPU) Serial interface (SIO) µ PD70F3102A-33 Address bus Internal RAM DSP function µ PD703102A-33 V850E CPU core External bus interface V850E/MS2 A/D converter 8 ch (10-bit resolution) 4 ch (10-bit resolution) DMA controller 4 ch 4 ch ---- ---- I/O 114 76 Input 9 5 Memory access control function (EDO DRAM, SRAM, page ROM, etc., directly connectable) Memory access control function (EDO DRAM, SRAM, page ROM, etc., directly connectable) Real-time output port Ports Other peripheral I/O functions HALT, IDLE, STOP Power save function HALT, IDLE, STOP Operating frequency 2 to 40MHz Power supply voltage Internal unit: 3.3 V, A/D converter: 3.3 V External pin: 3.3 V Internal unit: 3.3 V, A/D converter: 5 V External pin: 5 V Power consumption (Typ.) 330mW (@ 40 MHz) 270mW (@ 33 MHz) 381mW (@ 33 MHz) Package 144-pin plastic LQFP (20 × 20 mm) 144-pin plastic LQFP (20 × 20 mm) 157-pin plastic FBGA (14 × 14 mm) 100-pin plastic LQFP (14 × 14 mm) 10 to 33MHz 2 to 33MHz Note Number of external interrupts that can be used to release STOP mode Pamphlet U15412EJ1V0PF 45 (5/11) V850ES/SA2 µ PD70F3201/ µ PD70F3201Y µ PD703201/ µ PD703201Y Item µ PD703204/ µ PD703204Y CPU performance (Dhrystone) 21 MIPS (@ 17 MHz)/16 MIPS (@ 13.5 MHz) Internal ROM 256 KB (mask ROM) 256 KB (flash memory) 256 KB (mask ROM) 16 KB Internal RAM External bus interface Address bus 22 bits Data bus 8/16 bits Programmable waits 24 bits 0 to 7 Note 1 External: 8 (8)Note 1 Internal: 31 (Y products: 32) External: 8 (8) Internal 30 (Y products: 31) Interrupt sources 32×32 64 32×32+32 16×16 0.24 to 0.29µs (@ 17 MHz) 32 0.35µs (@ 17 MHz) 0.06 to 0.12µs (@ 17 MHz) 32 16×16+32 32 0.18µs (@ 17 MHz) 16-bit timer/event counter × 2 ch 8-bit timer/event counter × 4 ch (usable as 16-bit timer/event counter × 2 ch) Timer/counter (RPU) 2 ch 3 ch 1 ch 1 ch CSI/UART 1 ch 1 ch UART 1 ch 1 ch Dedicated BRG 2 ch (UART-dedicated) 2 ch A/D converter 12 ch (10-bit resolution) 16 ch (10-bit resolution) DMA controller 4 ch Serial interface (SIO) CSI CSI/I2C Note 2 ---- Real-time output port Ports I/O 68 84 Input 14 18 Other peripheral I/O functions Real-time counter (for watch): 1 ch Watchdog timer: 1 ch Power save function HALT, IDLE, STOP Operating frequency When using main clock: 2 to 17 MHz (@ 2.4 V)/2 to 13.5 MHz (@ 2.3 V) When using subclock: 32.768 kHz (only real-time counter operating) Power supply voltage 2.3 to 2.7 V (@ 17 MHz)/2.2 to 2.7 V (@ 13.5 MHz) Power consumption (Typ.) When using main clock: 30 mW* (@ 2.5 V, 17 MHz) Package 100-pin plastic LQFP (14 × 14 mm) 121-pin plastic FBGA (12 × 12 mm) Notes1. Number of external interrupts that can be used to release STOP mode 2. Only Y products have an on-chip I2C bus interface. CSI/I2C : µPD703201Y, 703204Y, 70F3201Y, 70F3204Y CSI : µPD703201, 703204, 70F3201, 70F3204 Remark Values with * are target values. 46 µ PD70F3204/ µ PD70F3204Y V850ES CPU core DSP function V850ES/SA3 Pamphlet U15412EJ1V0PF 256 KB (flash memory) (6/11) V850/SA1 µ PD703014A/ µ PD703014AY Item µ PD703014B/ µ PD703014BY µ PD703015A/ µ PD703015AY CPU performance (Dhrystone) 23MIPS (@ 20 MHz)/19MIPS (@ 17 MHz) Internal ROM 64 KB (mask ROM) 128 KB (mask ROM) 128 KB (flash memory) µ PD703017A/ µ PD703017AY µ PD70F3017A/ µ PD70F3017AY External bus interface Address bus 22 bits Data bus 16 bits Programmable waits 0 to 3 256 KB (mask ROM) 256 KB (flash memory) 8 KB 4 KB Internal RAM External: 9 (6)Note 1 Internal: 22 Interrupt sources 32×32 ---- 64 32×32+32 16×16 32 ---- 32 0.15µs (@ 20 MHz) 0.05 to 0.10µs (@ 20 MHz) 32 16×16+32 16-bit timer/event counter × 2 ch 8-bit timer/event counter × 4 ch (usable as 16-bit timer/event counter × 2 ch) Timer/counter (RPU) Serial interface (SIO) 1 ch CSI CSI/I2C Note 2 1 ch CSI/UART 1 ch UART 1 ch Dedicated BRG 2 ch (UART-dedicated) A/D converter 12 ch (10-bit resolution) DMA controller 3 ch (only for internal RAM Ports on-chip peripheral I/O) 8-bit × 1 ch or 4-bit × 2 ch Real-time output port I/O 72 Input 13 Other peripheral I/O functions Watch timer: 1 ch Watchdog timer: 1 ch Power save function HALT, IDLE, STOP Operating frequency Using main clock: 2 to 20 MHz (@ 3.3 V)/2 to 17 MHz (@ 3 V) Using subclock: 32.768 kHz Power supply voltage 3.0 to 3.6 V (@ 20 MHz)/2.7 to 3.6 V (@ 17 MHz) Power consumption (Typ.) Package µPD70F3015B/ µ PD70F3015BY V850 CPU core DSP function µ PD703015B/ µ PD703015BY Using main clock: 66 mW (@ 3.3 V, 20 MHz)/56 mW (@ 3.3 V, 17 MHz) Using main clock: 105 mW(@ 3.3 V, 20 MHz)/ 99 mW (@ 3.3 V, 17 MHz) Using main clock: Using main clock: 66 mW (@ 3.3 V, 20 MHz)/ 105 mW (@ 3.3 V, 20 MHz)/ 56 mW (@ 3.3 V, 17 MHz) 99 mW (@ 3.3 V, 17 MHz) 100-pin plastic LQFP (14 × 14 mm) 121-pin plastic FBGA (12 × 12 mm)Note 4 Note 3 Notes1. Number of external interrupts that can be used to release STOP mode 2. Only Y products have an on-chip I2C bus interface. CSI/I2C : µPD703014AY, 703014BY, 703015AY, 703015BY, 703017AY, 70F3015BY, 70F3017AY CSI : µPD703014A, 703014B, 703015A, 703015B, 703017A, 70F3015B, 70F3017A 3. µPD703014B, 703014BY, 703015B, 703015BY, 703017A, 703017AY, 70F3015B, 70F3015BY, 70F3017A, 70F3017AY 4. µPD703014A, 703014AY, 703015A, 703015AY, 703017A, 703017AY, 70F3017A, 70F3017AY Caution The maximum operating frequency of the I2C bus interface is 17 MHz. Pamphlet U15412EJ1V0PF 47 (7/11) V850/SV1 µ PD703041/ µ PD703041Y Item µPD703039/ µPD703039Y CPU core V850 CPU performance (Dhrystone) 23 MIPS (@ 20 MHz)/18 MIPS (@ 16 MHz) Internal ROM 192 KB (mask ROM) Internal RAM Address bus 22 bits Data bus 16 bits Programmable waits 0 to 3 µ PD70F3040/ µ PD70F3040Y µ PD703038/ µ PD703038Y µ PD70F3038/ µ PD70F3038Y 256 KB (flash memory) 384 KB (mask ROM) 384 KB (flash memory) 148 mW (@ 3.3 V, 20 MHz)/ 132 mW (@ 3.3 V, 16 MHz) 82 mW (@ 3.3 V, 20 MHz) 72 mW (@ 3.3 V. 16 MHz) 148 mW (@ 3.3 V, 20 MHz) 132 mW (@ 3.3 V, 16 MHz) 16 KB External: 9 (6)Note 1 Internal: 43 (Y products: 44) Interrupt sources DSP function 256 KB (mask ROM) 8 KB External bus interface µ PD703040/ µPD703040Y 32×32 64 32×32+32 16×16 ---32 32 16×16+32 0.05 to 0.10µs (@ 20 MHz) 32 0.15µs (@ 20 MHz) 24-bit timer/event counter × 2 ch 16-bit timer/event counter × 2 ch 8-bit timer/event counter × 8 ch (usable as 16-bit timer/event counter × 4 ch) Timer/counter (RPU) Serial interface (SIO) ---- CSI 1 ch CSI/I2CNote 2 2 ch CSI/UART 2 ch UART ---- Dedicated BRG 3 ch A/D converter 16 ch (10-bit resolution ) DMA controller 6 ch (only for internal RAM 8-bit × 2 ch or 4-bit × 4 ch Real-time output port Ports on-chip peripheral I/O) I/O 135 Input 16 Other peripheral I/O functions Vsync/Hsync separator Watch timer: 1 ch Watchdog timer: 1 ch PWM: 4 ch (12 to 16-bit resolution) Power save function HALT, IDLE, STOP Operating frequency 4 to 20 MHz (@ 3.3 V)/4 to 16 MHz (@ 3 V) Power supply voltage 3.1 to 3.6 V (@ 20 MHz)/2.7 to 3.6 V (@ 16 MHz) Power consumption (Typ.) 82 mW (@ 3.3 V, 20 MHz)/72 mW (@ 3.3 V, 16 MHz) Package 176-pin plastic LQFP (24 × 24 mm) 176-pin plastic LQFP (24 × 24 mm) 180-pin plastic FBGA (13 × 13 mm) Notes1. Number of external interrupts that can be used to release STOP mode 2. Only Y products have an on-chip I2C bus interface. CSI/I2C : µPD703038Y, 703039Y, 703040Y, 703041Y, 70F3038Y, 70F3040Y CSI : µPD703038, 703039, 703040, 703041, 70F3038, 70F3040 Caution The maximum operating frequency of the I2C bus interface is 17 MHz. 48 Pamphlet U15412EJ1V0PF 180-pin plastic FBGA (13 × 13 mm) (8/11) Item V850/SC1 V850/SC2 V850/SC3 µ PD703068Y µPD703069Y µPD703088Y V850/SC1, V850/SC2, V850/SC3 µ PD703089Y µ PD70F3089Y CPU core V850 V850 V850 V850 CPU performance (Dhrystone) 23MIPS (@ 20 MHz) 21MIPS (@ 19 MHz) 18MIPS (@ 16 MHz) 23MIPS (@ 20 MHz) Internal ROM 512 KB (mask ROM) 512 KB (mask ROM) 512 KB (mask ROM) 512 KB (flash memory) 24 KB 24 KB 24 KB 24 KB Address bus 22 bits 22 bits 22 bits 22 bits Data bus 16 bits 16 bits 16 bits 16 bits 0 to 3 0 to 3 0 to 3 0 to 3 External: 12 (9)Note Internal: 39 External: 12 (9)Note Internal: 41 External: 12 (9) Internal: 43 ---- ---- ---- ---- ---- ---- ---- ---- Internal RAM External bus interface Programmable waits Interrupt sources DSP function 32×32 64 32×32+32 32 Note Note External: 12 (9) Internal: 46 Note External: 12 (9) Internal: 46 0.05 to 0.10µs (@ 20 MHz) 0.053 to 0.106µs (@ 19 MHz) 0.06 to 0.12µs (@ 16 MHz) 0.05 to 0.10µs (@ 20 MHz) 0.15µs (@ 20 MHz) 0.159µs (@ 19 MHz) 0.18µs (@ 16 MHz) 0.15µs (@ 20 MHz) 16-bit timer/ event counter × 10 ch 16-bit timer/ event counter × 10 ch 16-bit timer/event counter × 10 ch 16-bit timer/ event counter × 10 ch CSI 2 ch 2 ch 2 ch 2 ch CSI/I2C 2 ch 2 ch 2 ch 2 ch CSI/UART 2 ch 2 ch 2 ch 2 ch UART 2 ch 2 ch 2 ch 2 ch Dedicated BRG 5 ch 5 ch 5 ch 5 ch A/D converter 12 ch (10-bit resolution) 12 ch (10-bit resolution) 12 ch (10-bit resolution) DMA controller 6 ch (only for internal RAM on-chip peripheral I/O) 6 ch (only for internal RAM on-chip peripheral I/O) 6 ch (only for internal RAM 16×16 32 16×16+32 32 Timer/counter (RPU) Serial interface (SIO) 6 ch (only for internal RAM on-chip peripheral I/O) ---- ---- ---- ---- I/O 112 112 112 112 Input 12 12 12 ---- IEBus (simple version): 1 ch FCAN : 1 ch Watch timer: 1 ch Watchdog timer: 1 ch Watch timer: 1 ch Watchdog timer: 1 ch Watch timer: 1 ch Watchdog timer: 1 ch Real-time output port Ports 12 ch (10-bit resolution) on-chip peripheral I/O) Other peripheral I/O functions 12 FCAN : 2 ch IEBus (simple version): 1 ch/FCAN: 2 ch Watch timer: 1 ch Watchdog timer: 1 ch Power save function HALT, IDLE, STOP HALT, IDLE, STOP HALT, IDLE, STOP HALT, IDLE, STOP Operating frequency Using main clock: 4 to 20 MHz (@ 5 V) Using subclock: 32.768 kHz Using main clock: 4 to 19 MHz (@ 5 V) Using subclock: 32.768 kHz Using main clock: 4 to 16 MHz (@ 5 V) Using subclock: 32.768 kHz Using main clock: 4 to 20 MHz (@ 5 V) Using subclock: 32.768 kHz Power supply voltage 3.5 to 5.5 V (A/D converter: 4.5 to 5.5 V) 3.5 to 5.5 V (A/D converter: 4.5 to 5.5 V) 3.5 to 5.5 V (A/D converter: 4.5 to 5.5 V) 4.0 to 5.5 V (A/D converter: 4.5 to 5.5 V) Power consumption (Typ.) Using main clock: 125 mW* (@ 5 V, 20 MHz) Using main clock: 120 mW* (@ 5 V, 19 MHz) Using main clock: 110 mW* (@ 5 V, 16 MHz) Using main clock: 150 mW* (@ 5 V, 20 MHz) Package 144-pin plastic LQFP (20 × 20 mm) 144-pin plastic LQFP (20 × 20 mm) 144-pin plastic LQFP (20 × 20 mm) 144-pin plastic LQFP (20 × 20 mm) Note Number of external interrupts that can be used to release STOP mode Remark Values with * are target values. Pamphlet U15412EJ1V0PF 49 (9/11) V850/SB1 V850/SF1 µ PD703078Y Item µ PD703079Y CPU core V850 CPU performance (Dhrystone) 18MIPS (@ 16 MHz) Internal ROM 256 KB (mask ROM) Internal RAM External bus interface 128 KB (mask ROM) 256 KB (mask ROM) 16 KB 12 KB 22 bits Data bus 16 bits 16 bits Programmable waits 0 to 3 0 to 3 64 External: 9 (6)Note 1 Internal: 35 256 KB (flash memory) 512 KB (mask ROM) 20 KB 24 KB Note 1 32 ---- ---- 0.06 to 0.12µs (@ 16 MHz) 0.05 to 0.10µs (@ 20 MHz) 32 0.18µs (@ 16 MHz) 0.15µs (@ 20 MHz) 16-bit timer/event counter × 8 ch 16-bit timer/event counter × 2 ch 8-bit timer/event counter × 4 ch (usable as 16-bit timer/event counter × 2 ch) 8-bit timer × 2 ch (usable as 16-bit timer × 1 ch) CSI 1 ch 1 ch CSI/I2CNote 2 1 ch 2 ch CSI/UART 2 ch 2 ch UART ---- ---- Dedicated BRG 32 16×16+32 Timer/counter (RPU) 3 ch 3 ch A/D converter 12 ch (10-bit resolution) 12 ch (10-bit resolution) DMA controller 6 ch (only for internal RAM on-chip peripheral I/O) 6 ch (only for internal RAM ---- 8 bits × 1 or 4 bits × 2 I/O 72 71 Input 12 Real-time output port Other peripheral I/O functions FCAN : 1 ch 512 KB (flash memory) External: 9 (6) Internal: 30 (Y products: 31) ---- 16×16 on-chip peripheral I/O) 12 FCAN : 2 ch ---- Watch timer : 1 ch Watchdog timer : 1 ch Watch timer: 1 ch Watchdog timer: 1 ch Power save function HALT, IDLE, STOP HALT, IDLE, STOP Operating frequency Using main clock: 4 to 16 MHz (@ 5 V) Using subclock: 32.768 kHz Using main clock: 2 to 20 MHz (@ 5 V) Using subclock: 32.768 kHz Power supply voltage 4.0 to 5.5 V (A/D converter: 4.5 to 5.5 V) (@ 16 MHz) 4.0 to 5.5 V (A/D converter: 4.5 to 5.5 V) Power consumption (Typ.) Using main clock: 75 mW (mask ROM)/ 125 mW (flash memory)(@ 5 V, 16 MHz) Using main clock: 125 mW (@ 5 V, 20 MHz) Package 100-pin plastic LQFP (14 × 14 mm) 100-pin plastic QFP (14 × 20 mm) 100-pin plastic LQFP (14 × 14 mm) 100-pin plastic QFP (14 × 20 mm) Notes1. Number of external interrupts that can be used to release STOP mode 2. Only Y products have an on-chip I2C bus interface. CSI/I2C : µPD703030AY, 703031AY, 703032AY, 703033AY, 703078Y, 703079Y, 70F3032AY, 70F3033AY, 70F3079Y CSI : µPD703030A, 703031A, 703032A, 703033A, 70F3032A, 70F3033A 50 384 KB (mask ROM) ---- 32×32+32 Ports µ PD703032A/ µ PD70F3032A/ µ PD703032AY µ PD70F3032AY 23MIPS (@ 20 MHz) 256 KB (flash memory) 16 KB 32×32 µ PD703033A/ µPD70F3033A/ µPD703030A/ µ PD703033AY µPD70F3033AY µPD703030AY V850 22 bits External: 9 (6)Note 1 Internal: 32 Serial interface (SIO) µ PD703031A/ µ PD703031AY Address bus Interrupt sources DSP function µ PD70F3079Y Pamphlet U15412EJ1V0PF Using main clock: 165 mW (@ 5 V, 20 MHz) Using main clock: 125 mW (@ 5 V, 20 MHz) 100-pin plastic QFP (14 × 20 mm) Using main clock: 165 mW (@ 5 V, 20 MHz) (10/11) V850/SB2 µ PD703034A/ µ PD703034AY Item µ PD703035A/ µ PD703035AY CPU core V850 CPU performance (Dhrystone) 15MIPS (@ 13 MHz) Internal ROM 128 KB (mask ROM) 256 KB (mask ROM) 12 KB 16 KB Internal RAM External bus interface Address bus 22 bits Data bus 16 bits Programmable waits 0 to 3 256 KB (flash memory) µ PD703036A/ µ PD703036AY µPD703037A/ µ PD703037AY 384 KB (mask ROM) 512 KB (mask ROM) 20 KB 24 KB µPD70F3037A/ µ PD70F3037AY 512 KB (flash memory) External: 9 (6)Note 1 Internal: 32 (Y products: 33) Interrupt sources DSP function µPD70F3035A/ µPD70F3035AY 32×32 64 32×32+32 16×16 ---32 32 16×16+32 0.077 to 0.154µs (@ 13 MHz) 32 CSI 1 ch CSI/I2CNote 2 2 ch CSI/UART 2 ch UART ---- Dedicated BRG A/D converter 3 ch 12 ch (10-bit resolution) DMA controller 6 ch (only for internal RAM on-chip peripheral I/O) 8 bits × 1 or 4 bits × 2 Real-time output port Ports 0.231µs (@ 13 MHz) 16-bit timer/event counter × 2 ch 8-bit timer/event counter × 4 ch (usable as 16-bit timer/event counter × 2 ch) 8-bit timer × 2 ch (usable as 16-bit timer × 1 ch) Timer/counter (RPU) Serial interface (SIO) ---- I/O 71 Input 12 Other peripheral I/O functions IEBus (simple version) Watch timer: 1 ch Watchdog timer: 1 ch Power save function HALT, IDLE, STOP Operating frequency Using main clock: 2 to 13 MHz (@ 5 V) Using subclock: 32.768 kHz Power supply voltage 4.0 to 5.5 V (A/D converter: 4.5 to 5.5 V) Power consumption (Typ.) Using main clock: 75 mW (@ 5 V, 13 MHz) Package 100-pin plastic LQFP (14 × 14 mm) 100-pin plastic QFP (14 × 20 mm) Using main clock: 125 mW (@ 5 V, 13 MHz) Using main clock: 75 mW (@ 5 V, 13 MHz) Using main clock: 125 mW (@ 5 V, 13 MHz) 100-pin plastic QFP (14 × 20 mm) Notes1. Number of external interrupts that can be used to release STOP mode 2. Only Y products have an on-chip I2C bus interface. CSI/I2C : µPD703034AY, 703035AY, 703036AY, 703037AY, 70F3035AY, 70F3037AY CSI : µPD703034A, 703035A, 703036A, 703037A, 70F3035A, 70F3037A Pamphlet U15412EJ1V0PF 51 (11/11) V853 µ PD703003A Item µ PD703025A CPU performance (Dhrystone) 38MIPS (@ 33 MHz) Internal ROM 128 KB (mask ROM) 96 KB (mask ROM) 4 KB Internal RAM External bus interface Address bus 20 bits Data bus 16 bits Programmable waits 0 to 3 External: 17 (1) Internal: 32 Interrupt sources 32×32 µ PD70F3025A 16×16 ---- 32 0.09µs (@ 33 MHz) 8 KB 4 KB 8 KB 450 mW (@ 5V, 33 MHz) 425 mW (@ 5 V, 33 MHz) 480 mW (@ 5 V, 33 MHz) 16-bit timer/event counter × 4 ch 16-bit timer × 1 ch CSI 2 ch CSI/I2C ---- CSI/UART 2 ch UART ---- Dedicated BRG 3 ch A/D converter 8 ch (10-bit resolution) DMA controller ---- ---- Real-time output port Ports 256 KB (flash memory) 0.03 to 0.06µs (@ 33 MHz) Timer/counter (RPU) Serial interface (SIO) 128 KB (flash memory) Note 32 32 16×16+32 256 KB (mask ROM) ---- 64 32×32+32 I/O 67 Input 8 Other peripheral I/O functions PWM: 2 ch (8/9/10/12-bit resolution) D/A converter: 2 ch Power save function HALT, IDLE, STOP Operating frequency 5 to 33 MHz (@ 5 V) Power supply voltage 4.5 to 5.5V Power consumption (Typ.) 365 mW (@ 5 V, 33 MHz) Package 100-pin plastic LQFP (14 × 14 mm) Note Number of external interrupts that can be used to release STOP mode 52 µ PD70F3003A V850 CPU core DSP function µ PD703004A Pamphlet U15412EJ1V0PF Comfortable Development Environment Development Flow Product planning PM System design Hardware design Software design RX850, RX850 Pro Coding Fabrication Standalone testing Compiling/ assembly CA850 Debugging SM850 +RD850, +RD850 Pro +AZ850 ID850 System debugging System evaluation IE DF703xxx Hardware tools Commercialization Software tools Development Tools (1/3) Software tools Product Name Software package SP850 C compiler CA850Note 1 Device file DF703xxxNote 1 Project Manager PMNotes 1, 2 Integrated debugger ID850Note 1 System simulator SM850Note 1 Real-time OS RX850, RX850 Pro Task debugger RD850, RD850 ProNote 3 System performance analyzer AZ850Note 1 Middleware AP703000-Bxxx, AP703100-Bxxx Notes 1. Packaged in SP850 2. Included with CA850 3. Included with RX850, RX850 Pro Remark For details, refer to the V800 SeriesTM Development Environment Pamphlet (U10782E). Pamphlet U15412EJ1V0PF 53 Development Tools (2/3) Hardware tools Target Device Device Name V850E/MA1 In-Circuit Emulator Package Main Unit 144-pin plastic LQFP (20 × 20 mm) IE-V850E-MC-A Emulation Board IE-703107-MC-EM1 161-pin plastic FBGA (13 × 13 mm) IE-703107-MC-EM1 + CSSOCKET161A1413N01S1 (under development)Note 1 Note 1 LSPACK161A1413N01 (under development) Note 1 CSICE161A1413N02 (under development) V850E/MA2 100-pin plastic LQFP (14 × 14 mm) IE-703107-MC-EM1 + VP-V850E/MA1-MA2 (under development)Note 2 V850E/IA1 144-pin plastic LQFP (20 × 20 mm) V850E/IA2 100-pin plastic LQFP (14 × 14 mm) V850E/MS1 (5V) 144-pin plastic LQFP (20 × 20 mm) V850E/MS1 (3.3V) 144-pin plastic LQFP (20 × 20 mm) IE-703102-MC-EM1-A 157-pin plastic FBGA (14 × 14 mm) IE-703102-MC-EM1-A + CSPACK157A1614N01Note 1 CSICE157A1614N01Note 1 100-pin plastic LQFP (14 × 14 mm) IE-703102-MC-EM1 + VP-V850E/MS1-MS2Note 2 V850E/MS2 (5V) V850/SA1 V850/SB1, V850/SB2 V850/SV1 100-pin plastic LQFP (14 × 14 mm) IE-V850E-MC IE-703116-MC-EM1 IE-703114-MC-EM1 IE-703102-MC IE-703002-MC IE-703102-MC-EM1 IE-703017-MC-EM1 121-pin plastic FBGA (12 × 12 mm) IE-703017-MC-EM1 + CSPACK121A1312N02Note 1 CSICE121A1312N02Note 1 100-pin plastic LQFP (14 × 14 mm) IE-703037-MC-EM1 100-pin plastic QFP (14 × 20 mm) IE-703037-MC-EM1 + NEXB-100SD/RBNote 1 176-pin plastic LQFP (24 × 24 mm) IE-703040-MC-EM1 180-pin plastic FBGA (13 × 13 mm) IE-703040-MC-EM1 + CSSOCKET180A1513N01NNote 1 CSSOCKET180A1513N01S01Note 1 EXC-180A/SV1Note 1 100-pin plastic LQFP (14 × 14 mm) IE-703079-MC-EM1 100-pin plastic QFP (14 × 20 mm) IE-703079-MC-EM1 + SWEX100SD/GF-N17DNote 1 NQPACK100RBNote 1 YQPACK100RBNote 1 HQPACK100RBNote 1 YQSOCKET100RBNNote 1 YQGUIDENote 1 V850/SC1, V850/SC2, V850/SC3 144-pin plastic LQFP (20 × 20 mm) IE-703089-MC-EM1 V853 100-pin plastic LQFP (14 × 14 mm) IE-703003-MC-EM1 V850/SF1 Notes 1. Tokyo Eletech Corp. 2. Naito Densei Machida Mfg. Co., Ltd. Remarks 1. The following parts are required as common products. • PC interface board : IE-70000-PCI-IF-A or IE-70000-CD-IF-A • Power supply : IE-70000-MC-PS-B 2. For details, refer to the V800 SeriesTM Development Environment Pamphlet (U10782E). 54 Pamphlet U15412EJ1V0PF Development Tools (3/3) V850E/MA1, V850E/MA2, V850E/IA1, V850E/IA2 hardware tool configuration example In-circuit emulator (main unit) Emulation board Power supply unit Conversion adapter/conversion socket To common interface block V850E/MS1, V850E/MS2 hardware tool configuration example In-circuit emulator (main unit) Emulation board Power supply unit Conversion adapter/conversion socket To common interface block V850/SA1, V850/SB1, V850/SB2, V850/SV1, V850/SF1, V850/SC1 ,V850/SC2, V850/SC3, V853 hardware tool configuration example In-circuit emulator (main unit) Emulation board Power supply unit Conversion adapter/conversion socket To common interface block Pamphlet U15412EJ1V0PF 55 Development Environment (1/2) Development environment using in-circuit emulator Real-time OS Debugger Compiler In-circuit emulator Analyzer Task debugger Integrated development environment NEC NEC ID850 NEC RX850 RX850 Pro AZ850 CA850 Note NEC GHS RD850 Note RD850 Pro Note ID850 CCV850 CCV850E Note The RD850, RD850 Pro, and AZ850 can be used with ID850, MULTI, PARTNER, and WATCHPOINT. V850 IE Series NEC CATS Remarks 1. ATI CATS ZIPC850 GHS ATI Metrowerks Nucleus Plus MULTI CodeWarrior® TM Midas Lab GAIO GHS RTE-V85x-IE Series AZ850 Red Hat Mispo NORTi®3 GAIO AZ850 KMC G-OS KMC : Kyoto Microcomputer Corporation Metrowerks : Metrowerks Corporation Midas Lab : Midas Lab Co., Ltd. Mispo : MiSPO, Inc. Red Hat : Red Hat Corporation Sophia Systems : Sophia Systems Co., Ltd. YDC : Yokogawa Digital Computer Corporation 2. For details, refer to the V800 Series Development Environment Pamphlet (U10782E). PARTNER GNU Sophia Systems Sophia Systems exeGCC WATCHPOINT TM GAIO UniSTAC Series AZ850 XCC-V XASS-V YDC advice Series YDC : Accelerated Technology, Inc. : Communication And Technology Systems, Inc. : Gaio Technology Co., Ltd. : Green Hills SoftwareTM, Inc. micro VIEW-G GAIO XDDI-V Development environment using ROM emulator and evaluation board Real-time OS Compiler Task debugger Debugger ROM emulator Evaluation board Low-cost evaluation board (limited functions) Evaluation board Analyzer NEC CA850 NEC Cosmo RX850 RX850 Pro CEB-V85x Series KMC RD850 Note RD850 Pro Note exeGCC PARTNER Note The RD850, RD850 Pro, and AZ850 can be used with ID850, MULTI, and PARTNER. AZ850 Note GHS CCV850 CCV850E ATI Nucleus Plus KMC GHS Metrowerks Code Warrior PARTNER-ET II Midas Lab MULTI RTE-V85x-PC/CB Series AZ850 Midoriya EMUSE Mispo Lightwell Red Hat NORTi3 GNU TornadoTM GNU MDX700 WRS 56 CrossWind Pamphlet U15412EJ1V0PF Remarks 1. ATI : Accelerated Technology, Inc. Cosmo : Cosmo Co., Ltd. GAIO : Gaio Technology Co., Ltd. GHS : Green Hills SoftwareTM, Inc. KMC : Kyoto Microcomputer Corporation Lightwell : Lightwell Co., Ltd. Metrowerks : Metrowerks Corporation Midas Lab : Midas Lab Co., Ltd. Midoriya : Midoriya Electric Co., Ltd. Mispo : MiSPO, Inc. Red Hat : Red Hat Corporation WRS : Wind River Systems, Inc. 2. For details, refer to the V800 Series Development Environment Pamphlet (U10782E). Development Environment (2/2) Development environment using simulator Real-time OS Compiler Debugger Task debugger Simulator Co-simulation tool Analyzer Integrated development environment NEC NEC RX850 RX850 Pro NEC CA850 SM850 AZ850 RD850 RD850 Pro NEC SM850 ZIPC850 CATS GHS MULTI YOKOGAWA Virtual ICE ® Synopsys Synopsys Eaglei® GHS ATI CCV850 Nucleus Plus Mispo NORTi3 GAIO XCCV/XASS-V GAIO XDEB GAIO G-OS Pamphlet U15412EJ1V0PF Remarks 1. ATI CATS : Accelerated Technology, Inc. : Communication And Technology Systems, Inc. GAIO : Gaio Technology Co., Ltd. GHS : Green Hills Software, Inc. Mispo : MiSPO, Inc. YOKOGAWA : Yokogawa Electric Corporation Synopsys : Nihon Synopsys, Inc. 2. For details, refer to the V800 Series Development Environment Pamphlet (U10782E). 57 Software Package (SP850) C Compiler (CA850) Product configuration Features The SP850 software package consists of the following software development •Complies with ANSI-C, a C language standard. tools. •Supports libraries for embedded systems •C compiler (CA850) •Compact code size and faster execution speed can be realized through •Project Manager (PM) powerful optimization •Integrated debugger (ID850) •Utilities useful for embedded systems (ROMization processor, etc.) •System simulator (SM850) •Description of embedded systems in C language (specification of memory •System performance analyzer (AZ850) allocation and I/O register access) is possible. •Device file (DF703xxx) System Simulator (SM850) Project Manager (PM) Features Features •Same operability as debugger •Project management (management of target chip, source, and environment •Target-less evaluation prior to target completion possible during debugging is possible.) •In addition to the operation of the CPU itself, target system operation •Automation of series of operations consisting of edit, build, and debug including on-chip peripheral unit and interrupt servicing can also be •Integration of Help function simulated. •Included with C compiler package •Pseudo-target system construction and I/O operation are possible through external parts. •Data generated by 0/1 logic and timing charts can be input to the program being simulated. •Larger number of events than in-circuit emulator •Execution speed estimates can be done on the host machine to accurately simulate pipeline operationNote. •Construction by user target system users is possible through user open interface. •A peripheral I/O register status can be specified and when this status occurs, the system can be made to output an interrupt at the desired timing or transfer data to memory (peripheral I/O register event & action function). Note The pipeline mode is supported by the V853. Target devices V853, V850/SA1, V850/SB1, V850/SB2, V850/SF1, V850E/MS1, V850E/ MA1, V850E/IA1 58 Pamphlet U15412EJ1V0PF Integrated Debugger (ID850) In-Circuit Emulator Features Features •Supports object files •Realization of high transparency with emulator functions concentrated in •Debugging at source level a dedicated chip •Debugging using target resources •V850 core IE enabling easy product expansion •Real-time execution on target •V850E1 core IE enabling high-speed operation •Event setting according to complex software operation •Connectable to various personal computers •Online help function Real-Time OSs (RX850, RX850 Pro) Features Task Debuggers (RD850, RD850 Pro) Features •Comply with global standard (µITRON 3.0 specifications). •Display detailed information on OS resources such as tasks. •Support power management function. •Issue system calls. •Enable embedding of required functions only (selection of system calls to •Display source of referenced tasks. •Included with real-time OS (RX850, RX850 Pro) be used). •Support sophisticated task development through task debugger (RD). •Support application operation analysis through system performance analyzer (AZ) •Inherit attributes of real-time OS of 16-bit V Series and 78K Series System Performance Analyzer (AZ850) Features TCP/IP Software Library (RX-NET) for V850E Products Product configuration •Detection of bugs through system timing errors •TCP/IP protocol stack •Detection of bugs due to simultaneous operation of complex tasks •Applications •Detection/analysis of real-time system execution performance •LAN control driver •Operation linked to various debuggers Features •RFC-compliant •Multiprotocol stack •Support of numerous socket interfaces/libraries •Support of applications as option products •Simplified device driver •Support of NEC real-time OS (RX850 Pro) Target devices V850E products Pamphlet U15412EJ1V0PF 59 OSEK/VDX Specification-Compliant OS (RX-OSEK850) Features • Kernel OSEK/VDX OS Ver. 2.0 specification-compliant Supports four conformance classes (BCC1, BCC2, ECC1, ECC2). • Communications OSEK/VDX COM Ver. 2.1 Rev. 1 specification-compliant Supports three conformance classes (CCC1, CCC2, CCC3). • Configurator Configurator simplifying construction of system information (OIL850) OIL Ver. 2.0-compliant format supported for configuration files • Task debugger (RD-OSEK850) Task debugger effective for debugging applications that use the RX-OSEK850 included as standard. RISC Microcontroller Reference Platform (SolutionGearTM) Features • General-purpose evaluation boards available as development platforms for RISC microcontroller software • Supported CPU: V850E/MA1 • Global and PC-compatible interfaces provided, including PCI, ISA, PCMCIA, E-IDE, EthernetTM, Serial, Parallel, PS/2, and USB • Used combined with CPU-independent motherboard (usable in common with VR Series) and any of various CPU boards • Real-time OS, middleware, and sample drivers are included. • Development environment of Green Hills Software (evaluation version) provided • MULTI/PARTNER remote monitor version can be used. • Reference design information provided It's actually testable H/W S/W This board usable for comparison purposes It does not work properly. Is this a hardware or software problem? This is my first device so I want sample circuits Can such a performance be realized? Device selection I want to measure the CPU performance Circuit diagrams are provided Board design/development I want to use OS /middleware Debugging Software design/development Time I want to start software development ahead of board development The OS and middleware are bundled. Since various peripheral devices are mounted,debugging can be started from device-independent parts. The OS and middleware look difficult to start up and use A user-own coding part matching this board is provided as sample. At such times, RISC microcontroller reference platform is ideal Cooperation with Third Parties By strengthening its cooperation with third-party companies and creating tool groups that combine the best characteristics of NEC tools and third-party tools, NEC provides a development environment that answers diversified user needs. 60 Pamphlet U15412EJ1V0PF Information V850 Series Website Introduction For information about the V850 Series and the V850 Series development environment, check out the NEC Microcomputer website. http://www.ic.nec.co.jp/micro/index_e.html Product Information Product information on the V850 Series, development environments for the V850 Series, and the middleware reference platform can be referenced. Downloading Development Tools Development tools for the V850 Series can be downloaded. Upgrade information is provided. Downloading Documents Documents about the V850 Series and V850 Series development environment can be downloaded. FAQ Answer to questions about the V850 Series development environment are introduced. Pamphlet U15412EJ1V0PF 61 IEBus, EEPROM, Solution Gear, V Series, V800 Series, V850 Series, V830 Family, V853, V850/SA1, V850/SB1, V850/SB2, V850/SC1, V850/SC2, V850/SC3, V850/SF1, V850/SV1, V850E/IA1, V850E/IA2, V850E/MA1, V850E/MA2, V850E/MS1, V850E/MS2, V850ES/SA2, V850ES/SA3, and VR Series are trademarks of NEC Corporation. TrueSpeech is a trademark of DSP Group, Inc. JAVA and all trademarks and logos related to JAVA are trademarks of Sun Microsystems, Inc. Windows and Windows NT are either registered trademarks or trademarks of Microsoft Corporation in the United States and/or other countries. NORTi is a trademark of MiSPO, Inc. CodeWarrior is a trademark of Metrowerks Corporation. Green Hills Software and MULTI are trademarks of Green Hills Software, Inc. WATCHPOINT is a trademark of Sophia Systems Co., Ltd. Tornado is a trademark of Wind River Systems, Inc. Virtual ICE is a trademark of Yokogawa Electric Corporation. Synopsys Eaglei is a trademark of Synopsys, Inc. TRON stands for The Realtime Operating system Nucleus. ITRON is an abbreviation of Industrial TRON. Ethernet is a trademark of Xerox Corporation. Caution: The I2C bus interface circuit is incorporated in the µPD703014AY, 703014BY, 703015AY, 703015BY, 70F3015BY, 703017AY, 70F3017AY, 703030AY, 703031AY, 703032AY, 70F3032AY, 703033AY, 70F3033AY, 703034AY, 703035AY, 70F3035AY, 703036AY, 703037AY, 70F3037AY, 703038Y, 70F3038Y, 703039Y, 703040Y, 70F3040Y, 703041Y, 703068Y, 703069Y, 703078Y, 703079Y, 70F3079Y, 703088Y, 703089Y, 70F3089Y, 703201Y, 70F3201Y, 703204Y, 70F3204Y. Those who use the I2 C bus interface can be granted the license below by giving prior notification before ordering the custom code. Purchase of NEC I2 C components conveys a license under the Philips I2C Patent Rights to use these components in an I2 C system, provided that the system conforms to the I2C Standard Specification as defined by Philips. 62 Pamphlet U15412EJ1V0PF The export of these products from Japan is regulated by the Japanese government. The export of some or all of these products may be prohibited without governmental license. To export or re-export some or all of these products from a country other than Japan may also be prohibited without a license from that country. Please call an NEC sales representative. • The information in this document is current as of August, 2001. The information is subject to change without notice. For actual design-in, refer to the latest publications of NEC's data sheets or data books, etc., for the most up-to-date specifications of NEC semiconductor products. Not all products and/or types are available in every country. Please check with an NEC sales representative for availability and additional information. • No part of this document may be copied or reproduced in any form or by any means without prior written consent of NEC. NEC assumes no responsibility for any errors that may appear in this document. • NEC does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of NEC semiconductor products listed in this document or any other liability arising from the use of such products. No license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC or others. • Descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. The incorporation of these circuits, software and information in the design of customer's equipment shall be done under the full responsibility of customer. NEC assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. • While NEC endeavours to enhance the quality, reliability and safety of NEC semiconductor products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To minimize risks of damage to property or injury (including death) to persons arising from defects in NEC semiconductor products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment, and anti-failure features. • NEC semiconductor products are classified into the following three quality grades: "Standard", "Special" and "Specific". The "Specific" quality grade applies only to semiconductor products developed based on a customer-designated "quality assurance program" for a specific application. The recommended applications of a semiconductor product depend on its quality grade, as indicated below. Customers must check the quality grade of each semiconductor product before using it in a particular application. "Standard": Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots "Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) "Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc. The quality grade of NEC semiconductor products is "Standard" unless otherwise expressly specified in NEC's data sheets or data books, etc. If customers wish to use NEC semiconductor products in applications not intended by NEC, they must contact an NEC sales representative in advance to determine NEC's willingness to support a given application. (Note) (1) "NEC" as used in this statement means NEC Corporation and also includes its majority-owned subsidiaries. (2) "NEC semiconductor products" means any semiconductor product developed or manufactured by or for NEC (as defined above). M8E 00. 4 Pamphlet U15412EJ1V0PF 63 For further information, please contact: NEC Corporation NEC Building 7-1, Shiba 5-chome, Minato-ku Tokyo 108-8001, Japan Tel: 03-3454-1111 http://www.ic.nec.co.jp/ [North & South America] [Europe] [Asia & Oceania] NEC Electronics Inc. 2880 Scott Blvd. Santa Clara, CA 95050-2554, U.S.A. Tel: 408-588-6000 800-366-9782 Fax: 408-588-6130 800-729-9288 http://www.necel.com/ NEC Electronics (Europe) GmbH Oberrather Str. 4 40472 Düsseldorf, Germany Tel: 0211-6503-01 Fax: 0211-6503-327 http://www.ee.nec.de/ NEC Electronics Hong Kong Limited 12/F., Cityplaza 4, 12 Taikoo Wan Road, Hong Kong Tel: 2886-9318 Fax: 2886-9022/9044 Branch The Netherlands Boschdijk 187a 5612 HB Eindhoven, The Netherlands Tel: 040-2445845 Fax: 040-2444580 NEC do Brasil S.A. Electron Devices Division Rodovia Presidente Dutra, Km 214 07210-902-Guarulhos-SP Brasil Tel: 011-6462-6810 Fax: 011-6462-6829 Branch Sweden P.O. Box 134 18322 Taeby, Sweden Tel: 08-6380820 Fax: 08-6380388 NEC Electronics (UK) Limited Cygnus House, Sunrise Parkway, Linford Wood, Milton Keynes, MK14 6NP, U.K. Tel: 01908-691-133 Fax: 01908-670-290 Seoul Branch 10F, ILSONG Bldg., 157-37, Samsung-Dong, Kangnam-Ku Seoul, the Republic of Korea Tel: 02-528-0303 Fax: 02-528-4411 NEC Electronics Taiwan Ltd. 7F, No. 363 Fu Shing North Road Taipei, Taiwan, R. O. C. Tel: 02-2719-2377 Fax: 02-2719-5951 NEC Electronics Singapore Pte. Ltd. 238A Thomson Road #12-01/10 Novena Square Singapore 307684 Tel: 253-8311 Fax: 250-3583 NEC Electronics (France) S.A. 9, rue Paul Dautier-B.P. 52 78142 Velizy-Villacoublay Cédex France Tel: 01-3067-5800 Fax: 01-3067-5899 Madrid Office Juan Esplandiu, 15 28007 Madrid, Spain Tel: 091-504-2787 Fax: 091-504-2860 NEC Electronics Italiana s.r.l. Via Fabio Filzi, 25/A, 20124 Milano, Italy Tel: 02-667541 Fax: 02-66754299 G02. 1 Document No. U15412EJ1V0PF00 (1st edition) Date Published February 2002 N CP(K) © NEC Corporation 2002 Printed in Japan