ILX585K 10680 pixel × 6line pixel× CCD Linear Sensor (Color) Description The ILX585K is reduction type CCD linear sensor developed for color image scanner.This sensor reads A4-size documents at a density of 1200DPI and 2400DPI 24 pin DIP (Plastic) Sensor Line Features staggered 2400DPI Number of effective pixels: 64080 pixels(10680pixels×6) Pixel size: 4μm×4μm(4μm pitch) Distance between main line : 48μ m(12 lines) Distance between main line and Sub line: 8μ m(2 lines) Common Features Single-sided readout Ultra low lag Single 12V power supply Maximum data rate: 10MHz/Color Input clock pulse: CMOS 5V drive Number of output: 3(R,G,B) Package: 24pin Plastic-DIP(400mil) Absolute Maximum Ratings Supply voltage VDD 15 V Operating temperature − 10to＋ 55 Configuration(Top 1 1 2 1 φ3 View) 24 1 1 1 φ2 1 Pin ℃ φRS 3 φ1 23 φL1 22 φ4 NC 7 B (main) VOUT-G 6 B (sub) 20 GND G (main) 5 G (sub) 21 φCLP VOUT-R R (main) 4 R (sub) VDD 19 VOUT-B 18 NC 9 16 SW VDD 10 NC 11 φROG-B 12 10680 10680 10680 17 φ1 φROG-G 10680 10680 8 10680 φROG-R 15 GND 14 φ2 13 GND Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. 1 02.07.30 Block Diagram φ1 φ2 VDD φ1 VDD φ2 Sub line Overflow Drain Readout gate CCD register Readout gate CCD register Main line (Red) Sub line (Red) D75' D75 CCD register Readout gate D106 D106' Driver φROG-G Driver φROG-R D106 φROG-B D106' D75' Sub line (Green) S5340' Main line (Green) S5340 Readout gate D75 CCD register Driver D106' D106 D75' S5340 S5340' D74 D74' S1 S1' S2 S2' S3 S3' Readout gate S5340' S5340 D40' D40 D40' VOUT-R Sub line (Blue) CCD register D74 D74' S1 S1' S2 S2' S3 S3' D40 2 VOUT-G Main line (Blue) D74 D74' S1 S1' S2 S2' S3 S3' D40 D40' VOUT-B D75 Readout gate CCD register SW φCLP φRS φ3 φ4 φL1 SW GND (1200/2400DPI Sensor) ILX585K 02.07.30 ILX585K Pin Description Pin No. Symbol Description Pin No. Symbol Description 1 φ2 Clock pulse input 13 GND GND 2 φ3 Clock pulse input 14 φ2 Clock pulse input 3 φRS Clock pulse input 15 GND GND 4 VDD 12V power supply 16 SW Switch(1200/2400dpi) 5 VOUT-R Signal output (red) 17 φ1 Clock pulse input 6 VOUT-G Signal output (green) 18 NC NC 7 NC NC 19 VOUT-B Signal output (blue) 8 φROG-R Clock pulse input 20 GND GND 9 φROG-G Clock pulse input 21 φCLP Clock pulse input 10 VDD 12V power supply 22 φ4 Clock pulse input 11 NC NC 23 φL1 Clock pulse input 12 φROG-B Clock pulse input 24 φ1 Clock pulse input Recommended Supply Voltage Item VDD Min. Typ. Max. Unit 11.4 12 12.6 V Clock Characteristics Item Symbol Min. Typ. Max. Unit Input capacity of φ1, φ2 Cφ1, Cφ 2 ─ 3000 ─ pF Input capacity of φRS CφRS ─ 10 ─ pF Input capacity of φROG CφROG ─ 10 ─ pF Input capacity of φ3, φ4, φL1 CφL1 , Cφ3, Cφ4 ─ 20 ─ pF 3 02.07.30 ILX585K Clock Frequency 2400 DPI Staggered Item Symbol Min. Typ. Max. Unit φ1, φ2, φL1 fφ1, fφ2 , fφL1 ─ 1 5*1 MHz φ3, φ4, φRS fφ3, fφ4 , fφRS ─ 1 10 MHz *1 The frequency is 10MHz during the dump mode. Input Clock Pulse Voltage Condition Item φ1, φ2, φRS, φROG, φL1, φ3, φ4 pulse voltage Min. Typ. Max. Unit High level 4.75 5.0 5.25 V Low level 0 0 0.1 V SW mode SW HI (5V) 1200 DPI LO (0V) 2400 DPI 4 02.07.30 ILX585K Electrooptical Characteristics (Note 1, 2) (Ta=25c‚VDD=12V, ffRS=1MHz, Input clock=5Vp-p, Light source=3200K, IR cut filter CM500S (t = 1.0mm) Symbol Item Min. Typ. Max. Unit Remarks V/(lx･s) Note 2 Red RR 1.4 2.0 2.6 Green RG 1.8 2.6 3.4 Blue RB 1.4 2.0 2.6 Sensitivity nonuniformity PRNU ─ 4 20 % Note 3 Saturation output voltage VSAT 2.0 2.5 ─ V Note 4 Red SER ─ 1.25 ─ Green SEG ─ 0.96 ─ Blue SEB ─ 1.25 ─ Saturation electrons Nelec ─ 30 ─ Ke- at 2.0V Dark voltage average VDRK ─ 0.1 1.6 mV Note 6 Dark signal nonuniformity DSNU ─ 0.5 3.2 mV Supply current IVDD ─ 30 60 mA Total transfer efficiency TTE 92 98 ─ % Output impedance ZO ─ 360 ─ Ω Sensitivity Saturation exposure lx･s Note 5 Note 7 5 02.07.30 ILX585K Item Symbol Min. Typ. Max. Unit Remarks Offset level VOS ─ 5.8 ─ V Note 8 Random Noise NDσ ─ 0.6 ─ mV Note 9 Notes: 1. In accordance with the given electrooptical characteristics, the black level is defined as the average value of D40, D41 to D73. 2. For the sensitivity test light is applied with a uniform intensity of illumination. 3. PRNU us defubed as indicated below. Ray iincidence conditions are the same as for Note 2. Vout=500mV(typ.) PRNU = (VMAX - VMIN)/2 VAVE x 100 [%] 6 02.07.30 ILX585K 4. Use below the minimum value of the saturation output voltage. 5. Saturation exposure is defined as follows. SE = VSAT R Where R indicates RR, RG, RB and SE indicates SER, SEG, SEB. 6. Optical signal accumulated time τ int stands at 4ms. 7. Supply current means the total current of this device. 8. Vos is defined as indicated bellow. VOUT indicates VOUT-R, VOUT-G, and VOUT-B. VOUT VOS GND 9. Random noise is defined on the output waveform with the external clamp and is defined as the standard deviation (sigma) of the output level difference between two adjacent effective pixels under no illumination (i.e.dark conditions) calculated by the following procedure. Output waveform (effective pixels under dark condition) CCD output CCD output 200ns 200ns pixel (n) pixel (n +1) ∆V a) Two adjacent pixels (pixel n and n + 1) in one reading are fixed as measurement points. b) Each of the output level at video output periods is averaged over 200ns period to get V (n) and V (n + 1). c) V (n + 1) is subtracted from V (n) to get ƒ¢V. ƒ¢V = Vn •|V (n + 1) d) The standard deviation of ƒ¢V is calculated after procedure b) and c) are repeated 30 times (30 readings). ∆V = 1 30 30 i=1 Σ | ∆Vi | σ= 1 30 30 2 Σ (| ∆Vi |•|∆V) i=1 e) Procedure b), c) and d) are repeated 10 times to get sigma value. f) 10 sigma values are averaged. σ= 1 10 10 Σ σj i=1 g) σ value calculated using the above procedure is observed √2 times larger than that measured relative to the ground level. So we specify random noise as follows. NDσ= 1 √2 σ 7 02.07.30 Clock Timing Chart 1 2400 DPI Staggered(pixel clamp mode) SW mode SW L φROG 5 φ1, φL1 φ2 2 1 0 5 0 5 φ3 4 3 2 5 1 0 0 φ4 5 0 8 φRS 5 0 D106' D102' D102 D101' D80' D80 D79' D79 D78' D75' D75 S10680' S10680 S10679' S1' S1 D74' D74 D40' D40 D39' D39 D2 0 D1' VOUT 5 D1 φCLP Optical black (34 pixels × 2) Dummy signal (74 pixels × 2) Effective pixels signal (10680 pixels × 2) Dummy signal (32 pixels × 2) 1-line output period (10786pixels × 2) ILX585K 02.07.30 Note)The transfer pulses (φ1, φ2) must have more than 10786 cycles. The transfer pulses (φ3, φ4) must have more than 21572 cycles. VOUT indicates VOUT-R, VOUT-G, VOUT-B. Clock Timing Chart 2 2400 DPI Staggered(line clamp mode) SW mode SW L φROG 5 φ1, φL1 φ2 2 1 0 5 0 5 φ3 4 3 2 5 1 0 0 φ4 5 0 9 φRS 5 0 φCLP 5 D106' D102' D102 D101' D80' D80 D79' D79 D78' D75' D75 S10680' S10680 S10679' S1' S1 D74' D74 D40 D20' VOUT D20 0 Optical black (34 pixels × 2) Dummy signal (74 pixels × 2) Effective pixels signal (10680 pixels × 2) Dummy signal (32 pixels × 2) 1-line output period (10786pixels × 2) Note)The transfer pulses (φ1, φ2) must have more than 10786 cycles. The transfer pulses (φ3, φ4) must have more than 21572 cycles. VOUT indicates VOUT-R, VOUT-G, VOUT-B. ILX585K 02.07.30 Clock Timing Chart 3 1200 DPI Linear(pixel clamp mode) SW mode SW H 5 φ1,φL1,φ3 φ2,φ4 φRS 4 2 3 0 1 φROG 5 0 5 0 5 0 D117 D116 D87 D86 S10680 S10679 S2 S1 D85 D84 D83 D52 D51 D50 D3 D2 0 D1 10 5 φCLP VOUT Optical black (34 pixels) Dummy signal (85 pixels) Effective pixel signal (10680 pixels) Dummy signal (32 pixels) 1-line output period (10797 pixels) Note) The transfer pulses (φ1, φ2) must have more than 10797 cycles. VOUT indicates VOUT-R, VOUT-G, VOUT-B. ILX585K 02.07.30 Clock Timing Chart 4 1200 DPI Linear(line clamp mode) SW mode SW H 5 3 4 2 0 1 φROG φ1,φL1,φ3 5 0 φ2,φ4 φRS 5 0 5 0 VOUT D117 D116 D87 D86 S10680 S2 S1 D85 D84 D83 D51 D50 D26 D25 0 S10679 5 D1 11 φCLP Optical black (34pixels) Dummy signal (85 pixels) Effective pixel signal (10680 pixels) Dummy signal (32 pixels) 1-line output period (10797 pixels) Note) The transfer pulses (φ1, φ2) must have more than 10797 cycles. VOUT indicates VOUT-R, VOUT-G, VOUT-B. ILX585K 02.07.30 ILX585K Clock Timing Chart5 2400 DPI Staggered t4 t5 fROG t2 t6 f1 t7 t1 t3 f2 t7 t6 ClockTiming Chart 6 (2400 DPI pixel clamp mode) t7, t9 t6 t8 f1,fL1 t6, t8 t7 t9 f2 t15 t11 t10 f3 f4 t10 t11 t12 t13 t17 t16 fRS t14 fCLP t18 t19 VOUT t20 Sub line Main line 12 02.07.30 ILX585K ClockTiming Chart 7 (1200 DPI pixel clamp mode) t6,t8,t10 t7,t9,t11 f1,fL1,f3 f2,f4 t7,t9,t11 t6,t8,t10 t17 t10 t12 t16 fRS t13 t14 fCLP t18 t20 t19 Main line Main line VOUT ClockTiming Chart 8 (2400 DPI line clamp mode) t7, t9 t6 t8 φ1,φL1 t6, t8 t7 t9 φ2 t15 t11 t10 φ3 φ4 t10 t11 t12 t13 t17 t16 φRS t14 φCLP t18 t19 VOUT t20 Main line Sub line 13 02.07.30 ILX585K ClockTiming Chart 9 (1200 DPI line clamp mode) t7,t9,t11 t6,t8,t10 f1,fL1,f3 f2,f4 t6,t8,t10 t7,t9,t11 t17 t12 t16 fRS fCLP t13 t14 t18 t19 t20 Main line Main line VOUT 14 02.07.30 ILX585K Clock Pulse Recommended Timing Item Symbol Min. Typ. Max. Unit φROG, φ1 pulse timing t1 50 100 ─ ns φROG pulse high level period t2 5 10 ─ μs φROG, φ1 pulse timing t3 3 5 ─ μs φROG pulse rise time t4 0 5 10 ns φROG pulse fall time t5 0 5 10 ns φ1 pulse rise time/φ2 pulse fall time t6 0 50 80 ns φ1 pulse fall time/φ2 pulse rise time t7 0 50 80 ns φL1 pulse rise time/φ2 pulse fall time t8 0 10 30 ns φL1 pulse fall time/φ2 pulse rise time t9 0 10 30 ns φ3 pulse rise time/φ4 pulse fall time t10 0 10 30 ns φ3 pulse fall time/φ4 pulse rise time t11 0 10 30 ns φRS pulse rise time t12 0 10 30 ns φRS pulse fall time t13 0 30 ns φRS pulse high level period t14 30 10 100∗1 ─ ns φL1,φ2-φ3 pulse timing t15 0 10 ─ ns ─ ns φRS,φCLP pulse timing φCLP,φL1,φ3 pulse timing φCLP pulse high level period Signal output delay time 250∗1 t16 0 t17 60 250∗1 ─ ns t18 20 100 ─ ns t19 ─ 40 ─ ns t20 ─ 20 ─ ns ∗1 These timing is the recommended condition under fφRS = 1MHz. 15 02.07.30 ILX585K Application Circuit∗ <IC1> φL1 φ1 φCLP φ4 IC2 VOUT-B IC1 2Ω 100Ω 100Ω 100Ω φ2 φ1 Tr1 SW IC1 IC1 3kΩ 2Ω 2Ω 2Ω 12V 0.1µF 47µF/ 16V 24 23 22 21 φ1 φL 1 φ4 φCLP φ2 φ3 φRS VDD 1 2 3 20 19 GND VOUT -B 18 17 NC φ1 4 100Ω 2Ω IC2 IC1 φ2 5 6 14 13 SW φ2 GND 7 8 9 100Ω 10 100Ω 100Ω VOUT -R Tr1 IC2 φRS NC φROG -B 11 12 100Ω IC2 100Ω 3kΩ φROG -R φROG -G VOUT -G φ3 15 GND VOUT -R VOUT -G NC φROG -R φROG -G VDD 3kΩ 2Ω 16 φROG -B Tr1 IC1: 74AC04 × 3pcs IC2: 74HC04 Tr1: 2SA1175 ∗ Data rate fφRS = 1MHz Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same. 16 02.07.30 ILX585K Example of Representative Characteristics <2400DPI> Spectral sensitivity characteristics (Standard characteristics) 1 R 0.9 G 0.8 B 0.7 Relative sensitivity 0.6 0.5 0.4 0.3 0.2 0.1 0 400 500 600 700 800 900 1000 Wavelength [nm] 17 02.07.30 ILX585K Notes of Handling 1) Static charge prevention CCD image sensors are easily damaged by static discharge. Before handling be sure to take the following protective measures. a) Either handle bare handed or use non chargeable gloves, clothes or material. Also use conductive shoes. b) When handling directly use an earth band. c) Install a conductive mat on the floor or working table to prevent the generation of static electricity. d) Ionized air is recommended for discharge when handling CCD image sensor. e) For the shipment of mounted substrates, use boxes treated for prevention of static charges. 2) Notes on Handling CCD Packages The following points should be observed when handling and installing packages. a) Remain within the following limits when applying static load to the package: (1) Compressive strength: 39N/surface (Do not apply load more than 0.7mm inside the outer perimeter of the glass portion.) (2) Shearing strength: 29N/surface (3) Tensile strength: 29N/surface (4) Torsional strength: 0.9Nm Cover glass Plastic portion 29N 39N 0.9Nm 29N Adhesive Ceramic portion (1) (2) (3) (4) b) In addition, if a load is applied to the entire surface by a hard component, bending stress may be generated and the package may fracture, etc., depending on the flatness of the ceramic portion. Therefore, for installation, either use an elastic load, such as a spring plate, or an adhesive. c) Be aware that any of the following can cause the package to crack or dust to be generated. (1) Applying repetitive bending stress to the external leads. (2) Applying heat to the external leads for an extended period of time with soldering iron. (3) Rapid cooling or heating. (4) Prying the plastic portion and ceramic portion away at a support point of the adhesive layer. (5) Applying the metal a crash or a rub against the plastic portion. Note that the preceding notes should also be observed when removing a component from a board after it has already been soldered. d) The notch of the plastic portion is used for directional index, and that can not be used for reference of fixing. In addition, the cover glass and seal resin may overlap with the notch or ceramic may overlap with the notch of the plastic portion. 3) Soldering a) Make sure the package temperature does not exceed 80°C. b) Solder dipping in a mounting furnace causes damage to the glass and other defects. Use a 30W soldering iron with a ground wire and solder each pin in less then 2 seconds. For repairs and remount, cool sufficiently. c) To dismount an imaging device, do not use a solder suction equipment. When using an electric desoldering tool, ground the controller. For the control system, use a zero cross type. 18 02.07.30 ILX585K 4) Dust and dirt protection a) Operate in clean environments. b) Do not either touch glass plates by hand or have any object come in contact with glass surfaces. Should dirt stick to a glass surface, blow it off with an air blower. (For dirt stuck through static electricity ionized air is recommended.) c) Clean with a cotton bud and ethyl alcohol if the glass surface is grease stained. Be careful not to scratch the glass. d) Keep in a case to protect from dust and dirt. To prevent dew condensation, preheat or precool when moving to a room with great temperature differences. 5) Exposure to high temperatures or humidity will affect the characteristics. Accordingly avoid storage or usage in such conditions. 6) CCD image sensors are precise optical equipment that should not be subject to mechanical shocks. 19 02.07.30 42.72 (4µm X 10680Pixels) 0.25 12 3.58 20 4.0 ± 0.5 1 ( 8.59 ) 1.778 10.16 No.1 Pixel (Green) of 2400 DPI 5.334 0.46 0.3 4.28 ± 0.5 H 13 Unit: mm 5.0 ± 0.3 24 10.0 ± 0.3 7.830 ± 0.3 V 0˚ to 9˚ 55.7 ± 0.3 Package Outline 24 pin DIP (400mil) M 1. The height from the bottom to the sensor surface is 2.38 ± 0.3mm. PACKAGE STRUCTURE PACKAGE MATERIAL Plastic, Ceramic LEAD TREATMENT GOLD PLATING LEAD MATERIAL 42 ALLOY PACKAGE MASS 5.43g DRAWING NUMBER LS-B41(E) 2. The thickness of the cover glass is 0.7mm, and the refractive index is 1.5. ILX585K 02.07.30