Features • • • • • • • • • Full Compliance with USB Spec Rev 1.1 Four Downstream Ports Full-speed and Low-speed Data Transfers Bus-powered Controller Bus-powered or Self-powered Hub Operation Port Overcurrent Monitoring Port Power Switching 5V Operation with On-chip 3.3V Regulator 24-pin SOIC Description The AT43301 is a 5-port USB hub chip supporting one upstream and four downstream ports. The AT43301 connects to an upstream hub or host/root hub via Port0, while the other ports connect to external downstream USB devices. The hub re-transmits the USB differential signal between Port0 and Ports[1:4] in both directions. The AT43301 is designed for very low-cost bus-powered or self-powered hub applications and comes in a 24-pin SOIC package. The AT43301 supports the 12 Mb/s full speed as well as 1.5 Mb/s slow speed USB transactions. To reduce EMI, the AT43301’s oscillator frequency is 6 MHz even though some internal circuitry operates at 48 MHz. Low-cost USB Hub Controller AT43301 Pin Configurations Top View VCC VSS CEXT1 OSC1 OSC2 LFT STAT PWR OVC LPSTAT TEST SELF/BUS 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 NC DP4 DM4 DP3 DM3 DP2 DM2 DP1 DM1 DP0 DM0 VSS Rev. 1137C–08/99 1 The AT43301 consists of a Serial Interface Engine, a Hub Repeater, and a Hub Controller. The Serial Interface Engine’s tasks are: • Manage the USB communication protocol • USB signaling detection/generation • Clock/data separation, data encoding/decoding, CRC generation/checking • Data serialization/deserialization The Hub Repeater is responsible for: • Providing upstream connectivity between the selected device and the host • Managing connectivity setup and tear-down • Handling bus fault detection and recovery • Detecting connect/disconnect on each port The Hub Controller is responsible for: • Hub enumeration • Providing configuration information to the Host • Providing status of each port to the Host • Controlling each port per host command • Managing port power supply Block Diagram Figure 1. UPSTREAM PORT PORT 0 HUB CONTROLLER ENDPOINT 0 ENDPOINT 1 SERIAL INTERFACE ENGINE PORT 1 HUB REPEATER PORT 2 PORT 3 PORT 4 TO DOWNSTREAM DEVICES Note: 2 This document assumes that the reader is familiar with the Universal Serial Bus and therefore only describes the unique features of the AT43301 chip. For detailed information about the USB and its operation, the reader should refer to the Universal Serial Bus Specification Version 1.1, September 23, 1998. AT43301 AT43301 Pin Assignment Type: I = IS = O = OD = B = V = Table 2. Pin Assignment in Alphabetical Order Input Input, Schmitt Trigger Output Output, open drain Bi-directional Power supply, ground Table 1. Pin Assignment in Numerical Order Pin# Signal Type 3 CEXT1 O 14 DM0 B 16 DM1 B 18 DM2 B 20 DM3 B 22 DM4 B Pin# Signal Type 15 DP0 B 1 VCC V 17 DP1 B 2 VSS V 19 DP2 B 3 CEXT1 O 21 DP3 B 4 OSC1 I 23 DP4 B 5 OSC2 O 6 LFT I 6 LFT I 10 LPSTAT IS 7 STAT OD 24 NC - 8 PWR OD 4 OSC1 I 9 OVC IS 5 OSC2 O 10 LPSTAT IS 9 OVC IS 11 TEST I 8 PWR OD 12 SELF/BUS IS 12 SELF/BUS IS 13 VSS V 7 STAT OD 14 DM0 B 11 TEST I 15 DP0 B 1 VCC V 16 DM1 B 2 VSS V 17 DP1 B 13 VSS V 18 DM2 B 19 DP2 B 20 DM3 B 21 DP3 B 22 DM4 B 23 DP4 B 24 NC - 3 Table 3. Signal Descriptions CEXT1 O External Capacitor. For proper operation of the on-chip regulator, a 0.27 µF capacitor must be connected to CEXT1. DP0 B Upstream Plus USB I/O. This pin should be connected to the CEXT1 pin through an external 1.5 kΩ pull-up resistor. DP0 and DM0 form the differential signal pin pairs connected to the USB host controller or an upstream Hub. DM0 B Upstream Minus USB I/O. DP[1:4] B Port Plus USB I/O. This pin should be connected to VSS through an external 15 kΩ resistor. DP[1:4] and DM[1:4] are the differential signal pin pairs to connect downstream USB devices. DM[1:4] B Port Minus USB I/O. This pin should be connected to VSS through an external 15 kΩ resistor. LFT I PLL Filter. For proper operation of the PLL, this pin should be connected through a 2.2 nF capacitor in parallel with a 100Ω resistor in series with a 10 nF capacitor to ground (VSS). LPSTAT I Local Power Status. Schmitt Trigger input pin that is used in the self-powered mode to indicate the condition of the local power supply. This pin should be connected to the local power supply through a 100 kΩ resistor. OSC1 I Oscillator Input. Input to the inverting 6 MHz oscillator amplifier. OSC2 O Oscillator Output. Output of the inverting oscillator amplifier. OVC I Port Overcurrent. This is the Schmitt Trigger input signal used to indicate to the AT43301 that there is a power supply problem with the ports. If OVC is asserted, the AT43301 will de-assert PWR and report the status to the USB Host. PWR O Power Switch. This is an output signal to enable or disable the external port power switch for the port power supply. PWR is de-asserted when an overcurrent is detected at OVC. SELF/BUS I Power Mode. Schmitt Trigger input pin to set power mode of hub. If high, the AT43301 works in the self-powered mode. If low, the bus-powered mode. STAT O Status. Output pin which is asserted by the AT43301 whenever it is enumerated. STAT is de-asserted when the hub enters the suspend state. An LED in series with a resistor can be connected to this pin to provide visual feedback to the user. TEST I Test. This pin has an internal pull up and should be left unconnected in the normal operating mode. VCC V 5V Power Supply from the USB. VSS V Ground. NC - No Connect. This pin should be left unconnected. Functional Description Summary USB Ports The Atmel AT43301 USB hub controller chip contains various features that makes it the ideal solution for very lowcost USB hubs. These features are: on-chip regulator, lowfrequency oscillator, bus or self-powered operation, ganged port power switching and global overcurrent protection. Such a hub can be a stand-alone hub used with portable computers to allow convenient connectivity to standard desktop peripheral devices. Alternatively, the hub can be added to an existing non-USB peripheral such a keyboard. The AT43301 provides 4 downstream USB ports and can operate in a self-powered or bus-powered mode. The AT43301’s upstream port, Port0, is a full speed port. A 1.5 kΩ pull-up resistor to the 3.3V regulator output, CEXT, is required for proper operation. The downstream ports support both full-speed as well as low-speed devices. 15 kΩ pull down resistors are required at their inputs. Full speed signal requirements demand controlled rise/fall times and impedance matching of the USB ports. To meet these requirements, 22 Ω resistors must be inserted in series between the USB data pins and the USB connectors. 4 AT43301 AT43301 Hub Repeater The Hub Repeater is responsible for port connectivity setup and teardown. It also supports exception handling such as bus fault detection and recovery, and connect/disconnect detection. Port0 is the root port and is connected to the root hub or an upstream hub. When a packet is received at Port0, the AT43301 propagates it to all the enabled downstream ports. Conversely, a packet from a downstream port is transmitted from Port0. The AT43301 supports downstream port data signaling at both 1.5 Mb/s and 12 Mb/s. Devices attached to the downstream ports are determined to be either full speed or low speed depending which data line (DP or DM) is pulled high. If a port is enumerated as low speed, its output buffers operate at a slew rate of 75-300 ns, and the AT43301 will not propagate any traffic to that port unless it is prefaced with a preamble PID. Low speed data following the preamble PID is propagated to both low- and full-speed devices. The AT43301 will enable low-speed drivers within four fullspeed bit times of the last bit of a preamble PID, and will disable them at the end of an EOP. The upstream traffic from all ports is propagated by Port0 using the full speed 420ns slew rate drivers. All the AT43301 ports independently drive and monitor their DP and DM pins so that they are able to detect and generate the ‘J’, ‘K’, and SE0 bus signaling states. Each hub port has single-ended and differential receivers on its DP and DM lines. The ports’ I/O buffers comply with the voltage levels and drive requirements as specified in the USB Specifications Rev 1.0. The Hub Repeater implements a frame timer which is timed by the 12 MHz USB clock and gets reset every time an SOF token is received from the host. Serial Interface Engine The Serial Interface Engine handles the USB communication protocol. It performs the USB clock/data separation, the NRZI data encoding/decoding, bit stuffing, CRC generation and checking, USB packet ID decoding and generation, and data serialization and de-serialization. The onchip phase locked loop generates the high frequency clock for the clock/data separation circuit. Power Management A hub is allowed to draw up to 500 mA of power from the host or upstream hub. The AT43301’s itself and its external circuitry typically consume about 24 mA. Therefore, in the bus-powered mode, 100 mA is available for each of the hub’s downstream devices. In the self-powered mode, an external power supply is required which must be capable of supplying 500 mA per port. The power supplied to the ports is monitored and controlled by the AT43301. The AT43301 reports overcurrent on a global basis. The overcurrent signal, which needs to be detected by an external device, is read through the OVC pin. A logic low at OVC is interpreted as an overcurrent condition. This could be caused by an overload, or a short circuit, and causes the AT43301 to set the Over-Current Indicator bit of the Hub Status Field, wHubStatus, as well as the Over-Current Indicator Change bit of the Hub Change Field, wHubChange. At the same time, power to the ports is switched off by deasserting PWR. An external device is needed to perform the actual switching of the ports’ power under control of the AT43301. The signal to control the external switch is the PWR pin which is an open drain signal and requires an external pull-up resistor. 47 k Ω is a typical value for this resistor. Any type of suitable switch or device is acceptable. However, the switch should have a low-voltage drop across it even when the port absorbs full power. In its simplest form, this switch can be a high side MOSFET switch. The advantage of using a MOSFET switch is its very low-voltage drop. The power control pin, PWR, is asserted only when a SetPortFeature[PORT-POWER] request is received from the host. PWR is de-asserted under the following conditions: 1. Power up 2. Reset and initialization 3. Overcurrent condition 4. Requested by the host though a ClearPortFeature[PORT_POWER] for ALL the ports Self-powered Mode In the self-powered mode, power to the downstream ports must be supplied by an external power supply. This power supply must be capable of supplying 500 mA per port or 2A total with good voltage tolerance and regulation. At full hub operating power, that is all downstream ports drawing 500 mA each, the minimum voltage at the downstream port connector must be 4.75V. The USB specification requires that the voltage drop at the power switch and board traces be no more than 100 mV. A good conservative maximum drop at the power switch itself should be no more than 75 mV. Careful design and selection of the power switch and PC board layout is required to meet the specifications. When using a MOSFET switch, its resistance must be 40 mΩ or less under worst case conditions. A suitable MOSFET switch for an AT43301 based hub is an integrated highside MOSFET switch such as the Micrel MIC2505. 5 Bus-Powered Mode In the bus-powered mode all the power for the hub itself as well as the downstream ports is supplied by the root hub or upstream hub through the USB. Only 100 mA is available for each of the hub’s downstream devices and therefore only low-power devices are supported. The power switch works exactly like the self-powered mode, except that the allowable switch resistance is higher: 140 mΩ or less under the worst case condition. An example of a suitable high side switch for a bus-powered hub is the Micrel MIC2525. The diagrams of Figure 2 and Figure 3 show examples of the power supply and power management scheme in the self-powered mode and bus-powered mode using an integrated switch with built-in overcurrent protection. Figure 2. Bus-powered Hub BUS_POWER GND U1 GND VCC AT43301 PWR OVC PORT_POWER GND PORT_POWER GND U2 CTL FLG IN OUT SWITCH PORT_POWER GND TO DOWNSTREAM DEVICES PORT_POWER GND Figure 3. Self-powered Hub BUS_POWER GND U1 GND VCC AT43301 PWR PS5 POWER SUPPLY OVC PORT_POWER GND U2 CTL 5V OUT GND PORT_POWER GND FLG IN OUT SWITCH PORT_POWER GND PORT_POWER GND 6 AT43301 TO DOWNSTREAM DEVICES AT43301 Hub Controller The Hub Controller of the AT43301 provides the mechanism for the host to enumerate the hub and the AT43301 to provide the host with its configuration information. It also provides a mechanism for the host to monitor and control the downstream ports. The Hub Controller supports two endpoints, Endpoint0 and Endpoint1. The Hub Controller maintains a status register, Controller Status Register, which reflects the AT43301’s current settings. At power up, all bits in this register will be set to 0’s. Table 4. Controller Status Register Bit Function 0 Value Hub configuration status 1 Description 0 1 Set to 0 or 1 by a Set_Configuration Request Hub is not currently configured Hub is currently configured 0 1 Set to 0 or 1 by ClearFeature or SetFeature request. Default value is 0. Hub is currently not enabled to request remote wakeup Hub is currently enabled to request remote wakeup Hub remote wakeup status 2 Endpoint0 STALL status 0 1 Endpoint0 is not stalled Endpoint0 is stalled 3 Endpoint1 STALL status 0 1 Endpoint1 is not stalled Endpoint1 is stalled Endpoint 0 Endpoint 0 is the AT43301’s default endpoint used for enumeration of the hub and exchange of configuration information and requests between the host and the AT43301. Endpoint 0 supports control transfers. The Hub Controller supports the following descriptors through Endpoint 0: Device Descriptor, Configuration Descriptor, Interface Descriptor, Endpoint Descriptor, and Hub Descriptor. These descriptors are described in detail elsewhere in this document. Standard USB Device Requests and class-specific Hub Requests are also supported through Endpoint 0. There is no endpoint descriptor for Endpoint0. Endpoint 1 Endpoint1 is used by the Hub Controller to send status change information to the host. This endpoint supports interrupt transfers. The Hub Controller samples the changes at the end of every frame at time marker EOF2 in preparation for a potential data transfer in the subsequent frame. The sampled information is stored in a byte wide register, the Status Change Register, using a bitmap scheme. Each bit in the Status Change Register corresponds to one port as shown below: Table 5. Status Change Register Bit Function Value Meaning 0 Hub status change 0 1 No change in status Change in status detected 1 Port1 status change 0 1 No change in status Change in status detected 2 Port2 status change 0 1 No change in status Change in status detected 3 Port3 status change 0 1 No change in status Change in status detected 4 Port4 status change 0 1 No change in status Change in status detected 5-7 Reserved 000 Default values 7 An IN Token packet from the host to Endpoint 1 indicates a request for port change status. If the hub has not detected any change on its ports, or any changes in itself, then all bits in this register will be 0 and the Hub Controller will return a NAK to requests on Endpoint1. If any of bits 0-4 is 1, the Hub Controller will transfer the whole byte. The Hub Controller will continue to report a status change when polled until that particular change has been removed by a ClearPortFeature request from the Host. No status change will be reported by Endpoint 1 until the AT43301 has been enumerated and configured by the host. Figure 4. External Oscillator and PLL Circuit U1 OSC1 Y1 6.000 MHz OSC2 R1 100 C1 10nF AT43301 LFT C2 2nF Oscillator and Phase-Locked-Loop All the clock signals required to run the AT43301 are derived from an on-chip oscillator. To reduce EMI and power dissipation in the system, the AT43301 is designed to operate with a 6 MHz crystal. An on-chip PLL generates the high frequency for the clock/data separator of the Serial Interface Engine. In the suspended state, the oscillator circuitry is turned off. To assure quick startup, a crystal with a high Q, or low ESR, should be used. To meet the USB hub frequency accuracy and stability requirements for hubs, the crystal should have an accuracy and stability of better than 100 ppm. Even though the oscillator circuit would work with a ceramic resonator, its use is not recommended because a resonator would not have the frequency accuracy and stability. A 6 MHz series resonance quartz crystal with a load capacitance of approximately 10 pF is recommended. The oscillator is a special low-power design and in most cases no external capacitors and resistors are necessary. If the crystal used cannot tolerate the drive levels of the oscillator, a series resistor between OSC2 and the crystal pin is recommended. Status Pin The status pin, STAT, is provided to allow feedback to the user. If an LED and a series resistor is connected between STAT and VCC, the LED will light when the hub is enumerated. During an overcurrent condition, the LED will blink. It will continue to blink until the host turns off the power to the ports or until the hub is re-enumerated. 8 AT43301 The clock can also be externally sourced. In this case, connect the clock source to the OSC1 pin, while leaving OSC2 pin floating. The switching level at the OSC1 pin can be as low as 0.47V (see “Electrical Specification” on page 9) and a CMOS device is required to drive this pin to maintain good noise margins at the low switching level. For proper operation of the PLL, an external RC filter consisting of a series RC network of 100Ω and 10 nF in parallel with a 2 nF capacitor must be connected from the LFT pin to VSS. Power Supply The AT43301 is powered from the USB bus, but has an internal voltage regulator to supply the 3.3V operating power to its circuitry. For proper operation, an external high quality, low ESR, 0.27 µF, or larger, capacitor should be connected to the output of the regulator, CEXT1 and ground. The CEXT1 pin can also be used to supply the voltage to the 1.5 kΩ pull up resistor at Port 0’s DP pin. To provide the best operating condition for the AT43301, careful consideration of the power supply connections are recommended. Use short, low impedance connections to all power supply lines: VCC and VSS. Use sufficient decoupling capacitance to reduce noise: 0.1 µF of high quality ceramic capacitor soldered as close as possible to the VCC and VSS package pins are recommended. AT43301 Electrical Specification Absolute Maximum Ratings* Symbol Parameter VCC5 5V Power Supply VI DC Input Voltage VO Max Unit 5.5 V -0.3V VCEXT + 0.3 4.6 max V DC Output Voltage -0.3 VCEXT + 0.3 4.6 max V TO Operating Temperature -40 +125 °C TS Storage Temperature -65 +150 °C *NOTICE: Condition Min Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. DC Characteristics The values shown in this table are valid for TA = 0°C to 85°C, VCC = 4.4V to 5.25V, unless otherwise noted. Table 6. Power Supply Symbol Parameter VCC 5V Power Supply ICC ICCS Condition Min Max Unit 4.4 5.25 V 5V Supply Current 24 mA Suspended Device Current 150 µA Max Unit Table 7. USB Signals: DPx, DMx Symbol Parameter Condition VIH Input Level High (driven) 2.0 VIHZ Input Level High (floating) 2.7 VIL Input Level Low VDI Differential Input Sensitivity VCM Differential Common Mode Range VOL1 Static Output Low RL of 1.5 kΩ to 3.6V VOH1 Static Output High RL of 15 kΩ to GND VCRS Output Signal Crossover CIN Input Capacitance DPx and DMx Min V 3.6 V 0.8 V 0.2 0.8 V 2.5 V 0.3 V 2.8 3.6 V 1.3 2.0 V 20 pF 9 Table 8. PWR, STAT, OVC Symbol Parameter Condition VOL2 Output Low Level, PWR, STAT COUT Output Capacitance VIL3 Input Low Level VIH3 Input High Level COUT Output Capacitance 1 MHz VOH2 Output High Level, PWR IOH = 4 mA Min Max Unit IOL = 4 mA 0.5 V 1 MHz 10 pF 0.3VCEXT V 0.7VCEXT V 10 pF VCEXT - 0.5 V Table 9. Oscillator Signals: OSC1, OSC2 Symbol Parameter VLH Min Max Unit OSC1 Switching Level 0.47 1.20 V VHL OSC1 Switching Level 0.67 1.44 V CX1 Input Capacitance, OSC1 17 pF CX2 Output Capacitance, OSC2 17 pF C12 OSC1/2 Capacitance 1 pF tsu Start-up Time 6 MHz, fundamental 2 ms DL Drive Level VCC = 3.3V, 6 MHz crystal, 100Ω equiv series resistor 150 µW Note: Condition OSC2 must not be used to drive other circuitry. AC Characteristics Table 10. DPx, DMx Driver Characteristics, Full Speed Operation Symbol Parameter Condition Min Max Unit tR Rise Time CL = 50 pF 4 20 ns tF Fall Time CL = 50 pF 4 20 ns tRFM tR/tF Matching 90 110 % ZDRV Driver Output Resistance(1) 28 44 Ω Note: 10 Steady state drive 1. With external 22Ω series resistor. AT43301 AT43301 Table 11. DPx, DMx Source Timings, Full Speed Operation Symbol Parameter Condition tDRATE Full Speed Data Rate(1) Average bit rate (1) tFRAME Frame Interval tRFI Min Max Unit 11.97 12.03 Mb/s 0.9995 1.0005 ms (1) No clock adjustment 42.0 ns (1) With clock adjustment 126.0 ns Consecutive Frame Interval Jitter tRFIADJ Consecutive Frame Interval Jitter tDJ1 tDJ2 Source Diff Driver Jitter To Next Transition For Paired Transitions -3.5 -4.0 3.5 4.0 ns ns tFDEOP Source Jitter for Differential Transition to SEO Transitions -2.0 5.0 ns tJR1 tJR2 Recvr Data Jitter Tolerance To Next Transition For Paired Transitions -18.5 -9.0 18.5 9.0 ns ns tFEOPT Source SEO interval of EOP 160.0 175.0 ns tFEOPR Receiver SEO interval of EOP 82.0 Width of SEO interval during differential transition tFST Note: ns 14.0 ns 1. With 6.000 MHz, 100 ppm crystal. Table 12. DPx, DMx Driver Characteristics, Low-speed Operation Symbol Parameter Condition Min Max Unit tR Rise time CL = 200 - 600 pF 75.0 300.0 ns tF Fall time CL = 200 - 600 pF 75.0 300.0 ns tRFM tR/tF matching 80.0 125.0 % Min Max Unit 44.0 ns Table 13. DPx, DMx Hub Timings, High-Speed Operation Symbol Parameter Condition tHDD2 Hub Differential Data Delay without Cable tHDJ1 tHDJ2 Hub Diff Driver Jitter To Next Transition For Paired Transitions -3.0 -1.0 3.0 1.0 ns ns tFSOP Data Bit Width Distortion after SOP -5.0 5.0 ns tFEOPD Hub EOP Delay Relative to tHDD 0 15.0 ns tFHESK Hub EOP Output Width Skew -15.0 15.0 ns 11 Table 14. DPx, DMx Hub Timings, Low-speed Operation Symbol Parameter Condition tLHDD Hub Differential Data Delay tLHDJ1 tLHDJ2 tLUHJ1 tLUHJ2 Downstr Hub Diff Driver Jitter To Next Transition, downst For Paired Transitions, downst To Next Transition, upstr For Paired Transitions, upstr tSOP Data Bit Width Distortion after SOP tLEOPD Hub EOP Delay Relative to tHDD tLHESK Hub EOP Output Width Skew Min Max Unit 300.0 ns -45.0 -15.0 -45.0 -45.0 45.0 15.0 45.0 45.0 ns ns ns ns -60.0 60.0 ns 0 200.0 ns -300.0 300.0 ns Table 15. Hub Event Timings Symbol Parameter tDCNN tDDIS Condition Min Max Unit Time to Detect a Downstream Port Connect Event Awake Hub Suspended Hub 2.5 2.5 2000.0 12000.0 µs µs Time to Detect a Disconnect Event on Downstream Port Awake Hub Suspended Hub 2.5 2.5 2.5 10000.0 µs µs 100.0 µs 10.0 20.0 ms tURSM Time from Detecting Downstream Resume to Rebroadcast tDRST Duration of Driving Reset to a Downstream Device tURLK Time to Detect a Long K from Upstream 2.5 100.0 µs tURLSEO Time to Detect a Long SEO from Upstream 2.5 10000.0 µs tURPSEO Duration of repeating SEO Upstream 23 FS bit time 12 AT43301 Only for a SetPortFeature (PORT_RESET) request AT43301 Timing Waveforms Figure 5. Data Signal Rise and Fall Time RISE TIME VCRS 10% FALL TIME 90% 90% 10% DIFFERENTIAL DATA LINES tF tR Figure 6. Full-Speed Load RS TxD+ CL RS TxD- CL CL = 50pF Figure 7. Low-speed Downstream Port Load TxD+ RS CL TxD- 3.6V 1.5KΩ RS CL CL = 200pF to 600pF Figure 8. Differential Data Jitter TPERIOD DIFFERENTIAL DATA LINES CROSSOVER POINTS CONSECUTIVE TRANSITIONS N*TPERIOD+TXJR1 PAIRED TRANSITIONS N*TPERIOD+TXJR2 13 Figure 9. Differential-to-EOP Transition Skew and EOP Width CROSSOVER POINT EXTENDED TPERIOD DIFFERENTIAL DATA LINES DIFF. DATA-toSE0 SKEW N*TPERIOD+TDEOP SOURCE EOP WIDTH: TFEOPT TLEOPT RECEIVER EOP WIDTH: TFEOPR, TLEOPR Figure 10. Receiver Jitter Tolerance TPERIOD DIFFERENTIAL DATA LINES TJR TJR1 TJR2 CONSECUTIVE TRANSITIONS N*TPERIOD+TJR1 CONSECUTIVE TRANSITIONS N*TPERIOD+TJR1 Figure 11. Hub Differential Delay, Differential Jitter, and SOP Distortion UPSTREAM END OF CABLE DOWNSTREAM PORT 50% POINT OF INITIAL SWING VSS DIFFERENTIAL DATA LINES VSS CROSSOVER POINT VSS HUB DELAY DOWNSTREAM THDD1 CROSSOVER POINT UPSTREAM PORT VSS A. DOWNSTREAM HUB DELAY WITH CABLE DOWNSTREAM PORT HUB DELAY UPSTREAM THDD2 B. UPSTREAM HUB DELAY WITHOUT CABLE CROSSOVER POINT VSS UPSTREAM PORT OR END OF CABLE VSS HUB DELAY UPSTREAM THDD1, THDD2 CROSSOVER POINT C. UPSTREAM HUB DELAY WITH OR WITHOUT CABLE 14 AT43301 CROSSOVER POINT AT43301 Hub Differential Jitter: THDJ1 = THDDX(J) - THDDX(K) or THDDX(K) - THDDX(J) Consecutive Transitions THDJ2 = THDDX(J) - THDDX(J) or THDDX(K) - THDDX(K) Paired Transitions Bit After Sop Width Distortion (Same as Data Jitter for Sop and Next J Transition): TSOP = THDDX(NEXTJ) - THDDX(SOP) Low-speed timings are determined in the same way for: TLHDD, TLDHJ1, TLDJH2, TLUHJ1, TLUJH2, and TLSOP Figure 12. Hub EOP Delay and EOP Skew 50% POINT OF INITIAL SWING UPSTREAM END OF CABLE VSS DOWNSTREAM PORT CROSSOVER POINT EXTENDED UPSTREAM PORT VSS TEOP- TEOP+ CROSSOVER POINT EXTENDED DOWNSTREAM PORT VSS TEOP- TEOP+ CROSSOVER POINT EXTENDED VSS A. DOWNSTREAM EOP DELAY WITH CABLE B. DOWNSTREAM EOP DELAY WITHOUT CABLE CROSSOVER POINT EXTENDED DOWNSTREAM PORT VSS UPSTREAM PORT OR END OF CABLE VSS TEOP- TEOP+ CROSSOVER POINT EXTENDED C. UPSTREAM EOP DELAY WITH OR WITHOUT CABLE EOP Delay: TEOPD = TEOP - THDDX EOP Skew: THESK = TEOP + -TEOPLow-speed timings are determined in the same way for: TLEOPD and TLHESK 15 R16 47K OVC D1 22 R1 22 14 15 R2 11 24 L11 FB 6 R4 100 C3 2.2nF 9 OVC 8 PWR STAT DM2 DP2 LPSTAT AT43301 DM0 DP0 DM4 DP4 TEST NC LFT DM3 DP3 16 17 18 19 20 21 22 23 R7 22 DM1 DP1 R9 22 R8 22 DM2 DP2 R11 22 R10 22 DM3 DP3 R13 22 R12 22 DM4 DP4 R14 22 RP1 15K Y1 C2 0.01UF 6.000MHz 9 10 11 12 13 14 15 16 1 2 3 4 DM1 DP1 8 7 6 5 4 3 2 1 10 CEXT VSS VSS 5 6 USB-B R3 1.5K VCC 2 13 C1 0.27UF FB JP1 3 OSC1 L1 C12 4.7UF 4 1 + 7 U1 12 LED SELF/BUS 1N4148 OSC2 D2 5 R5 470 Schematic Diagrams AT43301 PWR The following pages shows schematic diagrams of an AT43301 based bus-powered hub and self-powered hub. VBUS Figure 13. Bus-powered Hub 16 VBUS Figure 14. Bus-powered Hub VBUS U2 PWR OVC 1 2 IN NC OUT OUT EN NC FLG GND MIC2525-2 L2 FB 8 6 DM1 DP1 4 L3 FB L12 FB 3 C8 + + DM2 C9 DP2 47uF L13 FB C4 47uF 1 2 3 4 5 6 7 8 9 10 7 5 JP2 USB-2A 11 12 VBUS 0.1uF C5 0.1uF DM3 DP3 L5 FB C10 47uF + + DM4 C11 DP4 47uF L14 FB L15 FB C7 0.1uF 5 6 7 8 JP3 USB-2A AT43301 C6 0.1uF 1 2 3 4 9 10 FB 11 12 L4 17 Figure 15. Self-powered Hub 18 VBUS VLOCAL AT43301 R5 Q1 2N4401 470 R16 47K D1 LED PWR R35 470 1 2 3 4 22 14 15 R2 11 24 L11 FB 6 R4 100 C3 2.2nF 9 OVC 8 PWR DM0 DP0 DM4 DP4 TEST NC LFT DM3 DP3 18 19 20 21 22 23 R7 22 DM1 DP1 R9 22 R8 22 DM2 DP2 R11 22 R10 22 DM3 DP3 R13 22 R12 22 DM4 DP4 R14 22 RP1 15K Y1 C2 0.01UF 6.000MHz 9 10 11 12 13 14 15 16 6 USB-B AT43301 22 R1 OSC2 JP1 DM2 DP2 LPSTAT 5 5 1.5K 16 17 8 7 6 5 4 3 2 1 10 DM1 DP1 VSS VSS R3 OSC1 0.27UF 4 L1 FB R6 47K CEXT 2 13 C1 VCC SELF/BUS 3 STAT 1 7 U1 12 OVR Figure 16. Self-powered Hub VLOCAL 0.1 UF C14 4.7 UF J1 C15 1 2 + CON2 U2 PWR OVC 1 2 OUT OUT CTL GATE FLG GND L2 FB 6 8 DM1 DP1 4 L3 FB L12 FB 3 MIC2505-2 C8 + + DM2 C9 DP2 100 UF L13 FB C4 100 UF 1 2 3 4 5 6 7 8 9 10 IN IN JP2 USB-2A 11 12 7 5 0.1uF C5 0.1uF DM3 DP3 C10 100 UF + + DM4 C11 DP4 100 UF L14 FB L15 FB C6 0.1uF C7 0.1uF 5 6 7 8 JP3 USB-2A AT43301 L5 FB 1 2 3 4 9 10 FB 11 12 L4 19 Packaging Information 24S, 24-lead, 0.300" Wide Plastic Gull Wing Small Outline Package (SOIC) Dimensions in Inches and (Millimeters) .020(.508) .013(.330) .299(7.60) .420(10.7) .291(7.39) .393(9.98) PIN 1 ID .050(1.27) BSC .616(15.6) .598(15.2) .105(2.67) .092(2.34) .012(.305) .003(.076) .013(.330) .009(.229) 0 REF 8 20 .050(1.27) .015(.381) AT43301 Atmel Headquarters Atmel Operations Corporate Headquarters Atmel Colorado Springs 2325 Orchard Parkway San Jose, CA 95131 TEL (408) 441-0311 FAX (408) 487-2600 Europe 1150 E. Cheyenne Mtn. Blvd. Colorado Springs, CO 80906 TEL (719) 576-3300 FAX (719) 540-1759 Atmel Rousset Atmel U.K., Ltd. Coliseum Business Centre Riverside Way Camberley, Surrey GU15 3YL England TEL (44) 1276-686-677 FAX (44) 1276-686-697 Zone Industrielle 13106 Rousset Cedex France TEL (33) 4-4253-6000 FAX (33) 4-4253-6001 Asia Atmel Asia, Ltd. Room 1219 Chinachem Golden Plaza 77 Mody Road Tsimhatsui East Kowloon Hong Kong TEL (852) 2721-9778 FAX (852) 2722-1369 Japan Atmel Japan K.K. 9F, Tonetsu Shinkawa Bldg. 1-24-8 Shinkawa Chuo-ku, Tokyo 104-0033 Japan TEL (81) 3-3523-3551 FAX (81) 3-3523-7581 Fax-on-Demand North America: 1-(800) 292-8635 International: 1-(408) 441-0732 e-mail [email protected] Web Site http://www.atmel.com BBS 1-(408) 436-4309 © Atmel Corporation 1999. Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company’s standard warranty which is detailed in Atmel’s Terms and Conditions located on the Company’s web site. The Company assumes no responsibility for any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does not make any commitment to update the information contained herein. No licenses to patents or other intellectual property of Atmel are granted by the Company in connection with the sale of Atmel products, expressly or by implication. Atmel’s products are not authorized for use as critical components in life support devices or systems. Marks bearing ® and/or ™ are registered trademarks and trademarks of Atmel Corporation. Terms and product names in this document may be trademarks of others. Printed on recycled paper. 1137C–08/99/xM