ETC HFCT

SC Duplex Single Mode Transceiver
Technical Data
HFCT-5103B/D
Features
Description
• SC Duplex Single Mode
Transceiver
• Single +5 V Power Supply
• Multisourced 1 x 9 Pin
Configuration
• Aqueous Washable Plastic
Package
• Interchangeable with
HFBR-5103 and other LED
multisourced 1 x 9
Transceivers
• Unconditionally eye safe
laser IEC 825/CDRH Class 1
Compliant
• Conforms to ANSI X3.1841993 Standard for FDDI
SMF-PMD Category 1
Optoelectronic performance
• Compatible with the
HFCT-5205
The HFCT-5103 transceiver is a
high performance, cost effective
module for serial optical data
communications applications
specified for a signal rate of
125 MBd. It is designed to provide
an FDDI SMF-PMDl link for FDDI
or Fast Ethernet applications and
is also compatible with
ATM/SONET/SDH transceivers.
This module is designed for single
mode fiber and operates at a
nominal wavelength of 1300 nm.
It incorporates Agilent’s high
performance, reliable, long
wavelength optical devices and
proven circuit technology to give
long life and consistent service.
Applications
• FDDI SMF-PMDl
• Fast Ethernet
• ATM Compatible
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The transmitter section uses an
advanced Fabry Perot laser with
full IEC 825 and CDRH Class I eye
safety.
The receiver section uses an
MOVPE grown planar PIN
photodetector for low dark
current and excellent
responsivity.
A pseudo-ECL logic interface
simplifies interface to external
circuitry.
2
Connection Diagram
RECEIVER SIGNAL GROUND
RECEIVER DATA OUT
RECEIVER DATA OUT BAR
SIGNAL DETECT
RECEIVER POWER SUPPLY
TRANSMITTER POWER SUPPLY
TRANSMITTER DATA IN BAR
TRANSMITTER DATA IN
TRANSMITTER SIGNAL GROUND
o
o
o
o
o
o
o
o
o
1
2
3
4
5
6
7
8
9
N/C
Top View
N/C
Pin Descriptions:
Pin 1 Receiver Signal Ground
VEE:
Directly connect this pin to the
receiver ground plane.
Pin 2 Receiver Data Out RD+:
See recommended circuit
schematic, Figure 4.
Pin 3 Receiver Data Out Bar
RD-:
See recommended circuit
schematic, Figure 4.
Pin 4 Signal Detect SD:
Normal optical input levels to the
receiver result in a logic “1”
output.
Low optical input levels to the
receiver result in a fault condition
indicated by a logic “0” output.
Pin 5 Receiver Power Supply
VCC:
Provide +5 V dc via the
recommended transmitter power
supply filter circuit. Locate the
power supply filter circuit as
close as possible to the VCC pin.
Pin 6 Transmitter Power
Supply VCC :
Provide +5 V dc via the
recommended transmitter power
supply filter circuit. Locate the
power supply filter circuit as
close as possible to the VCC pin.
Pin 7 Transmitter Data In Bar
TD-:
See recommended circuit
schematic, Figure 4.
This Signal Detect output can be
used to drive a PECL input on an
upstream circuit, such as Signal
Detect input or Loss of Signal-bar.
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Pin 8 Transmitter Data In
TD+:
See recommended circuit
schematic, Figure 4.
Pin 9 Transmitter Signal
Ground VEE:
Directly connect this pin to the
transmitter ground plane.
Mounting Studs
The mounting studs are provided
for mechanical attachment to the
circuit board. They are embedded
in the nonconductive plastic
housing and are not tied to the
transceiver internal circuit and
should be soldered into
plated-through holes on the
printed circuit board.
3
Functional Description
Receiver Section
These components will also
reduce the sensitivity of the
receiver as the signal bit rate is
increased above 155 MBd.
Design
The receiver section contains an
InGaAs/InP photo detector and a
preamplifier within the receptacle,
coupled to a postamp/decision
circuit on a separate circuit board.
Noise Immunity
The receiver includes internal
circuit components to filter
power supply noise. Under some
EMI and power supply noise
conditions, external power supply
filtering may be necessary. If
receiver sensitivity is degraded by
power supply noise, the filter
network illustrated in Figure 2
may be employed to improve
performance. The values of the
filter components are general
recommendations and may be
changed to suit a particular
system environment. Shielded
inductors are recommended.
The postamplifier is ac coupled to
the preamplifier as illustrated in
Figure 1. The coupling capacitor
is large enough to pass the FDDI
test pattern at 125 MBd and the
SONET/SDH test pattern at
155 MBd without significant
distortion or performance penalty
If a lower signal rate, or a code
which has significantly more low
frequency content is used,
sensitivity, jitter and pulse
distortion could be degraded.
Figure 1 also shows a filter
network which limits the
bandwidth of the preamp output
signal. The filter is designed to
bandlimit the preamp output
noise and thus improve the
receiver sensitivity.
Terminating the Outputs
The PECL Data outputs of the
receiver may be terminated with
the standard Thevenin-equivalent
50 ohm to Vcc -2 V termination.
Other standard PECL terminating
techniques may be used.
The Signal Detect Circuit
The Signal Detect circuit works
by sensing the peak level of the
received signal and comparing
this level to a reference.
DATA OUT
FILTER
TRANSIMPEDANCE
PREAMPLIFIER
The two outputs of the receiver
should be terminated with
identical load circuits to avoid
unnecessary large ac current in
Vcc. If the outputs are loaded
identically, the ac current is
largely nulled. The Signal Detect
output of the receiver is PECL
logic and must be loaded if it is to
be used. The Signal Detect circuit
is much slower that the data path,
so the ac noise generated by an
asymmetrical load is negligible.
Power consumption may be
reduced by using a higher than
normal load impedance for the
Signal Detect output.
Transmission line effects are not
generally a problem as the
switching rate is slow.
PECL
OUTPUT
BUFFER
LIMITING
AMPLIFIER
DATA OUT
RECEIVER
RECEPTACLE
GND
SIGNAL
DETECT
CIRCUIT
Figure 1 - Receiver Block Diagram
3.3 µH
VCC
10 µF
100 nF
FILTERED VCC to DATA LINK
100 nF
Figure 2 - pÿFilter Network for Noise Filtering
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PECL
OUTPUT
BUFFER
SD
4
Functional Description
Transmitter Section
Design
The transmitter section, Figure 3,
uses a buried heterostructure
Fabry-Perot laser as its optical
source. The packaging of this
laser is designed for repeatable
coupling into single mode fiber
while maintaining compliancy
with IEC 825 Class 1 and CDRH
Class I eye safety requirements.
The optical output is controlled
by a custom IC which detects the
laser output via the monitor
photo-diode. This IC provides
both dc and ac current drive to
the laser to ensure correct
modulation, eye diagram and
extinction ratio over temperature,
supply voltage and life.
PCB mounting
The HFCT-5103 has two
solderable mounting studs. These
studs are not electrically
connected. The transceiver is
designed for common production
processes. It may be wave
soldered and aqueous washed
providing the process plug is in
place.
Each process plug can only be
used once during processing,
although with subsequent use, it
can be used as a dust cover.
LASER
DATA
LASER
MODULATOR
DATA
PECL
INPUT
LASER BIAS
DRIVER
LASER BIAS
CONTROL
Figure 3 - Simplified Transmitter Schematic
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PHOTODIODE
(rear facet monitor)
5
NO INTERNAL
CONNECTION
NO INTERNAL
CONNECTION
TOP VIEW
Rx
VEE
1
RD
2
Rx
VCC
5
SD
4
RD
3
Tx
VCC
6
C1 C7
Tx
VEE
9
TD
8
TD
7
C8 C2
VCC
L1
VCC
TERMINATE
AT THE
DEVICE
INPUTS
R6
R5
L2
C3
R7
R2
Vcc FILTER
AT Vcc PINS
TRANSCEIVER
C6
R8
R10
RD
RD
SD
R3
C4
VCC
R1
C5
R4
TERMINATION AT
TRANSCEIVER
INPUTS
TD
TD
NOTES:
THE SPLIT-LOAD TERMINATIONS FOR ECL SIGNALS
NEED TO BE LOCATED AT THE INPUT OF DEVICES
RECEIVING THOSE ECL SIGNALS. RECOMMEND
4-LAYER PRINTED CIRCUIT BOARD WITH 50 W
MICROSTRIP SIGNAL PATHS BE USED.
R1 = R4 = R6 = R8 = 130 W
R2 = R3 = R5 = R7 = 82 W
R10 = 10 kW
C1 = C2 = C5 = C6 = 0.1 µF.
C3 = C4 = 10 µF.
C7 = C8 = 100 nF.
L1 = L2 = 3.3 µH COIL OR FERRITE INDUCTOR.
Figure 4 - Recommended Circuit Schematic
Regulatory Compliance
Feature
Test Method
Electrostatic Discharge MIL-STD-883C
(ESD) to the Electrical Method 3015.4
Pins
Electrostatic Discharge Variation of IEC 801-2
(ESD) to the Duplex
SC Receptacle
Electromagnetic
Interference (EMI)
Immunity
Eye Safety
Performance
Class 1 (>1 kV) - Human Body Model
Products of this type, typically, withstand at least
25 kV without damage when the Duplex SC
Connector Receptacle is contacted by a Human Body
Model probe.
FCC Class B
Typically provide a 17 dB margin to the noted
CENELEC EN55022 Class B standard limits up to 6 GHz, when tested in a GTEM
(CISPR 22A)
cell with the transceiver mounted to a circuit card
VCCI Class 1
with a chassis enclosure.
Variation of IEC 801-3
Typically show no measurable effect from a 10 V/m
field swept from 10 to 450 MHz applied to the
transceiver without a chassis enclosure.
FDA CDRH 21-CFR 1040
CDRH Accession Number: 9521220-27
Class I
TUV Bauart License: 933/510916/02
IEC 825 Issue 1 1993:11
Class 1
CENELEC EN60825 Class 1
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6
Performance Specifications
Absolute Maximum Ratings
Stresses in excess of the absolute maximum ratings can cause catastrophic damage to the device. Limits apply to each parameter in isolation,
all other parameters having values within the recommended operating conditions. It should not be assumed that limiting values of more than one
parameter can be applied to the product at the same time. Exposure to the absolute maximum ratings for extended periods can adversely affect
device reliability.
Parameter
Storage Temperature
Operating Temperature
Lead Soldering Temperature/Time
Output Current (other outputs)
Input Voltage
Power Supply Voltage
Symbol
TS
IOUT
-
Minimum
-40
0
0
GND
0
Maximum
+85
+70
+240/10
30
VCC
+6
Units
°C
°C
°C/s
mA
V
V
Symbol
VCC
TOP
Minimum
+4.75
0
Maximum
+5.25
+70
Units
V
°C
Operating Environment
Parameter
Power Supply Voltage
Ambient Operating Temperature
Transmitter Section
(Ambient Operating Temperature Ta = O°C to +7O°C, VCC = 4.75 V to 5.25 V)
Parameter
Symbol
Minimum
Maximum
Units
Notes
Output Center Wavelength
1261
1360
nm
lC
7.7
nm
Output Spectral Width (RMS)
Dl
Average Optical Output Power
PO
-20
-14
dBm
1
Extinction Ratio
Er
8.2
dB
140
mA
2
Power Supply Current
ICC
Output Eye
Compliant with Bellcore TR-NWT-000253 and ITU recommendation G.957
Receiver Section
(Ambient Operating Temperature Ta = O°C to +7O°C, VCC = 4.75 V to 5.25 V)
Parameter
Receiver Sensitivity
Maximum Input Power
Signal Detect - Asserted
Signal Detect - Deasserted
Signal Detect - Hysteresis
Power Supply Current
Data Outputs PECL
Alarm Output PECL
Symbol
PA
PD
PA - PD
ICC
Minimum
-8.0
PD +0.5
-43
0.5
-
Typical
80
Maximum
-31
-31
4.0
100
Units
dBm
dBm
dBm avg.
dBm.avg
dB
mA
Notes
3
4
Notes:
1. Output power is power coupled into a single mode fiber.
2. The power supply current varies with temperature. Maximum current is specified at VCC = Maximum @ maximum temperature
(not inchxding terminations) and end of life.
3. Minimum sensitivity and saturation levels for a FDDI test pattern as defined in FDDI SMF-PMDl with 4B/5B NRZI encoded data
that contains a duty cycle baseline wander effect of 50 kHz and a 223-1 PRBS with 72 ones and 72 zeros inserted
(ITU-T recommendation G.958).
4. The current excludes the output load current.
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7
Drawing Dimensions
Agilent XXXX-XXXX
ZZZZZ LASER PROD
TX
39.6
MAX.
(1.56)
12.7
(0.50)
(
KEY:
YYWW = DATE CODE
XXXX-XXXX = HFCT-5103
ZZZZ = 1300 nm
4.7
(0.185)
AREA
RESERVED
FOR
PROCESS
PLUG
25.4 MAX.
(1.00)
+0.1
0.25 -0.05
+0.004
0.010 -0.002
21CFR(J) CLASS 1
COUNTRY OF ORIGIN YYWW
RX
SLOT DEPTH
12.7
(0.50)
SLOT WIDTH
2.5
(0.10)
2.0 ± 0.1
(0.079 ± 0.004)
)
9.8
MAX.
(0.386)
0.51
(0.020)
3.3 ± 0.38
(0.130 ± 0.015)
9X «
(
23.8
(0.937)
+0.25
0.46 -0.05
+0.010
0.018 -0.002
20.32
(0.800)
2X «
20.32
(0.800)
)
8X 2.54
(0.100)
1.3
(0.051)
DIMENSIONS ARE IN MILLIMETERS (INCHES).
TOLERANCES: X.XX ±0.025 mm
UNLESS OTHERWISE SPECIFIED.
X.X ±0.05 mm
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15.8 ± 0.15
(0.622 ± 0.006)
2X «
(
20.32
(0.800)
+0.25
1.27 -0.05
+0.010
0.050 -0.002
)
Ordering Information
Temperature Range 0°C to +70°C
HFCT-5103B
Black Case
HFCT-5103D
Blue Case
Supporting Documentation
Application Note 1098
Characterization Report
Qualification Report
Class 1 Laser Product: This product conforms to the
applicable requirements of 21 CFR 1040 at the date of
manufacture
Date of Manufacture:
Agilent Technologies Ltd., Whitehouse Road, Ipswich, England
Handling Precautions
1. The HFCT-5103 can be damaged by current surges or overvoltage.
Power supply transient precautions should be taken.
2. Normal handling precautions for electrostatic sensitive devices
should be taken.
www.semiconductor.agilent.com
Data subject to change.
Copyright © 2000 Agilent Technologies, Inc.
Obsoletes: 5968-9459E (02/00)
5968-9459E (03/00)
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