NTD32N06 Power MOSFET 32 Amps, 60 Volts N–Channel DPAK Designed for low voltage, high speed switching applications in power supplies, converters and power motor controls and bridge circuits. http://onsemi.com Features • • • • • • • 32 AMPERES 60 VOLTS RDS(on) = 26 mΩ Smaller Package than MTB36N06V Lower RDS(on) Lower VDS(on) Lower Total Gate Charge Lower and Tighter VSD Lower Diode Reverse Recovery Time Lower Reverse Recovery Stored Charge N–Channel D Typical Applications • • • • G Power Supplies Converters Power Motor Controls Bridge Circuits 4 4 1 2 3 MAXIMUM RATINGS (TJ = 25°C unless otherwise noted) Rating Drain–to–Source Voltage Drain–to–Gate Voltage (RGS = 10 MΩ) Gate–to–Source Voltage – Continuous – Non–Repetitive (tp10 ms) Drain Current – Continuous @ TA = 25°C – Continuous @ TA = 100°C – Single Pulse (tp10 µs) Total Power Dissipation @ TA = 25°C Derate above 25°C Total Power Dissipation @ TA = 25°C (Note 1.) Total Power Dissipation @ TA = 25°C (Note 2.) Operating and Storage Temperature Range Single Pulse Drain–to–Source Avalanche Energy – Starting TJ = 25°C (Note 3.) (VDD = 50 Vdc, VGS = 10 Vdc, L = 1.0 mH, IL(pk) = 25 A, VDS = 60 Vdc, RG = 25 Ω) Thermal Resistance – Junction–to–Case – Junction–to–Ambient (Note 1.) – Junction–to–Ambient (Note 2.) Maximum Lead Temperature for Soldering Purposes, 1/8″ from case for 10 seconds Symbol Value Unit VDSS VDGR 60 Vdc 60 Vdc VGS VGS 20 30 ID ID IDM PD 32 22 90 Adc 93.75 0.625 2.88 1.5 W W/°C W W TJ, Tstg –55 to +175 °C EAS 313 mJ Vdc °C/W RθJC RθJA RθJA 1.6 52 100 TL 260 March, 2001 – Rev. 1 1 CASE 369A DPAK (Bent Lead) STYLE 2 NTD32N06 Y WW T 2 3 CASE 369 DPAK (Straight Lead) STYLE 2 = Device Code = Year = Work Week = MOSFET MARKING DIAGRAMS & PIN ASSIGNMENTS Apk 4 Drain 4 Drain YWW NTD 32N06 YWW NTD 32N06 1 Gate 2 Drain 3 Source 1 Gate 3 Source 2 Drain ORDERING INFORMATION °C 1. When surface mounted to an FR4 board using 1″ pad size, (Cu Area 1.127 in2). 2. When surface mounted to an FR4 board using minimum recommended pad size, (Cu Area 0.412 in2). 3. Repetitive rating; pulse width limited by maximum junction temperature. Semiconductor Components Industries, LLC, 2001 S 1 Device NTD32N06 Package Shipping DPAK 75 Units/Rail NTD32N06–1 DPAK Straight Lead 75 Units/Rail NTD32N06T4 DPAK 2500 Tape & Reel Publication Order Number: NTD32N06/D NTD32N06 ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted) Characteristic Symbol Min Typ Max Unit 60 – 70 41.6 – – – – – – 1.0 10 – – ±100 2.0 – 2.8 7.0 4.0 – – 21 26 – – – 0.417 0.680 0.633 0.62 – – gFS – 21.1 – mhos Ciss – 1231 1725 pF Coss – 346 485 Crss – 77 160 td(on) – 10 25 tr – 84 180 td(off) – 31 70 tf – 93 200 QT – 33 60 Q1 – 6.0 – Q2 – 15 – VSD – – – 0.89 0.96 0.75 1.0 – – Vdc trr – 52 – ns ta – 37 – tb – 14.3 – QRR – 0.095 – OFF CHARACTERISTICS Drain–to–Source Breakdown Voltage (Note 4.) (VGS = 0 Vdc, ID = 250 µAdc) Temperature Coefficient (Positive) V(BR)DSS Zero Gate Voltage Drain Current (VDS = 60 Vdc, VGS = 0 Vdc) (VDS = 60 Vdc, VGS = 0 Vdc, TJ = 150°C) IDSS Gate–Body Leakage Current (VGS = ±20 Vdc, VDS = 0 Vdc) IGSS Vdc mV/°C µAdc nAdc ON CHARACTERISTICS (Note 4.) Gate Threshold Voltage (Note 4.) (VDS = VGS, ID = 250 µAdc) Threshold Temperature Coefficient (Negative) VGS(th) Static Drain–to–Source On–Resistance (Note 4.) (VGS = 10 Vdc, ID = 16 Adc) RDS(on) Static Drain–to–Source On–Voltage (Note 4.) (VGS = 10 Vdc, ID = 20 Adc) (VGS = 10 Vdc, ID = 32 Adc) (VGS = 10 Vdc, ID = 16 Adc, TJ = 150°C) VDS(on) Forward Transconductance (Note 4.) (VDS = 6 Vdc, ID = 16 Adc) Vdc mV/°C mOhm Vdc DYNAMIC CHARACTERISTICS Input Capacitance (VDS = 25 Vd Vdc, VGS = 0 Vdc, Vd f = 1.0 MHz) Output Capacitance Transfer Capacitance SWITCHING CHARACTERISTICS (Note 5.) Turn–On Delay Time (VDD = 30 Vdc, ID = 32 Adc, VGS = 10 Vdc, Vdc RG = 9.1 Ω) (Note 4.) Rise Time Turn–Off Delay Time Fall Time Gate Charge (VDS = 48 Vdc, Vd ID = 32 Adc, Ad VGS = 10 Vdc) (Note 4.) ns nC SOURCE–DRAIN DIODE CHARACTERISTICS Forward On–Voltage (IS = 20 Adc, VGS = 0 Vdc) (Note 4.) (IS = 32 Adc, VGS = 0 Vdc) (Note 4.) (IS = 20 Adc, VGS = 0 Vdc, TJ = 150°C) Reverse Recovery Time (IS = 32 Adc, Ad VGS = 0 Vdc, Vd dIS/dt = 100 A/µs) (Note 4.) Reverse Recovery Stored Charge 4. Pulse Test: Pulse Width ≤ 300 µs, Duty Cycle ≤ 2%. 5. Switching characteristics are independent of operating junction temperatures. http://onsemi.com 2 µC NTD32N06 60 60 VGS = 6 V 50 40 VGS = 6.5 V VGS = 7 V VGS = 5.5 V 30 VGS = 8 V ID, DRAIN CURRENT (AMPS) ID, DRAIN CURRENT (AMPS) VGS = 10 V VGS = 5 V 20 VGS = 4.5 V 10 VDS > = 10 V 50 40 30 20 TJ = 25°C 10 TJ = 100°C VGS = 4 V TJ = –55°C 0 0 1 3 2 3 4 TJ = 100°C 0.03 0.026 TJ = 25°C 0.022 0.018 TJ = –55°C 0.014 0 10 20 30 40 50 60 5 5.4 5.8 6.2 7 6.6 0.024 0.023 0.022 VGS = 10 V 0.021 0.02 VGS = 15 V 0.019 0.018 0 10 20 30 40 50 60 ID, DRAIN CURRENT (AMPS) ID, DRAIN CURRENT (AMPS) Figure 3. On–Resistance vs. Gate–to–Source Voltage Figure 4. On–Resistance vs. Drain Current and Gate Voltage 10000 ID = 16 A VGS = 10 V VGS = 0 V IDSS, LEAKAGE (nA) RDS(on), DRAIN–TO–SOURCE RESISTANCE (NORMALIZED) 4.6 Figure 2. Transfer Characteristics 0.034 1.6 4.2 Figure 1. On–Region Characteristics VGS = 10 V 1.8 3.8 VGS, GATE–TO–SOURCE VOLTAGE (VOLTS) 0.038 0.01 3.4 VDS, DRAIN–TO–SOURCE VOLTAGE (VOLTS) RDS(on), DRAIN–TO–SOURCE RESISTANCE (Ω) RDS(on), DRAIN–TO–SOURCE RESISTANCE (Ω) 0 1.4 1.2 1 TJ = 150°C 1000 TJ = 125°C 100 TJ = 100°C 0.8 0.6 –50 –25 10 0 25 50 75 100 125 150 175 0 10 20 30 40 50 TJ, JUNCTION TEMPERATURE (°C) VDS, DRAIN–TO–SOURCE VOLTAGE (VOLTS) Figure 5. On–Resistance Variation with Temperature Figure 6. Drain–to–Source Leakage Current vs. Voltage http://onsemi.com 3 60 12 3200 VGS = 0 V VDS = 0 V TJ = 25°C 2800 C, CAPACITANCE (pF) VGS, GATE–TO–SOURCE VOLTAGE (VOLTS) NTD32N06 2400 2000 Crss Ciss 1600 1200 800 Coss 400 Crss 0 10 5 VGS 0 VDS 5 10 15 25 20 Q2 6 4 2 ID = 32 A TJ = 25°C 0 0 4 8 12 16 20 24 28 32 Figure 7. Capacitance Variation Figure 8. Gate–to–Source and Drain–to–Source Voltage vs. Total Charge 36 32 100 IS, SOURCE CURRENT (AMPS) t, TIME (ns) Q1 Qg, TOTAL GATE CHARGE (nC) VDS = 30 V ID = 32 A VGS = 10 V tr tf td(off) td(on) 1 10 100 20 16 12 8 4 0 0.6 0.64 0.68 0.72 0.76 0.8 0.84 0.88 0.92 0.96 Figure 9. Resistive Switching Time Variation vs. Gate Resistance Figure 10. Diode Forward Voltage vs. Current VGS = 20 V SINGLE PULSE TC = 25°C RDS(on) Limit Thermal Limit Package Limit dc 10 10 ms 1 ms 100 µs 1 Mounted on 3″ sq. FR4 board (1″ sq. 2 oz. Cu 0.06″ thick single sided) with one die operating,10 s max 0.1 0.1 24 VSD, SOURCE–TO–DRAIN VOLTAGE (VOLTS) 1 10 100 EAS, SINGLE PULSE DRAIN–TO–SOURCE AVALANCHE ENERGY (mJ) 100 VGS = 0 V TJ = 25°C 28 RG, GATE RESISTANCE (Ω) 1000 ID, DRAIN CURRENT (AMPS) 8 VGS GATE–TO–SOURCE OR DRAIN–TO–SOURCE VOLTAGE (VOLTS) 1000 10 QT 10 Ciss 350 ID = 32 A 300 250 200 150 100 50 0 25 50 75 100 125 150 VDS, DRAIN–TO–SOURCE VOLTAGE (VOLTS) TJ, STARTING JUNCTION TEMPERATURE (°C) Figure 11. Maximum Rated Forward Biased Safe Operating Area Figure 12. Maximum Avalanche Energy vs. Starting Junction Temperature http://onsemi.com 4 175 NTD32N06 r(t), EFFECTIVE TRANSIENT THERMAL RESISTANCE (NORMALIZED) 10 Normalized to RθJC at Steady State 1 0.1 0.01 0.00001 0.0001 0.001 0.01 0.1 1 10 t, TIME (s) Figure 13. Thermal Response r(t), EFFECTIVE TRANSIENT THERMAL RESPONSE (NORMALIZED) 10 Normalized to RθJA at Steady State, 1″ square Cu Pad, Cu Area 1.127 in2, 3 x 3 inch FR4 board 1 0.1 0.01 0.00001 0.0001 0.001 0.01 0.1 1 t, TIME (s) Figure 14. Thermal Response http://onsemi.com 5 10 100 1000 NTD32N06 PACKAGE DIMENSIONS DPAK CASE 369A–13 ISSUE AA C B V NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. SEATING PLANE –T– E R 4 Z A S 1 2 3 U K F J L H D G 2 PL 0.13 (0.005) M T DIM A B C D E F G H J K L R S U V Z INCHES MIN MAX 0.235 0.250 0.250 0.265 0.086 0.094 0.027 0.035 0.033 0.040 0.037 0.047 0.180 BSC 0.034 0.040 0.018 0.023 0.102 0.114 0.090 BSC 0.175 0.215 0.020 0.050 0.020 --0.030 0.050 0.138 --- STYLE 2: PIN 1. 2. 3. 4. http://onsemi.com 6 GATE DRAIN SOURCE DRAIN MILLIMETERS MIN MAX 5.97 6.35 6.35 6.73 2.19 2.38 0.69 0.88 0.84 1.01 0.94 1.19 4.58 BSC 0.87 1.01 0.46 0.58 2.60 2.89 2.29 BSC 4.45 5.46 0.51 1.27 0.51 --0.77 1.27 3.51 --- NTD32N06 PACKAGE DIMENSIONS DPAK CASE 369–07 ISSUE M C B V E R 4 A 1 2 3 S –T– SEATING PLANE K J F H D G 3 PL 0.13 (0.005) M NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. DIM A B C D E F G H J K R S V INCHES MIN MAX 0.235 0.250 0.250 0.265 0.086 0.094 0.027 0.035 0.033 0.040 0.037 0.047 0.090 BSC 0.034 0.040 0.018 0.023 0.350 0.380 0.175 0.215 0.050 0.090 0.030 0.050 STYLE 2: PIN 1. 2. 3. 4. T http://onsemi.com 7 GATE DRAIN SOURCE DRAIN MILLIMETERS MIN MAX 5.97 6.35 6.35 6.73 2.19 2.38 0.69 0.88 0.84 1.01 0.94 1.19 2.29 BSC 0.87 1.01 0.46 0.58 8.89 9.65 4.45 5.46 1.27 2.28 0.77 1.27 NTD32N06 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. 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