ETC 74F174SJX

Revised September 2000
74F174
Hex D-Type Flip-Flop with Master Reset
General Description
Features
The 74F174 is a high-speed hex D-type flip-flop. The
device is used primarily as a 6-bit edge-triggered storage
register. The information on the D inputs is transferred to
storage during the LOW-to-HIGH clock transition. The
device has a Master Reset to simultaneously clear all
flip-flops.
■ Edge-triggered D-type inputs
■ Buffered positive edge-triggered clock
■ Asynchronous common reset
■ Guaranteed 4000V minimum ESD protection
Ordering Code:
Order Number
Package Number
Package Description
74F174SC
M16A
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow
74F174SJ
M16D
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74F174PC
N16E
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Logic Symbols
Connection Diagram
IEEE/IEC
© 2000 Fairchild Semiconductor Corporation
DS009489
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74F174 Hex D-Type Flip-Flop with Master Reset
April 1988
74F174
Unit Loading/Fan Out
Pin Names
Description
U.L.
Input IIH/IIL
HIGH/LOW
Output IOH/IOL
D0–D5
Data Inputs
1.0/1.0
20 µA/−0.6 mA
CP
Clock Pulse Input (Active Rising Edge)
1.0/1.0
20 µA/−0.6 mA
MR
Master Reset Input (Active LOW)
1.0/1.0
20 µA/−0.6 mA
Q0–Q5
Outputs
50/33.3
−1 mA/20 mA
Functional Description
Truth Table
The 74F174 consists of six edge-triggered D-type flip-flops
with individual D inputs and Q outputs. The Clock (CP) and
Master Reset (MR) are common to all flip-flops. Each D
input’s state is transferred to the corresponding flip-flop’s
output following the LOW-to-HIGH Clock (CP) transition. A
LOW input to the Master Reset (MR) will force all outputs
LOW independent of Clock or Data inputs. The 74F174 is
useful for applications where the true output only is
required and the Clock and Master Reset are common to
all storage elements.
Inputs
MR
CP
L
H
H
X
Outputs
Dn
Qn
X
L
H
H
L
L
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
= LOW-to-HIGH Clock Transition
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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2
Recommended Operating
Conditions
Storage Temperature
−65°C to +150°C
Ambient Temperature under Bias
−55°C to +125°C
Free Air Ambient Temperature
Junction Temperature under Bias
−55°C to +150°C
Supply Voltage
0°C to +70°C
+4.5V to +5.5V
−0.5V to +7.0V
VCC Pin Potential to Ground Pin
Input Voltage (Note 2)
−0.5V to +7.0V
Input Current (Note 2)
−30 mA to +5.0 mA
Voltage Applied to Output
in HIGH State (with VCC = 0V)
Standard Output
−0.5V to VCC
3-STATE Output
−0.5V to +5.5V
Note 1: Absolute maximum ratings are values beyond which the device
may be damaged or have its useful life impaired. Functional operation
under these conditions is not implied.
Current Applied to Output
in LOW State (Max)
Note 2: Either voltage limit or current limit is sufficient to protect inputs.
twice the rated IOL (mA)
ESD Last Passing Voltage (Min)
4000V
DC Electrical Characteristics
Symbol
Parameter
Min
Typ
Max
VCC
VIL
Input LOW Voltage
0.8
V
VCD
Input Clamp Diode Voltage
−1.2
V
Min
V
Min
V
Min
5.0
µA
Max
VIN = 2.7V
7.0
µA
Max
VIN = 7.0V
50
µA
Max
VOUT = VCC
V
0.0
3.75
µA
0.0
−0.6
mA
Max
−150
mA
Max
VOUT = 0V
45
mA
Max
CP =
Output HIGH
Voltage
VOL
IIH
10% VCC
2.5
5% VCC
2.7
V
Conditions
Input HIGH Voltage
VOH
2.0
Units
VIH
Output LOW
10% VCC
0.5
Voltage
10% VCC
0.5
Input HIGH
Current
IBVI
Input HIGH Current
Breakdown Test
ICEX
Output HIGH
Leakage Current
VID
Input Leakage
Test
IOD
4.75
Output Leakage
Circuit Current
IIL
Input LOW Current
IOS
Output Short-Circuit Current
ICCH
Power Supply Current
−60
30
Recognized as a HIGH Signal
Recognized as a LOW Signal
IIN = −18 mA
IOH = −1 mA
IOH = −1 mA
IOL = 20 mA
IOL = 20 mA
IID = 1.9 µA
All Other Pins Grounded
VIOD = 150 mV
All Other Pins Grounded
VIN = 0.5V
Dn = MR = HIGH
ICCL
Power Supply Current
30
3
45
mA
Max
VO = LOW
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74F174
Absolute Maximum Ratings(Note 1)
74F174
AC Electrical Characteristics
Symbol
Parameter
Min
TA = +25°C
TA = −55°C to +125°C
TA = 0°C to +70°C
VCC = +5.0V
VCC = +5.0V
VCC = +5.0V
CL = 50 pF
CL = 50 pF
CL = 50 pF
Typ
Max
Min
Max
Min
Max
fMAX
Maximum Clock Frequency
80
tPLH
Propagation Delay
3.5
5.5
8.0
3.0
10.0
3.5
9.0
tPHL
CP to Qn
4.0
7.0
10.0
4.0
12.0
4.0
11.0
tPHL
Propagation Delay
5.0
10.0
14.0
5.0
16.0
5.0
15.0
MR to Qn
70
Units
80
MHz
ns
ns
AC Operating Requirements
Symbol
Parameter
TA = +25°C
TA = −55°C to +125°
VCC = +5.0V
VCC = +5.0V
Min
Max
Min
Max
TA = 0°C to +70°C
VCC = +5.0V
Min
tS(H)
Setup Time, HIGH or LOW
4.8
5.0
4.8
tS(L)
Dn to CP
4.0
5.0
4.0
tH(H)
Hold Time, HIGH or LOW
0
2.0
0
tH(L)
Dn to CP
0
2.0
0
tW(H)
CP Pulse Width
4.0
5.0
4.0
tW(L)
HIGH or LOW
6.0
7.5
6.0
tW(L)
MR Pulse Width, LOW
5.0
6.5
5.0
tREC
Recovery Time, MR to CP
5.0
6.0
5.0
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Units
Max
ns
ns
ns
74F174
Physical Dimensions inches (millimeters) unless otherwise noted
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow
Package Number M16A
5
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74F174
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
Package Number M16D
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6
74F174 Hex D-Type Flip-Flop with Master Reset
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Package Number N16E
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
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FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
2. A critical component in any component of a life support
device or system whose failure to perform can be reasonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the
user.
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