ETC DSP5685XUMAD

Freescale Semiconductor, Inc.
DSP5685XUMAD/D
Rev. 3.0, 10/2003
DSP5685XUMAD/D
Freescale Semiconductor, Inc...
DSP5685XUM/D Rev. 2.0 Addendum
This addendum supplements, and should be used in conjunction with, the DSP56853/854/
855/857/858 User’s Manual, Rev 2.0 (order number DSP5685XUM/D). Part 1 of this
document corrects particular information, or clarifies certain ambiguities in the User’s
Manual, while Part 2 provides additional information, including copy changes, or
additions.
Part 1 Corrections
Table A identifies and corrects errors appearing in more than one location in the user’s
manual. Subsequent subsections identify and correct entries in specific chapters.
1.1 Multiple Corrections Throughout the Manual
Table A corrects consistent errors and omissions throughout the DSP5685x User’s Manual, Rev 2.0.
Table A: Multiple Manual Errors
Error Location
Error
Multiple
Typographical
Correction
Correct: CGM_Base = $1FFFF10
To read: $1FFF10
© Motorola, Inc., 2003. All rights reserved.
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1.2 Corrections to Chapter 1, Overview
Table B corrects errors and omissions in Chapter 1 of the DSP5685x User’s Manual, Rev 2.0.
Table B: Chapter 1 Errors
Error Location
Page 1-24, Below Fig. 1-8
Freescale Semiconductor, Inc...
Page 1-24, Below Fig. 1-8
Page 1-34, Sec. 1.12.12
third bullet
Error
Correction
Heading Added
Move: the paragraph immediately below Figure 1-8 to
above Figure 1-8.
Assign: this moved paragraph the section number:
1.5.2.1 and heading System Side Operation
Correct Section
Number
and Add sentence
Change: Section 1.5.3 (Peripheral Side Operation) to
become 1.5.2.2.
Add: at the end of this paragraph: The IPBus operates
at half of the core frequency.
Correction/Clarifica- Delete: 25 percent
tion
Replace w/: 33 percent
1.3 Corrections to Chapter 2, Pin Descriptions
Table C corrects errors and omissions in Chapter 2 of the DSP5685x User’s Manual, Rev 2.0.
Table C: Chapter 2 Errors
Error Location
Error
Correction
Page 2-5, Fig. 2-1
Host Interface Pins
Correction
Delete: B in HRWB (3rd pin down in the group)
Change: HRW to read HWR (4th pin down in the grp)
Page 2-6, Fig. 2-2
Host Interface Pins
Correction
Delete: B in HRWB (3rd pin down in the group)
Change: HRW to read HWR (4th pin down in the grp)
Page 2-8, Fig. 2-4
Host Interface Pins
Correction
Delete: B in HRWB (3rd pin down in the group)
Change: HRW to read HWR (4th pin down in the grp)
Page 2-9, Fig. 2-5
Host Interface Pins
Correction
Delete: B in HRWB (3rd pin down in the group)
Change: HRW to read HWR (4th pin down in the grp)
Page 2-11, Table 2-6
(3rd row down, 1st column)
Correction
Delete: B in HRWB to read HRW
Page 2-11, Table 2-6
(4th row down, 1st column)
Correction
Change: HRW
To: HWR
2
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1.4 Corrections to Chapter 3, Memory Operating Modes (MEM)
Table D corrects errors and omissions in Chapter 3 of the DSP5685x User’s Manual, Rev 2.0.
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Table D: Chapter 3 Errors
Error Location
Error
Correction
Page 3-3, Sec. 3.1.1
Clarification
Add: Boot ROM contents and operations (see Part 2 of
this document)
Page 3-8, New Table
Omission
Insert: COP Address Map table before Table 3-4 (see
Part 2 of this document)
Page 3-8, Table 3-4
Column 1, row 2
Typographical
Page 3-8, Table 3-4
Column 1, rows 7 & 8
Transposed Entry
Page 3-8, Table 3-4
Column 1, rows 10 & 11
Transposed Entry
Page 3-12, Table 3-16
Column 2, row 3
Incorrect Data
Delete: $E
Replace w/: $16
Page 3-13, Table 3-16
Column 2, rows 12 & 14
Incorrect Data
Delete: Address offsets $F and $1F
Replace w/: $D (row 12) $1D (row 14)
Page 3-16, Sec. 3.2.2
First paragraph
Incorrect Data
Delete: the reference to Table 8-2
Replace w/: Table 8-4
Correct: TRQP4 to read IRQP4
Transpose: FIVAL1 & FIVAH1 (Low = $E, High = $F)
Transpose: FIVAL0 & FIVAH0 (Low = $B, High = $C)
1.5 Corrections to Chapter 4, System Integration Module (SIM)
Table E corrects errors and omissions in Chapter 4 of the DSP5685x User’s Manual, Rev 2.0.
Table E. Chapter 4 Errors
Error Location
Error
Page 4-3, Sec. 4.2
First feature
SIM re-design
Delete: Four
Replace w/: Five
Page 4-3, Sec. 4.2
First feature After second
secondary bullet
SIM re-design
Insert: System external memory interface four-phase
clock with hold off control
Page 4-8, Sec. 4.6.1
SIM re-design
Delete: register
Replace w/: *register shown immediately below this
table
Page 4-8, Sec. 4.6.1.2
Second paragraph
Incorrect Data
Delete: “....or software reset”.....
MOTOROLA
Correction
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Table E. Chapter 4 Errors
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Error Location
Error
Correction
Page 4-8, Sec. 4.6.1.2
Second paragraph
immediately after
“deasserts.”
SIM re-design
Add: Synchronous reset (software or COP) do not
update Boot mode assuming applications software will
set the desired field value prior to the reset. The core
always begins execution after reset from the base of
the on-chip ROM. The software in ROM will perform
one of the several boot actions based on the value of
Boot mode.
Page 4-9, Sec. 4.6.1.2
Top of pg, first line
SIM re-design
Insert: For Boot mode 1, the four-byte....
Page 4-10, Sec. 4.6.1.2.4
First line
SIM re-design
Delete: remains at
Replace w/: is set to
Page 4-10, Sec. 4.6.1.2.5
Below exisitng paragraph
SIM re-design
Add: Note: This mode becomes a reserved mode on
parts lacking a host port interface.
Page 4-10, Sec. 4.6.1.2.6
SIM re-design
Add: Note: This mode becomes a reserved mode on
parts lacking a host port interface.
Page 4-10, Sec. 4.6.1.3
SIM re-design
*This refers to the register below and Section 4.6.1
above.
Delete: Reserved
Replace w/: Static read only value (currently 0001)
indicating chip revision. This is intended to be used by
application software to facilitate support of backwards
compatibility. Changes to the programming interface
can be tied to their associated chip revision.
Page 4-16, Sec. 4.10
End of first paragraph
SIM re-design
Add: “...POR reset detector and the Boot mode field in
the SIMCTL register, reset by the mode reset detector.”
Page 4-17,Sec. 4.10
Last paragraph, first line
Clarification
Delete: “the next chapter...”
Replace w/: Section 4.9
* Register from table above
$1FFF08
15
Read
0
Write
RESET
4
0
14
13
12
11
0
0
9
8
CHIP REV
BOOT MODE
0
10
0
0
0
7
0
1
0
6
5
4
3
2
1
0
EOnCE CLKOUT PRAM DRAM SW STOP WAIT
EBL
DBL
DBL
DBL RST DBL DBL
0
0
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0
0
0
0
0
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1.6 Corrections to Chapter 5, External Memory Interface (EMI)
Table F corrects errors and omissions in Chapter 5 of the DSP5685x User’s Manual, Rev 2.0.
Table F. Chapter 5 Errors
Error Location
Freescale Semiconductor, Inc...
All of Chapter 5
Error
EMI re-design
Correction
Replace with new Chapter 5 (see Part 2 for new
Chapter 5 content) NOTE: References to EMI in
other chapters within this manual are superceded
by this revised version.
1.7 Corrections to Chapter 6, On-Chip Clock Synthesis (OCCS)
Table G corrects errors and omissions in Chapter 6 of the DSP5685x User’s Manual, Rev 2.0.
Table G. Chapter 6 Errors
Error Location
Error
Correction
All of Chapter 6
Clarification
Replace w/: new Chapter 6 (see Part 2 for new Chapter 6 content)
1.8 Corrections to Chapter 7, Power-On Reset (POR)
Table H corrects errors and omissions in Chapter 7 of the DSP5685x User’s Manual, Rev 2.0.
Table H. Chapter 7 Errors
Error Location
Error
Page 7-4, New Section after
Sec. 7.3
Omission
MOTOROLA
Correction
Add: COP section (see Part 2 of this document)
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1.9 Corrections to Chapter 8, Interrupt Controller (ITCN)
Table I corrects errors and omissions in Chapter 8 of the DSP5685x User’s Manual, Rev 2.0.
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Table I. Chapter 8 Errors
Error Location
Error
Correction
Page 8-5, Table 8-2
Column 1, rows 7 & 8
Transposed Entry
Transpose: FIVAL1 & FIVAH1 (Low = $E, High = $F)
Page 8-5, Table 8-2
Column 1, rows 10 & 11
Transposed Entry
Transpose: FIVAL0 & FIVAH0 (Low = $B, High = $C)
Page 8-7, Table 8-3
Incorrect Data
Replace w/: correct table (see Part 2 of this document)
Page 8-24 (Bottom)
Omission
Add: IPR 8 Register and its bit descriptions (see Part 2
of this document)
Page 8-28, Sec 8.7.14
Repetition
Delete: bulleted items (they are repeated in Sec
8.7.14.1)
Page 8-31, Sec. 8.7.16
Incorrect Reference
Page 8-31, Table 8-4
Incorrect Data
Delete: Table 8-3
Replace w/: Table 8-4
Replace w/: correct table (see Part 2 of this document)
1.10 Corrections to Chapter 9, Direct Memory Access (DMA)
Table J corrects errors and omissions in Chapter 9 of the DSP5685x User’s Manual, Rev 2.0.
Table J. Chapter 9 Errors
6
Error Location
Error
Correction
Page 9-10, Sec 9.6.7.3
Typographical
Page 9-11, Sec 9.6.7.6
Clarification
Add: note below existing Note to read: Whenever
doing DMA transfers with peripherals, DATASIZE
should be set as Word mode.
Page 9-15, Sec 9.7.3
Clarification
Add: to the end of the sentence in the 3rd line: “...one
byte at a time, but it is stored as a word.”
Page 9-15, Sec 9.7.3
Clarification
Delete: the word byte after 40 and 400 in this paragraph.
Replace w/: word in each instance
Page 9-15, Figure 9-10
Clarification
Delete: the word byte used after 40 and 400.
Replace w/: word in each instance
Page 9-16, Item # 7
Correction
Replace: C in $C032 with D to read: $D032
Page 9-16, 4th bullet
Clarification
Replace: the word byte with word & the 0 with 1 in
DATASIZE to become( DATASIZE =1)
Page 9-16, 7th bullet
Clarification
Replace: the word bytes with words
Delete: deserted
Replace w/: deasserted
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1.11 Corrections to Chapter 10, Serial Communications
Interface (SCI)
Table K corrects errors and omissions in Chapter 10 of the DSP5685x User’s Manual, Rev 2.0.
Table K. Chapter 10 Errors
Error Location
Error
Correction
NONE
NONE
NONE
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1.12 Corrections to Chapter 11, Serial Peripheral Interface (SPI)
Table L corrects errors and omissions in Chapter 11 of the DSP5685x User’s Manual, Rev 2.0.
Table L. Chapter 11 Errors
Error Location
Error
Correction
NONE
NONE
NONE
1.13 Corrections to Chapter 12, Enhanced Synchronous Serial
Interface (ESSI)
Table M corrects errors and omissions in Chapter 12 of the DSP5685x User’s Manual, Rev 2.0.
Table M. Chapter 12 Errors
Error Location
Error
Correction
Page 12-16, Sec 12.5.2.1
Between paragraphs
Clarification
Add: Note: In case of Normal mode with external frame
sync, TE bit should be cleared after first bit of transmission only.
Page 12-46, Figure 12-23
Correction
Change: bit 2 from SCKD0 to read: SCD0
Page 12-51, Table 12-17
Correction
Delete: all 0s replacing with 1s in DIV4DIS column
Delete: all 1s replacing with 0s in DIV4DIS column
Page 12-56-7, Figs 12-28-9
Typographical
Invert: bit numbering to read 15:0 in Fig 12-28 and
31:16 in Fig 12-29
Add: steps 4 and 5 to correct sequence
Page 12-61
Clarification
4. Write data to the STX register(s)
5. Enable transmit and receive operations.
Add: note before Table 12-25
Page 12-61
MOTOROLA
Clarification
Note: The EMI bit clock must go low for at least one
complete period to ensure proper EMI reset.
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1.14 Corrections to Chapter 13, Quad Timer (TMR)
Table N corrects errors and omissions in Chapter 13 of the DSP5685x User’s Manual, Rev 2.0.
Table N. Chapter 13 Errors
Error Location
Error
Correction
NONE
NONE
NONE
1.15 Corrections to Chapter 14, Time of Day (TOD)
Freescale Semiconductor, Inc...
Table O corrects errors and omissions in Chapter 14 of the DSP5685x User’s Manual, Rev 2.0.
Table O. Chapter 14 Errors
Error Location
Error
Correction
NONE
NONE
NONE
1.16 Corrections to Chapter 15, General Purpose Input/Output
(GPIO)
Table P corrects errors and omissions in Chapter 15 of the DSP5685x User’s Manual, Rev 2.0.
Table P. Chapter 15 Errors
Error Location
Error
Page 15-3, Tables 15-1 thru
15-8
Clarification
Page 15-5, New Table
Below Table 15-7
Omission
Page 15-8, Sec. 15.8.1.2
Second bullet
Clarification
Delete: peripheral
Replace w/: the EMI
Page 15-9, Sec. 15.8.2.1
Second bullet
Clarification
Delete: peripheral
Replace w/: the Host Interface Eight
Page 15-9, Sec. 15.8.3.2
Second bullet
Clarification
Delete: peripheral
Replace w/: the ESSI0
Page 15-10, Sec. 15.8.4.2
Second bullet
Clarification
Delete: peripheral
Replace w/: the ESSI1
Page 15-10, Sec. 15.8.5.2
Second bullet
Clarification
Delete: peripheral
Replace w/: the SCI
Page 15-10, Sec. 15.8.6.2
Second bullet
Clarification
Delete: peripheral
Replace w/: the SPI
Page 15-10, Sec. 15.8.7.2
Second bullet
Clarification
Delete: peripheral
Replace w/: the TMR
Page 15-10, Sec. 15.8.8.2
Second bullet
Clarification
Delete: peripheral
Replace w/: the SIM
8
Correction
Delete: Select Register in each table
Replace w:/ Peripheral Enable (GPIO_X_PER)
Add: Table 15-8 GPIO H Register Map (GPIO_BASE
= $1FFE7C) (see Part 2 of this document)
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1.17 Corrections to Chapter 16, Host Interface Eight (HI8)
Table Q corrects errors and omissions in Chapter 16 of the DSP5685x User’s Manual, Rev 2.0.
Freescale Semiconductor, Inc...
Table Q. Chapter 16 Errors
Error Location
Error
Correction
Page 16-5, Table 16-1
Columns 1 & 2, row 3
Typographical
Delete: HRDS to read
Replace w/: HRD
Page 16-5, Table 16-1
Columns 1 & 2, row 3
Typographical
Delete: HRW to read
Replace w/: HRW
Page 16-5, Table 16-1
Columns 1 & 2, row 4
Typographical
Delete: HWRS
Replace w/: HWR
Page 16-6, Table 16-1
Column 1, row 2
Typographical
Delete: HRZQ
Replace w/: HREQ
Page 16-7, Figure 16-1
Left side of figure
Clarification
Delete: left vertical arrow labeled DSP Peripheral Data
Bus.
Delete: shorter horizontal arrows and their pin designations immediately to the right of the vertical arrow.
Page 16-8, Table 16-2
Address & Offset column
Correction
Delete: $2 offset in the HTX row
Replace w/: $A
Page 16-8, Table 16-2
Address & Offset column
Correction
Delete: $3 offset in the HRX row
Replace w/: $A
Page 16-8, Table 16-3
Clarification
Delete: the table
Replace w/: a new table (see Part 2 of this document)
Page 16-9, Figure 16-2
Typographical
Delete: REDMAEN in bit 5
Replace w/: RDMAEN
Add: (HDDS = 0) to the upper figure description to
Replace w/: Single Date Strobe Mode (HDDS = 0)
Add: (HDDS = 1) to the lower figure description Replace
w/: Dual Data Strobe Mode (HDDS =1)
Page 16-10, Figure 16-3
Clarification
Page 16-12, Figure 16-4
Bit 4
Typographical
Delete: HFI
Replace w/: HF1
Page 16-14, Figure 16-5
Register Address
Correction
Delete: $2 offset
Replace w/: $A
Page 16-14, Figure 16-5
Write Acronyms
Correction
Delete: RXH and RXL
Replace w/: HRX and LRX respectively
Page 16-14, Figure 16-5
Write Acronyms
Correction
Delete: TXH and TXL
Replace w/: HTX and LTX respectively
Page 16-17, Table 16-7
Clarification
Delete: the table. Data included in the new table above
makes this table redundant and unnecessary.
Page 16-18, Figure 16-8
Clarification
Delete: bits 15-8 of this register. Though shown as
reserved and unusable, leaving usable only an 8-bit register, it is deemed confusing to see a 16-bit register when
it is actually an 8-bit register.
Page 16-18, Sec. 16.9.1.1
Unnecessary
MOTOROLA
Delete: Reserved—Bits 15-8 and its text
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Table Q. Chapter 16 Errors (Continued)
Error Location
Error
Correction
Page 16-21, Sec. 16.9.1.6
end of the first line of text
Incomplete data
Add: Little Endian between in and or to read:...Host in Little Endian or Big Endian...
Page 16-22, Sec. 16.9.2
Clarification
Delete: text in this section and replace it with the revised
text provided in Part 2 of this document.
Page 16-22, Figure 16-9
Clarification
Delete: bits 15-8 of this register. Though shown as
reserved and unusable, leaving usable only an 8-bit register, it is deemed confusing to see a 16-bit register when
it is actually an 8-bit register.
Page 16-23, Sec. 16.9.2.1
Unnecessary
Delete: Reserved—Bits 15-8 and its text
Page 16-24, Figure 16-10
Clarification
Delete: bits 15-8 of this register. Though shown as
reserved and unusable, leaving usable only an 8-bit register, it is deemed confusing to see a 16-bit register when
it is actually an 8-bit register.
Page 16-24, Figure 16-10
Wrong data
Delete: Bit 1 RESET 0
Replace w/: 1
Page 16-24, Sec. 16.10.1.1
Unnecessary
Delete: Reserved—Bits 15-8 and its text
Page 16-25, Sec. 16.10.1.7
4th line of text
Clarification
Delete: text from For example, if the Host...through the
end of the paragraph.
Page 16-25, Sec. 16.10.1.8
4th line of text
Correction
Delete: (TXL or TXH according to HLEND bit) register
Replace w/: register at address seven is written...
Page 16-26, Sec. 16.10.1.9
4th line of text
Correction
Delete: (RXL or RXH according to HLEND bit)
Replace w/: ...at address seven is read by the...
Page 16-26, Figure 16-11
Clarification
Delete: bits 15-8 of this register. Though shown as
reserved and unusable, leaving usable only an 8-bit register, it is deemed confusing to see a 16-bit register when
it is actually an 8-bit register.
Page 16-26, Figure 16-11
Wrong data
Delete: Bits 3-0 RESET 0
Replace w/: 1s
Page 16-29, Figure 16-12
Incomplete data
Page 16-29, Sec. 16.10.8
3rd line of text
Incorrect word
Page 16-35, Sec.
16.10.10.2 revision and
rewrite of the final
paragraph
Clarification
10
Delete: RXD on top right set of boxes
Replace w/: RXDF
Delete: Interrupt in Interrupt Status Register
Replace w/: Interface Status Register
Delete: paragraph (see Part 2 in this document)
Replace w:/ paragraph shown in Part 2 of this document
identified as: 16.10.10.2
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1.18 Corrections to Chapter 17, JTAG
Table R corrects errors and omissions in Chapter 17 of the DSP5685x User’s Manual, Rev 2.0.
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Table R. Chapter 17 Errors
Error Location
Error
Page 17-16, Table 17-5
Correction
Correction
Delete: B in HRWB in 5th row series (bits 157-9) to
read HRW
1.19 Corrections to Appendices
Table S corrects errors and omissions in Appendices of the DSP5685x User’s Manual, Rev 2.0.
Table S. Appendices Errors
Error Location
Error
Page B-25 thru 27
Omission
Add: COP registers (see Part 2 of this document)
Page B-79
Correction
Change: Bit 0 reset value from 0 to 1 in this register
Page B-138 and B139
Correction
Delete: $2 offset
Replace w/: $A
Page C-3
Correction
Delete: B in HRWB (Pin # 85) to read HRW
Page C-4
Correction
Delete: B in HRWB (Pin # 85) to read HRW
Page C-6
Correction
Delete: B in HRWB (Pin # 85) to read HRW
Page C-6
Correction
Delete: B in HRWB (Pin # 85) to read HRW
Page C-12
Correction
Delete: B in HRWB (Pin # 65) to read HRW
Page C-13
Correction
Delete: B in HRWB (Pin # 65) to read HRW
Page C-15
Correction
Delete: B in HRWB (Pin # 93) to read HRW
Page C-16
Correction
Delete: B in HRWB (Pin # 93) to read HRW
MOTOROLA
Correction
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Part 2 Additional Information/Copy
The following addition refers to entry Page 3-3, Section 3.2.
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3.2 Program Boot ROM
The DSP5685x has 1K-word × 16-bit on-chip Program ROM. The program ROM
contains the bootstrap firmware program that performs initial loading of the internal
program RAM. It is located in Program memory space at locations $1F0000-$1F03FF.
The bootstrap program can load any Program RAM segment from an external memory or
serial EEPROM. On exiting the reset state the first instruction is fetched from the program
ROM ($1F0000) to start execution of the bootstrap program.
The value on the input pins, MODA, MODB, and MODC, when the last active reset
source—reset pin, power-on reset, or software reset—deasserts will determine which
bootstrap mode is entered.
Note:
A COP reset via RST does not alter these registers since a COP reset by
definition occurs unexpectedly during system operation, therefore possibly no
longer providing the required MODE inputs.
Note:
A software reset via RST_SW does not alter these registers, thereby allowing
users to reboot in a different mode without altering the hardware.
Some boot modes, specifically those transferring code to internal PRAM for execution,
require header data to synchronize the peripheral, define the transfer start address in
PRAM, and define the number of words to load. The following four points describe the
required format for boot mode:
1. The four byte ASCII sequence BOOT (mode 1 only)
2. Two words (4 bytes) defining the number of program words to be loaded (modes 0,
1, 4, 5, and 6 only)
3. Two words (4 bytes) starting address where loaded in the program memory (modes
0, 1, 4, 5, and 6 only)
4. The user program (two bytes for each 16-bit program word) on all boot modes
12
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The four-byte string BOOT loads B first in Boot Mode One. The bytes/words for the
remaining data are loaded least significant byte/word first. The boot code is generalpurpose, and assumes the number of program words and starting address are valid for the
users system. If the values are invalid, unpredictable results will occur. If a reserved mode
is specified, the debughlt instruction will be executed causing the software to enter an
infinite loop.
Once the bootstrap program completes loading the specified number of words, if
applicable to that Boot mode, the bootstrap program jumps to the starting address and
executes the loaded program. Some of the bootstrap routines reconfigure the memory map
by setting the PRAM DISABLE field in the SIM Control Register. Some bootstrap
routines also make specific assumptions about the external clock frequency being applied
to the part.
3.2.1 Boot Mode 0: Bootstrap From Byte-Wide External Memory
The PRAM DISABLE remains zero, leaving both internal program and data RAM
enabled. The bootstrap program loads program memory from a byte-wide memory located
at $040000 using CS0 as the chip select, before jumping to the start of the user code.
3.2.2 Boot Mode 1: Bootstrap From SPI
The PRAM DISABLE remains zero, leaving both internal program and data RAM
enabled. The bootstrap program loads program memory from a serial EEPROM via the
SPI. GPIOF3 is an alternative function of the SS. When configured and programmed, the
alternative function can be used as the SS output. This mode is compatible with ATMEL
AT25xxx and AT45xxx series serial EEPROMs. In order to determine the correct SPI
configuration, the first four bytes in the serial memory must be the string BOOT in ASCII.
They are: $42, $4F, $4F and $54. If, after trying all three configurations, BOOT is not
read, the part will move to the DEBUG HALT state. After the string BOOT, the data
should continue as described in the data sequence above. After loading the user program,
GPIOF3 is returned to its power-on reset state—input under peripheral control—and the
bootstrap program jumps to the start of the user code. This boot loader assumes the
external clock is being applied at a frequency between 2MHz and 4MHz. For some
external devices, it enables the PLL during boot loading but always leaves the PLL off
when complete.
3.2.3 Boot Mode 2: Normal Expanded Mode
The PRAM DISABLE remains at zero, leaving both internal program and data RAM
enabled. No code is loaded. The bootstrap program simply vectors to external program
memory location P:$040000 using CS0 as the chip select.
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3.2.4 Boot Mode 3: Development Expanded Mode
The PRAM DISABLE remains at one, leaving internal data RAM enabled, but the internal
program RAM is disabled. All references to internal program memory space are
subsequently directed to external program memory. No code is loaded. The bootstrap
program simply vectors to program memory location P:$000000 using CS0 as the chip
select.
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3.2.5 Boot Mode 4: Bootstrap From Host Port–Single Strobe Clocking
The PRAM DISABLE remains at zero, leaving both internal program and data RAM
enabled. The bootstrap program configures the Host Port for single strobe access, loading
program memory from the Host Port before jumping to the start of the user code.
3.2.6 Boot Mode 5: Bootstrap From Host Port–Dual Strobe Clocking
The PRAM DISABLE remains at zero, leaving both internal program and data RAM
enabled. The bootstrap program configures the Host Port for dual strobe access, loading
program memory from the Host Port before jumping tot he start of the user code.
3.2.7 Boot Mode 6: Bootstrap From SCI
The PRAM DISABLE remains at zero, leaving both internal program and data RAM
enabled. It configures the SCI for 38400 baud transfers with a 4MHz or 19200 with 2MHz
crystals. It also enables the PLL to operate during the boot process. The bootstrap program
then loads program memory from the SCI port and jumps to the start of the user code.
External clocking must be between 2MHz and 4MHz. It uses the PLL but leaves it off
when complete. The data format is:
•
One start bit
•
Eight-data bits
•
No parity bit
•
One Stop bit
•
Flow Control off
3.2.8 Boot Mode 7: Reserved for Future Use
14
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The following addition refers to entry Page 3-8, New Table.
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Table 3-5. COP Module Registers Address Map
(COP_BASE = $1FFFD0) Chapter 7
Register Acronym
Address
COPCTL
$0
COP Control Register
Register Description
COPTO
$1
COP Timeout Register
COPCTR
$2
COP Counter Register
The following is the complete replacement of Chapter 5. External Memory
Interface (EMI) NOTE: References to EMI in other chapters within this manual are superceded
by this revised version.
5.1 Introduction
The External Memory Interface (EMI) provides an interface allowing the 56800E core to
utilize external asynchronous devices, including memory. The 56800E core EMI operates
from the system bus.
The 56800E core EMI is implemented as a core bus peripheral. Data can be transferred
through the EMI to the 56800E core directly.
Note:
The EMI described in this document is intended to be interfaced to 16-bit wide
external memory. External arrays may be implemented either using single 16bit wide parts or pairs of 8-bit wide memories. An external data space memory
interface to the 56800E core accommodating single 8-bit wide external data
memories could be implemented (at a substantial performance penalty) with
appropriate programming of the CSOR register(s).
5.2 Features
The External Memory Interface supports the following general characteristics:
•
Can convert any internal bus memory request to a request for external memory
•
Can manage multiple internal bus requests for external memory access
•
Has up to four CSn configurable outputs for external device decoding
— Each CS can be configured for Program or Data space
— Each CS can be configured for Read only, Write only, or Read/Write access
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— Each CS can be configured for the number of Wait states required for device
access
— Each CS can be configured for the size and location of its activation
— Each CS is independently configured for setup and hold timing controls for both
read and write
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5.3 Functional Description
The DSP56800E core architecture contains three separate buses for access to memory/
peripherals. The EMI attaches to all of these buses and provides an interface to external
memory over a single external bus. The EMI serializes these internal requests to external
memory in a manner avoiding conflicts and contention.
5.3.1 Core Interface Detail
Managing the core access to the external memory consists of four issues: (Please refer to
Figure 5-1.)
1. Any of the three buses can request external access at any time. This means the EMI
can potentially have three requests it must complete before the core can proceed.
The EMI must hold off further execution of the core until it can serialize the
requests over the external bus. This provides simultaneous data for all buses to the
core for read operations.
2. There may be a mixture of read and write requests on the core buses. For instance,
the program memory bus may request a read operation while the primary data bus
(XAB1) is requesting a write operation.
3. The primary data bus (XAB1) may request an 8-bit transfer. This request must
access the appropriate external byte.
4. The primary data bus (XAB1) may request a 32-bit transfer. This request requires
two accesses of the external bus. The EMI must hold off further core execution
until all 32 bits have been transferred. This action may happen in conjunction with
item one above.
16
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5.4 Block Diagram
A simplified block diagram illustrating the connections to the EMI is illustrated in
Figure 5-1. The left side of the figure shows connections to the DSP56800E core buses
and clocks. All available external EMI signals are shown on the right side of the figure.
Freescale Semiconductor, Inc...
PRIMARY DATA ACCESS
XAB1[23:0]
XAB1[23:0]
CBW[31:0]
CDBW[31:0]
CDBR_M[31:0]
CDBR_M[31:0]
A[20:0]
SECONDARY DATA READ
D[16:0]
XAB2[23:0]
XAB2[23:0]
XDB2_m[15:0]
XDB2_M[15:0]
RD
WR
PROGRAM MEMORY ACCESS
PAB[20:0]
PAB[20:0]
CDBW[15:0]
PDB_M[31:0]
PDB_M[31:0]
CS[3:0]
HOLDOFF
CLK
C7WAITST
56800E CORE
CLOCK
GEN.
EMI
Figure 5-1. EMI Block Diagram
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5.5 Register Descriptions
The address of a register is the sum of a base address and an address offset. The base
address is $1FFE40. Registers are summarized in Table 5-1.
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Table 5-1. Register Summary
Address Offset
Register Acronym
Base + $0
CSBAR0
Chip Select Base Address Register 0
Base + $1
CSBAR1
Chip Select Base Address Register 1
Base + $2
CSBAR2
Chip Select Base Address Register 2
Base + $3
CSBAR3
Chip Select Base Address Register 3
Base + $4
Reserved
Base + $5
Reserved
Base + $6
Reserved
Base + $7
Reserved
Base + $8
CSOR0
Chip Select Option Register 0
Base + $9
CSOR1
Chip Select Option Register 1
Base + $A
CSOR2
Chip Select Option Register 2
Base + $B
CSOR3
Reserved
Base + $D
Reserved
Base + $E
Reserved
Base + $F
Reserved
Base + $10
CSTC0
Chip Select Timing Control Register 0
Base + $11
CSTC1
Chip Select Timing Control Register 1
Base + $12
CSTC2
Chip Select Timing Control Register 2
Base + $13
CSTC3
Chip Select Timing Control Register 3
Base + $14
Reserved
Base + $15
Reserved
Base + $16
Reserved
Base + $18
Chapter Location
Section 5.5.1
Section 5.5.2
Chip Select Option Register 3
Base + $C
Base + $17
18
Register Name
Section 5.5.3
Reserved
BCR
Bus Control Register
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Table 5-2. Register Map Summary
Add. Register
Offset
Name
$0
CSBAR0
$1
CSBAR1
$2
CSBAR2
$3
CSBAR3
R
W
R
W
R
W
R
W
15
14
13
12
11
10
9
8
7
6
5
4
ADR
23
ADR
22
ADR
21
ADR
20
ADR
19
ADR
18
ADR
17
ADR
16
ADR
15
ADR
14
ADR
13
ADR
12
3
2
1
BLKSZ
ADR
23
ADR
22
ADR
21
ADR
20
ADR
19
ADR
18
ADR
17
ADR
16
ADR
15
ADR
14
ADR
13
ADR
12
BLKSZ
ADR
23
ADR
22
ADR
21
ADR
20
ADR
19
ADR
18
ADR
17
ADR
16
ADR
15
ADR
14
ADR
13
ADR
12
BLKSZ
ADR
23
ADR
22
ADR
21
ADR
20
ADR
19
ADR
18
ADR
17
ADR
16
ADR
15
ADR
14
ADR
13
ADR
12
BLKSZ
0
Reserved
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Reserved
Reserved
Reserved
$8
CSOR0
$9
CSOR1
$A
CSOR2
$B
CSOR3
R
W
R
W
R
W
R
W
RWS
BYTE_EN
R/W
PS/DS
WWS
RWS
BYTE_EN
R/W
PS/DS
WWS
RWS
BYTE_EN
R/W
PS/DS
WWS
RWS
BYTE_EN
R/W
PS/DS
WWS
Reserved
Reserved
Reserved
Reserved
$10
CSTC0
$11
CSTC1
$12
CSTC2
$13
CSTC3
R
W
R
W
R
W
R
W
WWSS
WWSH
RWSS
RWSH
WWSS
WWSH
RWSS
RWSH
WWSS
WWSH
RWSS
RWSH
WWSS
WWSH
RWSS
RWSH
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
MDAR
MDAR
MDAR
MDAR
Reserved
Reserved
Reserved
Reserved
$18
BCR
R
W
R
W
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DRV
0
BMDAR
0
0
BWWS
BRWS
= Read as 0
= Reserved
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5.5.1 Chip Select Base Address Registers 0 –3 (CSBAR0–CSBAR3)
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The CSBAR registers are defined as shown in Figure 5-2. It determines the active address
range of a given CSn. The Block Size (BLKSZ) field determines the size of the memory
map covered by the CSn. This field also determines which of the address bits to use when
specifying the base address of the CSn. This encoding is detailed in Table 5-3. When the
active bits match the address and the constraints specified in the CSOR are also met, the
CSn is asserted.
The chip-select address compare logic uses only the most significant bits to match an
address within a block. The value of the base address must be an integer multiple of the
block size (i.e., the base address can be at block size boundaries only). For example, for a
block size of 64k, the base address can be 64k, 128k, 192k, 256k, 320k, etc.
Note:
The default reset value for a Chip Select Base Address (CSn) register will
enable a 32k block of external memory starting at address zero. This may be
defined to be something else for a specific chip. In such a case, the chip data
sheet will detail the specific reset value.
Note:
If an internal resource and an externally defined resource overlap (same address
and constraints), the internal resource will win the conflict.
Note:
If two externally defined resources overlap (same address and constraints),
unexpected results may occur.
Base + $0 - $3
Read
Write
RESET
15
13
12
11
10
9
8
7
6
5
4
3
ADR23 ADR22 ADR21 ADR20 ADR19 ADR18 ADR17 ADR16 ADR15 ADR14 ADR13 ADR12
0
Figure 5-2.
20
14
0
0
0
0
0
0
0
0
0
0
0
2
1
0
BLKSZ
0
0
1
1
Chip Select Base Address Registers 0–3 (CSBAR0–CSBAR3)
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Table 5-3. CSBAR Encoding of the BLKSZ Field
BLKSZ
Block Size
Address Lines Compared
0000
4K
X: ADR[23:12], P: ADR[20:12]
0001
8K
X: ADR[23:13], P: ADR[20:13]
0010
16K
X: ADR[23:14], P: ADR[20:14]
0011
32K
X: ADR[23:15], P: ADR[20:15]
0100
64K
X: ADR[23:16], P: ADR [20:16]
0101
128K
X: ADR[23:17], P: ADR[20:17]
0110
256K
X: ADR[23:18], P: ADR[20:18]
0111
512K
X: ADR[23:19], P: ADR [20:19]
1000
1M
X: ADR[23:20], P: ADR[20:20]
1001
2M
X: ADR[23:21]. All program address space decoded.
1010
4M
X: ADR[23:22]. No program address space decoded.
1011
8M
X: ADR[23:23]. No program address space decoded.
1100
16M
All data address space decoded. No program address space decoded.
1101
Reserved
No data address space decoded. No program address space decoded.
1110
Reserved
No data address space decoded. No program address space decoded.
1111
Reserved
No data address space decoded. No program address space decoded.
5.5.2 Chip Select Option Registers 0–3 (CSOR0–CSOR3)
A Chip Select Option Register (CSOR) is required for every chip select. This register
specifies operation mode of the chip select and the timing requirements of the external
memory mapped device.
Note:
The CSn logic can be used to define external memory wait states even if the
CSn pin is used as GPIO.
Note:
The CSn output can be disabled by setting either the PS/DS, R/W or BYTE_EN
fields to zero.
Base + $8 - $B
15
14
Read
13
12
11
RWS
Write
RESET
1
0
Figure 5-3.
1
10
9
8
BYTE_EN
1
1
0
0
7
R/W
0
6
5
4
3
PS/DS
0
0
0
2
1
0
1
1
WWS
1
0
1
Chip Select Option Registers 0–3 (CSOR0–CSOR3)
5.5.2.1 Read Wait States (RWS)—Bits 15–11
The RWS field specifies the number of additional system clocks, 0-30 (31 is invalid) to
delay for read access to the selected memory mapped device. The value of RWS should be
set as indicated in Section 5.6.1.
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5.5.2.2 Upper/Lower Byte Option (BYTE_EN)—Bits 10–9
The BYTE_EN field specifies whether the memory mapped device is 16 bits wide or one
byte wide. If the device is a byte wide, the option of upper or lower byte of a 16-bit word
is selectable. Table 5-4 provides the encoding of this field.
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Table 5-4. CSOR Encoding BYTE_EN Values
Value
Meaning
00
Disable
01
Lower Byte Selected
10
Upper Byte Selected
11
Both Bytes Selected
5.5.2.3 Read/Write Enable (R/W)—Bits 8–7
The Read/Write (R/W) field determines the read/write capabilities of the associated
memory mapped devices, illustrated in Table 5-5.
Table 5-5. CSOR Encoding of Read/Write Values
Value
Meaning
00
Disable
01
Write-Only
10
Read-Only
11
Read/Write
5.5.2.4 Program/Data Space Select (PS/DS)—Bits 6–5
The Program/Data Space Select (PS/DS) field determines the mapping of a chip select to
program and/or data space illustrated in Table 5-6.
Table 5-6. CSOR Encoding of PS/DS Values
Value
22
Meaning
Flash_Security_Enable = 0
Flash_Security_Enable = 1
00
Disable
Disable
01
DS Only
DS Only
10
PS Only
Disable
11
Both PS and DS
DS Only
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5.5.2.5 Write Wait States (WWS)—Bits 4–0
The Write Wait States (WWS) field specifies the number of additional system clocks 0-30
(31 is invalid) to delay for write access to the selected memory mapped device. The value
of WWS should be set as indicated in Write Timing.
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5.5.3 Chip Select Timing Control Registers 0–3 (CSTC0–CSTC3)
A Chip Select Timing Control (CSTC) register is required for every chip select. This
register specifies the detailed timing required for accessing devices in the selected
memory map. At reset, these registers are configured for minimal timing in the external
access waveforms. Therefore, these registers need only be adjusted if required by slower
memory/peripheral devices.
Base + $10-$17
Read
Write
Reset
15
14
13
12
WWSS
WWSH
0
0
0
0
11
10
RWSS
0
0
9
8
RWSH
0
0
7
6
5
4
3
0
0
0
0
0
0
0
0
0
0
2
1
0
MDAR
0
1
1
Figure 5-1. Chip Select Timing Control Registers 0–3 (CSTC0–CSTC3)
5.5.3.1 Write Wait States Setup Delay (WWSS)—Bits 15–14
The Write Wait States Setup (WWSS) field affects the write cycle timing diagram,
illustrated in Figure 5-10 and Figure 5-12. The WWSS field specifies the number of
additional system clocks to provide between the assertion of CSn and address lines and the
assertion of WR. The value of WWSS should be set as indicated in Section 5.6.2.
5.5.3.2 Write Wait States Hold Delay (WWSH)—Bits 13–12
The Write Wait States Hold WWSH) field affects the write cycle timing diagram,
illustrated in Figure 5-11 and Figure 5-13. The WWSH field specifies the number of
additional system clocks to hold the address, data, and CSn signals after the WR signal is
deasserted. The value of WWSH should be set as indicated in Section 5.6.2.
5.5.3.3 Read Wait States Setup Delay (RWSS)—Bits 11–10
The Read Wait States Setup (RWSS) field affects the read cycle timing diagram,
illustrated in Figure 5-6. The RWSS field specifies the number of additional system
clocks to provide between the assertion of CSn and address lines and the assertion of RD.
The value of RWSS should be set as indicated in Section 5.6.1.
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5.5.3.4 Read Wait States Hold Delay (RWSH)—Bits 9–8
The Read Wait States Hold (RWSH) field affects the read cycle timing diagram,
illustrated in Figure 5-7. The RWSH field specifies the number of additional system
clocks to hold the address, data, and CSn signals after the RD signal is deasserted. The
value of RWSH should be set as indicated in Section 5.6.1.
Note:
If both, the RWSS and RWSH fields are set to zero, the EMI read timing is set
for Consecutive mode. In this mode, the RD signal will remain active during
back-to-back reads from the same CSn controlled memory mapped device.
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5.5.3.5 Reserved—Bits 7–3
This bit field is reserved or not implemented. It is read as 0 and cannot be modified by
writing.
5.5.3.6 Minimal Delay After Read (MDAR)—Bits 2–0
The Minimal Delay After Read (MDAR) field specifies the number of system clocks to
delay between reading from a memory mapped device in a CSn controlled space and
reading from another device. A read followed by write also triggers this delay.
Figure 5-2 illustrates the timing issue requiring the introduction of the MDAR field. In
this diagram, CS1 is assumed to operate a slow Flash Memory in P-space while CS2 is
operating a faster RAM in X-space. In some bus contention cases, it is possible to
encounter data integrity problems where the contention is occurring at the time the data
bus is sampled.
24
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.
RAM READ
FLASH READ
INT_SYS_CLK
tCS_FLASH
tCS_FLASH
FLASH CS1
tCE
tOHZ
FLASH_DATA
tCS_RAM
tCS_RAM
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RAM CS2
BUS CONTENTION
tHZOE
tACE
RAM_DATA
Bus Contention with two devices driving data at the same time.
Figure 5-2. Data Bus Contention Timing Requiring MDAR Field Assertion
5.5.4 Bus Control Register (BCR)
The Bus Control Register (BCR) defines the default read and write timing for external
memory accesses to addresses not covered by the CS/CSOR/CSTC registers. The timing
specified by the BCR applies to both Program and Data Space accesses because the PS
and DS control signals are not directly available on the chip pinouts.
Note:
Any of the CSn signals can be configured to mirror the PS and/or DS function,
but then the associated CSn configuration registers control the timing.
Base + $18
Read
Write
Reset
15
14
DRV
0
13
12
BMDAR
0
0
0
11
10
0
0
0
1
9
8
7
6
5
4
3
BWWS
1
0
0
2
1
0
0
0
BRWS
1
0
1
1
1
Figure 5-3. Bus Control Register (BCR)
5.5.4.1 Drive (DRV)—Bit 15
The Drive (DRV) control bit is used to specify what occurs on the external memory port
pins when no external access is performed (whether the pins remain driven or are placed in
tri-state). Table 5-7 summarizes the action of the EMI when the DRV bit is cleared or is
set. DRV bit is cleared on hardware reset.
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Table 5-7. DRV Effect on EMI Pin Operation
DRV
0
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1
800E Core Operating State
Pins
A23:A0
RD, WR, CSn
D15:D0
EMI is Between External Memory Accesses
Tri-stated
Tri-stated
Tri-stated
Reset Mode
Tri-stated
Pulled High Internally
Tri-stated
EMI is Between External Memory Accesses
Reset Mode
Driven
Driven (RD, WR, CSn are Deasserted) Tri-stated
Tri-stated
Pulled High Internally
Tri-stated
5.5.4.2 Base Minimal Delay After Read (BMDAR)—Bits 14–12
The Base Minimal Delay After Read (BMDAR) field specifies the number of system
clocks to delay after reading from a memory mapped device not in CS controlled space
and reading from one in a CSn controlled space. A read followed by write also triggers
this delay. Please see the description of the MDAR field of the CSTC registers in Section
5.5.3.6 for a discussion of the function of this control.
5.5.4.3 Reserved—Bits 11–10
This bit field is reserved or not implemented. It is read as 0 and cannot be modified by
writing.
5.5.4.4 Base Write Wait States (BWWS)—Bits 9–5
The Base Write Wait States (BWWS) field specifies the number of additional system
clocks 0-30 (31 is invalid) to delay for write access to the selected memory mapped device
when the address does not fall within CS controlled range. The value of BWWS should be
set as indicated in Section 5.6.
5.5.4.5 Base Read Wait States (BRWS)—Bits 4–0
The Base Read Wait States (BRWS) field specifies the number of additional system
clocks 0-30 (31 is invalid) to delay for read access to the selected memory mapped device
when the address does not fall within CS controlled range. The value of BRWS should be
set as indicated in Section 5.6.
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5.6 Timing Specifications
5.6.1 Read Timing
5.6.1.1 Consecutive Mode Operation
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Figure 5-4 and Figure 5-5 illustrate the read timing for external memory access. For
comparison, a single read cycle is illustrated followed by a null cycle followed by a backto-back read.
Figure 5-4 assumes zero wait states are required for the access (RWS = 0). Figure 5-5
illustrates a timing diagram with one wait state added (RWS = 1).
Note:
During back-to-back reads, RD remains low to provide the fastest read cycle
time.
Note:
For all of the following timing diagrams, INT_SYS_CLK is the internal system
clock from which everything is referenced.
Read (RWS = 0)
IDLE
Read (RWS = 0)
Read (RWS = 0)
INT_SYS_CLK
A[23:0]
CS[7:0]
RD, OE
WR
D[15:0]
Data In
Data In
Data In
Figure 5-4. External Read Cycle with RWS = RWSH = RWSS = 0
.
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Read (RWS = 1)
IDLE
Read (RWS = 1)
Read (RWS = 1)
INT_SYS_CLK
A[23:0]
CS[7:0]
RD, OE
WR
Freescale Semiconductor, Inc...
D[15:0]
Data In
Data In
Time added to Figure
Data In
5-4 by setting RWS = 1
Figure 5-5. External Read Cycle with RWS = 1, RWSH = RWSS = 0
5.6.1.2 Read Setup and Hold Timing
Although most memory devices can perform consecutive reads by holding the CSn and
RD(OE) signals in the active state and changing the address, there are peripheral devices
requiring RD(OE) transition to the inactive state between reads of certain registers. This
timing can be accommodated with the Read Wait State Setup (RWSS) and/or Read Wait
State Hold (RWSH) control fields illustrated in Figure 5-6 and Figure 5-7.
Read (RWSS = RWS = 1)
IDLE
Read (RWSS = RWS = 1)
Read (RWSS = RWS = 1)
INT_SYS_CLK
A[23:0]
CS[7:0]
RD, OE
WR
D[15:0]
Data In
Data In
Data In
Time added to by setting RWSS = 1
Figure 5-6. External Read Cycle with RWSS = RWS = 1, and RWSH = 0
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Read (RWS = RWSH = 1)
IDLE
Read (RWS = RWSH = 1)
Read (RWS = RWSH = 1)
Data In
Data In
INT_SYS_CLK
A[23:0]
CS[7:0]
RD, OE
WR
Data In
D[15:0]
Freescale Semiconductor, Inc...
Time added to Figure
5-6 by setting RWSH = 1
Figure 5-7. External Read Cycle RWSH = RWS = 1 and RWSS = 0
5.6.2 Write Timing
Figure 5-8 and Figure 5-9 illustrate the write timing for external memory access. For
comparison, a single write cycle is illustrated followed by a null cycle followed by a backto-back write.
Figure 5-8 assumes zero wait states are required for the access (WWS = 0). Figure 5-9
illustrates a timing diagram with one wait state added (WWS = 1).
Note:
For all of the following timing diagrams, INT_SYS_CLK is the internal system
clock from which everything is referenced.
Write (WWS = 0)
IDLE
Write (WWS = 0) Write (WWS = 0)
IDLE
INT_SYS_CLK
A[23:0]
RD, OE
D[15:0]
CS[7:0]
WR
Figure 5-8. External Write Cycle with WWS = WWSH = WWSS = 0
Note:
When WWS = 0 the timing of the WR strobe is generated from different clock
edges than when it is set to some other value. This change in timing allows the
possibility of single cycle write operation, but reduces the pulse width of WR to
one quarter clock. This may make it difficult to meet write timing requirements
for most devices when operating at normal clock rates.
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Write (WWS = 1)
IDLE
Write (WWS = 1)
Write (WWS = 1)
IDLE
INT_SYS_CLK
A[23:0]
RD, OE
D[15:0]
CS[7:0]
Freescale Semiconductor, Inc...
WR
Time added to Figure
5-8 by setting WWS = 1
Figure 5-9. External Write Cycle with WWS = 1, WWSH = WWSS = 0
5.6.2.1 Write Setup and Hold Timing
Although most memory devices require a zero setup and hold time, there are some
peripheral devices where a setup/hold time is required. The WWSS and WWSH field of
the CSTC register provides the ability for a write setup and/or hold time requirement
illustrated in Figure 5-10, Figure 5-11, Figure 5-12, and Figure 5-13.
Since the timing of the strobes is different when WWS = 0 than it is when WWS > 0, two
sets of timing diagrams follow.
5.6.2.1.1 WWS = 0
Write
(WWSS=1,WWS=0)
IDLE
Write
Write
(WWSS=1,WWS=0) (WWSS=1,WWS=0)
IDLE
INT_SYS_CLK
A[23:0]
RD, OE
D[15:0]
CS[7:0]
WR
Time added to Figure
5-8 by setting WWSS =
Figure 5-10. External Write Cycle with WWSS = 1, WWS = WWSH = 0
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Write
Write
(WWS=0,WWSH=1)
IDLE
Write
(WWS=0,WWSH=1) (WWS=0,WWSH=1)
IDLE
INT_SYS_CLK
A[23:0]
RD, OE
D[15:0]
CS[7:0]
Freescale Semiconductor, Inc...
WR
Time added to Figure
5-8 by setting WWSH
Figure 5-11. External Write Cycle with WWSH = 1, WWS = WWSS = 0
5.6.2.1.2 WWS > 1
Write
Write
Write
(WWSS = WWS = 1) IDLE (WWSS = WWS = 1) (WWSS = WWS = 1) IDLE
INT_SYS_CLK
A[23:0]
RD, OE
D[15:0]
CS[7:0]
WR
Time added to Figure
5-9 by setting WWSS
Figure 5-12. External Write Cycle with WWSS = WWS = 1 and WWSH = 0
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Write
Write
Write
(WWS = WWSH = 1) IDLE (WWS = WWSH = 1) (WWS = WWSH = 1) IDLE
INT_SYS_CLK
A[23:0]
RD, OE
D[15:0]
CS[7:0]
Freescale Semiconductor, Inc...
WR
Time added to Figure
5-9 by setting WWSH =
Figure 5-13. External Write Cycle with WWS = WWSH = 1, WWSS = 0
5.7 Clocks
The EMI operates from clocks internal to the chip and does not require or provide clocks
external to the chip.
5.8 Interrupts
There are no interrupts generated by this module.
5.9 Resets
All reset types are equivalent for the EMI, therefore they have the same effect. The EMI
outputs during reset are controlled by the DRV bit of the BCR. During reset this bit is set
to zero. Table 5-7 defines the reset state of all EMI pins.
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The following is the complete replacement of Chapter 6. On-Chip Clock
Synthesis (OCCS)
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6.1 Introduction
The On-Chip Clock Synthesis (OCCS) module allows product design using an
inexpensive 4MHz crystal or an external clock source to run the DSP56F826 at any
frequency from 0 to 120MHz. The OCCS module is comprised of two major blocks: the
Oscillator (OSC), and the PLL/CGM (analog - Phase Locked Loop/digital - Clock
Generation Module (CGM)). The OSC output clocks feed the PLL/CGM block. The PLL/
CGM generates a time clock for Computer Operating Properly (COP) timer use. The PLL/
CGM also generates a master clock which is consumed by the System Integration Module
(SIM). The SIM generates derivative clocks for consumption by the core logic and IPBus
peripherals.
The SIM divides the MSTR_CLK (typically 240 MHz) by 2 to create the Hawk DSP core
clock (typically 120 MHz) and by 4 to create the IPBUS_CLK (typically 60 MHz). All
peripherals on the DSP56F826 run off the IPBus clock frequency. The COP and TOD
peripherals also consumes the much lower frequency TIME_CLK (typically 31.25 KHz).
The PLL may be used to generate a high frequency clock from the low-frequency crystalreferenced (or external clock driven) OSC circuit. The PLL provides an exact integer
multiple of the oscillator’s output reference frequency (Fref). The frequency
multiplication is in the range of 20 to 120.
The CGM controls the PLL’s output frequency. The CGM also selects between the PLL
(PLL_OUT) and OSC (Fref) as potential master clock sources and routes the selection to
the SIM. The CGM also contains circuitry to detect if the PLL is unlocked and generates
an interrupt signal for the condition.
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OSC
Oscillator
Loss_Of_Lock_Interrupt
PLL / CGM
Fref
(4 MHz)
IP B U S _ C L K
(6 0 M H z )
COP
Phase Locked Loop
Clock Generation Module
PLL_OUT
(240 MHz)
(60 MHz)
SIM
1
EXTAL
4 MHz
Ftime
(31.25 KHz)
P LL _ S H U T D O W N *
O S C _L O P W R *
(4 MHz)
Time Of Day
TIME_CLK (31.25 KHz)
XTAL
System
Integration
Module
(120 MHz)
HAWK
DSP Core
Freescale Semiconductor, Inc...
divide
by 4
OCCS
CGMCR[SEL]
On-Chip Clock Synthesis
CLKOUT (30 MHz)
IPBB
IP Bus Bridge
0
MSTR_CLK
other peripherals
BOLD represents default states or typical
conditions.
* see STOP Mode Features for further details
Figure 6-14. OCCS Integration Overview
Out of reset, the CGMCR[SEL] control bit is 0, selecting the Fref path as the source of
MSTR_CLK. The core will proceed to execute code using a clock divided down from the
oscillator’s Fref output. The core will run at Fref/2 and the IPBUS_CLK will run at Fref/4.
Among the first things applications typically do is turn on the PLL, wait for lock
indication and set CGMCR[SEL] to 1, enabling high speed operation.
6.1.1 OCCS Features
34
•
OSC connects to external crystals in the range of 2 to 4 MHz
•
OSC can optionally accept an external active clock (0 to 240 MHz)
•
PLL generates any integer multiple frequency, allowing DC to 120 MHZ execution
•
CGM provides glitch-free transition between OSC and PLL clock sources
•
CGM provides digital loss of lock detection
•
Ultra Low Power modes are available while COP timer and TOD are kept alive
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6.2 OSC (Oscillator) Circuit Detail
Oscillator
Bandwidth limited
to 4 MHz
(1)
. 128
.
PLL / CGM
Ftime
(31.25 KHz)
0
EXTAL
CL1
TIME_CLK (31.25 KHz)
Rbias
. CGMTOD[TOD]
.
XTAL
CL2
Rs
Freescale Semiconductor, Inc...
BOLD represents default states and typical
conditions.
OSC_LOPWR
Notes (1) & (2)
Fref
(4 MHz)
.
.
2
1
4 MHz
TIME_CLK feeds
the TOD and COP
watchdog timer.
CGMCR[TOD_SEL]
“0” is default path
Note (1)
1) See STOP Mode Features for further details
2) When OSC_LOPWR is asserted, this grayed
portion of the OCCS is disabled. OSC_LOPWR
assertion is prevented whenever CGMCR[TOD_SEL]
= 1. This automatic interlock prevents TIME_CLK from
being killed accidentally.
Figure 6-15. OSC Supplying Clocks to PLL/CGM
A typical connection for the OSC module is shown above. The weak differential signal
coming in directly from EXTAL/XTAL pin pair is routed to a very low power differential
amplifier. Because the amplifier is so low in power, it has a usable bandwidth limit
somewhat above just 4 MHz. The resulting clock frequency is divided down by a fixed
value of 128 to yield a 31.25 KHz clock. Out of reset, the register CGMCR[TOD_SEL] is
0, so this is the path selected through the mux to create the TIME_CLK used by the COP
and TOD. If the signal present on XTAL is above 4 MHz (e.g. driven by an external active
clock) then it is necessary to set CGMCR[TOD_SEL] to 1.
The signal from XTAL is buffered up (becoming Fref) and is consumed everywhere else.
6.2.1 Using an External Crystal
The figure below shows the typical application details for using an external crystal. A
4MHz, AT cut, parallel resonant crystal is mounted across XTAL and EXTAL pins. A 1
Mohm bias resistor is paralleled to that connection. The default path for TIME_CLK
generation (the differential amplifier path) is recommended and therefore CGMCR[TOD]
register setting is a don’t care. Please see Section 6.2.4 for further details.
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Bandwidth
limited
to 4 MHz
(1)
.. 128
Ftime
(31.25 KHz)
0
EXTAL
CL1
CL2
1 Mohm
.
.
XTAL
Rs
.
.
TIME_CLK (31.25 KHz)
1
4 MHz
Note (2)
2
CGMCR[TOD] = (don’t care)
BOLD represents default states and typical
conditions.
OSC_LOPWR
Notes (1)
Fref
(4 MHz)
CGMCR[TOD_SEL] = 0
Note (1)
Freescale Semiconductor, Inc...
1) See STOP Mode Features for further
details
2) AT cut quartz crystal or ceramic
resonator. Crystal vendor to supply values
for Rs, CL1 and CL2
Figure 6-16. Using an External Crystal
The values of Rs, CL1 and CL2 are determined with assistance of your crystal
manufacturer. In general, CL1 and CL2 are used to pull the crystal to the intended
frequency and establish the Equivalent Series Resistance (ESR). Rs is used to kill off
some of the inverter’s gain (by an amount appropriate for the resulting ESR).
Note:
36
The CGMCR register’s TOD_SEL field may be set to either 0 or 1. The
recommended setting of 0 allows very low power operation when executing a
STOP instruction.
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6.2.2 Using an External Active Clock Source Below 4 MHz
When using an external active clock source of a frequency less then or equal to 4 MHz
then the connections shown below are recommended. Here the EXTAL pin is biased to
1.65 V and XTAL is driven with a 0 to 3.3 V square wave clock signal. The TIME_CLK
source path is the same as above, using the fixed divide by 128 block and channel 0 of the
mux.
Bandwidth limited
to 4 MHz
(1)
. 128
.
Ftime
(31.25 KHz)
Low Frequency Digital Clock
(4 MHz)
0
.
.
XTAL
.
.
TIME_CLK (31.25 KHz)
2
1
Freescale Semiconductor, Inc...
EXTAL
CGMCR[TOD] = (don’t care)
BOLD represents default states and typical
conditions.
OSC_LOPWR
Notes (1)
Fref
(4 MHz)
CGMCR[TOD_SEL] = 0
Note (1)
1) See STOP Mode Features for further
details
Figure 6-17. Using an External Active Low Frequency Clock, < 4 MHz
Note:
The CGMCR register’s TOD_SEL field may be set to either 0 or 1. The
recommended setting of 0 allows very low power operation when executing a
STOP instruction. If however a setting of 1 is used, then EXTAL can be tied to
ground, to mid-rail (as shown), or high. If TOD_SEL is set to 1, then the
optimal connection of EXTAL is to ground.
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6.2.3 Using an External Active Clock Source Above 4 MHz
When using an external active clock source that is of a higher frequency than 4 MHz (up
to 240 MHz is allowable) the settings detailed below should be used.
The amplifier’s bandwidth is limited to 4 MHz, so its
output is invalid in a High Frequency input scenario.
CGMCR[TOD] must be set to 1 and the CGMCR[TOD]
divider must be set to a reasonable value in order to
enable a valid TIME_CLK signal.
(1)
.
.
128
Ftime
(invalid signal)
Freescale Semiconductor, Inc...
High Frequency Digital Clock
(30 MHz)
0
EXTAL
XTAL
..
TIME_CLK (31.25 KHz)
1
..
2
CGMCR[TOD] = 480
OSC_LOPWR
Notes (1)
BOLD represents default states and typical
conditions.
Fref
(30 MHz)
CGMCR[TOD_SEL] = 1
Note (1)
1) See STOP Mode Features for further details
Figure 6-18. Using an External Active High Frequency Clock, > 4 MHz
Since the differential amplifier is band limited to just over 4 MHz, in this example the
default TIME_CLK path’s divide by 128 counter will no longer have an adequate signal
for proper operation. Instead, the user programmable divide by circuit should be used.
This requires correct setting of both the CGMCR[TOD] and [TOD_SEL] register fields as
shown in the figure.
In this particular example, the externally applied clock, and hence Fref are running at 30
MHz. This requires TOD_SEL be set to 1 and the TOD register set to 480. The input
frequency of 30 MHz divided down by 480 and then again by a fixed value of 2 yields the
desired 31.25 KHz TIME_CLK frequency.
Note:
With the CGMCR register’s TOD_SEL field set to 1, EXTAL can be tied to
ground (as shown), to mid-rail, or high. The optimal connection of EXTAL is to
ground.
6.2.4 STOP Mode Features
In an attempt to conserve power, applications may power the device down by executing
STOP or WAIT instructions. The DSP5685x OCCS module supports three variants of
STOP mode processing.
1. Case where CGMCR[TOD_SEL] = 0
A STOP instruction will result in the MSTR_CLK clock source being forced back
to Fref and the PLL being powered down (PLL_SHUTDOWN asserts. If
CGMCR[TOD_SEL] is 0, then OSC_LOWPWR will assert, bringing the OSC
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module into its lowest power alive state. Only the inverter, differential amplifier
and the fixed divide by 128 block remain enabled, but that is enough to keep
TIME_CLK and the associated COP counter alive and running. Fref is held
quiescent.
When waking up from this "deep stop", the PLL will need to be re-started, lock
status re-queried and the PLL output re-selected to source MSTR_CLK.
Freescale Semiconductor, Inc...
2. Case where CGMCR[TOD_SEL] =1
A STOP instruction will result in the MSTR_CLK clock source being forced back
to Fref and the PLL being powered down (PLL_SHUTDOWN asserts). If
CGMCR[TOD_SEL] is 1 when the STOP instruction is executed, then the SIM
will not assert OSC_LOWPWR for in doing so, the TIME_CLK (and COP) would
be killed. This is usually an undesirable situation from an applications perspective.
3. Fast STOP Recovery
A Fast STOP Recovery is available in which neither the OSC_LOWPWR or
PLL_SHUTDOWN signal are asserted. As such, no time is required to re-start the
PLL, but it comes at the cost of increased power consumption by the PLL during
STOP. Fast Stop Recovery is available by setting the OMR register’s bit 6 to 1.
For further details on STOP and Fast STOP Recovery, please see Section 4.9, Power
Mode Controls.
6.3 PLL (Phase Locked Loop) Circuit Detail
Fref
UP
Phase/Freq
Detector
Charge
Pump
PLL_OUT
Loop
Filter
VCO
POSTSCALER
DOWN
Down Counter
(n = 19 to 119)
Lock Detector
(part of CGM)
VCO_OUT
Loss of Lock Interrupt
Figure 6-19. PLL Block Diagram
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6.3.1 Phase Frequency Detector
The Phase Frequency Detector (PFD) compares the clock signal from the feedback divider
to the input clock. When the input clock comes before the feedback clock the PFD
generates a down pulse signal. The down pulse signal continues until the feedback clock
signal arrives. If the feedback clock arrives at the PFD before the input clock, the PFD
generates an up pulse, continuing until the input clock signal arrives.
Freescale Semiconductor, Inc...
6.3.2 Charge Pump
The Charge Pump draws charge into or out of the Loop Filter depending upon the signals
from the Phase Frequency Detector. As charge is added to the Loop Filter the VCO
control voltage increases. As charge is pulled out of the Loop Filter, the VCO control
voltage decreases.
6.3.3 Loop Filter
The Loop Filter produces a voltage proportional to the amount of charge pumped into or
out of the Loop Filter by the charge pump. The Loop Filter is a single pole RC filter.
6.3.4 Voltage Controlled Oscillator
The Voltage Controlled Oscillator (VCO) produces a frequency inversely proportional to
the value of the control voltage signal coming out of the Loop Filter. The VCO gain is
approximately 109MHz/Volt. The VCO has a frequency range of 80MHz to 380MHz with
a center frequency of 240MHz.
6.3.5 Down Counter
The Down Counter is a programmable divide by n counter where the divide integer n is
user-set to develop the PLL output frequency of interest. By presenting only one return
pulse out of n input pulses to the return clock of the phase frequency detector, the PFD
will drive the charge pump to raise the VCO frequency until the Down Counter return
signal is in frequency and phase lock with the input clock signal. The output of the VCO
will, therefore, be n times the frequency of the input clock signal. The value of n has a
valid range of 19 to 119. The selected value of n depends upon the desired VCO output
frequency and the input clock frequency (Fref). For the 2MHz input crystal the valid range
of n will range from 39 to 119, producing a VCO frequency output of 80MHz to 240MHz
according to the formula:
Fvco_out = Fref × (n+1)
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The VCO’s output frequency is routed through a postscaler so the final PLL output
frequency is given by:
Fpll_out = Fvco_out / 2m
where m is the value on the postscaler and can range from 0 to 7.
Example: Let Fref = 32 MHz, n = 4, and m = 3, using the formulas gives:
Fpll_out = (32 MHz × (4+1)) / 8
Freescale Semiconductor, Inc...
Fpll_out = 20MHz.
For the 4MHz input crystal the valid range of n will be from 19 to 59, producing the same
VCO output range, 80MHz to 240MHz.
6.3.6 PLL Lock Time User Notes
The PLL’s Voltage Controlled Oscillator (VCO) has a characterized operating range
extending from 80MHz to 240MHz. The PLL is programmable via a divide by n+1
register, able to take on values varying between 1 and 128. For higher values of n, PLL
lock time becomes an issue. It is recommended to avoid values of n resulting in the VCO
frequency being greater than 240MHz. The graphic in Figure 6-10 depicts the range of
recommended output frequencies of VCO_OUT, plotting n versus the input frequency
(Fref). The lower the value of n, the quicker the PLL will be able to lock.
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1000
Fvco_out = 80
CGMDB[PLLDB] or "n"
Freescale Semiconductor, Inc...
Fvco_out = 240
The recommended VCO output range is bounded by
a high frequency of 240 MHz and a low frequency of
80 MHz. The lower the value of CGMDB[PLLDB]
("n"), the faster the lock time for the PLL.
100
10
1
0
5
10
15
20
25
30
35
40
Fref [MHz]
Figure 6-20. PLL Output Frequency vs. Input Frequency
The lock time of the PLL is, in many applications, the most critical PLL design parameter.
Proper use of the PLL ensures the highest stability and lowest lock time.
6.3.6.1 PLL Lock Time Determination
Typical control systems refer to the lock time as the reaction time, within specified
tolerances, of the system to a step input. In a PLL the step input occurs when the PLL is
turned on or when it suffers a noise hit. The tolerance is usually specified as a percent of
the step input or when the output settles to the desired value plus or minus a percent of the
frequency change. Therefore, the reaction time is constant in this definition regardless of
the size of the step input.
When the PLL is coming from a powered down state (PDN is high) to a powered up
condition (PDN is low) the maximum lock time is 10msec.
Other systems refer to lock time as the time the system takes to reduce the error between
the actual output and the desired output to within specified tolerances. Therefore, the lock
time varies according to the original error in the output. Minor errors may be shorter or
longer in many cases.
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6.3.6.2 PLL Parametric Influences on Reaction Time
Lock time is designed to be as short as possible while still providing the highest possible
stability. Many factors directly and indirectly affect the lock time.
Freescale Semiconductor, Inc...
The most critical parameter affecting the reaction time of the PLL, is the Reference
Frequency (Fref). This frequency is the input to the phase detector and controls how often
the PLL makes corrections. For stability, the corrections must be small compared to the
desired frequency, so several corrections are required to reduce the frequency error.
Therefore, the slower the reference frequency (Fref), the longer it takes to make these
corrections.
Temperature and processing also can affect acquisition time because the electrical
characteristics of the PLL change. The part operates as specified as long as these
influences stay within the specified limits.
6.4 CGM Functional Detail
The CGM controls the PLL, detects PLL lock, and is used to generate the master clock to
the SIM. The CPU clock is one half the frequency of the master clock and the IPBus clock
is one fourth the frequency. The SIM handles these clock divisions. The master clock
source can be either the oscillator output or the analog PLL output. The oscillator output
(Fref) will typically be 4MHz, but a faster active clock can be driven into the XTAL pin at
speeds of up to 240MHz. The PLL output can be up to 240MHz.
In order to use the PLL, the proper divide by factor and post scaler values should be
programmed into the CGMDB register. Next, the PLL is turned-on by setting the PowerDown (PDN) bit in the CGMCR to zero. The user should then wait for the PLL to achieve
lock before changing the SEL bit to select the PLL output as the master clock.
6.4.1 PLL Frequency Lock Detector
This CGM function monitors the VCO output clock and sets the LCK1 and LCK0 bits in
the CGM Control register based on the frequency accuracy. The lock detector is enabled
with the LCKON bit of the CGMCR as well as the PDN bit. Once enabled, the detector
starts two counters whose outputs are periodically compared. The input clocks to these
counters are the VCO output clock divided by the divide-by factor, feedback, and the
crystal reference clock, Fref. The period of the pulses being compared cover one whole
period of each clock because the feedback clock doesn’t guarantee a 50 percent duty
cycle.
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Counts are compared after 16, 32, and 64 cycles. If the counts match after 32 cycles, the
LCK0 bit is set to one. If the counts match after 64 cycles, the LCK1 bit is also set. The
LCK bits stay set until the counts fail to match or if a new value is written to the PLLDB
field or on reset caused by LCKON, PDN, or chip level reset. When the circuit sets LCK1,
the two counters are reset and start the count again. The lock detector is designed so if
LCK1 is reset to zero because the counts did not match when checked after 64 cycles, the
LCK0 bit can remain high if the counts matched after 32 cycles. This provides the
processor the accuracy of the two clocks with respect to each other.
Freescale Semiconductor, Inc...
6.5 CGM Module Memory Map
The base address of the CGM is $1FFF10.
Table 6-8.
Address
CGM Memory Map
Register Name
$1FFF10 + $0
Access
Control Register (CGMCR)
Read/Write
$1FFF10 + $1
Divide By Register (CGMDB)
Read/Write
$1FFF10 + $2
Time of Day Register (CGMTOD)
Read/Write
6.6 Register Descriptions (CGM_BASE = $1FFF10)
6.6.1 Clock Generation Module (CGM) Control Register
$1FFF10 + $0
15
14
Read
0
0
0
0
Write
RESET
13
12
LCK1 LCK0
0
0
11
SEL
0
10
9
8
7
0
0
0
0
0
0
0
0
6
5
4
3
LCK1_IE
LCK0_IE
0
0
0
0
2
1
0
LCKON TOD_SEL PDN
0
0
1
Figure 6-21. CGM Control Register (CGMCR)
See Programmer’s Sheet on Appendix page B-21
6.6.1.1 Reserved—Bits 15–14
This bit field is reserved or not implemented. It is read as 0, and cannot be modified by
writing.
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6.6.1.2 Lock 1 Status (LCK1)—Bit 13
This bit shows the status of the lock detector state for the LCK1 circuit. Changes in the
state of this bit can be used to cause interrupts in conjunction with the LCK1 Interrupt
Enable bits. The LCK1 interrupt is cleared by writing a one to this bit.
•
0 = PLL not locked
•
1 = PLL locked
Freescale Semiconductor, Inc...
6.6.1.3 Lock 0 Status (LCK0)—Bit 12
This bit shows the status of the lock detector state for the LCK0 circuit. Changes in the
state of this bit can be used to cause interrupts in conjunction with the LCK0 Interrupt
Enable bits. The LCK0 interrupt is cleared by writing a one to this bit.
•
0 = PLL not locked
•
1 = PLL locked
6.6.1.4 Clock Source Select (SEL)—Bit 11
This bit is used to control the source of the master clock to the SIM.
•
0 = Oscillator output selected by default
•
1 = PLL output selected
6.6.1.5 Reserved—Bits 10–7
This bit field is reserved or not implemented. It is read as 0, and cannot be modified by
writing.
6.6.1.6 Lock 1 Interrupt Enable (LCK1_IE)—Bits 6–5
An optional interrupt can be generated if the PLL lock status bit (LCK1) changes.
•
00 = Disable interrupt by default
•
01 = Enable interrupt on rising edge of LCK1
•
10 = Enable interrupt on falling edge of LCK1
•
11 = Enable interrupt on any edge of LCK1
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6.6.1.7 Lock 0 Interrupt Enable (LCK0_IE)—Bits 4–3
Freescale Semiconductor, Inc...
An optional interrupt can be generated if the PLL Lock (LCK0) status bit changes.
•
00 = Disable interrupt by default
•
01 = Enable interrupt on rising edge of LCK0
•
10 = Enable interrupt on falling edge of LCK0
•
11 = Enable interrupt on any edge of LCK0
6.6.1.8 Lock Detector On (LCKON)—Bit 2
• 0 = Lock detector disabled by default
•
1= Lock detector enabled
6.6.1.9
Time-of-Day Clock Source Select (TOD_SEL)—Bit 1
This bit is used to select between two possible TIME_CLK sources. The oscillator can
generate the TIME_CLK only when the input clock on either the EXTAL or XTAL pins in
4MHz or less. When driving high speed clocks into XTAL, the CGM must generate the
TIME_CLK using the CGMTOD register. This bit is only reset by Power-On Reset (POR)
conditions.
•
0 = TIME_CLK is generated by oscillator as default
•
1 = TIME_CLK is generated by CGM
6.6.1.10 PLL Power-Down (PDN)—Bit 0
The PLL can be turned off by setting the PDN bit to one. There is a four IPBus clock delay
from changing the bit to signaling the PLL. When the PLL is powered down, the clock
select logic automatically switches to the oscillator output in order to prevent loss of clock
to the core.
•
0 = PLL turned on
•
1 = PLL powered down by default
6.6.2 Clock Generation Module (CGM) Divide-By Register
$1FFF10 + $1
15
Read
13
POST
Write
RESET
14
0
0
0
12
11
10
9
8
7
0
0
0
0
0
0
0
0
0
0
0
0
6
5
4
3
2
1
0
0
1
1
PLLDB
0
1
1
1
Figure 6-22. CGM Divide-By Register (CGMDB)
See Programmer’s Sheet on Appendix page B-23
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6.6.2.1 PLL Post Scaler (POST)—Bits 15–13
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The output of the PLL is postscaler by one to 128 based on this field. When changing this
field, it is recommended the SEL bit is set to choose the oscillator output, changing this
field, then the SEL bit is returned to selecting the PLL’s postscaler output.
•
000 = PLL output is divided by one by default
•
001 = PLL output is divided by two
•
010 = PLL output is divided by four
•
011 = PLL output is divided by eight
•
100 = PLL output is divided by 16
•
101 = PLL output is divided by 32
•
110 = PLL output is divided by 64
•
111 = PLL output is divided by 128
6.6.2.2 Reserved—Bits 12–7
This bit field is reserved or not implemented. It is read as 0, and cannot be modified by
writing.
6.6.2.3 PLL Divide-By (PLLDB)—Bits 6–0
The VCO output frequency is controlled by the PLL divide-by value. Each time a new
value is written into the PLLDB field, the Lock Detector circuit is reset. Before changing
the divide-by value, it is recommended the SEL bit be set to choose the oscillator output.
The VCO output frequency is determined by using the following formula:
Fvco_out = Fref × (PLLDB + 1)
6.6.3 Clock Generation Module (CGM) Time-of-Day Register
$1FFF10 + $2
15
14
13
12
Read
0
0
0
0
0
0
0
0
11
10
9
8
7
6
4
3
2
1
0
0
0
0
0
0
0
TOD
Write
RESET
5
0
0
0
0
0
0
Figure 6-23. CGM Time-of-Day Register (CGMTOD)
See Programmer’s Sheet on Appendix page B-24
6.6.3.1 Reserved—Bits 15–12
This bit field is reserved or not implemented. It is read as 0, and cannot be modified by
writing.
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6.6.3.2 TOD Scale Factor (TOD)—Bits 11–0
The output of the oscillator is divided by (TOD + 1) and then divided by 2, generating the
TIME_CLK used by the COP module when TOD_SEL is high. The value of TOD should
be chosen to result in a TOD clock frequency in the range of 15.12KHz to 31.25KHz. This
register is only reset during Power-On Reset (POR).
6.7 OCCS Resets
Freescale Semiconductor, Inc...
The CGM registers are reset by a chip level reset. This forces all registers to their reset
state and selects the oscillator output as the master clock source for the SIM.
6.8 OCCS Interrupts
The CGM generates a single interrupt request to the INTC. This interrupt is generated by
the lock detector circuitry LCK0 and LCK1 outputs and is enabled by the LCK0 Interrupt
Enable and LCK1 Interrupt Enable bits in the CGMCR. This interrupt can be used to detect
when the PLL goes into lock or when it falls out of lock. The interrupt is cleared by writing
a 1 to the LCK0 and/or LCK1 bits of the CGMCR.
The following addition refers to the new entry on Page 7-3, Add New Section
after Section 7.1
7.2 Features
•
The circuit monitors both the core power supply and peripheral power supply
•
Holds a wide chip reset once either of these supply voltages are below the
thresholds
•
Generates the address of the reset vector provided to the core after exit Reset
•
The address of reset vector (same as the COP Reset) is located at $1F0000
The COP module design includes these features:
•
Programmable timeout period = (COP_PRESCALER × (CT + 1)) oscillator clock
cycles, where CT can be from $0000 to $FFFF
•
Programmable Wait and Stop mode operations
•
COP timer is disabled while host CPU is in Debug mode
Re-number Section 7.3 to 7.4.
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The following addition refers to entry Page 7-4, New Section after Sec.7.4
7.5 Computer Operating Properly (COP) Module
Freescale Semiconductor, Inc...
The Computer Operating Properly (COP) module is used to help software recover from
runaway code. The COP is a free-running down counter, once enabled is designed to
generate a Reset upon reaching zero. Software must periodically service the COP in order
to clear the counter and prevent a reset.
7.5.1 COP Functional Description
When the COP is enabled, each positive edge of OSCCLK will cause the counter to
decrement by one. If the count reaches a value of $0000, then the COP_RST signal is
asserted and the chip is reset. In order for the CPU to show it is operating properly, it must
perform a service routine prior to the count reaching $0000. The service routine consists
of writing $5555 followed by $AAAA to COPCTR.
7.5.2
Timeout Specifications
The COP uses a 16-bit counter, being clocked by the crystal oscillator clock prescaled by
COP_PRESCALER. This value is set in hardware and varies per design family. For the
following example, the COP_PRESCALER is set to 128.
Table 7-1. COP Timeout Ranges as a Function of Oscillator Frequency
CT
2MHz
4MHz
$0000
64 µsec
32 µsec
$FFFF
4.2 sec
2.1 sec
Table 7-1 presents the range of timeout values supported as a function of oscillator
frequency.
For a crystal operating at 4 MHz the clock to the COP counter will be 31.25 KHz. The
value of the COPTO register can be programmed from 1 to 65535 giving a timeout period
range from 32 µsec minimum to 2.1 sec maximum.
7.5.3
COP After Reset
COPCTL is cleared out of reset. Thus the counter is disabled by default. In addition,
COPTO is set to it’s maximum value of $FFFF during reset so the counter is loaded with a
maximum timeout period when reset is released.
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7.5.4
Wait Mode Operation
If both CEN and CWEN are set to one and the Wait mode is entered, the COP counter will
continue to count down. If either CEN or CWEN is set to zero when Wait mode is entered,
the counter will be disabled and will reload using the value in the COPTO register.
7.5.5
Stop Mode Operation
Freescale Semiconductor, Inc...
If both CEN and CSEN set to one and the Stop mode is entered, the COP counter will
continue to count down. If either CEN or CSEN is set to zero when Stop mode is entered,
the counter will be disabled and will reload using the value in the COPTO register.
7.5.6
Debug Mode Operation
The COP counter does not count when the chip is in the Debug mode. Additionally, the
CEN bit in the COPCTL always reads as zero when the chip is in the Debug mode. The
actual value of CEN is unaffected by debug however, and it resumes it’s previously set
value upon exiting Debug.
7.6
Modes of Operation
The COP module design contains two major modes of operation:
•
Functional Mode
The COP by default is in this mode and will remain in this mode for as long as the
SCANTESTMODE input remains low.
•
Debug Mode
The COP timer is stopped while the processor is in the Debug mode. If the COP is
enabled, the timer will resume, counting upon exiting Debug mode. The CEN bit in
COPCTL register always reads as zero when in the Debug mode, even when it has
a value of one.
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7.7
Block Diagram
OSCCLK
IPBus CLK
IPBus
I/F
Freescale Semiconductor, Inc...
IPBus
Registers
Counter
COP_RST
Figure 7-1. COP Module Block Diagram and Interface Signals
7.8
Pin Description
The COP module primarily interfaces to the IPBus. There are no chip I/O interfaces driven
directly by this module.
7.9
Internal Module I/O Pin Definitions
Table 7-2. COP Module Interface Signals
Signal Name
Signal
Type
Reset
State
RD_DATA_Z[15:0]
Output
$0000
COP_RST
Output
1
CLK
Input
Driven
IPBus clock
OSCCLK
Input
Driven
Prescaled clock from oscillator
Function
IPBus read data bus
Timeout reset, active low
RST
Input
0
Asynchronous active low reset signal
MODULE_EN
Input
1
IPBus module enable
DBUG_SESS
Input
1
DSP5685x core is in Debug mode
WAIT_MODE
Input
0
Chip is in Wait mode
STOP_MODE
Input
0
Chip is in Stop mode
ADDR[1:0]
Input
R/W
Input
1
WR_DATA[15:0]
Input
$0000
SCANTESTMODE
Input
0
MOTOROLA
IPBus address bus
IP bus transaction type indicator
0=Write, 1=Read
IP bus write data bus
Chip is in Scan Test mode
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7.10 Module Memory Map
Freescale Semiconductor, Inc...
Table 7-3. COP Module Memory Map (COP_BASE = $1FFFD0)
Address
Register Name
Access
COP_BASE + $0
Control Register (COPCTL)
Read/Write
COP_BASE + $1
Timeout Register (COPTO)
Read/Write
COP_BASE + $2
Counter Register (COPCTR)
Read/Write
7.11 Register Descriptions (COP_BASE = $1FFFD0)
7.11.1 COP Control Register (COPCTL)
$1FFFD0
15
14
13
12
11
10
9
8
7
6
5
Read
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
4
3
2
BYPS CSEN CWEN
1
0
CEN
CWP
0
0
Write
RESET
0
0
0
Figure 7-3. COP Control Register (COPCTL)
7.11.1.1Reserved—Bits 15–5
This bit field is reserved or not implemented. Each bit in the field is read as zero, but
cannot be modified by writing.
7.11.1.2 Bypass (BYPS)—Bit 4
This bit is intended for factory use only. Setting this bit allows testing time of the COP to
be accelerated by routing the IPBus clock to the counter instead of the OSCCLK. This bit
should not be set during normal operation of the chip. If this bit is used, however, it should
only be changed while the CEN bit is set to zero.
•
0 = Counter uses OSCCLK (default)
•
1 = Counter uses IPBus clock
7.11.1.3 COP Stop Mode Enable (CSEN)—Bit 3
This bit controls the operation of the COP counter in the Stop mode. This bit can only be
changed when the CWP bit is set to zero.
•
52
0 = COP counter will stop in the Stop mode (default)
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•
1 = COP counter will run in the Stop mode if CEN is set to one
7.11.1.4 COP Wait Mode Enable (CWEN)—Bit 2
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This bit controls the operation of the COP counter in the Wait mode. This bit can only be
changed when the CWP bit is set to zero.
•
0 = COP counter will stop in the Wait mode (default)
•
1 = COP counter will run in the Wait mode if CEN is set to one
7.11.1.5 COP Enable (CEN)—Bit 1
This bit controls the operation of the COP counter. This bit can only be changed when the
CWP bit is set to zero. This bit always reads as zero when the chip is in the Debug mode.
•
0 = COP counter is disabled (default)
•
1 = COP counter is enabled
7.11.1.6 COP Write Protect (CWP)—Bit 0
This bit controls the write protection feature of the COP Control (COPCTL) register and
the COP Timeout (COPTO) register. Once set, this bit can only be cleared by resetting the
module.
•
0 = COPCTL and COPTO are readable and writable (default)
•
1 = COPCTL and COPTO are read only
7.11.2
COP Timeout Register (COPTO)
$1FFFD1
15
14
13
12
11
10
9
Read
7
6
5
4
3
2
1
0
1
1
1
1
1
1
1
TIMEOUT
Write
RESET
8
1
1
1
1
1
1
1
1
1
Figure 7- 4. COP Timeout Register (COPTO)
7.11.2.1 COP Timeout Period (TIMEOUT)—Bits 15–0
The value in this register determines the timeout period of the COP counter. TIMEOUT
should be written before the COP is enabled. Once the COP is enabled, the recommended
procedure for changing TIMEOUT is to disable the COP, write to COPTO, then re-enable
the COP, ensuring the new TIMEOUT is loaded into the counter. Alternatively, the CPU
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can write to COPTO, then write the proper patterns to COPCTR, causing the counter to
reload with the new TIMEOUT value. The COP counter is not reset by a write to COPTO.
Changing TIMEOUT while the COP is enabled will result in a timeout period differing
from the expected value. These bits can only be changed when the CWP bit is set to zero.
7.11.3
$1FFFD2
COP Counter Register (COPCTR)
15
14
13
12
11
10
9
8
Freescale Semiconductor, Inc...
Write
RESET
7
6
5
4
3
2
1
0
1
1
1
1
1
1
1
COUNT
Read
SERVICE
1
1
1
1
1
1
1
1
1
Figure 7-5. COP Counter Register (COPCTR)
7.11.3.1 COP Count (COUNT)—Bits 15–0
This is the current value of the COP counter as it counts down from the timeout value to
zero. A reset is issued when this count reaches zero.
7.11.3.2 COP Service (SERVICE)—Bits 15–0
When enabled, the COP requires a service sequence be performed periodically in order to
clear the COP counter and prevent a reset from being issued. This routine consists of
writing $5555 to the COPCTR followed by writing $AAAA before the timeout period
expires. The writes to COPCTR must be performed in the correct order, but any number of
other instructions, and writes to other registers, may be executed between the two writes.
7.12
Clocks
The COP timer base is the oscillator clock divided by a fixed prescaler value. The
prescaler divisor for this chip is 128. All register timing is with regard to the IPBus clock.
7.13
Resets
Any system reset forces all registers to their reset state, clearing the RST signal when it is
asserted. The counter will be loaded with its maximum value of $FFFF, but it will not start
when Reset is released because the CEN bit is disabled by default.
7.14
Interrupts
The COP module does not generate any interrupts. It does generate the RST signal when
the counter reaches a value of $0000, causing a chip wide reset.
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The following addition refers to entry Page 8-7, Table 8-3.
Table 8-3. Interrupt Vector Table Contents
Freescale Semiconductor, Inc...
Vector
Peripheral Number
Priority
Level
Vector
Base
Address +
Interrupt Function
0
Reserved
1
Reserved
core
2
3
P:$04
Illegal Instruction
core
3
3
P:$06
SW interrupt 3
core
4
3
P:$08
HW Stack Overflow
core
5
3
P:$0A
Misaligned Long Word Access
core
6
1-3
P:$0C
EOnCE Step Counter
core
7
1-3
P:$0E
EOnCE Breakpoint Unit 0
core
EOnCE Breakpoint Unit 1
8
1-3
P:$10
core
9
1-3
P:$12
EOnCE Trace Buffer
core
10
1-3
P:$14
EOnCE Transmit Register Empty
core
11
1-3
P:$16
12
EOnCE Receive Register Full
Reserved
13
Reserved
core
14
2
P:$1C
SW Interrupt 2
core
15
1
P:$1E
SW Interrupt 1
core
16
0
P:$20
SW Interrupt 0
core
17
0-2
P:$22
IRQA
core
18
0-2
P:$24
IRQB
Reserved
0-2
P:$28
PLL Loss Of Lock
Reserved
19
PLL
20
21
DMA
22
0-2
P:$2C
DMA_DONE 0
DMA
23
0-2
P:$2E
DMA_DONE 1
DMA
24
0-2
P:$30
DMA_DONE 2
DMA
25
0-2
P:$32
DMA_DONE 3
DMA
26
0-2
P:$34
DMA_DONE 4
DMA
27
0-2
P:$36
DMA_DONE 5
ESSI 0
28
0-2
P:$38
ESSI 0 Receive Data with Exception Status
ESSI 0
29
0-2
P:$3A
ESSI 0
30
0-2
P:$3C
ESSI 0 Receive Data
ESSI 0 Receive Last Slot
ESSI 0
31
0-2
P:$3E
ESSI 0 Transmit Data with Exception Status
ESSI 0
32
0-2
P:$40
ESSI 0 Transmit Data
ESSI 0
33
0-2
P:$42
ESSI 0 Transmit Last Slot
ESSI 1
34
0-2
P:$44
ESSI 1 Receive Data with Exception Status
ESSI 1
35
0-2
P:$46
ESSI 1 Receive Data
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Table 8-3. Interrupt Vector Table Contents (Continued)
Freescale Semiconductor, Inc...
Vector
Peripheral Number
56
Priority
Level
Vector
Base
Address +
Interrupt Function
ESSI 1
36
0-2
P:$48
ESSI 1 Receive Last Slot
ESSI 1
37
0-2
P:$4A
ESSI 1 Transmit Data with Exception Status
ESSI 1
38
0-2
P:$4C
ESSI 1 Transmit Data
ESSI 1
39
0-2
P:$4E
ESSI 1 Transmit Last Slot
SPI
40
0-2
P:$50
SPI Receiver Full
SPI
41
0-2
P:$52
SPI Transmitter Empty
SCI 0
42
0-2
P:$54
SCI 0 Transmitter Empty
SCI 0
43
0-2
P:$56
SCI 0 Transmitter Idle
SCI 0
44
0-2
P:$58
SCI 0 Receiver Idle
SCI 0
45
0-2
P:$5A
SCI 0 Receiver Error
(Receiver Overrun, Noise Error, Framing Error, Parity Error)
SCI 0
46
0-2
P:$5C
HI8
47
0-2
P:$5E
SCI 0 Receiver Full
Host Receiver Full
HI8
48
0-2
P:$60
Host Transmit Data
HI8
49
0-2
P:$62
Host Command (default)
TOD
TOD
50
0-2
P:$64
TOD Alarm
51
0-2
P:$66
TOD One Second Interval
TMR
52
0-2
P:$68
Timer Compare 0
TMR
53
0-2
P:$6A
Timer Overflow 0
TMR
54
0-2
P:$6C
Timer Input Edge Flag 0
TMR
55
0-2
P:$6E
Timer Compare 1
TMR
56
0-2
P:$70
Timer Overflow 1
TMR
57
0-2
P:$72
Timer Input Edge Flag 1
TMR
58
0-2
P:$74
Timer Compare 2
TMR
59
0-2
P:$76
Timer Overflow 2
TMR
60
0-2
P:$78
Timer Input Edge Flag 2
TMR
61
0-2
P:$7A
Timer Compare 3
TMR
62
0-2
P:$7C
Timer Overflow 3
TMR
core
63
0-2
P:$7E
Timer Input Edge Flag 3
64
-1
P:$80
SW Interrupt LP
SCI 1
65
0-2
P:$82
SCI 1 Transmitter Empty
SCI 1
66
0-2
P:$FE
SCI 1 Transmitter Idle
SCI 1
67
0-2
P:$86
SCI 1 Receiver Idle
SCI 1
68
0-2
P:$88
SCI 1 Receiver Error
(Receiver Overrun, Noise Error, Framing Error, Parity Error)
SCI 1
69
0-2
P:$8A
SCI 1 Receiver Full
HI8
70
0-2
P:$8C
Available for Host Command
HI8
71
0-2
P:$8E
Available for Host Command
HI8
72
0-2
P:$90
Available for Host Command
HI8
73
0-2
P:$92
Available for Host Command
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Table 8-3. Interrupt Vector Table Contents (Continued)
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Vector
Peripheral Number
Priority
Level
Vector
Base
Address +
Interrupt Function
HI8
74
0-2
P:$94
Available for Host Command
HI8
75
0-2
P:$96
Available for Host Command
HI8
76
0-2
P:$98
Available for Host Command
HI8
77
0-2
P:$9A
Available for Host Command
HI8
78
0-2
P:$9C
Available for Host Command
HI8
79
0-2
P:$9E
Available for Host Command
HI8
80
0-2
P:$A0
Available for Host Command
HI8
81
0-2
P:$A2
Available for Host Command
HI8
82
0-2
P:$A4
Available for Host Command
HI8
83
0-2
P:$A6
Available for Host Command
HI8
84
0-2
P:$A8
Available for Host Command
HI8
85
0-2
P:$AA
Available for Host Command
HI8
86
0-2
P:$AC
Available for Host Command
HI8
87
0-2
P:$AE
Available for Host Command
HI8
88
0-2
P:$B0
Available for Host Command
HI8
89
0-2
P:$B2
Available for Host Command
HI8
90
0-2
P:$B4
Available for Host Command
HI8
91
0-2
P:$B6
Available for Host Command
HI8
92
0-2
P:$B8
Available for Host Command
HI8
93
0-2
P:$BA
Available for Host Command
HI8
94
0-2
P:$BC
Available for Host Command
HI8
95
0-2
P:$BE
Available for Host Command
HI8
96
0-2
P:$C0
Available for Host Command
HI8
97
0-2
P:$C2
Available for Host Command
HI8
P:$C4
Available for Host Command
98
0-2
HI8
99
0-2
P:$C6
Available for Host Command
HI8
100
0-2
P:$C8
Available for Host Command
HI8
101
0-2
P:$CA
Available for Host Command
HI8
102
0-2
P:$CC
Available for Host Command
HI8
103
0-2
P:$CE
Available for Host Command
HI8
104
0-2
P:$D0
Available for Host Command
HI8
105
0-2
P:$D2
Available for Host Command
HI8
106
0-2
P:$D4
Available for Host Command
HI8
107
0-2
P:$D6
Available for Host Command
HI8
108
0-2
P:$D8
Available for Host Command
HI8
109
0-2
P:$DA
Available for Host Command
HI8
110
0-2
P:$DC
Available for Host Command
HI8
111
0-2
P:$DE
Available for Host Command
HI8
112
0-2
P:$E0
Available for Host Command
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Table 8-3. Interrupt Vector Table Contents (Continued)
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Vector
Peripheral Number
58
Priority
Level
Vector
Base
Address +
Interrupt Function
HI8
113
0-2
P:$E2
Available for Host Command
HI8
114
0-2
P:$E4
Available for Host Command
HI8
115
0-2
P:$E6
Available for Host Command
HI8
116
0-2
P:$E8
Available for Host Command
HI8
117
0-2
P:$EA
Available for Host Command
HI8
118
0-2
P:$EC
Available for Host Command
HI8
119
0-2
P:$EE
Available for Host Command
HI8
120
0-2
P:$F0
Available for Host Command
HI8
121
0-2
P:$F2
Available for Host Command
HI8
122
0-2
P:$F4
Available for Host Command
HI8
123
0-2
P:$F6
Available for Host Command
HI8
124
0-2
P:$F8
Available for Host Command
HI8
125
0-2
P:$FA
Available for Host Command
HI8
126
0-2
P:$FC
Available for Host Command
HI8
127
0-2
P:$FE
Available for Host Command
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The following addition refers to entry (bottom) Page 8-24, New register and
bit description.
8.7.9 Interrupt Priority Register 8 (IPR8)
$1FFF28
15
14
13
12
11
10
Read
0
0
0
0
0
0
0
0
0
0
0
0
Write
RESET
9
8
SCI1_RCV
IPL
0
0
7
6
5
4
SCI1_RERR SCI1_RIDL
IPL
IPL
0
0
0
0
3
2
SCI1_TIDL
IPL
0
0
1
0
SCI1_XMIT
IPL
0
0
Freescale Semiconductor, Inc...
Figure 8-10. Interrupt Priority Register 8 (IPR8)
8.7.9.1 Reserved—Bits 15-10
These bits are reserved or not implemented. They are read as zero, but cannot be modified
by writing.
8.7.9.2
Receiver Full Interrupt Priority Level (SCI1_RCV IPL)—Bits 9–8
These fields are used to set the interrupt priority levels for certain peripheral IRQs. These
IRQs are limited to priorities 0-2 and are disabled by default.
•
00 = IRQ disabled (default)
•
01 = IRQ is priority level 0
•
10 = IRQ is priority level 1
•
11 = IRQ is priority level 2
8.7.9.3 Receiver Error Interrupt Priority Level (SCI1_RERR IPL)—Bits 7–6
These fields are used to set the interrupt priority levels for certain peripheral IRQs. These
IRQs are limited to priorities 0-2 and are disabled by default.
•
00 = IRQ disabled (default)
•
01 = IRQ is priority level 0
•
10 = IRQ is priority level 1
•
11 = IRQ is priority level 2
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8.7.9.4 Receiver Idle Interrupt Priority Level (SCI1_RIDL IPL)—Bits 5–4
Freescale Semiconductor, Inc...
These fields are used to set the interrupt priority levels for certain peripheral IRQs. These
IRQs are limited to priorities 0-2 and are disabled by default.
•
00 = IRQ disabled (default)
•
01 = IRQ is priority level 0
•
10 = IRQ is priority level 1
•
11 = IRQ is priority level 2
8.7.9.5
Transmitter Idle Interrupt Priority Level (SCI1_TIDL IPL)—Bits 3–2
These fields are used to set the interrupt priority levels for certain peripheral IRQs. These
IRQs are limited to priorities 0-2 and are disabled by default.
•
00 = IRQ disabled (default)
•
01 = IRQ is priority level 0
•
10 = IRQ is priority level 1
•
11 = IRQ is priority level 2
8.7.9.6
Transmitter Empty Interrupt Priority Level
(SCI1_XMIT IPL)—Bits 1–0
These fields are used to set the interrupt priority levels for certain peripheral IRQs. These
IRQs are limited to priorities 0-2 and are disabled by default.
60
•
00 = IRQ disabled (default)
•
01 = IRQ is priority level 0
•
10 = IRQ is priority level 1
•
11 = IRQ is priority level 2
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The following addition refers to entry Page 15-5, New Table Below Table 15-7.
Freescale Semiconductor, Inc...
Table 15-8. GPIO H Register Map (GPIOH_BASE = $1FFE7C)
Register
Acronym
Address
GPIO_H_PER
$1FFE7C
Peripheral Enable Register
Read/Write
GPIO_H_DDR
$1FFE7B
Data Direction Register
Read/Write
GPIO_H_DR
$1FFE7D
Data Register
Read/Write
GPIO_H_PUER
$1FFE7E
Pull-Up Enable Register
Read/Write
Register Description
Access Type
The following addition refers to entry Page 16-8, New Table 16-3.
Table 16-3. HI8 Host Side Register Map
Register Acronym
Register Name
Host
Address
Offset
Interface Control
+ $0
ICR
ICR
Used by the host to control HI8 interrupts and flags
Read/Write
Command Vector
+ $1
CVR
CVR
Used by the host to cause DSP core to
execute an interrupt
Read/Write
Interface Status
+ $2
ISR
ISR
Used by the host to interrogate status
and flags of the HI8
Read Only
Interrupt Vector
+ $3
IVR
IVR
Used by the host to hold the interrupt
vector number used with the MC68000
family processor vectored interface
Read/Write
Unused
+ $4
—
—
—
Read as 00
Unused
+ $5
—
—
—
Read as 00
+ $6
RXH/TXH
RXL/TXL
One of two register used to transfer
data between the host and the DSP
Read/Write
+ $7
RXL/TXL
RXH/TXH
One of two register used to transfer
data between the host and the DSP
Read/Write
HLEND = 0
HLEND = 1
(Big Endian) (Little Endian)
Receive/Transmit
Bytes
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Access
Type
61
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The following addition refers to entry Page 16-22, Section 16.9.2.
16.9.2 Command Vector Register (CVR)
Freescale Semiconductor, Inc...
The Command Vector Register (CVR) is used by the Host Processor, causing the DSP core
to execute an interrupt. The Host Command feature is independent of any of the data
transfer mechanisms in the HI8. The Host Interface can execute any of the 128 possible
interrupt requests to the DSP core. Please refer to the Interrupt Controller (ITCN) chapter
for further details.
This entry refers to Page 16-35 in the Addendum, Section 16.10.10.2 . Replace
the section with the following rewriten text:
16.10.10.2 DSP Programmer Considerations
Reading HF1 and HF0 as an encoded pair:
•
DMA
•
HF1
•
HF0
•
HCP
•
HTDE
•
HRDF
The above status bits are set, or cleared, by the Host Processor side of the interface. They
are also individually synchronized to the DSP clock.
When HF1 and HF0 are encoded as a pair, e.g. the four combinations 00, 01, 10, and 11,
each have significance, presenting the only feasible system problem while reading the
status. This potential problem would be due to the improbability DSP will read the status
bits synchronized during transition. A solution to this situation is to read the bits a second
time to make certain they have not changed.
62
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