PI49FCT20807 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 1-10 Clock Buffer for Networking Applications Product Features Description High Frequency >150 MHz The PI49FCT20807, a 2.5V compatible, high-speed, low-noise 1-10 non-inverting clock buffer, is designed to target networking applications that require low-skew, low-jitter, and high-frequency clock distribution. Providing output-to-output skew as low as 150ps, the PI49FCT20807 is an ideal clock distribution device for synchronous systems. Designing synchronous networking systems requires a tight level of skew from a large number of outputs. High-speed, low-noise, non-inverting 1-10 buffer Low-skew (<150ps) between any two output clocks Low duty cycle distortion <300ps Low propagation delay <3.5ns Multiple VDD, GND pins for noise reduction 2.5V supply voltage Available in SOIC, SSOP, and QSOP packages Product Pin Description Pin Name Block Diagram D e s cription BUF_IN Input CLK [0:9] O utputs GND Ground VDD Power Pin Configuration CLK0 CLK1 BUF_IN CLK2 CLK3 BUF_IN 1 20 VDD GND 2 19 CLK9 CLK0 3 18 CLK8 VDD 4 17 GND CLK1 5 16 CLK7 GND 6 15 VDD CLK2 7 14 CLK6 VDD 8 13 GND CLK3 9 12 CLK5 GND 10 11 CLK4 20-Pin H, Q, S CLK9 1 PS8558 08/08/01 PI49FCT20807 1-10 Clock Buffer for Networking Applications 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 Maximum Ratings (Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ...................................................... 65°C to +150°C VDD Voltage ...................................................................... 0.5V to +3.6V Output Voltage(4) ................................................................... 0.5V to VDD+0.5V Input Voltage(4) ....................................................................... 0.5V to VDD+0.5V DC Output Current ....................................................... 60mA to +60mA Power Dissipation ........................................................................ 500mW Note: Stresses greater than those listed under MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Operating Range VDD Voltage ........................................................................... 2.5V ± 0.2V Industrial Temperature .................................................... 40°C to +85°C Input Frequency ............................................................. DC to 150 MHz Capacitive Loading ............................................................. 10pF to 25pF DC Electrical Characteristics (Over the Operating Range) Te s t Conditions (1) Parame te rs De s cription VIH Input HIGH Voltage Guaranteed Logic HIGH Level (Input Pins) VIL Input LOW Voltage Guaranteed Logic LOW Level (Input Pins) II Input Current VIK Clamp Diode Voltage VDD = Min., IIN = 18mA VOH Output HIGH Voltage VDD = Min., VIN = VIH or VIL VOL Output LOW Voltage VDD = Min., VIN = VIH or VIL VDD = Max., VIN = VDD or GND VIN = VDD IOH = 1mA M in. Typ.(2) 1.7 M ax. 0.7 ±1 0.7 1 2 (3) IOH = 8mA 1.8 IOL = 1mA IOL = 8mA Units V mA V 0.4 0.6 Notes: 1. For Max. or Min. conditions, use appropriate value specified under Electrical Characteristics for the applicable device type. 2. Typical values are at VDD = 2.5V, +25°C ambient and maximum loading. 3. VOH = VDD 0.6V at rated current. 4. This value is limited to 3.6V maximum. Power Supply Characteristics Te s t Conditions (1) M in. Typ.(2) M ax. VIN = GND or VDD 0.1 20 VDD = Max. VIN = VDD 0.6V(3) 47 300 VDD = 2.7V, 15pF & 33- ohm load 150 MHz 136 Parame te rs D e s cription IDDQ Q uiescent Power Supply Current VDD = Max. ∆IDD Supply Current per Inputs @ TTL HIGH IDD Dynamic Supply Current (See Graph 1) Units µA mA Notes: 1. For Max. or Min. conditions, use appropriate value specified under Electrical Characteristics for the applicable device. 2. Typical values are at VDD = 2.5V, +25°C ambient. 3. Per TTL driven input (VIN = VDD 0.6V); all other inputs at VDD or GND. 2 PS8558 08/08/01 PI49FCT20807 1-10 Clock Buffer for Networking Applications 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 Graph 1. Dynamic Current vs. Clock Frequency Dynamic Current - IDD [mA] 160 140 120 100 Load = 15pF & 33 ohms 80 60 Load = 0 40 20 0 0 50 100 150 200 Clock Frequency [MHz] Capacitance (TA = 25°C, f = 1 MHz) Parame te rs (1) De s cription Te s t Conditions Typ(5) M ax. 3 4 CIN Input Capacitance VIN = 0V COUT Output Capacitance VOUT = 0V Units pF 6 Note: 1. This parameter is determined by device characterization but is not production tested. Switching Characteristics (VDD = 2.5V ± 0.2V, TA = 85°C) Parame te rs tR/tF tPLH tPHL De s cription CLKn Rise/Fall Time 0.7V ~ 1.7 V Propagation Delay BUF_IN to CLKn Te s t Conditions (1) M in. Typ. M ax. CL = 22pF, 100 MHz 1.0 1.25 CL = 12pF, 150 MHz 1.0 1.2 CL = 22pF, 100 MHz 3.0 3.5 CL = 12pF, 150 MHz 2.4 2.7 tSK(o)(2) Skew between two outputs of the same package (same transition) CL = 22pF, 100 MHz 100 150 CL = 12pF, 150 MHz 100 150 tSK(p)(2) Skew between opposite transitions (tPHL- tPLH) of the same output CL = 22pF, 100 MHz 250 300 CL = 12pF, 150 MHz 250 300 CL = 12pF, 150 MHz 400 600 tSK(t)(2) Skew between two outputs of different package (4) Units ns ps Notes: 1. See test circuit and waveforms. 2. Skew measured at worse cast temperature (max. temp). Test Circuits for All Outputs VDD Pulse Generator VOUT VIN D.U.T. CL Definitions: CL = Load capacitance: includes jig and probe capacitance. 3 PS8558 08/08/01 PI49FCT20807 1-10 Clock Buffer for Networking Applications 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 Switching Waveforms Pulse Skew tSK(P) Propagation Delay 2.5V Input 2.5V 1.25V Input 1.25V 0V 0V tPHL tPLH tPHL tPLH VOH 1.7V Output VOH 1.25V 0.7V Output VOL tR 1.25V tF VOL tSK(p) = | tPHL – tPLH | Output Skew tSK(O) Package Skew tSK(T) 2.5V Input 2.5V 1.25V Input 1.25V 0V 0V tPHLx tPLHx tPLH1 VOH CLKx VOH 1.25V Package 1 Output VOL tSK(o) tPHL1 1.25V VOL tSK(o) tSK(t) VOH CLKy VOH 1.25V Package 2 Output VOL tPLHy tSK(t) tPHLy 1.25V VOL tPLH2 tSK(o) = ú tPLHy – tPLHx ú or ú tPHLy – tPHLx ú tPHL2 tSK(t) = tPLH2 – tPLH1 or tPHL2 – tPHL1 20-Pin SOIC (S) Package 20 .2914 .2992 7.40 7.60 .010 .029 0.254 x 45˚ 0.737 1 .496 12.60 .511 12.99 .020 0.508 REF .030 0.762 .013 .020 0.33 0.51 0.23 0.32 0.41 .016 1.27 .050 .0926 .1043 2.35 2.65 SEATING PLANE .050 BSC 1.27 .0091 .0125 0-8˚ .0040 .0118 .394 .419 10.00 10.65 0.10 0.30 X.XX DENOTES CONTROLLING X.XX DIMENSIONS IN MILLIMETERS 4 PS8558 08/08/01 PI49FCT20807 1-10 Clock Buffer for Networking Applications 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 20-Pin SSOP (H) Package 20 5.00 5.60 .197 .220 1 0.09 0.25 .004 .009 .272 .295 6.90 7.50 0.55 .022 0.95 .037 .078 2.00 Max .291 .322 7.40 8.20 SEATING PLANE .002 Min 0.050 .0098 Max. 0.25 .0256 BSC 0.65 X.XX DENOTES DIMENSIONS X.XX IN MILLIMETERS 20-Pin QSOP (Q) Package 20 .008 0.20 MIN. .150 .157 .008 .013 0.20 0.33 3.81 3.99 Guage Plane .010 0.254 1 Detail A .337 8.56 .344 8.74 .058 REF 1.47 .041 1.04 REF .015 x 45˚ 0.38 .053 1.35 .069 1.75 Detail A .007 .010 SEATING PLANE .016 .050 .025 BSC 0.635 0˚-6˚ .016 .035 0.41 0.89 .004 0.101 .010 0.254 0.178 0.254 0.41 1.27 .228 .244 5.79 6.19 .008 0.203 .012 0.305 X.XX DENOTES DIMENSIONS X.XX IN MILLIMETERS Ordering Information Orde ring Code Package Type PI49FCT20807S 20- pin 300 mil wide SOIC PI49FCT20807Q 20- pin 150 mil wide QSO P PI49FCT20807H 20- pin 209 mil wide SSO P Ope rating Range Industrial Pericom Semiconductor Corporation 2380 Bering Drive • San Jose, CA 95131 • 1-800-435-2336 • Fax (408) 435-1100 • http://www.pericom.com 5 PS8558 08/08/01