ETC 54HSC/TSERIES

54HSC/T Series
54HSC/T Series
Radiation Hard High Speed CMOS/SOS Logic
Replaces May 1995 version, DS3594-3.3
The CMOS/SOS HSC/T Series offer the combined benefits
of low power, high speed CMOS with the inherent latch up
immunity, Single Event Upset (SEU) immunity and the high
level of radiation hardness of Silicon on Sapphire technology.
The 54HSC/T Series of circuits are pin for pin compatible with
the 54LS series range.
HSC and HST devices have CMOS and TTL compatible
inputs/outputs respectively.
FEATURES
■ Radiation Hard to 1MRad (Si)
■ High SEU Immunity, Latch Up Free
■ Low Power CMOS/SOS Technology
■ Plug In Replacement for 54/74LS, HC and HCT
■ Dual In Line or Flatpack Packages
DS3594-4.0 November 2002
Adders
54HSC/T283 4-bit binary full adders with fast carry
Counters
54HSC/T161 4-bit synchronous binary counter
54HSC/T163 Synchronous 4-bit counter
54HSC/T191 Synchronous 4-bit counter
Decoders/Demultiplexers
54HSC/T138 3-line to 8-line decoder/multiplexer
54HSC/T139 Dual 2 to 4 decoders/multiplexers
54HSC/T148 8-line to 3-line octal priority encoders
54HSC/T151 1 of 8 data selectors/multiplexers
54HSC/T154 4 to 16-line decoders/demultiplexers
54HSC/T157 Quad 2-line to 1-line data selectors/multiplexers
54HSC/T238 3 to 8 decoder/demultiplexer
54HSC/T253 Dual 4 to 1 data selectors/multiplexers
Gates and Buffers
54HSC/T00 Quadruple 2-input positive NAND gates
54HSC/T02 Quadruple 2-input positive NOR gates
54HSC/TO3 Quadruple 2-input positive NAND gates with
open collector outputs
54HSC/T04 Hex Inverters
54HSC/T08 Quadruple 2-input positive AND gates
54HSC/T10 Triple 3-input positive NAND gates
54HSC14
Hex schmitt-trigger inverters
54HSC/T21 Dual 4-input positive AND gates
54HSC/T27 Triple 3-input positive NOR gates
54HSC/T32 Quadruple 2-input positive OR gates
54HSC/T86 Quadruple 2-input Exclusive OR gates
54HSC/T125 Quadruple bus buffer gates with tri-state outputs
(Active low enable)
54HSC/T126 Quadruple bus buffer gates wlth tri-state outputs
(Active high enable)
Registers
54HSC/T164 8-bit parallel output serial shift register
54HSC/T165 Parallel load 8-bit shift register
54H5C/T166 8-bit shift register
Flip-Flops
54HSC/T74
54HSC/T109
54HSC/T273
54HSC/T374
54HSC/T574
Latches
54HSC/T373 Octal transparent latch, 3-state outputs
54HSC/T573 Octal transparent latch, 3-state outputs
Dual D-type flip-flops wlth preset and clear
Dual J-KB flip-flop with preset and clear
Octal D-type flip-flops
Octal D-type edge triggered flip-flops
Octal D-type edge triggered flip-flops
Comparators
54HSC/T521 8-bit magnitude comparator
Line Drivers
54HSC/T240
54HSC/T241
54HSC/T244
54HSC/T540
54HSC/T541
Octal 3-state driver inverting
Octal 3-state driver complementary enable
Octal 3-state driver
Octal 3-state driver/buffer inverting
Octal 3-state driver/buffer
Transceivers
54HSC/T245 OctaI bus transceiver
Miscellaneous
54HSC/T670 4 x 4 register files with tri-state outputs
1/101
www.dynexsemi.com
54HSC/T Series
DC CHARACTERISTICS AND RATINGS
Parameter
Min.
Max.
Units
Supply Voltage
-0.5
10
V
Input Voltage
-0.3
VDD+0.3
V
Current Through Any Pin
-25
+25
mA
Operating Temperature
-55
125
°C
Storage Temperature
-65
150
°C
Note: Stresses above those listed may cause permanent
damage to the device. This is a stress rating only and
functional operation of the device at these conditions, or at
any other condition above those indicated in the operations
section of this specification, is not implied. Exposure to
absolute maximum rating conditions for extended periods
may affect device reliability.
Figure 1: Absolute Maximum Ratings
Total dose radiation not
exceeding 3x105 Rad(SI)
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Units
VDD
Supply Voltage
-
4.5
5.0
5.5
V
VIH1
HST Input High Voltage
-
2.0
-
-
V
VIL1
HST Input Low Voltage
-
-
-
0.8
V
VIH2
HSC Input High Voltage
-
3.5
-
-
V
VIL2
HSC Input Low Voltage
-
-
-
1.5
V
VOH
Output High Voltage
VIN = VIH or VIL
IOH = -20µA*
IOH = 6mA*
IOH = -11mA
VDD-0.1
3.7
2.5
-
-
V
V
V
VIN = VIH or VIL
IOL = -20µA*
IOL = 6mA*
IOL = 9mA
-
-
0.1
0.2
0.4
V
V
V
VIN = VDD or VSS
All inputs
-
1
5
µA
VOL
Output Low Voltage
IIL
Input Leakage Current
IOL
Output Leakage Current
VOUT = VDD or VSS
Outputs disabled
-
20
50
µA
IDD
Quiescent Current
VIN = VDD
Outputs unloaded
-
†
†
µA
VDD = 5V±10%, over full operating temperature range.
* Guaranteed but not tested.
† Refer to individual device types (-55°C / +125°C).
Figure 2: Electrical Characteristics
2/101
www.dynexsemi.com
54HSC/T Series
54HSC/T00 : Quadruple 2-Input Positive NAND Gates
The 54HSC/T00 is a Quadruple 2-Input Positive NAND gate.
Inputs
Outputs
A
B
Y
L
L
H
L
H
H
H
L
H
H
H
L
Figure 2: Logic Diagram
H = high level, L = low level
Figure 1: Function Table
1A
1
14 VDD
1B
2
13 4B
1Y
3
12 4A
Top
View
2A
4
2B
5
10 3B
2Y
6
9 3A
VSS
7
8 3Y
11 4Y
Figure 3: Pin Out
+25°C
Symbol
Parameter
tPLH
tPHL
-55°C / +125°C
Typ.
Max.
Typ.
Max.
Units
Propagation delay time, low to high level output
11
20
17
22
ns
Propagation delay time, high to low level output
10
18
18
20
ns
Figure 4: Switching Characteristics
Limits
+25°C
Symbol
Parameter
IDD
Quiescent Current
VOL
-55°C / +125°C
Test Conditions
Min.
Max.
Min.
Max.
Units
VIN = 0V or VDD
-
10
-
300
µA
Output Voltage Low Level
IOL = 9mA
-
0.4
-
0.4
V
VOH
Output Voltage High Level
IOH = -11mA
2.5
-
2.5
-
V
VIL1
Voltage Input Low (CMOS)
-
-
1.5
-
1.5
V
VIH1
Voltage Input High (CMOS)
-
3.5
-
3.5
-
V
VIL2
Voltage Input Low (TTL)
-
-
0.8
-
0.8
V
VIH2
Voltage Input High (TTL)
-
2.0
-
2.0
-
V
IIN
Input Leakage Current
VIN = VDD or VSS
-
±0.5
-
±5.0
µA
Figure 5: DC Characteristics
3/101
www.dynexsemi.com
54HSC/T Series
54HSC/T02 : Quadruple 2-Input Positive NOR Gates
The 54HSC/T02 is a Quadruple 2-Input Positive NOR gate.
Inputs
Outputs
A
B
Y
L
L
H
L
H
L
H
L
L
H
H
L
Figure 2: Logic Diagram
1Y
1
14 VDD
1A
2
13 4Y
1B
3
2Y
4
2A
5
10 3Y
2B
6
9 3B
VSS
7
8 3A
H = high level, L = low level
Figure 1: Function Table
12 4B
Top
View
11 4A
Figure 3: Pin Out
+25°C
Symbol
Parameter
tPLH
tPHL
-55°C / +125°C
Typ.
Max.
Typ.
Max.
Units
Propagation delay time, low to high level output
11
20
17
22
ns
Propagation delay time, high to low level output
10
18
18
20
ns
Figure 4: Switching Characteristics
Limits
+25°C
Symbol
Parameter
IDD
Quiescent Current
-55°C / +125°C
Test Conditions
Min.
Max.
Min.
Max.
Units
VIN = 0V or VDD
-
10
-
300
µA
VOL
Output Voltage Low Level
IOL = 9mA
-
0.4
-
0.4
V
VOH
Output Voltage High Level
IOH = -11mA
2.5
-
2.5
-
V
VIL1
Voltage Input Low (CMOS)
-
-
1.5
-
1.5
V
VIH1
Voltage Input High (CMOS)
-
3.5
-
3.5
-
V
VIL2
Voltage Input Low (TTL)
-
-
0.8
-
0.8
V
VIH2
Voltage Input High (TTL)
-
2.0
-
2.0
-
V
IIN
Input Leakage Current
VIN = VDD or VSS
-
±0.5
-
±5.0
µA
Figure 5: DC Characteristics
4/101
www.dynexsemi.com
54HSC/T Series
54HSC/T03 : Quadruple 2-Input Positive NAND Gates
With Open Collector Outputs
The 54HSC/T03 is a Quadruple 2-Input Positive NAND gate
with open collector output.
Inputs
Outputs
A
B
Y
L
L
H
L
H
H
H
L
H
H
H
L
Figure 2: Logic Diagram
H = high level, L = low level
Figure 1: Function Table
1A
1
14 VDD
1B
2
13 4B
1Y
3
12 4A
Top
View
2A
4
2B
5
10 3B
2Y
6
9 3A
VSS
7
8 3Y
11 4Y
Figure 3: Pin Out
+25°C
Symbol
Parameter
tPLH
tPHL
-55°C / +125°C
Typ.
Max.
Typ.
Max.
Units
Propagation delay time, low to high level output
11
20
17
22
ns
Propagation delay time, high to low level output
10
18
18
20
ns
Figure 4: Switching Characteristics
Limits
+25°C
Symbol
Parameter
IDD
Quiescent Current
VOL
Output Voltage Low Level
VOH
Output Voltage High Level
VIL1
Voltage Input Low (CMOS)
VIH1
Voltage Input High (CMOS)
VIL2
Voltage Input Low (TTL)
VIH2
Voltage Input High (TTL)
IIN
Input Leakage Current
VIN = VDD or VSS
-55°C / +125°C
Test Conditions
Min.
Max.
Min.
Max.
Units
VIN = 0V or VDD
-
10
-
300
µA
IOL = 9mA
-
0.4
-
0.4
V
IOH = -11mA
2.5
-
2.5
-
V
-
-
1.5
-
1.5
V
-
3.5
-
3.5
-
V
-
-
0.8
-
0.8
V
-
2.0
-
2.0
-
V
-
±0.5
-
±0.5
µA
Figure 5: DC Characteristics
5/101
www.dynexsemi.com
54HSC/T Series
54HSC/T04 : Hex Inverters
The 54HSC/T04 consists of six Hex Inverters.
Inputs
Outputs
A
Y
H
L
L
H
Figure 2: Logic Diagram
H = high level, L = low level
Figure 1: Function Table
1A
1
14 VDD
1Y
2
13 6A
2A
3
12 6Y
Top
View
2Y
4
3A
5
10 5Y
3Y
6
9 4A
VSS
7
8 4Y
11 5A
Figure 3: Pin Out
+25°C
Symbol
Parameter
tPLH
tPHL
-55°C / +125°C
Typ.
Max.
Typ.
Max.
Units
Propagation delay time, low to high level output
11
20
17
22
ns
Propagation delay time, high to low level output
10
18
18
20
ns
Figure 4: Switching Characteristics
Limits
+25°C
Symbol
Parameter
IDD
Quiescent Current
-55°C / +125°C
Test Conditions
Min.
Max.
Min.
Max.
Units
VIN = 0V or VDD
-
10
-
300
µA
VOL
Output Voltage Low Level
IOL = 9mA
-
0.4
-
0.4
V
VOH
Output Voltage High Level
IOH = -11mA
2.5
-
2.5
-
V
VIL1
Voltage Input Low (CMOS)
-
-
1.5
-
1.5
V
VIH1
Voltage Input High (CMOS)
-
3.5
-
3.5
-
V
VIL2
Voltage Input Low (TTL)
-
-
0.8
-
0.8
V
VIH2
Voltage Input High (TTL)
-
2.0
-
2.0
-
V
IIN
Input Leakage Current
VIN = VDD or VSS
-
±0.5
-
±5.0
µA
Figure 5: DC Characteristics
6/101
www.dynexsemi.com
54HSC/T Series
54HSC/T08 : Quadruple 2-Input Positive AND Gates
The 54HSC/T08 is a Quadruple 2-Input Positive AND gate.
Inputs
Outputs
A
B
Y
L
L
L
L
H
L
H
L
L
H
H
H
Figure 2: Logic Diagram
H = high level, L = low level
Figure 1: Function Table
1A
1
14 VDD
1B
2
13 4B
1Y
3
12 4A
Top
View
2A
4
2B
5
10 3B
2Y
6
9 3A
VSS
7
8 3Y
11 4Y
Figure 3: Pin Out
+25°C
Symbol
Parameter
tPLH
tPHL
-55°C / +125°C
Typ.
Max.
Typ.
Max.
Units
Propagation delay time, low to high level output
11
20
17
22
ns
Propagation delay time, high to low level output
10
18
18
20
ns
Figure 4: Switching Characteristics
Limits
+25°C
Symbol
Parameter
IDD
Quiescent Current
VOL
Output Voltage Low Level
VOH
Output Voltage High Level
VIL1
Voltage Input Low (CMOS)
VIH1
Voltage Input High (CMOS)
VIL2
Voltage Input Low (TTL)
VIH2
Voltage Input High (TTL)
IIN
Input Leakage Current
VIN = VDD or VSS
-55°C / +125°C
Test Conditions
Min.
Max.
Min.
Max.
Units
VIN = 0V or VDD
-
10
-
300
µA
IOL = 9mA
-
0.4
-
0.4
V
IOH = -11mA
2.5
-
2.5
-
V
-
-
1.5
-
1.5
V
-
3.5
-
3.5
-
V
-
-
0.8
-
0.8
V
-
2.0
-
2.0
-
V
-
±0.5
-
±5.0
µA
Figure 5: DC Characteristics
7/101
www.dynexsemi.com
54HSC/T Series
54HSC/T10 : Triple 3-Input Positive NAND Gates
The 54HSC/T10 is a Triple 3-Input Positive NAND gate.
Inputs
Outputs
A
B
C
Y
L
X
X
H
X
L
X
H
X
X
L
H
H
H
H
L
Figure 2: Logic Diagram
H = high level, L = low level, X = irrelevant
Figure 1: Function Table
1A
1
14 VDD
1B
2
13 1C
2A
3
2B
4
12 1Y
Top
View
11 3C
2C
5
10 3B
2Y
6
9 3A
VSS
7
8 3Y
Figure 3: Pin Out
+25°C
Symbol
Parameter
tPLH
tPHL
-55°C / +125°C
Typ.
Max.
Typ.
Max.
Units
Propagation delay time, low to high level output
11
20
17
22
ns
Propagation delay time, high to low level output
10
18
18
20
ns
Figure 4: Switching Characteristics
Limits
+25°C
Symbol
Parameter
IDD
Quiescent Current
VOL
-55°C / +125°C
Test Conditions
Min.
Max.
Min.
Max.
Units
VIN = 0V or VDD
-
10
-
300
µA
Output Voltage Low Level
IOL = 9mA
-
0.4
-
0.4
V
VOH
Output Voltage High Level
IOH = -11mA
2.5
-
2.5
-
V
VIL1
Voltage Input Low (CMOS)
-
-
1.5
-
1.5
V
VIH1
Voltage Input High (CMOS)
-
3.5
-
3.5
-
V
VIL2
Voltage Input Low (TTL)
-
-
0.8
-
0.8
V
VIH2
Voltage Input High (TTL)
-
2.0
-
2.0
-
V
IIN
Input Leakage Current
VIN = VDD or VSS
-
±0.5
-
±5.0
µA
Figure 5: DC Characteristics
8/101
www.dynexsemi.com
54HSC/T Series
54HSC14 : Hex Schmitt-Trigger Inverters
The 54HSC/T14 consists of six Hex Schmitt-Trigger Inverters.
Inputs
Outputs
A
Y
L
H
H
L
Figure 2: Logic Diagram
H = high level, L = low level
Figure 1: Function Table
1A
1
14 VDD
1Y
2
13 6A
2A
3
2Y
4
3A
5
10 5Y
3Y
6
9 4A
VSS
7
8 4Y
12 6Y
Top
View
11 5A
Figure 3: Pin Out
+25°C
Symbol
Parameter
tPLH
tPHL
-55°C / +125°C
Typ.
Max.
Typ.
Max.
Units
Propagation delay time, low to high level output
11
20
17
22
ns
Propagation delay time, high to low level output
10
18
18
20
ns
Figure 4: Switching Characteristics
Limits
+25°C
Symbol
Parameter
IDD
Quiescent Current
VOL
-55°C / +125°C
Test Conditions
Min.
Max.
Min.
Max.
Units
VIN = 0V or VDD
-
10
-
300
µA
Output Voltage Low Level
IOL = 9mA
-
0.4
-
0.4
V
VOH
Output Voltage High Level
IOH = -11mA
2.5
-
2.5
-
V
VIL1
Voltage Input Low (CMOS)
-
-
1.5
-
1.5
V
VIH1
Voltage Input High (CMOS)
-
3.5
-
3.5
-
V
VIL2
Voltage Input Low (TTL)
-
-
0.8
-
0.8
V
VIH2
Voltage Input High (TTL)
-
2.0
-
2.0
-
V
IIN
Input Leakage Current
VIN = VDD or VSS
-
±0.5
-
±5.0
µA
Figure 5: DC Characteristics
9/101
www.dynexsemi.com
54HSC/T Series
54HSC/T21 : Dual 4-Input Positive AND Gates
The 54HSC/T21 is a Dual 4-Input Positive AND gate.
Inputs
Outputs
A
B
C
D
Y
L
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H
L
L
L
L
H
H
H
H
L
L
L
L
H
H
H
H
L
L
H
H
L
L
H
H
L
L
H
H
L
L
H
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
Figure 2: Logic Diagram
1A
1
14 VDD
1B
2
13 2D
NC
3
1C
4
1D
5
10 2B
1Y
6
9 2A
VSS
7
8 2Y
12 2C
Top
View
11 NC
Figure 3: Pin Out
H = high level, L = low level
Figure 1: Function Table
+25°C
Symbol
Parameter
tPLH
tPHL
-55°C / +125°C
Typ.
Max.
Typ.
Max.
Units
Propagation delay time, low to high level output
11
20
17
22
ns
Propagation delay time, high to low level output
10
18
18
20
ns
Figure 4: Switching Characteristics
Limits
+25°C
Symbol
Parameter
IDD
Quiescent Current
-55°C / +125°C
Test Conditions
Min.
Max.
Min.
Max.
Units
VIN = 0V or VDD
-
10
-
300
µA
VOL
Output Voltage Low Level
IOL = 9mA
-
0.4
-
0.4
V
VOH
Output Voltage High Level
IOH = -11mA
2.5
-
2.5
-
V
VIL1
Voltage Input Low (CMOS)
-
-
1.5
-
1.5
V
VIH1
Voltage Input High (CMOS)
-
3.5
-
3.5
-
V
VIL2
Voltage Input Low (TTL)
-
-
0.8
-
0.8
V
VIH2
Voltage Input High (TTL)
-
2.0
-
2.0
-
V
IIN
Input Leakage Current
VIN = VDD or VSS
-
±0.5
-
±5.0
µA
Figure 5: DC Characteristics
10/101
www.dynexsemi.com
54HSC/T Series
54HSC/T27 : Triple 3-Input Positive NOR Gates
The 54HSC/T27 is a Triple 3-Input Positive NOR gate.
Inputs
Outputs
A
B
C
Y
L
L
L
H
L
L
H
L
L
H
L
L
L
H
H
L
1A
1
14 VDD
H
L
L
L
1B
2
13 1C
H
L
H
L
2A
3
2B
4
H
H
L
L
H
H
H
L
Figure 2: Logic Diagram
H = high level, L = low level
12 1Y
Top
View
11 3C
2C
5
10 3B
2Y
6
9 3A
VSS
7
8 3Y
Figure 1: Function Table
Figure 3: Pin Out
+25°C
Symbol
Parameter
tPLH
tPHL
-55°C / +125°C
Typ.
Max.
Typ.
Max.
Units
Propagation delay time, low to high level output
11
20
17
22
ns
Propagation delay time, high to low level output
10
18
18
20
ns
Figure 4: Switching Characteristics
Limits
+25°C
Symbol
Parameter
IDD
Quiescent Current
VOL
-55°C / +125°C
Test Conditions
Min.
Max.
Min.
Max.
Units
VIN = 0V or VDD
-
10
-
300
µA
Output Voltage Low Level
IOL = 9mA
-
0.4
-
0.4
V
VOH
Output Voltage High Level
IOH = -11mA
2.5
-
2.5
-
V
VIL1
Voltage Input Low (CMOS)
-
-
1.5
-
1.5
V
VIH1
Voltage Input High (CMOS)
-
3.5
-
3.5
-
V
VIL2
Voltage Input Low (TTL)
-
-
0.8
-
0.8
V
VIH2
Voltage Input High (TTL)
-
2.0
-
2.0
-
V
IIN
Input Leakage Current
VIN = VDD or VSS
-
±0.5
-
±5.0
µA
Figure 5: DC Characteristics
11/101
www.dynexsemi.com
54HSC/T Series
54HSC/T32 : Quadruple 2-Input Positive OR Gates
The 54HSC/T32 is a Quadruple 2-Input Positive OR gate.
Inputs
Outputs
A
B
Y
L
L
L
L
H
H
H
L
H
H
H
H
Figure 2: Logic Diagram
1A
1
14 VDD
1B
2
13 4B
1Y
3
2A
4
2B
5
10 3B
2Y
6
9 3A
VSS
7
8 3Y
H = high level, L = low level
Figure 1: Function Table
12 4A
Top
View
11 4Y
Figure 3: Pin Out
+25°C
Symbol
Parameter
tPLH
tPHL
-55°C / +125°C
Typ.
Max.
Typ.
Max.
Units
Propagation delay time, low to high level output
11
20
17
22
ns
Propagation delay time, high to low level output
10
18
18
20
ns
Figure 4: Switching Characteristics
Limits
+25°C
Symbol
Parameter
IDD
Quiescent Current
VOL
-55°C / +125°C
Test Conditions
Min.
Max.
Min.
Max.
Units
VIN = 0V or VDD
-
10
-
300
µA
Output Voltage Low Level
IOL = 9mA
-
0.4
-
0.4
V
VOH
Output Voltage High Level
IOH = -11mA
2.5
-
2.5
-
V
VIL1
Voltage Input Low (CMOS)
-
-
1.5
-
1.5
V
VIH1
Voltage Input High (CMOS)
-
3.5
-
3.5
-
V
VIL2
Voltage Input Low (TTL)
-
-
0.8
-
0.8
V
VIH2
Voltage Input High (TTL)
-
2.0
-
2.0
-
V
IIN
Input Leakage Current
VIN = VDD or VSS
-
±0.5
-
±5.0
µA
Figure 5: DC Characteristics
12/101
www.dynexsemi.com
54HSC/T Series
54HSC/T86 : Quadruple 2-Input Exclusive OR Gates
The 54HSC/T86 is a Quadruple 2-Input Exclusive OR gate.
Inputs
Outputs
A
B
Y
L
L
L
L
H
H
H
L
H
H
H
L
Figure 2: Logic Diagram
1A
1
14 VDD
1B
2
13 4B
1Y
3
2A
4
2B
5
10 3B
2Y
6
9 3A
VSS
7
8 3Y
H = high level, L = low level
Figure 1: Function Table
12 4A
Top
View
11 4Y
Figure 3: Pin Out
+25°C
Symbol
Parameter
tPLH
tPHL
-55°C / +125°C
Typ.
Max.
Typ.
Max.
Units
Propagation delay time, low to high level output
11
20
17
22
ns
Propagation delay time, high to low level output
10
18
18
20
ns
Figure 4: Switching Characteristics
Limits
+25°C
Symbol
Parameter
IDD
Quiescent Current
VOL
-55°C / +125°C
Test Conditions
Min.
Max.
Min.
Max.
Units
VIN = 0V or VDD
-
10
-
300
µA
Output Voltage Low Level
IOL = 9mA
-
0.4
-
0.4
V
VOH
Output Voltage High Level
IOH = -11mA
2.5
-
2.5
-
V
VIL1
Voltage Input Low (CMOS)
-
-
1.5
-
1.5
V
VIH1
Voltage Input High (CMOS)
-
3.5
-
3.5
-
V
VIL2
Voltage Input Low (TTL)
-
-
0.8
-
0.8
V
VIH2
Voltage Input High (TTL)
-
2.0
-
2.0
-
V
IIN
Input Leakage Current
VIN = VDD or VSS
-
±0.5
-
±5.0
µA
Figure 5: DC Characteristics
13/101
www.dynexsemi.com
54HSC/T Series
54HSC/T125 : Quadruple Bus Buffer Gates with Tri-State Outputs
(Active Low Enable)
The 54HSC/T125 is a Quadruple Bus Buffer Gate. When G is
low the A input is transferred to the Y output. When G is high the
output is in a high impedance state.
Inputs
Outputs
G
A
Y
L
L
L
L
H
H
H
L
Z
H
H
Z
Figure 2: Logic Diagram
H = high level, L = low level, Z = high impedance
Figure 1: Function Table
1G
1
14 VDD
1A
2
13 4G
1Y
3
12 4A
Top
View
2G
4
2A
5
10 3G
2Y
6
9 3A
VSS
7
8 3Y
11 4Y
Figure 3: Pin Out
+25°C
Symbol
Parameter
tPLH
-55°C / +125°C
Typ.
Max.
Typ.
Max.
Units
Propagation delay A to Y
15
18
18
28
ns
tPHL
Propagation delay A to Y
15
20
18
28
ns
tPZH
Propagation delay G to Y
12
25
15
28
ns
tPZL
Propagation delay G to Y
12
25
15
28
ns
tPHZ
Propagation delay Y to Tri-State
12
25
15
28
ns
tPLZ
Propagation delay Y to Tri-State
12
25
15
28
ns
Figure 4: Switching Characteristics
14/101
www.dynexsemi.com
54HSC/T Series
54HSC/T125 : Quadruple Bus Buffer Gates with Tri-State Outputs
(Active Low Enable)
Limits
+25°C
Symbol
Parameter
IDD
Quiescent Current
VOL
-55°C / +125°C
Test Conditions
Min.
Max.
Min.
Max.
Units
VIN = 0V or VDD
-
10
-
400
µA
Output Voltage Low Level
IOL = 9mA
-
0.4
-
0.4
V
VOH
Output Voltage High Level
IOH = -11mA
2.5
-
2.5
-
V
VIL1
Voltage Input Low (CMOS)
-
-
1.5
-
1.5
V
VIH1
Voltage Input High (CMOS)
-
3.5
-
3.5
-
V
VIL2
Voltage Input Low (TTL)
-
-
0.8
-
0.8
V
VIH2
Voltage Input High (TTL)
-
2.0
-
2.0
-
V
IIN
Input Leakage Current
VIN = VDD or VSS
-
±0.5
-
±5.0
µA
Figure 5: DC Characteristics
15/101
www.dynexsemi.com
54HSC/T Series
54HSC/T126 : Quadruple Bus Buffer Gates with Tri-State Outputs
(Active High Enable)
The 54HSC/T126 is a Quadruple Bus Buffer Gate. When G is
high the A input is transferred tp the Y output. When G is low the
output is in a high impedance state.
Inputs
Outputs
G
A
Y
H
L
L
H
H
H
L
L
Z
L
H
Z
Figure 2: Logic Diagram
1
14 VDD
1A
2
13 4G
1Y
3
1G
H = high level, L = low level, Z = high impedance
Figure 1: Function Table
2G
12 4A
Top
View
4
11 4Y
2A
5
10 3G
2Y
6
9 3A
VSS
7
8 3Y
Figure 3: Pin Out
+25°C
Symbol
Parameter
tPLH
tPHL
-55°C / +125°C
Typ.
Max.
Typ.
Max.
Units
Propagation delay A to Y
14
25
17
28
ns
Propagation delay A to Y
15
25
19
28
ns
tPZH
Propagation delay G to Y
15
25
18
28
ns
tPZL
Propagation delay G to Y
17
25
19
28
ns
tPHZ
Propagation delay Y to Tri-State
17
25
20
28
ns
tPLZ
Propagation delay Y to Tri-State
15
25
19
28
ns
Figure 4: Switching Characteristics
16/101
www.dynexsemi.com
54HSC/T Series
54HSC/T126 : Quadruple Bus Buffer Gates with Tri-State Outputs
(Active High Enable)
Limits
+25°C
Symbol
Parameter
Test Conditions
Min.
-55°C / +125°C
Max.
Min.
Max.
Units
IDD
Quiescent Current
VIN = 0V or VDD
-
10
-
400
µA
VOL
Output Voltage Low Level
IOL = 9mA
-
0.4
-
0.4
V
VOH
Output Voltage High Level
IOH = -11mA
2.5
-
2.5
-
V
VIL1
Voltage Input Low (CMOS)
-
-
1.5
-
1.5
V
VIH1
Voltage Input High (CMOS)
-
3.5
-
3.5
-
V
VIL2
Voltage Input Low (TTL)
-
-
0.8
-
0.8
V
VIH2
Voltage Input High (TTL)
-
2.0
-
2.0
-
V
IIN
Input Leakage Current
VIN = VDD or VSS
-
±0.5
-
±5.0
µA
Figure 5: DC Characteristics
17/101
www.dynexsemi.com
54HSC/T Series
54HSC/T74 : Dual D-Type Flip-Flops with Preset and Clear
The 54HSC/T74 is a Dual D-Type Flip-Flop. The D inputs are
transferred to the Q outputs on the positive going edge of the
clock pulse. The clear is active low.
Inputs
Output
PRESET
CLEAR
CLOCK
D
Q
Q
L
H
X
X
H
L
H
L
X
X
L
H
L
L
X
X
H*
H*
H
H
L-H
H
H
L
H
H
L-H
L
L
H
H
H
L
X
Q0
Q0
H = high level, L = low level, X = irrelevant, * = unknown return state
Figure 1: Function Table
Figure 2: Logic Diagram
1CLEAR
1
14 VDD
1D
2
13 2CLEAR
1CLK
3
1PR
4
1Q
5
10 2PR
1Q
6
9 2Q
VSS
7
8 2Q
12 2D
Top
View
11 2CLK
Figure 3: Pin Out
+25°C
Symbol
Parameter
tPLH
-55°C / +125°C
Typ.
Max.
Typ.
Max.
Units
Propagation delay. Preset to Q or Q.
15
20
18
24
ns
tPHL
Propagation delay. Preset to Q or Q.
16
20
10
24
ns
tPLH
Propagation delay. Clear to Q or Q.
18
20
15
24
ns
tPHL
Propagation delay. Clear to Q or Q.
15
20
15
24
ns
tPLH
Propagation delay. Clock to Q or Q.
17
25
15
25
ns
tPHL
Propagation delay. Clock to Q or Q.
18
25
15
25
ns
Figure 4: Switching Characteristics
18/101
www.dynexsemi.com
54HSC/T Series
54HSC/T74 : Dual D-Type Flip-Flops with Preset and Clear
Limits
+25°C
Symbol
Parameter
IDD
Quiescent Current
VOL
-55°C / +125°C
Test Conditions
Min.
Max.
Min.
Max.
Units
VIN = 0V or VDD
-
10
-
400
µA
Output Voltage Low Level
IOL = 9mA
-
0.4
-
0.4
V
VOH
Output Voltage High Level
IOH = -11mA
2.5
-
2.5
-
V
VIL1
Voltage Input Low (CMOS)
-
-
1.5
-
1.5
V
VIH1
Voltage Input High (CMOS)
-
3.5
-
3.5
-
V
VIL2
Voltage Input Low (TTL)
-
-
0.8
-
0.8
V
VIH2
Voltage Input High (TTL)
-
2.0
-
2.0
-
V
IIN
Input Leakage Current
VIN = VDD or VSS
-
±0.5
-
±5.0
µA
Figure 5: DC Characteristics
19/101
www.dynexsemi.com
54HSC/T Series
54HSC/T109 : Dual J-KB Flip-Flops with Preset and Clear
The 54HSC/T109 is a Dual Positive-Edge-Triggered J-KB
Flip-Flop with preset and clear.
Inputs
Output
PRESET
CLEAR
CLOCK
J
KB
Q
Q
L
H
X
X
X
H
L
1CLR
1
16 VDD
H
L
X
X
X
L
H
1J
2
15 2CLR
L
L
X
X
X
H*
H*
1K
3
14 2J
1CK
4
H
H
↑
L
L
L
H
1PR
5
H
H
↑
H
L
1Q
6
11 2PR
H
H
↑
L
H
Q0
Q0
1Q
7
10 2Q
H
H
↑
H
H
H
L
VSS
8
9 2Q
H
H
L
X
X
Q0
Q0
Top
View
13 2K
12 2CK
Toggle Toggle
H = high level, L = low level, X = irrelevant, * = unknown return state
Figure 2: Function Table
Figure 1: Pin Out
Figure 3: Logic Diagram
+25°C
Symbol
Parameter
tPLH
-55°C / +125°C
Typ.
Max.
Typ.
Max.
Units
Propagation delay. Preset to Q or Q.
15
19
17
19
ns
tPHL
Propagation delay. Preset to Q or Q.
16
25
19
25
ns
tPLH
Propagation delay. Clear to Q or Q.
17
25
20
25
ns
tPHL
Propagation delay. Clear to Q or Q.
15
25
18
25
ns
tPLH
Propagation delay. Clock to Q or Q.
18
25
21
25
ns
tPHL
Propagation delay. Clock to Q or Q.
15
25
18
25
ns
Figure 4: Switching Characteristics
20/101
www.dynexsemi.com
54HSC/T Series
54HSC/T109 : Dual J-KB Flip-Flops with Preset and Clear
Limits
+25°C
Symbol
Parameter
IDD
Quiescent Current
VOL
-55°C / +125°C
Test Conditions
Min.
Max.
Min.
Max.
Units
VIN = 0V or VDD
-
20
-
400
µA
Output Voltage Low Level
IOL = 9mA
-
0.4
-
0.4
V
VOH
Output Voltage High Level
IOH = -11mA
2.5
-
2.5
-
V
VIL1
Voltage Input Low (CMOS)
-
-
1.5
-
1.5
V
VIH1
Voltage Input High (CMOS)
-
3.5
-
3.5
-
V
VIL2
Voltage Input Low (TTL)
-
-
0.8
-
0.8
V
VIH2
Voltage Input High (TTL)
-
2.0
-
2.0
-
V
IIN
Input Leakage Current
VIN = VDD or VSS
-
±0.5
-
±5.0
µA
Figure 5: DC Characteristics
21/101
www.dynexsemi.com
54HSC/T Series
54HSC/T273 : Octal D-Type Flip-Flops
The 54HSC/T273 is an Octal D-Type Flip-Flop with a direct
active low clear. The D-Inputs are transferred to the Q-Outputs
on the positive going edge of the clock pulse.
Inputs
CLEAR
1
20 VDD
1Q
2
19 8Q
1D
3
18 8D
Outputs
2D
4
CLEAR
CLOCK
D
Q
2Q
5
L
X
X
L
3Q
6
3D
7
14 6D
4D
8
13 5D
4Q
9
12 5Q
H
L-H
H
H
H
L-H
L
L
H
L
X
Q0
17 7D
16 7Q
Top
View
15 6Q
VSS 10
11 CLOCK
Q0 = level of Q before inputs were established
H = high level, L = low level, X = irrelevant
Figure 2: Pin Out
Figure 1: Function Table
Figure 3: Logic Diagram
+25°C
Symbol
Parameter
tPLH
-55°C / +125°C
Typ.
Max.
Typ.
Max.
Units
Propagation delay. Clear to Q or Q.
14
25
17
28
ns
tPHL
Propagation delay. Clear to Q or Q.
16
25
19
28
ns
tPLH
Propagation delay. Clock to Q or Q.
15
25
18
28
ns
tPHL
Propagation delay. Clock to Q or Q.
17
25
20
28
ns
Figure 4: Switching Characteristics
22/101
www.dynexsemi.com
54HSC/T Series
54HSC/T273 : Octal D-Type Flip-Flops
Limits
+25°C
Symbol
Parameter
IDD
Quiescent Current
VOL
-55°C / +125°C
Test Conditions
Min.
Max.
Min.
Max.
Units
VIN = 0V or VDD
-
20
-
600
µA
Output Voltage Low Level
IOL = 9mA
-
0.4
-
0.4
V
VOH
Output Voltage High Level
IOH = -11mA
2.5
-
2.5
-
V
VIL1
Voltage Input Low (CMOS)
-
-
1.5
-
1.5
V
VIH1
Voltage Input High (CMOS)
-
3.5
-
3.5
-
V
VIL2
Voltage Input Low (TTL)
-
-
0.8
-
0.8
V
VIH2
Voltage Input High (TTL)
-
2.0
-
2.0
-
V
IIN
Input Leakage Current
VIN = VDD or VSS
-
±0.5
-
±5.0
µA
Figure 5: DC Characteristics
23/101
www.dynexsemi.com
54HSC/T Series
54HSC/T374 : Octal D-Type Edge-Triggered Flip-Flops
The 54HSC/T374 consists of 8 Positive-Edge Triggered DType Flip-Flops with tri-state output.
Inputs
OC
CLOCK
OC
1
20 VDD
1Q
2
19 8Q
1D
3
18 8D
Outputs
D
Q
L
↑
H
H
L
↑
L
L
L
L
X
Q0
H
X
X
Z
2D
4
2Q
5
3Q
6
3D
7
14 6D
4D
8
13 5D
4Q
9
17 7D
16 7Q
Top
View
15 6Q
12 5Q
11 CLK
GND 10
H = high level, L = low level, X = irrelevant, Z = high impedance
Figure 1: Function Table
Figure 2: Pin Out
+25°C
Symbol
Parameter
tPLH
-55°C / +125°C
Min.
Typ.
Max.
Min.
Typ.
Max.
Units
Propagation delay. Low to high output.
-
14
22
-
17
25
ns
tPHL
Propagation delay. High to low output.
-
15
22
-
16
25
ns
tPZL
Propagation delay. Enable to low.
-
13
20
-
16
25
ns
tPZH
Propagation delay. Enable to high.
-
16
20
-
18
23
ns
tPLZ
Propagation delay. Disable from low.
-
14
20
-
16
22
ns
tPHZ
Propagation delay. Disable from high.
-
13
18
-
15
20
ns
Figure 3: Switching Characteristics
Limits
+25°C
Symbol
Parameter
Test Conditions
Min.
IDD
Quiescent Current
VIN = 0V or VDD
-
VOL
Output Voltage Low Level
IOL = 9mA
-
VOH
Output Voltage High Level
IOH = -11mA
2.5
VIL1
Voltage Input Low (CMOS)
-
-
VIH1
Voltage Input High (CMOS)
-
VIL2
Voltage Input Low (TTL)
-
VIH2
Voltage Input High (TTL)
IOZ
IIN
-55°C / +125°C
Max.
Min.
Max.
Units
20
-
600
µA
0.4
-
0.4
V
-
2.5
-
V
1.5
-
1.5
V
3.5
-
3.5
-
V
-
0.8
-
0.8
V
-
2.0
-
2.0
-
V
Tri-State Leakage
VO = 0V or VDD
-
±1
-
±50
µA
Input Leakage Current
VIN = VDD or VSS
-
±0.5
-
±5.0
µA
Figure 4: DC Characteristics
24/101
www.dynexsemi.com
54HSC/T Series
54HSC/T374 : Octal D-Type Edge-Triggered Flip-Flops
Figure 5: Logic Diagram
25/101
www.dynexsemi.com
54HSC/T Series
54HSC/T574 : Octal D-Type Edge-Triggered Flip-Flops
The 54HSC/T574 consists of 8 Positive-Edge Triggered DType Flip-Flops with tri-state output.
Inputs
OC
CLOCK
OC
1
20 VDD
1D
2
19 1Q
Outputs
2D
3
18 2Q
Q
3D
4
4D
5
5D
6
6D
7
14 6Q
7D
8
13 7Q
8D
9
12 8Q
D
L
↑
H
H
L
↑
L
L
L
L
X
Q0
H
X
X
Z
17 3Q
16 4Q
Top
View
15 5Q
11 CLK
GND 10
H = high level, L = low level, X = irrelevant, Z = high impedance
Figure 1: Function Table
Figure 2: Pin Out
+25°C
Symbol
Parameter
tPLH
-55°C / +125°C
Min.
Typ.
Max.
Min.
Typ.
Max.
Units
Propagation delay. Low to high output.
-
16
25
-
19
28
ns
tPHL
Propagation delay. High to low output.
-
19
27
-
22
30
ns
tPZL
Propagation delay. Enable to low.
-
13
21
-
16
24
ns
tPZH
Propagation delay. Enable to high.
-
16
24
-
19
27
ns
tPLZ
Propagation delay. Disable from low.
-
14
22
-
17
25
ns
tPHZ
Propagation delay. Disable from high.
-
13
21
-
16
24
ns
Figure 3: Switching Characteristics
Limits
+25°C
Symbol
Parameter
Test Conditions
Min.
IDD
Quiescent Current
VIN = 0V or VDD
-
VOL
Output Voltage Low Level
IOL = 9mA
-
VOH
Output Voltage High Level
IOH = -11mA
2.5
VIL1
Voltage Input Low (CMOS)
-
-
VIH1
Voltage Input High (CMOS)
-
VIL2
Voltage Input Low (TTL)
-
VIH2
Voltage Input High (TTL)
IOZ
IIN
-55°C / +125°C
Max.
Min.
Max.
Units
20
-
600
µA
0.4
-
0.4
V
-
2.5
-
V
1.5
-
1.5
V
3.5
-
3.5
-
V
-
0.8
-
0.8
V
-
2.0
-
2.0
-
V
Tri-State Leakage
VO = 0V or VDD
-
±1
-
±50
µA
Input Leakage Current
VIN = VDD or VSS
-
±0.5
-
±5.0
µA
Figure 4: DC Characteristics
26/101
www.dynexsemi.com
54HSC/T Series
54HSC/T574 : Octal D-Type Edge-Triggered Flip-Flops
Figure 5: Logic Diagram
27/101
www.dynexsemi.com
54HSC/T Series
54HSC/T283 : 4-Bit Binary Full Adders with Fast Carry
The 54HSC/T283 are 4-Bit Binary Full Adders with fast carry.
Input
Output
When CO=L / When C2=L When CO=H / When C2=H
∑2
1
B2
2
15 B3
A2
3
14 A3
A1/A3
B1/B3
A2/A4
B2/B4
∑1/∑3
∑2/∑4 C2/C4
L
L
L
L
L
L
H
L
L
L
H
L
H
L
L
H
H
H
L
L
L
L
H
L
H
L
H
L
L
H
H
H
H
L
16 VCC
∑1/∑3
∑2/∑4
C2/C4
L
H
L
L
∑1
4
L
L
L
H
L
A1
5
L
L
L
H
L
B1
6
11 B4
L
H
L
H
H
L
CO
7
10 ∑4
L
H
L
H
H
L
GND
8
9 C4
H
H
L
L
L
H
L
H
H
L
L
L
H
H
L
L
L
H
H
L
H
L
L
H
L
H
L
H
H
L
H
L
L
H
H
H
L
L
L
H
L
H
L
H
H
H
L
L
L
H
H
H
L
H
L
L
H
H
L
H
L
L
H
H
L
L
H
H
L
H
H
L
H
H
H
L
H
L
H
H
L
H
H
H
H
L
H
L
H
H
H
H
H
H
L
H
H
H
H
H
Top
View
13 ∑3
12 A4
Figure 2: Pin Out
H = high level, L = low level
Figure 1: Function Table
+25°C
Symbol
Parameter
tPLH
-55°C / +125°C
Typ.
Max.
Typ.
Max.
Units
Propagation delay. C0 to any ∑.
13
25
16
28
ns
tPHL
Propagation delay. C0 to any ∑.
12
25
15
28
ns
tPLH
Propagation delay. Ai or Bi to ∑i.
14
25
17
28
ns
tPHL
Propagation delay. Ai or Bi to ∑i.
12
25
15
28
ns
tPLH
Propagation delay. C0 to C4.
11
25
14
28
ns
tPHL
Propagation delay. C0 to C4.
16
25
19
28
ns
tPLH
Propagation delay. Ai or Bi to C4.
15
25
19
28
ns
tPHL
Propagation delay. Ai or Bi to C4.
14
25
17
28
ns
Figure 3: Switching Characteristics
28/101
www.dynexsemi.com
54HSC/T Series
54HSC/T283 : 4-Bit Binary Full Adders with Fast Carry
Limits
+25°C
Symbol
Parameter
IDD
Quiescent Current
VOL
-55°C / +125°C
Test Conditions
Min.
Max.
Min.
Max.
Units
VIN = 0V or VDD
-
20
-
600
µA
Output Voltage Low Level
IOL = 9mA
-
0.4
-
0.4
V
VOH
Output Voltage High Level
IOH = -11mA
2.5
-
2.5
-
V
VIL1
Voltage Input Low (CMOS)
-
-
1.5
-
1.5
V
VIH1
Voltage Input High (CMOS)
-
3.5
-
3.5
-
V
VIL2
Voltage Input Low (TTL)
-
-
0.8
-
0.8
V
VIH2
Voltage Input High (TTL)
-
2.0
-
2.0
-
V
IIN
Input Leakage Current
VIN = VDD or VSS
-
±0.5
-
±5.0
µA
Figure 4: DC Characteristics
29/101
www.dynexsemi.com
54HSC/T Series
54HSC/T283 : 4-Bit Binary Full Adders with Fast Carry
Figure 5: Logic Diagram
30/101
www.dynexsemi.com
54HSC/T Series
54HSC/T161 : 4-Bit Synchronous Binary Counter
The 54HSC/T161 is a Synchronous 4-Bit Binary Counter which features direct clear and
an internal carry look-ahead.
Inputs
Output
Clear
Enable P
Enable T
A→
→D
Load
Clock
QA→QD
L
X
X
X
X
X
0
H
L
X
X
H
X
Inhibit
H
X
L
X
H
X
Inhibit
H
X
X
Qn
L
↑
Qn
H
X
X
X
X
L
Q0
H
X
X
X
X
H
Q0
H
H
H
X
H
↑
Count
CARRY = H when QA→QD = H, Q0 = previous level of Q
H = high level, L = low level, X = irrelevant
Figure 1: Function Table
16 VDD
CLEAR
1
CLOCK
2
15 RCO
A
3
14 QA
B
4
C
5
D
6
11 QD
ENABLE P
7
10 ENABLE T
VSS
8
9 LOAD
Top
View
13 QB
12 QC
Figure 2: Pin Out
+25°C
Symbol
-55°C / +125°C
From (Input)
To (Output)
Typ.
Max.
Typ.
Max.
Units
tPLH
CLOCK
RIPPLE CARRY
20
25
23
28
ns
tPHL
CLOCK
RIPPLE CARRY
19
25
22
28
ns
tPLH
CLOCK (Load Input HIGH)
Any Q Output
16
25
19
28
ns
tPHL
CLOCK (Load Input HIGH)
Any Q Output
15
25
18
28
ns
tPLH
CLOCK (Load Input LOW)
Any Q Output
15
25
18
28
ns
tPHL
CLOCK (Load Input LOW)
Any Q Output
15
25
18
28
ns
tPLH
ENABLE
RIPPLE CARRY
14
25
17
28
ns
tPHL
ENABLE
RIPPLE CARRY
14
25
17
28
ns
tPHL
CLEAR
Any Q Output
18
25
21
28
ns
Figure 3: Switching Characteristics
31/101
www.dynexsemi.com
54HSC/T Series
54HSC/T161 : 4-Bit Synchronous Binary Counter
Limits
+25°C
Symbol
Parameter
IDD
Quiescent Current
VOL
-55°C / +125°C
Test Conditions
Min.
Max.
Min.
Max.
Units
VIN = 0V or VDD
-
20
-
400
µA
Output Voltage Low Level
IOL = 9mA
-
0.4
-
0.4
V
VOH
Output Voltage High Level
IOH = -11mA
2.5
-
2.5
-
V
VIL1
Voltage Input Low (CMOS)
-
-
1.5
-
1.5
V
VIH1
Voltage Input High (CMOS)
-
3.5
-
3.5
-
V
VIL2
Voltage Input Low (TTL)
-
-
0.8
-
0.8
V
VIH2
Voltage Input High (TTL)
-
2.0
-
2.0
-
V
IIN
Input Leakage Current
VIN = VDD or VSS
-
±0.5
-
±5.0
µA
Figure 4: DC Characteristics
32/101
www.dynexsemi.com
54HSC/T Series
54HSC/T161 : 4-Bit Synchronous Binary Counter
Figure 5: Logic Diagram
33/101
www.dynexsemi.com
54HSC/T Series
54HSC/T163 : Synchronous 4-Bit Counter
The 54HSC/T163 is a 4-Bit Counter with synchronous clear.
Inputs
Output
Clear
Enable P
Enable T
A→
→D
Load
Clock
QA→QD
L
X
X
X
X
X
0
H
L
X
X
H
X
Inhibit
H
X
L
X
H
X
Inhibit
H
X
X
Qn
L
↑
Qn
H
X
X
X
X
L
Q0
H
X
X
X
X
H
Q0
H
H
H
X
H
↑
Count
CARRY = H when QA→QD = H, Q0 = previous level of Q
H = high level, L = low level, X = irrelevant
Figure 1: Function Table
CLEAR
1
16 VDD
CLK
2
15 RCO
A
3
14 QA
B
4
C
5
Top
View
13 QB
12 QC
D
6
11 QD
ENP
7
10 ENT
GND
8
9 LOAD
Figure 2: Pin Out
+25°C
Symbol
Parameter
tPLH
-55°C / +125°C
Typ.
Max.
Typ.
Max.
Units
Propagation delay Clock to RCO
12
20
15
22
ns
tPHL
Propagation delay Clock to RCO
14
20
17
22
ns
tPLH
Propagation delay Clock to any Q
15
20
18
22
ns
tPHL
Propagation delay Clock to any Q
13
20
16
22
ns
tPLH
Propagation delay ENT to RCO
9
15
12
17
ns
tPHL
Propagation delay ENT to RCO
10
15
13
17
ns
Figure 3: Switching Characteristics
34/101
www.dynexsemi.com
54HSC/T Series
54HSC/T163 : Synchronous 4-Bit Counter
Limits
+25°C
Symbol
Parameter
IDD
Quiescent Current
VOL
-55°C / +125°C
Test Conditions
Min.
Max.
Min.
Max.
Units
VIN = 0V or VDD
-
20
-
400
µA
Output Voltage Low Level
IOL = 9mA
-
0.4
-
0.4
V
VOH
Output Voltage High Level
IOH = -11mA
2.5
-
2.5
-
V
VIL1
Voltage Input Low (CMOS)
-
-
1.5
-
1.5
V
VIH1
Voltage Input High (CMOS)
-
3.5
-
3.5
-
V
VIL2
Voltage Input Low (TTL)
-
-
0.8
-
0.8
V
VIH2
Voltage Input High (TTL)
-
2.0
-
2.0
-
V
IIN
Input Leakage Current
VIN = VDD or VSS
-
±0.5
-
±5.0
µA
Figure 4: DC Characteristics
35/101
www.dynexsemi.com
54HSC/T Series
54HSC/T163 : Synchronous 4-Bit Counter
Figure 5: Logic Diagram
36/101
www.dynexsemi.com
54HSC/T Series
54HSC/T191 : Synchronous 4-Bit Counter
The 54HSC/T191 is a 4-Bit Synchronous Counter with presettable up/down and asynchronous reset.
Inputs
PL
CE
U/D
CP
Function
P1
1
16 VCC
Q1
2
15 P0
14 CP
H
L
L
↑
Count Up
Q0
3
H
L
H
↑
Count Down
CE
4
L
X
X
X
Asyn. Preset
U/D
5
H
H
X
X
No Change
Q2
6
11 PL
Q3
7
10 P2
GND
8
9 P3
H = high level, L = low level, X = irrelevant, ↑ = low-to-high clock (CP) transition.
Note: U/D or CE should be changed only when clock (CP) is high.
Top
View
13 RC
12 TC
Figure 1: Function Table
Figure 2: Pin Out
+25°C
Symbol
Parameter
tPLH
tPHL
-55°C / +125°C
Typ.
Max.
Typ.
Max.
Units
Propagation delay PL to Qn
-
29
-
33
ns
Propagation delay PL to Qn
-
32
-
36
ns
tPLH
Propagation delay Pn to Qn
-
27
-
31
ns
tPHL
Propagation delay Pn to Qn
-
30
-
34
ns
tPLH
Propagation delay CP to Qn
-
26
-
30
ns
tPHL
Propagation delay CP to Qn
-
29
-
33
ns
tPLH
Propagation delay CP to RC
-
20
-
23
ns
tPHL
Propagation delay CP to RC
-
32
-
34
ns
tPLH
Propagation delay CP to TC
-
29
-
33
ns
tPHL
Propagation delay CP to TC
-
32
-
36
ns
tPLH
Propagation delay U/D to RC
-
27
-
31
ns
tPHL
Propagation delay U/D to RC
-
30
-
34
ns
tPLH
Propagation delay U/D to TC
-
26
-
30
ns
tPHL
Propagation delay U/D to TC
-
29
-
33
ns
tPLH
Propagation delay CE to RC
-
22
-
25
ns
tPHL
Propagation delay CE to RC
-
35
-
38
ns
Figure 3: Switching Characteristics
37/101
www.dynexsemi.com
54HSC/T Series
54HSC/T191 : Synchronous 4-Bit Counter
Limits
+25°C
Symbol
Parameter
IDD
Quiescent Current
VOL
-55°C / +125°C
Test Conditions
Min.
Max.
Min.
Max.
Units
VIN = 0V or VDD
-
20
-
600
µA
Output Voltage Low Level
IOL = 9mA
-
0.4
-
0.4
V
VOH
Output Voltage High Level
IOH = -11mA
2.5
-
2.5
-
V
VIL1
Voltage Input Low (CMOS)
-
-
1.5
-
1.5
V
VIH1
Voltage Input High (CMOS)
-
3.5
-
3.5
-
V
VIL2
Voltage Input Low (TTL)
-
-
0.8
-
0.8
V
VIH2
Voltage Input High (TTL)
-
2.0
-
2.0
-
V
IIN
Input Leakage Current
VIN = VDD or VSS
-
±0.5
-
±5.0
µA
Figure 4: DC Characteristics
P1
P0
15
P2
1
P3
10
9
14
13
CP
RC
5
U/D
12
11
PL
TC
PL
PL
PL
P
P
PL
P
P
T
Q
T
Q
T
Q
T
CP
Q
CP
Q
CP
Q
CP
FF1
FF0
FF2
Q
Q
FF3
4
CE
3
Q0
2
Q1
6
Q2
7
Q3
Figure 5: Logic Diagram
38/101
www.dynexsemi.com
54HSC/T Series
54HSC/T138 : 3-Line to 8-Line Decoder/Multiplexer
The 54HSC/T138 is a 3-Line to 8-Line Decoder/Multiplexer, with inverted outputs.
Enable Inputs
G1
G2A
X
X
Select Inputs
Outputs
G2B
C
B
A
Y0
Y1
Y2
Y3
Y4
Y5
Y6
Y7
H
X
X
X
X
H
H
H
H
H
H
H
H
X
H
X
X
X
H
H
H
H
H
H
H
H
L
X
X
X
X
X
H
H
H
H
H
H
H
H
H
L
L
L
L
L
L
H
H
H
H
H
H
H
H
L
L
L
L
H
H
L
H
H
H
H
H
H
H
L
L
L
H
L
H
H
L
H
H
H
H
H
H
L
L
L
H
H
H
H
H
L
H
H
H
H
H
L
L
H
L
L
H
H
H
H
L
H
H
H
H
L
L
H
L
H
H
H
H
H
H
L
H
H
H
L
L
H
H
L
H
H
H
H
H
H
L
H
H
L
L
H
H
H
H
H
H
H
H
H
H
L
H = high level, L = low level, X = irrelevant
Figure 1: Function Table
A
1
16 VDD
B
2
15 Y0
C
3
14 Y1
G2A
4
G2B
5
G1
6
11 Y4
YZ
7
10 Y5
VSS
8
9 Y6
Top
View
13 Y2
12 Y3
Figure 2: Pin Out
+25°C
Symbol
Parameter
tPLH
-55°C / +125°C
Typ.
Max.
Typ.
Max.
Units
Propagation delay. Address to Output.
17
25
20
28
ns
tPHL
Propagation delay. Address to Output.
19
25
22
28
ns
tPLH
Propagation delay. G to Output.
21
25
24
28
ns
tPHL
Propagation delay. G to Output.
21
25
24
28
ns
Figure 3: Switching Characteristics
39/101
www.dynexsemi.com
54HSC/T Series
54HSC/T138 : 3-Line to 8-Line Decoder/Multiplexer
Limits
+25°C
Symbol
Parameter
IDD
Quiescent Current
VOL
-55°C / +125°C
Test Conditions
Min.
Max.
Min.
Max.
Units
VIN = 0V or VDD
-
10
-
400
µA
Output Voltage Low Level
IOL = 9mA
-
0.4
-
0.4
V
VOH
Output Voltage High Level
IOH = -11mA
2.5
-
2.5
-
V
VIL1
Voltage Input Low (CMOS)
-
-
1.5
-
1.5
V
VIH1
Voltage Input High (CMOS)
-
3.5
-
3.5
-
V
VIL2
Voltage Input Low (TTL)
-
-
0.8
-
0.8
V
VIH2
Voltage Input High (TTL)
-
2.0
-
2.0
-
V
IIN
Input Leakage Current
VIN = VDD or VSS
-
±0.5
-
±5.0
µA
Figure 4: DC Characteristics
Figure 5: Logic Diagram
40/101
www.dynexsemi.com
54HSC/T Series
54HSC/T139 : Dual 2 to 4 Decoders/Multiplexers
The 54HSC/T139 consists of Two Independent 2 to 4 Line Decoder/Multiplexers.
Inputs
Enable
Output
Select
G
B
A
Y0
Y1
Y2
Y3
H
X
X
H
H
H
H
L
L
L
L
H
H
H
L
L
H
H
L
H
H
L
H
L
H
H
L
H
L
H
H
H
H
H
L
H = high level, L = low level, X = irrelevant
Figure 1: Function Table
1G
1
16 VDD
1A
2
15 2G
1B
3
14 2A
1Y0
4
1Y1
5
1Y2
6
11 2Y1
1Y3
7
10 2Y2
VSS
8
9 2Y3
Top
View
13 2B
12 2Y0
Figure 2: Pin Out
+25°C
Symbol
Parameter
tPLH
-55°C / +125°C
Typ.
Max.
Typ.
Max.
Units
Propagation delay. Address to Output.
16
28
22
34
ns
tPHL
Propagation delay. Address to Output.
17
28
20
34
ns
tPLH
Propagation delay. G to Output.
16
22
19
25
ns
tPHL
Propagation delay. G to Output.
17
22
20
25
ns
Figure 3: Switching Characteristics
41/101
www.dynexsemi.com
54HSC/T Series
54HSC/T139 : Dual 2 to 4 Decoders/Multiplexers
Limits
+25°C
Symbol
Parameter
IDD
Quiescent Current
VOL
-55°C / +125°C
Test Conditions
Min.
Max.
Min.
Max.
Units
VIN = 0V or VDD
-
10
-
400
µA
Output Voltage Low Level
IOL = 9mA
-
0.4
-
0.4
V
VOH
Output Voltage High Level
IOH = -11mA
2.5
-
2.5
-
V
VIL1
Voltage Input Low (CMOS)
-
-
1.5
-
1.5
V
VIH1
Voltage Input High (CMOS)
-
3.5
-
3.5
-
V
VIL2
Voltage Input Low (TTL)
-
-
0.8
-
0.8
V
VIH2
Voltage Input High (TTL)
-
2.0
-
2.0
-
V
IIN
Input Leakage Current
VIN = VDD or VSS
-
±0.5
-
±5.0
µA
Figure 4: DC Characteristics
Figure 5: Logic Diagram
42/101
www.dynexsemi.com
54HSC/T Series
54HSC/T148 : 8-Line to 3-Line Octal Priority Encoders
The 54HSC/T148 is an 8 to 3 Line Priority Encoder. Data inputs
and outputs are active at the low logic level. Data is accepted
on the eight priority inputs (I0-I7). The binary code,
corresponding to the highest priority input which is low, is
generated on the address outputs (A0-A2) if the enable input is
high. The group select (GS) is low when one or more priority
inputs and the enable input (EI) are low. The enable output
(EO) is low when all priority inputs are high and the enable is
low. When the enable input is high all outputs are high.
I4
1
16 VDD
I5
2
15 EO
I6
3
14 GS
I7
4
13 I3
Top
View
EI
5
A2
6
11 I1
A1
7
10 I0
VSS
8
9 A0
12 I2
Figure 1: Pin Out
Inputs
Outputs
EI
I0
I1
I2
I3
I4
I5
I6
I7
A2
A1
A0
GS
EO
H
X
X
X
X
X
X
X
X
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
L
L
X
X
X
X
X
X
X
L
L
L
L
L
H
L
X
X
X
X
X
X
L
H
L
L
H
L
H
L
X
X
X
X
X
L
H
H
L
H
L
L
H
L
X
X
X
X
L
H
H
H
L
H
H
L
H
L
X
X
X
L
H
H
H
H
H
L
L
L
H
L
X
X
L
H
H
H
H
H
H
L
H
L
H
L
X
L
H
H
H
H
H
H
H
H
L
L
H
L
L
H
H
H
H
H
H
H
H
H
H
L
H
H = high level, L = low level, X = irrelevant
Figure 2: Function Table
+25°C
-55°C / +125°C
Symbol
Parameter
Typ.
Max.
Typ.
Max.
Units
tPLH
Propagation delay EI to A
14
22
17
28
ns
tPHL
Propagation delay EI to A
15
22
18
28
ns
tPLH
Propagation delay EI to GS
15
22
18
28
ns
tPHL
Propagation delay EI to GS
15
22
18
28
ns
tPLH
Propagation delay EI to EO
14
22
17
28
ns
tPHL
Propagation delay EI to EO
15
22
18
28
ns
tPLH
Propagation delay I to A
12
22
15
28
ns
tPHL
Propagation delay I to A
14
22
17
28
ns
Figure 3: Switching Characteristics
43/101
www.dynexsemi.com
54HSC/T Series
54HSC/T148 : 8-Line to 3-Line Octal Priority Encoders
Limits
+25°C
Symbol
Parameter
IDD
Quiescent Current
VOL
-55°C / +125°C
Test Conditions
Min.
Max.
Min.
Max.
Units
VIN = 0V or VDD
-
20
-
400
µA
Output Voltage Low Level
IOL = 9mA
-
0.4
-
0.4
V
VOH
Output Voltage High Level
IOH = -11mA
2.5
-
2.5
-
V
VIL1
Voltage Input Low (CMOS)
-
-
1.5
-
1.5
V
VIH1
Voltage Input High (CMOS)
-
3.5
-
3.5
-
V
VIL2
Voltage Input Low (TTL)
-
-
0.8
-
0.8
V
VIH2
Voltage Input High (TTL)
-
2.0
-
2.0
-
V
IIN
Input Leakage Current
VIN = VDD or VSS
-
±0.5
-
±5.0
µA
Figure 4: DC Characteristics
44/101
www.dynexsemi.com
54HSC/T Series
54HSC/T148 : 8-Line to 3-Line Octal Priority Encoders
Figure 5: Logic Diagram
45/101
www.dynexsemi.com
54HSC/T Series
54HSC/T151 : 1 of 8 Data Selectors/Multiplexers
The 54HSC/T151 is a 1 of 8 Data Selector. When the strobe input is low the
device is enabled. When high this forces the W-output high and the Youtput low.
Inputs
Output
Select
D3
1
16 VDD
D2
2
15 D4
D1
3
14 D5
D0
4
D0
Y
5
W
6
11 A
STR
7
10 B
VSS
8
9 C
Strobe
C
B
A
STR
Y
W
X
X
X
H
L
H
L
L
L
L
D0
L
L
H
L
D1
D1
L
H
L
L
D2
D2
L
H
H
L
D3
D3
H
L
L
L
D4
D4
H
L
H
L
D5
D5
H
H
L
L
D6
D6
H
H
H
L
D7
D7
Top
View
13 D6
12 D7
Figure 2: Pin Out
H = high level, L = low level, X = irrelevant
Figure 1: Function Table
+25°C
Symbol
Parameter
tPLH
-55°C / +125°C
Typ.
Max.
Typ.
Max.
Units
Propagation delay A B or C to Y
15
22
18
25
ns
tPHL
Propagation delay A B or C to Y
16
22
19
25
ns
tPLH
Propagation delay A B or C to W
14
22
17
25
ns
tPHL
Propagation delay A B or C to W
15
22
18
25
ns
tPLH
Propagation delay Strobe to Y
14
22
17
25
ns
tPHL
Propagation delay Strobe to Y
16
22
19
25
ns
tPLH
Propagation delay Strobe to W
14
22
17
25
ns
tPHL
Propagation delay Strobe to W
15
22
18
25
ns
tPLH
Propagation delay D0-D7 to Y
12
22
15
25
ns
tPHL
Propagation delay D0-D7 to Y
14
22
17
25
ns
tPLH
Propagation delay D0-D7 to W
12
22
15
25
ns
tPHL
Propagation delay D0-D7 to W
14
22
17
25
ns
Figure 3: Switching Characteristics
46/101
www.dynexsemi.com
54HSC/T Series
54HSC/T151 : 1 of 8 Data Selectors/Multiplexers
Limits
+25°C
Symbol
Parameter
IDD
Quiescent Current
VOL
-55°C / +125°C
Test Conditions
Min.
Max.
Min.
Max.
Units
VIN = 0V or VDD
-
20
-
400
µA
Output Voltage Low Level
IOL = 9mA
-
0.4
-
0.4
V
VOH
Output Voltage High Level
IOH = -11mA
2.5
-
2.5
-
V
VIL1
Voltage Input Low (CMOS)
-
-
1.5
-
1.5
V
VIH1
Voltage Input High (CMOS)
-
3.5
-
3.5
-
V
VIL2
Voltage Input Low (TTL)
-
-
0.8
-
0.8
V
VIH2
Voltage Input High (TTL)
-
2.0
-
2.0
-
V
IIN
Input Leakage Current
VIN = VDD or VSS
-
±0.5
-
±5.0
µA
Figure 4: DC Characteristics
47/101
www.dynexsemi.com
54HSC/T Series
54HSC/T151 : 1 of 8 Data Selectors/Multiplexers
Figure 5: Logic Diagram
48/101
www.dynexsemi.com
54HSC/T Series
54HSC/T154 : 4 to 16 Line Decoders/Demultiplexers
The 54HSC/T154 consists of a 4 to 16 Line Decoder/Demultiplexer.
Inputs
Outputs
G1
G2
D
C
B
A
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
L
L
L
L
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
L
L
L
H
L
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
L
L
L
L
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
L
L
L
H
L
L
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
L
L
L
H
L
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
H
L
L
L
H
H
L
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
L
L
L
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
L
L
H
L
L
L
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
L
L
H
L
L
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
L
L
H
L
H
L
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
L
L
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
L
L
H
H
L
L
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
L
L
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
L
L
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
L
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
L
H
X
X
X
X
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
X
X
X
X
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
X
X
X
X
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H = high level, L = low level, X = irrelevant
Figure 1: Function Table
0
1
24 VDD
1
2
23 A
2
3
22 B
3
4
21 C
4
5
20 D
5
6
6
7
7
8
17 15
8
Top
View
19 G2
18 G1
9
16 14
9 10
15 13
10 11
14 12
VSS 12
13 11
Figure 2: Pin Out
49/101
www.dynexsemi.com
54HSC/T Series
54HSC/T154 : 4 to 16 Line Decoders/Demultiplexers
+25°C
Sym
Parameter
tPLH
-55°C / +125°C
Typ.
Max.
Typ.
Max.
Units
Propagation delay low to high level
output for change in A B C or D input
18
30
21
33
ns
tPHL
Propagation delay high to low level
output for change in A B C or D input
21
30
24
33
ns
tPLH
Propagation delay low to high level
output for change in G1 or G2
21
30
24
33
ns
tPHL
Propagation delay high to low level
output for change in G1 or G2
18
30
21
33
ns
Figure 3: Switching Characteristics
Limits
+25°C
Symbol
Parameter
IDD
Quiescent Current
VOL
-55°C / +125°C
Test Conditions
Min.
Max.
Min.
Max.
Units
VIN = 0V or VDD
-
100
-
600
µA
Output Voltage Low Level
IOL = 9mA
-
0.4
-
0.4
V
VOH
Output Voltage High Level
IOH = -11mA
2.5
-
2.5
-
V
VIL1
Voltage Input Low (CMOS)
-
-
1.5
-
1.5
V
VIH1
Voltage Input High (CMOS)
-
3.5
-
3.5
-
V
VIL2
Voltage Input Low (TTL)
-
-
0.8
-
0.8
V
VIH2
Voltage Input High (TTL)
-
2.0
-
2.0
-
V
IIN
Input Leakage Current
VIN = VDD or VSS
-
±0.5
-
±5.0
µA
Figure 4: DC Characteristics
50/101
www.dynexsemi.com
54HSC/T Series
54HSC/T154 : 4 to 16 Line Decoders/Demultiplexers
Figure 5: Logic Diagram
51/101
www.dynexsemi.com
54HSC/T Series
54HSC/T157 : Quad 2-Line to 1-Line Data Selectors/Multiplexers
The 54HSC/T157 is a Quadruple 2-Line to 1-Line Data Selector
with non-inverted output. The strobe must be low to enable the
device. When select is low, A is selected. When select is high,
B is selected.
Inputs
STR
Select
SEL
1
16 VDD
1A
2
15 STR
1B
3
14 4A
1Y
4
2A
5
2B
6
11 3A
2Y
7
10 3B
VSS
8
9 3Y
Outputs
A
B
Y
H
X
X
X
L
L
L
L
X
L
L
L
H
X
H
L
H
X
L
L
L
H
X
H
H
13 4B
Top
View
12 4Y
Figure 2: Pin Out
H = high level, L = low level, X = irrelevant
Figure 1: Function Table
+25°C
Symbol
Parameter
tPLH
tPHL
-55°C / +125°C
Typ.
Max.
Typ.
Max.
Units
Propagation delay A or B to Y
14
25
17
25
ns
Propagation delay A or B to Y
15
20
18
22
ns
tPZH
Propagation delay Strobe to Y
14
22
17
24
ns
tPZL
Propagation delay Strobe to Y
15
22
18
24
ns
tPHZ
Propagation delay Select to Y
14
25
17
25
ns
tPLZ
Propagation delay Select to Y
15
25
18
25
ns
Figure 3: Switching Characteristics
Limits
+25°C
Symbol
Parameter
IDD
Quiescent Current
-55°C / +125°C
Test Conditions
Min.
Max.
Min.
Max.
Units
VIN = 0V or VDD
-
20
-
600
µA
VOL
Output Voltage Low Level
IOL = 9mA
-
0.4
-
0.4
V
VOH
Output Voltage High Level
IOH = -11mA
2.5
-
2.5
-
V
VIL1
Voltage Input Low (CMOS)
-
-
1.5
-
1.5
V
VIH1
Voltage Input High (CMOS)
-
3.5
-
3.5
-
V
VIL2
Voltage Input Low (TTL)
-
-
0.8
-
0.8
V
VIH2
Voltage Input High (TTL)
-
2.0
-
2.0
-
V
IIN
Input Leakage Current
VIN = VDD or VSS
-
±0.5
-
±5.0
µA
Figure 4: DC Characteristics
52/101
www.dynexsemi.com
54HSC/T Series
54HSC/T157 : Quad 2-Line to 1-Line Data Selectors/Multiplexers
Figure 5: Logic Diagram
53/101
www.dynexsemi.com
54HSC/T Series
54HSC/T238 : 3-Line to 8-Line Decoder/Demultiplexer
The 54HSC/T238 is a 3-Line to 8-Line Decoder/Demultiplexer, with unlatched inputs and non-inverted outputs.
Enable Inputs
Select Inputs
Outputs
E3
E2/E1
A2
A1
A0
O0
O1
O2
O3
O4
O5
O6
O7
X
H
X
X
X
L
L
L
L
L
L
L
L
L
X
X
X
X
L
L
L
L
L
L
L
L
H
L
L
L
L
H
L
L
L
L
L
L
L
H
L
L
L
H
L
H
L
L
L
L
L
L
H
L
L
H
L
L
L
H
L
L
L
L
L
H
L
L
H
H
L
L
L
H
L
L
L
L
H
L
H
L
L
L
L
L
L
H
L
L
L
H
L
H
L
H
L
L
L
L
L
H
L
L
H
L
H
H
L
L
L
L
L
L
L
H
L
H
L
H
H
H
L
L
L
L
L
L
L
H
H = high level, L = low level, X = irrelevant
Figure 1: Function Table
A0
1
16 VDD
A1
2
15 O0
A2
3
14 O1
E1
4
E2
5
Top
View
13 O2
12 O3
E3
6
11 O4
O7
7
10 O5
VSS
8
9 O6
Figure 2: Pin Out
+25°C
Symbol
Parameter
tPLH
-55°C / +125°C
Typ.
Max.
Typ.
Max.
Units
Propagation delay, address to output, low to high level output
16
24
19
27
ns
tPHL
Propagation delay, address to output, high to low level output
17
25
20
28
ns
tPLH
Propagation delay, enable to output, low to high level output
19
27
22
30
ns
tPHL
Propagation delay, enable to output, high to low level output
19
27
22
30
ns
Figure 3: Switching Characteristics
54/101
www.dynexsemi.com
54HSC/T Series
54HSC/T238 : 3-Line to 8-Line Decoder/Demultiplexer
Limits
+25°C
Symbol
Parameter
IDD
Quiescent Current
VOL
-55°C / +125°C
Test Conditions
Min.
Max.
Min.
Max.
Units
VIN = 0V or VDD
-
20
-
600
µA
Output Voltage Low Level
IOL = 9mA
-
0.4
-
0.4
V
VOH
Output Voltage High Level
IOH = -11mA
2.5
-
2.5
-
V
VIL1
Voltage Input Low (CMOS)
-
-
1.5
-
1.5
V
VIH1
Voltage Input High (CMOS)
-
3.5
-
3.5
-
V
VIL2
Voltage Input Low (TTL)
-
-
0.8
-
0.8
V
VIH2
Voltage Input High (TTL)
-
2.0
-
2.0
-
V
IIN
Input Leakage Current
VIN = VDD or VSS
-
±0.5
-
±5.0
µA
Figure 4: DC Characteristics
Figure 5: Logic Diagram
55/101
www.dynexsemi.com
54HSC/T Series
54HSC/T253 : Dual 4 to 1 Data Selectors/Multiplexers
The 54HSC/T253 is a Dual 4-Line to 1-Line Data Selector/Multiplexer with tri-state outputs.
Select Inputs
Data Inputs
Output
Control
Output
1G
1
16 VDD
B
A
C0
C1
C2
C3
G
Y
B
2
15 2G
X
X
X
X
X
X
H
Z
1C3
3
14 A
L
1C2
4
13 2C3
1C1
5
1C0
6
11 2C1
1Y
7
10 2C0
VSS
8
9 2Y
L
L
L
X
X
X
L
L
L
H
X
X
X
L
H
L
H
X
L
X
X
L
L
L
H
X
H
X
X
L
H
H
L
X
X
L
X
L
L
H
L
X
X
H
X
L
H
H
H
X
X
X
L
L
L
H
H
X
X
X
H
L
H
Top
View
12 2C2
Figure 2: Pin Out
H = high level, L = low level, X = irrelevant, Z = high impedance
Figure 1: Function Table
+25°C
Symbol
Parameter
tPLH
-55°C / +125°C
Typ.
Max.
Typ.
Max.
Units
Propagation delay Data to Output
14
25
17
25
ns
tPHL
Propagation delay Data to Output
15
25
18
25
ns
tPLH
Propagation delay Select to Output
14
25
17
25
ns
tPHL
Propagation delay Select to Output
15
25
18
25
ns
tPZL
Propagation delay Tri-state to Output Low
12
25
15
25
ns
tPZH
Propagation delay Tri-state to Output High
13
25
16
25
ns
tPLZ
Propagation delay Low to Tri-state
12
25
15
25
ns
tPHZ
Propagation delay High to Tri-state
13
25
16
25
ns
Figure 3: Switching Characteristics
56/101
www.dynexsemi.com
54HSC/T Series
54HSC/T253 : Dual 4 to 1 Data Selectors/Multiplexers
Limits
+25°C
Symbol
Parameter
Test Conditions
Min.
-55°C / +125°C
Max.
Min.
Max.
Units
IDD
Quiescent Current
VIN = 0V or VDD
-
20
-
600
µA
VOL
Output Voltage Low Level
IOL = 9mA
-
0.4
-
0.4
V
VOH
Output Voltage High Level
IOH = -11mA
2.5
-
2.5
-
V
VIL1
Voltage Input Low (CMOS)
-
-
1.5
-
1.5
V
VIH1
Voltage Input High (CMOS)
-
3.5
-
3.5
-
V
VIL2
Voltage Input Low (TTL)
-
-
0.8
-
0.8
V
VIH2
Voltage Input High (TTL)
-
2.0
-
2.0
-
V
IOZ
Tri-State Leakage
VO = 0V or VDD
-
±1
-
±50
µA
IIN
Input Leakage Current
VIN = VDD or VSS
-
±0.5
-
±5.0
µA
Figure 4: DC Characteristics
Figure 5: Logic Diagram
57/101
www.dynexsemi.com
54HSC/T Series
54HSC/T164 : 8-Bit Parallel Output Serial Shift Register
The 54HSC/T164 is an 8-Bit Parallel Output Serial Shift Register with asynchronous clear.
Inputs
CLEAR CLOCK
Outputs
A
B
QA
QB
QH
A
1
14 VDD
B
2
13 QH
L
X
X
X
L
L
L
QA
3
H
L
X
X
QAO
QBO
QHO
QB
4
H
↑
H
H
H
QAN
QGN
QC
5
H
↑
L
X
L
QAN
QGN
QD
6
9 CLEAR
H
↑
X
L
L
QAN
QGN
VSS
7
8 CLOCK
H = high level, L = low level, X = irrelevant, ↑ = transition from low to high
level. QAO, QBO, QHO = the level of QA, QB or QH, respectively, before the
indicated steady-state input conditions were set up. QAN, QBN, QHN = the
level of QA or QG before the latest ↑ transition of the clock. Indicates a
one bit shift.
12 QG
Top
View
11 QF
10 QE
Figure 2: Pin Out
Figure 1: Function Table
+25°C
Symbol
Parameter
tPLH
-55°C / +125°C
Typ.
Max.
Typ.
Max.
Units
Propagation delay. Q output from clock input, low to high level output.
15
25
18
28
ns
tPHL
Propagation delay. Q output from clock input, high to low level output.
15
25
18
28
ns
tPHL
Propagation delay. Q output from clear input, high to low level output.
15
25
18
28
ns
Figure 3: Switching Characteristics
Limits
+25°C
Symbol
Parameter
IDD
Quiescent Current
-55°C / +125°C
Test Conditions
Min.
Max.
Min.
Max.
Units
VIN = 0V or VDD
-
20
-
400
µA
VOL
Output Voltage Low Level
IOL = 9mA
-
0.4
-
0.4
V
VOH
Output Voltage High Level
IOH = -11mA
2.5
-
2.5
-
V
VIL1
Voltage Input Low (CMOS)
-
-
1.5
-
1.5
V
VIH1
Voltage Input High (CMOS)
-
3.5
-
3.5
-
V
VIL2
Voltage Input Low (TTL)
-
-
0.8
-
0.8
V
VIH2
Voltage Input High (TTL)
-
2.0
-
2.0
-
V
IIN
Input Leakage Current
VIN = VDD or VSS
-
±0.5
-
±5.0
µA
Figure 4: DC Characteristics
58/101
www.dynexsemi.com
54HSC/T Series
54HSC/T164 : 8-Bit Parallel Output Serial Shift Register
Figure 5: Logic Diagram
59/101
www.dynexsemi.com
54HSC/T Series
54HSC/T165 : Parallel Load 8-Bit Shift Register
The 54HSC/T165 is an 8-Bit Serial Shift Register that shifts the data in the direction of QA to QH when clocked.
Inputs
Internal Outputs
Output
Shift/
Load
Clock
Inhibit
Clock
Serial
Parallel
A...H
QA
QB
QH
L
X
X
X
a...h
a
b
h
H
L
L
X
X
QAO
QBO
QHO
H
L
↑
H
X
H
QAN
QGN
H
L
↑
L
X
L
QAN
QGN
H
H
X
X
X
QAO
QBO
QHO
H = high level, L = low level, X = irrelevant, ↑ = transition from low to high, a...h = the level of steady state inputs
at inputs A through H. QO = level of Q before the indicated steady state input conditions were set up. QN = level
of Q before the most recent active transition indicated by ↑.
Figure 1: Function Table
SHIFT/LOAD
1
16 VDD
CLOCK
2
15 CLOCK INHIBIT
E
3
14 D
F
4
G
5
H
6
11 A
QH
7
10 SERIAL INPUT
VSS
8
9 QH
Top
View
13 C
12 B
Figure 2: Pin Out
+25°C
-55°C / +125°C
Symbol
Parameter
Typ.
Max.
Typ.
Max.
Units
tPLH
Propagation delay. Load to Any Output.
18
25
21
28
ns
tPHL
Propagation delay. Load to Any Output.
16
25
19
28
ns
tPLH
Propagation delay. Clock to Any Output.
18
25
21
28
ns
tPHL
Propagation delay. Clock to Any Output.
18
25
21
28
ns
tPLH
Propagation delay. H to QH.
18
25
21
28
ns
tPHL
Propagation delay. H to QH.
18
25
21
28
ns
tPLH
Propagation delay. H to QBH.
18
25
21
28
ns
tPHL
Propagation delay. H to QBH.
18
25
21
28
ns
Figure 3: Switching Characteristics
60/101
www.dynexsemi.com
54HSC/T Series
54HSC/T165 : Parallel Load 8-Bit Shift Register
Limits
+25°C
Symbol
Parameter
IDD
Quiescent Current
VOL
-55°C / +125°C
Test Conditions
Min.
Max.
Min.
Max.
Units
VIN = 0V or VDD
-
20
-
400
µA
Output Voltage Low Level
IOL = 9mA
-
0.4
-
0.4
V
VOH
Output Voltage High Level
IOH = -11mA
2.5
-
2.5
-
V
VIL1
Voltage Input Low (CMOS)
-
-
1.5
-
1.5
V
VIH1
Voltage Input High (CMOS)
-
3.5
-
3.5
-
V
VIL2
Voltage Input Low (TTL)
-
-
0.8
-
0.8
V
VIH2
Voltage Input High (TTL)
-
2.0
-
2.0
-
V
IIN
Input Leakage Current
VIN = VDD or VSS
-
±0.5
-
±5.0
µA
Figure 4: DC Characteristics
Figure 5: Logic Diagram
61/101
www.dynexsemi.com
54HSC/T Series
54HSC/T166 : 8-Bit Shift Register
The 54HSC/T166 is an 8-Bit parallel in or serial in, serial out Shift Register with a gated clock input and an overriding clear input.
Inputs
Internal Outputs
Output
Clear
Shift/
Load
Clock
Inhibit
Clock
Serial
Parallel
A...H
QA
QB
QH
L
H
H
H
H
H
X
X
L
H
H
X
X
L
L
L
L
H
X
L
↑
↑
↑
↑
X
X
X
H
L
X
X
X
a...h
X
X
X
L
QAO
a
H
L
QAO
L
QBO
b
QAN
QAN
QBO
L
QHO
h
QGN
QGN
QHO
H = high level, L = low level, X = irrelevant, ↑ = transition from low to high, a...h = the level of steady state inputs at inputs
A through H. QO = level of Q before the indicated steady state input conditions were set up. QN = level of Q before the most
recent active transition indicated by ↑.
Figure 1: Function Table
SERIAL INPUT
1
16 VDD
A
2
15 SHIFT/LOAD
14 H
B
3
C
4
Top
View
13 QH
D
5
CLOCK INHIBIT
6
11 F
CLOCK
7
10 E
VSS
8
9 CLEAR
12 G
Figure 2: Pin Out
+25°C
Symbol
Parameter
tPHL
-55°C / +125°C
Typ.
Max.
Typ.
Max.
Units
Propagation delay. Clear to QH.
15
25
18
28
ns
tPHL
Propagation delay. Clock to QH.
15
25
18
28
ns
tPLH
Propagation delay. Clock to QH.
15
25
18
28
ns
Figure 3: Switching Characteristics
62/101
www.dynexsemi.com
54HSC/T Series
54HSC/T166 : 8-Bit Shift Register
Limits
+25°C
Symbol
Parameter
IDD
Quiescent Current
VOL
-55°C / +125°C
Test Conditions
Min.
Max.
Min.
Max.
Units
VIN = 0V or VDD
-
20
-
400
µA
Output Voltage Low Level
IOL = 9mA
-
0.4
-
0.4
V
VOH
Output Voltage High Level
IOH = -11mA
2.5
-
2.5
-
V
VIL1
Voltage Input Low (CMOS)
-
-
1.5
-
1.5
V
VIH1
Voltage Input High (CMOS)
-
3.5
-
3.5
-
V
VIL2
Voltage Input Low (TTL)
-
-
0.8
-
0.8
V
VIH2
Voltage Input High (TTL)
-
2.0
-
2.0
-
V
IIN
Input Leakage Current
VIN = VDD or VSS
-
±0.5
-
±5.0
µA
Figure 4: DC Characteristics
63/101
www.dynexsemi.com
54HSC/T Series
54HSC/T166 : 8-Bit Shift Register
Figure 5: Logic Diagram
64/101
www.dynexsemi.com
54HSC/T Series
54HSC/T521 : 8-Bit Magnitude Comparator
The 54HSC/T521 is an 8-Bit Magnitude Comparator.
Inputs
Outputs
Data P,Q Enable G
P=Q
P=Q
L
L
P>Q
L
H
P<Q
L
H
X
H
H
H = high level, L = low level, X = irrelevant
Figure 1: Function Table
G
1
20 VDD
P0
2
19 P = Q
Q0
3
18 Q7
P1
4
17 P7
Q1
5
Top
View
16 Q6
15 P6
P2
6
Q2
7
14 Q5
P3
8
13 P5
Q3
9
12 Q4
VSS 10
11 P4
Figure 2: Pin Out
Figure 3: Logic Diagram
+25°C
Symbol
Parameter
-55°C / +125°C
Typ.
Max.
Typ.
Max.
Units
tPLH
Propagation delay. P or Q to PN = QN.
15
25
18
28
ns
tPHL
Propagation delay. P or Q to PN = QN.
16
25
19
28
ns
tPLH
Propagation delay. GN to PN = QN.
14
25
17
28
ns
tPHL
Propagation delay. GN to PN = QN.
15
25
18
28
ns
Figure 4: Switching Characteristics
65/101
www.dynexsemi.com
54HSC/T Series
54HSC/T521 : 8-Bit Magnitude Comparator
Limits
+25°C
Symbol
Parameter
Test Conditions
Min.
IDD
Quiescent Current
VIN = 0V or VDD
-
VOL
Output Voltage Low Level
IOL = 9mA
-
VOH
Output Voltage High Level
IOH = -11mA
2.5
VIL1
Voltage Input Low (CMOS)
-
VIH1
Voltage Input High (CMOS)
-
VIL2
Voltage Input Low (TTL)
VIH2
Voltage Input High (TTL)
IIN
Input Leakage Current
VIN = VDD or VSS
-55°C / +125°C
Max.
Min.
Max.
Units
20
-
600
µA
0.4
-
0.4
V
-
2.5
-
V
-
1.5
-
1.5
V
3.5
-
3.5
-
V
-
-
0.8
-
0.8
V
-
2.0
-
2.0
-
V
-
±0.5
-
±5.0
µA
Figure 5: DC Characteristics
66/101
www.dynexsemi.com
54HSC/T Series
54HSC/T240 : Octal 3-State Driver, Inverting
The 54HSC/T240 is an Octal 3-State Driver, inverting.
Inputs
Outputs
E
I0-3
O0-3
L
L
H
L
H
L
H
X
Z
H = high level
L = low level
X = irrelevant
Z = high impedance
Figure 1: Function Table
EA
1
20 VDD
I0A
2
19 EB
O0B
3
18 O0A
I1A
4
17 I0B
O1B
5
12A
6
O2B
7
14 O2A
I3A
8
13 I2B
O3B
9
12 O3A
Top
View
VSS 10
16 O1A
15 I1B
11 I3B
Figure 2: Pin Out
Figure 3: Logic Diagram
+25°C
Symbol
Parameter
tPLH
-55°C / +125°C
Typ.
Max.
Typ.
Max.
Units
Propagation delay, low to high level output.
12
20
15
23
ns
tPHL
Propagation delay, high to low level output.
14
22
17
25
ns
tPZL
Propagation delay, enable to low level.
19
27
21
30
ns
tPZH
Propagation delay, enable to high level.
14
22
17
25
ns
tPLZ
Propagation delay, disable from low.
22
30
25
33
ns
tPHZ
Propagation delay, disable from high.
21
30
24
33
ns
Figure 4: Switching Characteristics
67/101
www.dynexsemi.com
54HSC/T Series
54HSC/T240 : Octal 3-State Driver, Inverting
Limits
+25°C
Symbol
Parameter
IDD
Quiescent Current
VOL
-55°C / +125°C
Test Conditions
Min.
Max.
Min.
Max.
Units
VIN = 0V or VDD
-
20
-
600
µA
Output Voltage Low Level
IOL = 9mA
-
0.4
-
0.4
V
VOH
Output Voltage High Level
IOH = -11mA
2.5
-
2.5
-
V
VIL1
Voltage Input Low (CMOS)
-
-
1.5
-
1.5
V
VIH1
Voltage Input High (CMOS)
-
3.5
-
3.5
-
V
VIL2
Voltage Input Low (TTL)
-
-
0.8
-
0.8
V
VIH2
Voltage Input High (TTL)
-
2.0
-
2.0
-
V
IOZ
Tri-State Leakage
VO = 0V or VDD
-
±1
-
±50
µA
IIN
Input Leakage Current
VIN = VDD or VSS
-
±0.5
-
±5.0
µA
Figure 5: DC Characteristics
68/101
www.dynexsemi.com
54HSC/T Series
54HSC/T241 : Octal 3-State Driver, Complementary Enable
The 54HSC/T241 is an Octal 3-State Driver, complementary
enable.
Inputs
Outputs
EA
EB
I0-3
O0-3
L
H
L
H
L
H
H
L
H
L
X
Z
H = high level
L = low level
X = irrelevant
Z = high impedance
Figure 1: Function Table
EA
1
20 VDD
I0A
2
19 EB
O0B
3
18 O0A
I1A
4
17 I0B
O1B
5
12A
6
O2B
7
14 O2A
I3A
8
13 I2B
O3B
9
12 O3A
Top
View
VSS 10
16 O1A
15 I1B
11 I3B
Figure 2: Pin Out
Figure 3: Logic Diagram
+25°C
Symbol
Parameter
tPLH
-55°C / +125°C
Typ.
Max.
Typ.
Max.
Units
Propagation delay, low to high level output.
11
19
14
22
ns
tPHL
Propagation delay, high to low level output.
13
21
16
24
ns
tPZL
Propagation delay, enable to low level.
19
27
21
30
ns
tPZH
Propagation delay, enable to high level.
19
27
21
30
ns
tPLZ
Propagation delay, low to disable.
22
30
25
33
ns
tPHZ
Propagation delay, high to disable.
21
30
24
33
ns
Figure 4: Switching Characteristics
69/101
www.dynexsemi.com
54HSC/T Series
54HSC/T241 : Octal 3-State Driver, Complementary Enable
Limits
+25°C
Symbol
Parameter
IDD
Quiescent Current
VOL
-55°C / +125°C
Test Conditions
Min.
Max.
Min.
Max.
Units
VIN = 0V or VDD
-
20
-
600
µA
Output Voltage Low Level
IOL = 9mA
-
0.4
-
0.4
V
VOH
Output Voltage High Level
IOH = -11mA
2.5
-
2.5
-
V
VIL1
Voltage Input Low (CMOS)
-
-
1.5
-
1.5
V
VIH1
Voltage Input High (CMOS)
-
3.5
-
3.5
-
V
VIL2
Voltage Input Low (TTL)
-
-
0.8
-
0.8
V
VIH2
Voltage Input High (TTL)
-
2.0
-
2.0
-
V
IIN
Input Leakage Current
VIN = VDD or VSS
-
±0.5
-
±5.0
µA
Figure 5: DC Characteristics
70/101
www.dynexsemi.com
54HSC/T Series
54HSC/T244 : Octal 3-State Driver
The 54HSC/T244 is an Octal 3-State Driver.
Inputs
Outputs
E
I0-3
O0-3
L
L
H
L
H
L
H
X
Z
H = high level
L = low level
X = irrelevant
Z = high impedance
Figure 1: Function Table
EA
1
20 VDD
I0A
2
19 EB
O0B
3
18 O0A
I1A
4
O1B
5
17 I0B
Top
View
16 O1A
12A
6
O2B
7
14 O2A
I3A
8
13 I2B
O3B
9
12 O3A
VSS 10
15 I1B
11 I3B
Figure 2: Pin Out
Figure 3: Logic Diagram
+25°C
Symbol
Parameter
tPLH
-55°C / +125°C
Typ.
Max.
Typ.
Max.
Units
Propagation delay, low to high level output.
11
21
14
21
ns
tPHL
Propagation delay, high to low level output.
13
21
16
21
ns
tPZL
Propagation delay, enable to low level.
19
25
21
25
ns
tPZH
Propagation delay, enable to high level.
15
20
21
24
ns
tPLZ
Propagation delay, low to disable.
19
25
22
25
ns
tPHZ
Propagation delay, high to disable.
18
25
21
25
ns
Figure 4: Switching Characteristics
71/101
www.dynexsemi.com
54HSC/T Series
54HSC/T244 : Octal 3-State Driver
Limits
+25°C
Symbol
Parameter
IDD
Quiescent Current
VOL
-55°C / +125°C
Test Conditions
Min.
Max.
Min.
Max.
Units
VIN = 0V or VDD
-
20
-
600
µA
Output Voltage Low Level
IOL = 9mA
-
0.4
-
0.4
V
VOH
Output Voltage High Level
IOH = -11mA
2.5
-
2.5
-
V
VIL1
Voltage Input Low (CMOS)
-
-
1.5
-
1.5
V
VIH1
Voltage Input High (CMOS)
-
3.5
-
3.5
-
V
VIL2
Voltage Input Low (TTL)
-
-
0.8
-
0.8
V
VIH2
Voltage Input High (TTL)
-
2.0
-
2.0
-
V
IOZ
Tri-State Leakage
VO = 0V or VDD
-
±1
-
±50
µA
IIN
Input Leakage Current
VIN = VDD or VSS
-
±0.5
-
±5.0
µA
Figure 5: DC Characteristics
72/101
www.dynexsemi.com
54HSC/T Series
54HSC/T540 : Octal 3-State Driver/Buffer Inverting
The 54HSC/T540 is an Octal 3-State Driver/Buffer Inverting.
Inputs
Outputs
EA
EB
I0-7
O0-7
L
L
L
H
L
L
H
L
H
X
X
Z
X
H
X
Z
H = high level
L = low level
X = irrelevant
Z = high impedance
Figure 1: Function Table
EA
1
20 VDD
I0
2
19 EB
I1
3
18 O0
I2
4
I3
5
I4
6
I5
7
14 O4
I6
8
13 O5
I7
9
12 O6
VSS 10
11 O7
17 O1
Top
View
16 O2
15 O3
Figure 3: Logic Diagram
Figure 2: Pin Out
+25°C
Symbol
Parameter
tPLH
-55°C / +125°C
Typ.
Max.
Typ.
Max.
Units
Propagation delay, low to high level output.
13
21
16
24
ns
tPHL
Propagation delay, high to low level output.
13
21
16
24
ns
tPZL
Propagation delay, enable to low level.
21
29
24
32
ns
tPZH
Propagation delay, enable to high level.
16
24
19
27
ns
tPLZ
Propagation delay, low to disable.
24
32
27
35
ns
tPHZ
Propagation delay, high to disable.
23
31
26
34
ns
Figure 4: Switching Characteristics
73/101
www.dynexsemi.com
54HSC/T Series
54HSC/T540 : Octal 3-State Driver/Buffer Inverting
Limits
+25°C
Symbol
Parameter
IDD
Quiescent Current
VOL
-55°C / +125°C
Test Conditions
Min.
Max.
Min.
Max.
Units
VIN = 0V or VDD
-
20
-
600
µA
Output Voltage Low Level
IOL = 9mA
-
0.4
-
0.4
V
VOH
Output Voltage High Level
IOH = -11mA
2.5
-
2.5
-
V
VIL1
Voltage Input Low (CMOS)
-
-
1.5
-
1.5
V
VIH1
Voltage Input High (CMOS)
-
3.5
-
3.5
-
V
VIL2
Voltage Input Low (TTL)
-
-
0.8
-
0.8
V
VIH2
Voltage Input High (TTL)
-
2.0
-
2.0
-
V
IOZ
Tri-State Leakage
VO = 0V or VDD
-
±1
-
±50
µA
IIN
Input Leakage Current
VIN = VDD or VSS
-
±0.5
-
±5.0
µA
Figure 5: DC Characteristics
74/101
www.dynexsemi.com
54HSC/T Series
54HSC/T541 : Octal 3-State Driver/Buffer
The 54HSC/T541 is an Octal 3-State Driver/Buffer.
Inputs
Outputs
EA
EB
I0-7
O0-7
L
L
L
L
L
L
H
H
H
X
X
Z
X
H
X
Z
H = high level
L = low level
X = irrelevant
Z = high impedance
Figure 1: Function Table
EA
1
20 VDD
I0
2
19 EB
I1
3
18 O0
I2
4
I3
5
I4
6
I5
7
14 O4
I6
8
13 O5
I7
9
12 O6
VSS 10
11 O7
17 O1
Top
View
16 O2
15 O3
Figure 3: Logic Diagram
Figure 2: Pin Out
+25°C
Symbol
Parameter
tPLH
-55°C / +125°C
Typ.
Max.
Typ.
Max.
Units
Propagation delay, low to high level output.
11
19
14
22
ns
tPHL
Propagation delay, high to low level output.
13
21
16
22
ns
tPZL
Propagation delay, enable to low level.
17
21
20
35
ns
tPZH
Propagation delay, enable to high level.
16
24
19
30
ns
tPLZ
Propagation delay, low to disable.
24
21
27
25
ns
tPHZ
Propagation delay, high to disable.
23
21
26
25
ns
Figure 4: Switching Characteristics
75/101
www.dynexsemi.com
54HSC/T Series
54HSC/T541 : Octal 3-State Driver/Buffer
Limits
+25°C
Symbol
Parameter
IDD
Quiescent Current
VOL
-55°C / +125°C
Test Conditions
Min.
Max.
Min.
Max.
Units
VIN = 0V or VDD
-
20
-
600
µA
Output Voltage Low Level
IOL = 9mA
-
0.4
-
0.4
V
VOH
Output Voltage High Level
IOH = -11mA
2.5
-
2.5
-
V
VIL1
Voltage Input Low (CMOS)
-
-
1.5
-
1.5
V
VIH1
Voltage Input High (CMOS)
-
3.5
-
3.5
-
V
VIL2
Voltage Input Low (TTL)
-
-
0.8
-
0.8
V
VIH2
Voltage Input High (TTL)
-
2.0
-
2.0
-
V
IOZ
Tri-State Leakage
VO = 0V or VDD
-
±1
-
±50
µA
IIN
Input Leakage Current
VIN = VDD or VSS
-
±0.5
-
±5.0
µA
Figure 5: DC Characteristics
76/101
www.dynexsemi.com
54HSC/T Series
54HSC/T245 : Octal Bus Transceiver
The 54HSC/T245 is an Octal Bus Transceiver.
Inputs
Outputs
E
DIR
L
L
B data to Bus A
L
H
A data to Bus B
H
X
Isolation
H = high level, L = low level, X = irrelevant
Figure 1: Function Table
DIR
1
20 VDD
A0
2
19 E
A1
3
18 B0
A2
4
17 B1
A3
5
A4
6
A5
7
14 B4
A6
8
13 B5
A7
9
12 B6
VSS 10
11 B7
Top
View
16 B2
15 B3
Figure 2: Pin Out
Figure 3: Logic Diagram
+25°C
Symbol
Parameter
tPLH
-55°C / +125°C
Typ.
Max.
Typ.
Max.
Units
Propagation delay, low to high level output.
10
19
13
23
ns
tPHL
Propagation delay, high to low level output.
11
19
14
23
ns
tPZL
Propagation delay, enable to low level.
21
26
24
30
ns
tPZH
Propagation delay, enable to high level.
16
25
19
28
ns
tPLZ
Propagation delay, low to disable.
24
28
27
33
ns
tPHZ
Propagation delay, high to disable.
24
28
27
33
ns
Figure 4: Switching Characteristics
77/101
www.dynexsemi.com
54HSC/T Series
54HSC/T245 : Octal Bus Transceiver
Limits
+25°C
Symbol
Parameter
IDD
Quiescent Current
VOL
-55°C / +125°C
Test Conditions
Min.
Max.
Min.
Max.
Units
VIN = 0V or VDD
-
20
-
600
µA
Output Voltage Low Level
IOL = 9mA
-
0.4
-
0.4
V
VOH
Output Voltage High Level
IOH = -11mA
2.5
-
2.5
-
V
VIL1
Voltage Input Low (CMOS)
-
-
1.5
-
1.5
V
VIH1
Voltage Input High (CMOS)
-
3.5
-
3.5
-
V
VIL2
Voltage Input Low (TTL)
-
-
0.8
-
0.8
V
VIH2
Voltage Input High (TTL)
-
2.0
-
2.0
-
V
IOZ
Tri-State Leakage
VO = 0V or VDD
-
±1
-
±50
µA
IIN
Input Leakage Current
VIN = VDD or VSS
-
±0.5
-
±5.0
µA
Figure 5: DC Characteristics
78/101
www.dynexsemi.com
54HSC/T Series
54HSC/T373 : Octal Transparent Latch, 3-State Outputs
The 54HSC/T373 is an Octal Transparent Latch with 3-State
Outputs.
Inputs
OC
C
OC
1
20 VDD
1Q
2
19 8Q
1D
3
18 8D
Q
2D
4
2Q
5
3Q
6
3D
7
14 6D
4D
8
13 5D
4Q
9
12 5Q
Outputs
D
L
H
H
H
L
H
L
L
L
L
X
Q0
H
X
X
Z
H = high level
L = low level
X = irrelevant
Z = high impedance
17 7D
16 7Q
Top
View
15 6Q
VSS 10
Figure 1: Function Table
11 C
Figure 2: Pin Out
+25°C
Symbol
Parameter
tPLH
-55°C / +125°C
Min.
Typ.
Max.
Min.
Typ.
Max.
Units
Propagation delay. Low to high output.
-
15
20
-
20
24
ns
tPHL
Propagation delay. High to low output.
-
14
20
-
21
24
ns
tPZL
Propagation delay. Enable to low.
-
13
25
-
14
25
ns
tPZH
Propagation delay. Enable to high.
-
16
20
-
18
24
ns
tPLZ
Propagation delay. Low to disable.
-
14
25
-
18
25
ns
tPHZ
Propagation delay. High to disable.
-
13
25
-
19
25
ns
Figure 3: Switching Characteristics
Limits
+25°C
Symbol
Parameter
Test Conditions
Min.
-55°C / +125°C
Max.
Min.
Max.
Units
IDD
Quiescent Current
VIN = 0V or VDD
-
20
-
600
µA
VOL
Output Voltage Low Level
IOL = 9mA
-
0.4
-
0.4
V
VOH
Output Voltage High Level
IOH = -11mA
2.5
-
2.5
-
V
VIL1
Voltage Input Low (CMOS)
-
-
1.5
-
1.5
V
VIH1
Voltage Input High (CMOS)
-
3.5
-
3.5
-
V
VIL2
Voltage Input Low (TTL)
-
-
0.8
-
0.8
V
VIH2
Voltage Input High (TTL)
-
2.0
-
2.0
-
V
IOZ
Tri-State Leakage
VO = 0V or VDD
-
±1
-
±50
µA
IIN
Input Leakage Current
VIN = VDD or VSS
-
±0.5
-
±5.0
µA
Figure 4: DC Characteristics
79/101
www.dynexsemi.com
54HSC/T Series
54HSC/T373 : Octal Transparent Latch, 3-State Outputs
Figure 5: Logic Diagram
80/101
www.dynexsemi.com
54HSC/T Series
54HSC/T573 : Octal Transparent Latch, 3-State Outputs
The 54HSC/T573 is an Octal Transparent Latch with 3-State
Outputs.
Inputs
OC
C
1
1D
2
19 1Q
2D
3
18 2Q
Q
3D
4
17 3Q
4D
5
5D
6
6D
7
14 6Q
7D
8
13 7Q
8D
9
12 8Q
Outputs
D
20 GND
OC
L
H
H
H
L
H
L
L
L
L
X
Q0
H
X
X
Z
H = high level
L = low level
X = irrelevant
Z = high impedance
16 4Q
Top
View
15 5Q
VSS 10
Figure 1: Function Table
11 C
Figure 2: Pin Out
+25°C
Symbol
Parameter
tPLH
-55°C / +125°C
Min.
Typ.
Max.
Min.
Typ.
Max.
Units
Propagation delay. Low to high output.
-
19
24
-
22
29
ns
tPHL
Propagation delay. High to low output.
-
19
24
-
22
29
ns
tPZL
Propagation delay. Enable to low.
-
13
21
-
16
24
ns
tPZH
Propagation delay. Enable to high.
-
16
24
-
19
27
ns
tPLZ
Propagation delay. Low to disable.
-
14
22
-
17
25
ns
tPHZ
Propagation delay. High to disable.
-
13
21
-
16
24
ns
Figure 3: Switching Characteristics
Limits
+25°C
Symbol
Parameter
Test Conditions
Min.
-55°C / +125°C
Max.
Min.
Max.
Units
IDD
Quiescent Current
VIN = 0V or VDD
-
20
-
600
µA
VOL
Output Voltage Low Level
IOL = 9mA
-
0.4
-
0.4
V
VOH
Output Voltage High Level
IOH = -11mA
2.5
-
2.5
-
V
VIL1
Voltage Input Low (CMOS)
-
-
1.5
-
1.5
V
VIH1
Voltage Input High (CMOS)
-
3.5
-
3.5
-
V
VIL2
Voltage Input Low (TTL)
-
-
0.8
-
0.8
V
VIH2
Voltage Input High (TTL)
-
2.0
-
2.0
-
V
IOZ
Tri-State Leakage
VO = 0V or VDD
-
±1
-
±50
µA
IIN
Input Leakage Current
VIN = VDD or VSS
-
±0.5
-
±5.0
µA
Figure 4: DC Characteristics
81/101
www.dynexsemi.com
54HSC/T Series
54HSC/T573 : Octal Transparent Latch, 3-State Outputs
Figure 5: Logic Diagram
82/101
www.dynexsemi.com
54HSC/T Series
54HSC/T670 : 4 x 4 Register Files with Tri-State Outputs
The 54HSC/T670 is a register storing 4 words of 4 bits each.
Separate on-chip decoding is provided for addressing the four
word locations to either write or retrieve data. This allows
simultaneous writing into one location and reading from
another location.
D2
1
16 VDD
D3
2
15 D1
D4
3
14 WA
RB
4
RA
5
Q4
6
11 GR
Q3
7
10 Q1
VSS
8
9 Q2
Top
View
13 WB
12 GW
Figure 1: Pin Out
Write Inputs
Word
Read Inputs
Outputs
WB
WA
GW
1
2
3
4
WB
WA
GW
1
2
3
4
L
L
L
Q=D
Q0
Q0
Q0
L
L
L
W1D1
W1D2
W1D3
W1D4
L
H
L
Q0
Q=D
Q0
Q0
L
H
L
W2D1
W2D2
W2D3
W2D4
H
L
L
Q0
Q0
Q=D
Q0
H
L
L
W3D1
W3D2
W3D3
W3D4
H
H
L
Q0
Q0
Q0
Q=D
H
H
L
W4D1
W4D2
W4D3
W4D4
X
X
H
Q0
Q0
Q0
Q0
X
X
H
Z
Z
Z
Z
Q0 = level of Q before inputs were established
H = high level, L = low level, X = irrelevant
H = high level, L = low level, X = irrelevant, Z = high impedance
Figure 3: Read Function Table
Figure 2: Write Function Table
+25°C
Symbol
Parameter
tPLH
-55°C / +125°C
Typ.
Max.
Typ.
Max.
Units
Propagation delay. Read select to Q.
25
30
28
33
ns
tPHL
Propagation delay. Read select to Q.
18
25
21
28
ns
tPLH
Propagation delay. Write enable to Q.
18
25
21
28
ns
tPHL
Propagation delay. Write enable to Q.
18
25
21
28
ns
tPLH
Propagation delay. Data to Q.
27
35
30
38
ns
tPHL
Propagation delay. Data to Q.
23
25
26
28
ns
tPZH
Propagation delay. Read Enable to Q.
18
25
21
28
ns
tPZL
Propagation delay. Read Enable to Q.
18
25
21
28
ns
tPHZ
Propagation delay. Read Enable to Q.
18
25
21
28
ns
tPLZ
Propagation delay. Read Enable to Q.
18
25
21
28
ns
VCC = 5V, TMAX = +125°C, CL = 50pF
Figure 4: Switching Characteristics
83/101
www.dynexsemi.com
54HSC/T Series
54HSC/T670 : 4 x 4 Register Files with Tri-State Outputs
Limits
+25°C
Symbol
Parameter
IDD
Quiescent Current
VOL
-55°C / +125°C
Test Conditions
Min.
Max.
Min.
Max.
Units
VIN = 0V or VDD
-
20
-
600
µA
Output Voltage Low Level
IOL = 9mA
-
0.4
-
0.4
V
VOH
Output Voltage High Level
IOH = -11mA
2.5
-
2.5
-
V
VIL1
Voltage Input Low (CMOS)
-
-
1.5
-
1.5
V
VIH1
Voltage Input High (CMOS)
-
3.5
-
3.5
-
V
VIL2
Voltage Input Low (TTL)
-
-
0.8
-
0.8
V
VIH2
Voltage Input High (TTL)
-
2.0
-
2.0
-
V
IOZ
Tri-State Leakage
VO = 0V or VDD
-
±1
-
±50
µA
IIN
Input Leakage Current
VIN = VDD or VSS
-
±0.5
-
±5.0
µA
Figure 5: DC Characteristics
84/101
www.dynexsemi.com
54HSC/T Series
54HSC/T670 : 4 x 4 Register Files with Tri-State Outputs
Figure 6: Logic Diagram
85/101
www.dynexsemi.com
54HSC/T Series
CHARACTERISATION DATA
Device base listing as below:
MA9003 Base
Pin Count
MA9007 Base
Pin Count
BMS011 Base
Pin Count
00
02
03
04
08
10
14
21
27
32
74
86
109
125
126
148
151
157
164
253
14
14
14
14
14
14
14
14
14
14
14
14
16
14
14
16
16
16
14
16
154
161
163
165
166
191
273
283
670
24
16
16
16
16
16
20
16
16
138
139
238
240
241
244
245
373
374
521
540
541
573
574
16
16
16
20
20
20
20
20
20
20
20
20
20
20
86/101
www.dynexsemi.com
54HSC/T Series
PACKAGE: LI/AS/4/IN/02001 - 14 Lead Bottombraze Flatpack (MIL-STD-38510H)
87/101
www.dynexsemi.com
54HSC/T Series
FINISHED PRODUCT OUTLINE: LI/AS/4/IN/02001 - 14 Lead Bottombraze Flatpack (MIL-STD-38510H)
88/101
www.dynexsemi.com
54HSC/T Series
FINISHED PRODUCT OUTLINE: LI/AS/4/IN/02001 - 14 Lead Bottombraze Flatpack (MIL-STD-38510H)
89/101
www.dynexsemi.com
54HSC/T Series
FINISHED PRODUCT OUTLINE: LI/AS/4/IN/02001 - 14 Lead Bottombraze Flatpack (MIL-STD-38510H)
90/101
www.dynexsemi.com
54HSC/T Series
PACKAGE OUTLINE: XG 257 - 20 Lead Bottombraze Flatpack (MIL-STD-38510H)
91/101
www.dynexsemi.com
54HSC/T Series
PACKAGE OUTLINE: 16 Lead Bottombraze Flatpack (MIL-STD-38510H)
92/101
www.dynexsemi.com
54HSC/T Series
FINISHED PRODUCT OUTLINE: 24 Lead Ceramic Flatpack (MIL-M-38510)
93/101
www.dynexsemi.com
54HSC/T Series
FINISHED PRODUCT OUTLINE: 16 Lead Flatpack (MIL-M-38510H)
94/101
www.dynexsemi.com
54HSC/T Series
STATIC Idd Vs RADIATION
DYNAMIC Idd for OCTAL DEVICE BASES
450
BMS011
Base
15
BMS011
Base
400
STATIC Idd (µA)
DYNAMIC Idd (mA)
350
10
9007
Base
9003
Base
5
9007
Base
300
250
200
9003
Base
150
100
50
0
0
1
0
100
10
FREQUENCY (MHz)
100
200
RAD LEVELS (Krads)
IOZL Vs TEMP.
STATIC Idd Vs TEMP.
250
30
150
9003
Base
100
IOZL (-µA)
BMS011
Base
9007
Base
200
Idd (µA)
300
25
BMS011
Base
20
9007
Base
15
9003
Base
10
50
5
0
0
-100
-50
0
50
100
150
0
20
TEMPERATURE (deg C)
60
80
100
120
140
TEMPERATURE (deg C)
IIL Vs TEMP.
IOZH Vs TEMP.
300
BMS011
Base
250
9007
Base
200
9003
Base
150
100
350
9003
Base
300
250
IIL (-nA)
IOZH (nA)
40
200
150
9007
Base
BMS011
Base
100
50
50
0
0
0
20
40
60
80
100
TEMPERATURE (deg C)
120
140
0
20
40
60
80
100
TEMPERATURE (deg C)
120
140
95/101
www.dynexsemi.com
54HSC/T Series
IIH Vs TEMP.
VOL Vs TEMP.
500
0.22
0.2
9003
Base
400
9007
Base
BMS011
Base
VOL (V)
IIH (nA)
0.18
300
200
9007
Base
100
0
0.16
0.14
0.12
BMS011
Base
0
20
40
60
80
100
120
9003
Base
0.1
0.08
-60
140
-40
-20
0
20
40
60
80 100 120 140
TEMPERATURE (deg C)
TEMPERATURE (deg C)
VOL Vs IOL
VOH Vs TEMP.
MA9003 Base
4.1
0.4
4.0
Hot
(125)
0.3
9003
Base
3.8
VOL (V)
VOH (V)
3.9
3.7
3.6
Room
Temp.
Cold
(-55)
0.2
0.1
3.5
9007
Base
BMS011
Base
80 100 120 140
3.4
3.3
-60
-40
-20
0
20
40
60
TEMPERATURE (deg C)
0
0
2
4
6
8
10
Vdd = 5.5V
VOL Vs IOL
VOL Vs IOL
MA9007 Base
BMS011 Base
0.4
12
14
16
IOL (mA)
0.4
Hot
(125)
Hot
(125)
Room
Temp.
Cold
(-55)
0.2
0.1
Room
Temp.
0.3
VOL (V)
VOL (V)
0.3
Cold
(-55)
0.2
0.1
0
0
0
Vdd = 5.5V
2
4
6
8
IOL (mA)
10
12
14
16
0
Vdd = 5.5V
2
4
6
8
10
12
14
16
IOL (mA)
96/101
www.dynexsemi.com
VOH Vs IOH
VOH Vs IOH
MA9003 Base
MA9007 Base
4.5
4.5
4.3
4.3
4.1
4.1
3.9
Cold
(-55)
Room
Temp.
Hot
(125)
3.7
3.5
3.3
0
2
4
6
8
10
12
14
16
VOH (V)
VOH (V)
54HSC/T Series
3.9
3.7
Cold
(-55)
3.5
Room
Temp.
3.3
0
IOL (-mA)
Vdd = 4.5V
Vdd = 4.5V
2
4
6
8
10
12
14
Hot
16 (125)
IOL (-mA)
VOH Vs IOH
BMS011 Base
4.5
4.3
VOH (V)
4.1
3.9
3.7
3.5
3.3
0
Vdd = 4.5V
2
4
6
8
10
12
14
16
Cold
(-55)
Room
Temp.
Hot
(125)
IOL (-mA)
97/101
www.dynexsemi.com
54HSC/T Series
54 hsc 14 SCHMITT I/P HYSTERESIS
Cold at -55°C
i/p decreasing
i/p increasing
Test at +25°C
i/p decreasing
i/p increasing
Hot at +125°C
i/p decreasing
i/p increasing
6
O/P VOLTAGE
5
4
3
2
1
0
0
1
2
3
4
5
4
5
I/P VOLTAGE
i/p pin 3
54 hsc 14 SCHMITT I/P HYSTERESIS
Pre Rad
i/p decreasing
i/p increasing
Post Rad (100Krad)
i/p decreasing
i/p increasing
6
O/P VOLTAGE
5
4
3
2
1
0
0
i/p pin 9
1
2
3
I/P VOLTAGE
98/101
www.dynexsemi.com
54HSC/T Series
TIMING DIAGRAMS
Figure 3: Set-Up Times, Hold Times, Removal Time and Propagation Delay Times
Figure 4: Three-State Propagation Delay Wave Shapes and Test Circuit
99/101
www.dynexsemi.com
54HSC/T Series
RADIATION TOLERANCE
Total Dose (Function to specification)*
3x105 Rad(Si)
Transient Upset (Stored data loss)
1x1011 Rad(Si)/sec
Transient Upset (Survivability)
>1x1012 Rad(Si)/sec
Neutron Hardness (Function to specification)
>1x1015 n/cm2
Single Event Upset**
<1x10-10 Errors/bit day
Latch Up
Not possible
* Other total dose radiation levels available on request
** Worst case galactic cosmic ray upset - interplanetary/high altitude orbit
Figure 5: Radiation Hardness Parameters
ORDERING INFORMATION
Unique Circuit Designator
Radiation Tolerance
54xHSC139xxxxx
54xHST139xxxxx
No tolerance implied
‘Blank’
Radiation Hard Processing
S
100 kRads (Si) Guaranteed
R
300 kRads (Si) Guaranteed
Q
H 1000 kRads (Si) Guaranteed*
* HSC Only
Package Type
C
F
L
N
Ceramic DIL (Solder Seal)
Flatpack (Solder Seal)
Leadless Chip Carrier
Naked Die
For details of reliability, QA/QC, test and assembly
options, see ‘Manufacturing Capability and Quality
Assurance Standards’ Section 9.
QA/QCI Process
(See Section 9 Part 4)
Test Process
(See Section 9 Part 3)
Assembly Process
(See Section 9 Part 2)
Reliability Level
L
C
D
E
B
S
Rel 0
Rel 1
Rel 2
Rel 3/4/5/STACK
Class B
Class S
100/101
www.dynexsemi.com
http://www.dynexsemi.com
e-mail: space_comms@dynexsemi.com
HEADQUARTERS OPERATIONS
DYNEX SEMICONDUCTOR LTD
Doddington Road, Lincoln.
Lincolnshire. LN6 3LF. United Kingdom.
Tel: +44-(0)1522-500500
Fax: +44-(0)1522-500550
CUSTOMER SERVICE
Tel: +44 (0)1522 502753 / 502901. Fax: +44 (0)1522 500020
SALES OFFICE
Tel: +44 (0)1522 500500. Fax: +44 (0)1522 502777
These offices are supported by Representatives and Distributors in many countries world-wide.
© Dynex Semiconductor 2002 TECHNICAL DOCUMENTATION – NOT FOR RESALE. PRODUCED IN
UNITED KINGDOM
Datasheet Annotations:
Dynex Semiconductor annotate datasheets in the top right hard corner of the front page, to indicate product status. The annotations are as follows:Target Information: This is the most tentative form of information and represents a very preliminary specification. No actual design work on the product has been started.
Preliminary Information: The product is in design and development. The datasheet represents the product as it is understood but details may change.
Advance Information: The product design is complete and final characterisation for volume production is well in hand.
No Annotation: The product parameters are fixed and the product is available to datasheet specification.
This publication is issued to provide information only which (unless agreed by the Company in writing) may not be used, applied or reproduced for any purpose nor form part of any order or contract nor to be regarded
as a representation relating to the products or services concerned. No warranty or guarantee express or implied is made regarding the capability, performance or suitability of any product or service. The Company
reserves the right to alter without prior notice the specification, design or price of any product or service. Information concerning possible methods of use is provided as a guide only and does not constitute any guarantee
that such methods of use will be satisfactory in a specific piece of equipment. It is the user's responsibility to fully determine the performance and suitability of any equipment using such information and to ensure
that any publication or data used is up to date and has not been superseded. These products are not suitable for use in any medical products whose failure to perform may result in significant injury
or death to the user. All products and materials are sold and services provided subject to the Company's conditions of sale, which are available on request.
All brand names and product names used in this publication are trademarks, registered trademarks or trade names of their respective owners.
www.dynexsemi.com