www.fairchildsemi.com AN-9738 Design Guideline on 150W Power Supply for LED Street Lighting Design Using FL7930B and FAN7621S Introduction This application note describes a 150W rating design guideline for LED street lighting. The application design consists of CRM PFC and LLC SRC with high power factor and high power conversion efficiency using FL7930B and FAN7621S. To verify the validity of the application board and scheme, a demonstration board 150W (103V/1.46A) AC-DC converter was implemented and its results are presented in this application note. In CRM active PFC, the most popular topology is a boost converter. This is because boost converters can have continuous input current that can be manipulated with peak current mode control techniques to force peak current to track changes in line voltage. The FAN7930B is an active Power Factor Correction (PFC) controller for boost PFC applications that operate in critical conduction mode (CRM). Since it was first introduced in early 1990s, LLC-SRC (series resonant converter) has became a most popular topology because of its outstanding performance in areas such as the output regulation of switching frequency, ZVS capability for entire load range, low turn-off current, small resonant components using the integrated transformer, zero current switching (ZCS), and no reverse recovery loss on secondary rectifier. Figure 1 shows the typical application circuit, with the CRM PFC converter in the front end and the LLC SRC DC-DC converter in the back end. FL7930B and FAN7621S achieve high efficiency with medium power for 150W rating applications where CRM and LLC SRC operation with a two-stage shows best performance. CRM boost PFC converters can achieve better efficiency with light and medium power rating than Continuous Conduction Mode (CCM) boost PFC converters. These benefits result from the elimination of the reverse-recovery losses of the boost diode and Zero-Current Switching (ZCS). The LLC SRC DC-DC converter achieves higher efficiency than the conventional hard switching converter. The FL7930B provides a controlled on-time to regulate the output DC voltage and achieves natural power factor correction. The FAN7621S includes a high-side gate driver circuit, accurate current-controlled oscillator, frequency -limit circuit, soft-start, and built-in protections. The high-side gate drive circuit has a common-mode noise cancellation capability, which guarantees stable operation with excellent noise immunity. Using Zero Voltage Switching (ZVS) dramatically reduces switching losses and significantly improves efficiency. ZVS also reduces switching noise noticeably, which allows a small-sized Electromagnetic Interference (EMI) filter. Figure 1. Typical Application Circuit © 2011 Fairchild Semiconductor Corporation Rev. 1.0.0 • 4/20/11 www.fairchildsemi.com AN-9738 APPLICATION NOTE 1. Basic Operation of BCM PFC Pre-Regulator The most widely used operation modes for the boost converter are Continuous Conduction Mode (CCM) and Boundary Conduction Mode (BCM). These two descriptive names refer to the current flowing through the energy storage inductor of the boost converter, as depicted in Figure 2. As the names indicate, the inductor current in CCM is continuous; while in BCM, the new switching period is initiated when the inductor current returns to zero, which is at the boundary of continuous conduction and discontinuous conduction operations. Even though the BCM operation has higher RMS current in the inductor and switching devices, it allows better switching condition for the MOSFET and the diode. As shown in Figure 2, the diode reverse recovery is eliminated and a fast-recovery diode is not needed. The MOSFET is also turned on with zero current, which reduces the switching loss. IL ID L VLINE VIN A side effect of BCM is that the boost converter runs with variable switching frequency that depends primarily on the selected output voltage, the instantaneous value of the input voltage, the boost inductor value, and the output power delivered to the load. The operating frequency changes as the input current follows the sinusoidal input voltage waveform, as shown in Figure 3. The lowest frequency occurs at the peak of sinusoidal line voltage. VOUT IDS Line Filter Figure 3. Operation Waveforms of BCM PFC The voltage-second balance equation for the inductor is: V IN ( t ) ⋅ t ON = (VOUT − V IN ( t )) ⋅ t OFF (1) where VIN(t) is the rectified line voltage and VOUT is the output voltage. The switching frequency of BCM boost PFC converter is: f SW = = Figure 2. CCM vs. BCM Control tON + tOFF 1 tON ⋅ = 1 tON ⋅ VOUT − VIN ( t ) VOUT VOUT − VIN ,PK ⋅ sin(2 π ⋅ f LINE ⋅ t ) (2) VOUT where VIN,PK is the amplitude of the line voltage and fLINE is the line frequency. The fundamental idea of BCM PFC is that the inductor current starts from zero in each switching period, as shown in Figure 3. When the power transistor of the boost converter is turned on for a fixed time, the peak inductor current is proportional to the input voltage. Since the current waveform is triangular; the average value in each switching period is proportional to the input voltage. In a sinusoidal input voltage, the input current of the converter follows the input voltage waveform with very high accuracy and draws a sinusoidal input current from the source. This behavior makes the boost converter in BCM operation an ideal candidate for power factor correction. © 2011 Fairchild Semiconductor Corporation Rev. 1.0.0 • 4/20/11 1 Figure 4 shows how the MOSFET on-time and switching frequency change as output power decreases. When the load decreases, as shown in the right side of Figure 4, the peak inductor current diminishes with reduced MOSFET on-time and, therefore, the switching frequency increases. Since this can cause severe switching losses at light-load condition and too-high switching frequency operation may occur at startup, the maximum switching frequency of FL7930B is limited to 300kHz. www.fairchildsemi.com 2 AN-9738 APPLICATION NOTE IL Average of input current VGS Figure 5. Half-Bridge, LC Series Resonant Converter fSW To overcome the limitation of series resonant converters, the LLC resonant converter has been proposed. The LLC resonant converter is a modified LC series resonant converter implemented by placing a shunt inductor across the transformer primary winding, as depicted in Figure 6. When this topology was first presented, it did not receive much attention due to the counterintuitive concept that increasing the circulating current in the primary side with a shunt inductor can be beneficial to circuit operation. However, it can be very effective in improving efficiency for high-input voltage applications where the switching loss is more dominant than the conduction loss. t Figure 4. Frequency Variation of BCM PFC Since the design of the filter and inductor for a BCM PFC converter with variable switching frequency should be at minimum frequency condition, it is worthwhile to examine how the minimum frequency of BCM PFC converter changes with operating conditions. In most practical designs, this shunt inductor is realized using the magnetizing inductance of the transformer. The circuit diagram of LLC resonant converter looks much the same as the LC series resonant converter: the only difference is the value of the magnetizing inductor. While the series resonant converter has a magnetizing inductance larger than the LC series resonant inductor (Lr), the magnetizing inductance in an LLC resonant converter is just 3~8 times Lr, which is usually implemented by introducing an air gap in the transformer. 2. Consideration of LLC Resonant Converter The attempt to obtain ever-increasing power density in switched-mode power supplies has been limited by the size of passive components. Operation at higher frequencies considerably reduces the size of passive components, such as transformers and filters; however, switching losses have been an obstacle to high-frequency operation. To reduce switching losses and allow high-frequency operation, resonant switching techniques have been developed. These techniques process power in a sinusoidal manner and the switching devices are softly commutated. Therefore, the switching losses and noise can be dramatically reduced. Figure 6. Half-Bridge LLC Resonant Converter Among various kinds of resonant converters, the simplest and most popular is the LC series resonant converter, where the rectifier-load network is placed in series with the LC resonant network, as depicted in Figure 5. In this configuration, the resonant network and the load act as a voltage divider. By changing the frequency of driving voltage Vd, the impedance of the resonant network changes. The input voltage is split between this impedance and the reflected load. Since it is a voltage divider, the DC gain of a LC series resonant converter is always <1. At light-load condition, the impedance of the load is large compared to the impedance of the resonant network; all the input voltage is imposed on the load. This makes it difficult to regulate the output at light load. Theoretically, frequency should be infinite to regulate the output at no load. © 2011 Fairchild Semiconductor Corporation Rev. 1.0.0 • 4/20/11 An LLC resonant converter has many advantages over a series resonant converter. It can regulate the output over wide line and load variations with a relatively small variation of switching frequency. It can achieve zero voltage switching (ZVS) over the entire operating range. All essential parasitic elements; including the junction capacitances of all semiconductor devices, the leakage inductance, and magnetizing inductance of the transformer; are utilized to achieve soft switching. www.fairchildsemi.com 3 AN-9738 APPLICATION NOTE This application note presents design considerations for an LLC resonant half-bridge converter employing Fairchild’s FAN7621S. It includes explanation of the LLC resonant converter operation principles, designing the transformer and resonant network, and selecting the components. The step-by-step design procedure, explained with a design example, helps design the LLC resonant converter. 0 shows a simplified schematic of a half-bridge LLC resonant converter, where Lm is the magnetizing inductance that acts as a shunt inductor, Lr is the series resonant inductor, and Cr is the resonant capacitor. Figure 8 illustrates the typical waveforms of the LLC resonant converter. It is assumed that the operation frequency is the same as the resonance frequency, determined by the resonance between Lr and Cr. Since the magnetizing inductor is relatively small, a considerable amount of magnetizing current (Im) exists, which freewheels in the primary side without being involved in the power transfer. The primary-side current (Ip) is the sum of the magnetizing current and the secondary-side current referred to the primary. Figure 7. Schematic of Half-Bridge LLC Resonant Converter Ip In general, the LLC resonant topology consists of the three stages shown in 0; square-wave generator, resonant network, and rectifier network. IDS1 The square-wave generator produces a square-wave voltage, Vd, by driving switches Q1 and Q2 alternately with 50% duty cycle for each switch. A small dead time is usually introduced between the consecutive transitions. The square-wave generator stage can be built as a full-bridge or half-bridge type. ID VIN Vd The resonant network consists of a capacitor, leakage inductances, and the magnetizing inductance of the transformer. The resonant network filters the higher harmonic currents. Essentially, only sinusoidal current is allowed to flow through the resonant network even though a square-wave voltage is applied. The current (Ip) lags the voltage applied to the resonant network (that is, the fundamental component of the square-wave voltage (Vd) applied to the half-bridge totem pole), which allows the MOSFETs to be turned on with zero voltage. As shown in Figure 8, the MOSFET turns on while the voltage across the MOSFET is zero by flowing current through the anti-parallel diode. Vgs1 Vgs2 Figure 8. Typical Waveforms of Half-Bridge LLC Resonant Converter The filtering action of the resonant network allows the use of the fundamental approximation to obtain the voltage gain of the resonant converter, which assumes that only the fundamental component of the square-wave voltage input to the resonant network contributes to the power transfer to the output. Because the rectifier circuit in the secondary side acts as an impedance transformer, the equivalent load resistance is different from actual load resistance. Figure 9 shows how this equivalent load resistance is derived. The primary-side circuit is replaced by a sinusoidal current source, Iac, and a square wave of voltage, VRI, appears at the input to the rectifier. Since the average of |Iac| is the output current, Io, Iac, is obtained as: The rectifier network produces DC voltage by rectifying the AC current with rectifier diodes and a capacitor. The rectifier network can be implemented as a full-wave bridge or a center-tapped configuration with capacitive output filter. I ac = © 2011 Fairchild Semiconductor Corporation Rev. 1.0.0 • 4/20/11 Im π ⋅ Io 2 sin(ωt ) (3) www.fairchildsemi.com 4 AN-9738 APPLICATION NOTE and VRI is given as: VRI = +Vo if sin(ωt ) > 0 VRI = −Vo if sin(ωt ) < 0 Vd + VIN π sin(ωt ) VRI F 8 V 8 = 2 o = 2 Ro I ac π Io π 8n π Rac = 8n - 2 π2 Ro Lm (nVRIF) With the equivalent load resistance obtained in Equation 7, the characteristics of the LLC resonant converter can be derived. Using the AC equivalent circuit of Figure 10, the voltage gain, M, is obtained as: 4n ⋅ Vo sin(ωt ) VRO F n ⋅ VRI F 2n ⋅ Vo M = F = = π = F V 4 Vd Vd Vin in sin(ωt ) π 2 (7) By using the equivalent load resistance, the AC equivalent circuit is obtained, as illustrated in Figure 10, where VdF and VROF are the fundamental components of the driving voltage, Vd and reflected output voltage, VRO (nVRI), respectively. I ac Rac Figure 10. AC Equivalent Circuit for LLC Resonant Converter (6) Ro VRoF Lr Cr 2 2 Ro Np:Ns VdF Considering the transformer turns ratio (n=Np/Ns), the equivalent load resistance shown in the primary side is obtained as: Rac = + (5) Since harmonic components of VRI are not involved in the power transfer, AC equivalent load resistance can be calculated by dividing VRIF by Iac as: Rac = VO VRI - n=Np/Ns VRI = + Lm The fundamental component of VRI is given as: 4Vo Lr (4) where Vo is the output voltage. F Cr (8) ω 2 ) (m − 1) ωo = ω2 ω ω2 ( 2 − 1) + j ( 2 − 1)(m − 1)Q ωp ωo ωo ( pk where: L p = Lm + Lr , Rac = Q= Lr 1 , ωo = Cr Rac 8n 2 π 2 Ro , m = Lp Lr 1 , ωp = Lr Cr 1 L p Cr As can be seen in Equation (8), there are two resonant frequencies. One is determined by Lr and Cr, while the other is determined by Lp and Cr. I ac = π ⋅ Io VRI F = 2 Equation (8) shows the gain is unity at resonant frequency (ωo), regardless of the load variation, which is given as: sin( wt ) 4Vo π 2 2n ⋅ Vo ( m − 1) ⋅ ω p M = = = 1 at ω = ωo Vin ωo 2 − ω p 2 sin( wt ) The gain of Equation (8) is plotted in Figure 11 for different Q values with m=3, fo=100kHz, and fp=57kHz. As observed in Figure 11, the LLC resonant converter shows gain characteristics that are almost independent of the load when the switching frequency is around the resonant frequency, fo. This is a distinct advantage of LLC-type resonant converter over the conventional series resonant converter. Therefore, it is natural to operate the converter around the resonant frequency to minimize the switching frequency variation. Figure 9. Derivation of Equivalent Load Resistance Rac © 2011 Fairchild Semiconductor Corporation Rev. 1.0.0 • 4/20/11 (9) www.fairchildsemi.com 5 AN-9738 APPLICATION NOTE be divided into two categories; rising current when the MOSFET is on and output diode current when the MOSFET is off, as shown in Figure 12. The operating range of the LLC resonant converter is limited by the peak gain (attainable maximum gain), which is indicated with ‘Q’ in Figure 11. Note that the peak voltage gain does not occur at fo or fp. The peak gain frequency, where the peak gain is obtained, exists between fp and fo, as shown in Figure 11. As Q decreases (as load decreases), the peak gain frequency moves to fp and higher peak gain is obtained. Meanwhile, as Q increases (as load increases), the peak gain frequency moves to fo and the peak gain drops; the full-load condition should be worst case for the resonant network design. fp = 2π 1 L p Cr fo = 1 2π Lr Cr Figure 12. Inductor and Input Current Q= [email protected] fo Lr / Cr Because switching frequency is much higher than line frequency, input current can be assumed to be constant during a switching period, as shown in Figure 133. Rac =1 Figure 11. Typical Gain Curves of LLC Resonant Converter (m=3) 3. Design Considerations Figure 13. Inductor and Input Current This design procedure uses the schematic in Figure 1 as a reference. A 150W street lighting application with universal input range is selected as a design example. The design specifications are: With the estimated efficiency, Figure 12 and Figure 13, inductor current peak (IL,PK), maximum input current (IIN,MAX), and input Root Mean Square (RMS) current (IIN,MAXRMS) are given as: Line Voltage Range: 85VA~277VAC (50Hz) Output of Converter: 103V/1.46A (150W) PFC Output Voltage: 430V Overall Efficiency: 90% (PFC: 95%, LLC: 95%) I L , PK = 4 ⋅ POUT η ⋅ 2 ⋅ V LINE [ A] (10) , MIN I IN ,MAX = I L,PK / 2 [ A] (11) I IN ,MAXRMS = I IN ,MAX / 2 [ A ] (12) 3.1 PFC Section [STEP-1] Define System Specification (Design Example) Input voltage range is universal input, output load is 465mA, and estimated efficiency is selected as 0.9. Line Frequency Range (VLINE,MIN and VLINE,MAX) Line Frequency (fLINE) Output-Voltage (VOUT) Output Load Current (IOUT) Output Power (POUT =VOUT × IOUT) Estimated Efficiency (η) VLINE , MIN = 85V AC , V LINE , MAX = 277V AC f LINE = 50 Hz VOUT = 430V , I OUT = 465mA η = 0.9 I L , PK = To calculate the maximum input power, it is necessary to estimate the power conversion efficiency. At universal input range, efficiency is recommended at 0.9; 0.93~0.95 is recommended when input voltage is high. When input voltage is set at the minimum, input current becomes the maximum to deliver the same power compared at high line. Maximum boost inductor current can be detected at the minimum line voltage and at its peak. Inductor current can © 2011 Fairchild Semiconductor Corporation Rev. 1.0.0 • 4/20/11 4 ⋅ POUT η ⋅ 2 ⋅ VLINE ,MIN I IN ,MAX = I IN ,MAXRMS = 4 ⋅ 430V ⋅ 0.465 A 0.9 ⋅ 2 ⋅ 85 = 7.392 A I L, PK 7.392 A = = 3.696 A 2 2 I 3.696 A = IN , MAX = = 2.613 A 2 2 www.fairchildsemi.com 6 AN-9738 APPLICATION NOTE [STEP-2] Boost Inductor Design When selecting wire diameter and strands; current density, window area (AW, refer to Figure 14) of the selected core, and fill factor need to be considered. The winding sequence of the boost inductor is relatively simple compared to a DCDC converter, so fill factor can be assumed about 0.2~0.3. The boost inductor value is determined by the output power and the minimum switching frequency. The minimum switching frequency must be higher than the maximum audible frequency band of 20kHz. Minimum frequency near 20kHz can decrease switching loss with the cost of increased inductor size and line filter size. Too-high minimum frequency may increase the switching loss and make the system respond to noise. Selecting in the range of about 30~60kHz is a common choice; 40~50kHz is recommended with FL7930B. Layers cause the skin effect and proximity effect in the coil, so real current density may be higher than expected. The minimum switching frequency may appear at minimum input voltage or maximum input voltage, depending on the output voltage level. When PFC output voltage is less than 430V, minimum switching appears at the maximum input voltage (see Fairchild application note AN-6086). Inductance is obtained using the minimum switching frequency: L= ( η ⋅ 2 VLINE )2 2 VLINE 4 ⋅ f SW ,MIN ⋅ POUT ⋅ 1 + V − 2 V OUT LINE [H] (13) Figure 14. Typical B-H Curves of Ferrite Core where L is boost inductance and fSW,MIN is the minimum switching frequency. The maximum on-time needed to carry peak inductor current is calculated as: t ON, MAX = L ⋅ I L,PK 2 ⋅ V LINE, MIN [s] (14) Once inductance and the maximum inductor current are calculated, the turn number of the boost inductor should be determined considering the core saturation. The minimum number of turns is given as: N BOOST ≥ I L , PK ⋅ L [ µH ] Ae [ mm 2 ] ⋅ ∆B [ Turns ] Figure 15. Ae and AW (Design Example) Since the output voltage is 430V, the minimum frequency occurs at high-line (277VAC) and fullload condition. Assuming the efficiency is 90% and selecting the minimum frequency as 50kHz, the inductor value is obtained as: (15) where Ae is the cross-sectional area of the core and ∆B is the maximum flux swing of the core in Tesla. ∆B should be set below the saturation flux density. L= Figure 14 shows the typical B-H characteristics of a ferrite core from TDK (PC45). Since the saturation flux density (∆B) decreases as the temperature increases, the hightemperature characteristics should be considered. = RMS inductor current (IL,RMS) and current density of the coil (IL,DENSITY) can be given as: I L ,RMS = I L ,PK I L ,DENSITY = 6 [ A] 2 d π ⋅ wire ⋅ N wire 2 LINE 2 VLINE 4 ⋅ f SW ,MIN ⋅ POUT ⋅ 1 + V − V 2 OUT LINE ( 0.9 ⋅ 2 × 277 )2 2 ⋅ 277 4 ⋅ 50 ⋅10 3 ⋅ 200 ⋅ 1 + 430 − 2 ⋅ 277 N BOOST ≥ 2 [ A / mm ] (17) = 307.2 [ µH ] I L ,PK ⋅ L [ µH ] Ae [ mm 2 ] ⋅ ∆B = 7.392 ⋅ 307 = 55 [ T ] 137 ⋅ 0.3 The number of turns (NBOOST) of the boost inductor is determined as 55 turns. where dWIRE is the diameter of winding wire and NWIRE is the number of strands of winding wire. © 2011 Fairchild Semiconductor Corporation Rev. 1.0.0 • 4/20/11 ( 2 V )2 Assuming EER3019N core (PL-7, Ae=137mm2) is used and setting ∆B as 0.3T, the primary winding should be: (16) I L ,RMS η⋅ When 0.10mm diameter and 50-strand wire is used, RMS current of inductor coil and current density are: www.fairchildsemi.com 7 AN-9738 I L ,RMS = APPLICATION NOTE I L ,PK 6 I L ,DENSITY = = 7.392 6 I L,RMS 2 Auxiliary winding must give enough energy to trigger ZCD threshold to detect zero current. Minimum auxiliary winding turns are given as: = 3.017 [ A ] d π ⋅ wire ⋅ Nwire 2 = 3.017 π ⋅ (0.1 / 2 )2 ⋅ 50 = 7.68 [ A / mm2 ] N AUX ≥ 1.5 V ⋅ N BOOST VOUT − 2 VLINE,MAX [ Turns] (18) [STEP-3] Inductor Auxiliary Winding Design where 1.5V is the positive threshold of the ZCD pin. Figure 16 shows the application circuit of the nearby ZCD pin from auxiliary winding. To guarantee stable operation, it is recommended to add 2~3 turns to the auxiliary winding turns calculated in Equation (18). However, too many auxiliary winding turns raise the negative clamping loss at high line and positive clamping loss at low line. (Design Example) 55 turns are selected as boost inductor turns and auxiliary winding turns are calculated as: N AUX ≥ 1.5 V ⋅ N BOOST VOUT − 2 VLINE,MAX = 1.5 ⋅ 55 430 − 2 ⋅ 277 = 2.15 [Turns] Choice should be around 4~5 turns after adding 2~3 turns. [STEP-4] ZCD Circuit Design Figure 16. Application Circuit of ZCD Pin If a transition time when VAUXILIARY drops from 1.4V to 0V is ignored from Figure 17, the necessary additional delay by the external resistor and capacitor is one quarter of the resonant period. The time constant made by ZCD resistor and capacitor should be the same as one quarter of the resonant period: The first role of ZCD winding is detecting the zero-current point of the boost inductor. Once the boost inductor current becomes zero, the effective capacitance (Ceff) at the MOSFET drain pin and the boost inductor resonate together. To minimize the constant turn-on time deterioration and turn-on loss, the gate is turned on again when the drain source voltage of the MOSFET (VDS) reaches the valley point shown in Figure 17. When input voltage is lower than half of the boosted output voltage, Zero Voltage Switching (ZVS) is possible if MOSFET turnon is triggered at valley point. RZCD ⋅ CZCD = 2 π Ceff ⋅ L (19) 4 where Ceff is the effective capacitance at the MOSFET drain pin; CZCD is the external capacitance at the ZCD pin; and RZCD is the external resistance at the ZCD pin. The second role of RZCD is the current limit of the internal negative clamp circuit when auxiliary voltage drops to negative due to MOSFET turn on. ZCD voltage is clamped 0.65V and minimum RZCD can be given as: N AUX 2 VLINE,MAX − 0.65 V N BOOST [ Ω] RZCD ≥ 3 mA (20) where 3mA is the clamping capability of the ZCD pin. The calculation result of Equation (20) is normally higher than 15kΩ. If 20kΩ is assumed as RZCD, calculated CZCD from Equation (19) is around 10pF when the other components are assumed as conventional values used in the field. Because most IC pins have several pF of parasitic capacitance, CZCD can be eliminated when RZCD is higher than 30kΩ. However, a small capacitor would be helpful when auxiliary winding suffers from operating noise. The PFC control loop has two conflicting goals: output voltage regulation and making the input current shape the same as input voltage. If the control loop reacts to regulate output voltage smoothly, as shown in Figure 18, control Figure 17. ZCD Detection Waveforms © 2011 Fairchild Semiconductor Corporation Rev. 1.0.0 • 4/20/11 www.fairchildsemi.com 8 AN-9738 APPLICATION NOTE voltage varies widely with the input voltage variation. Input current acts to the control loop and sinusoidal input current shape cannot be attained. This is the reason control response of most PFC topologies is very slow and turn-on time over AC period is kept constant. This is also the reason output voltage ripple is made by input and output power relationship, not by control-loop performance. Figure 18. Input Current Deterioration by Fast Control Figure 20. Inductor Current at AC Voltage Zero If on-time is controlled constantly over one AC period, the inductor current peak follows AC input voltage shape and achieves good power factor. Off-time is basically inductor current reset time due to Boundary Mode and is determined by the input and output voltage difference. When input voltage is at its peak, the voltage difference between input and output voltage is small and long turn-off time is necessary. When input voltage is near zero, turn-off time is short, as shown in Figure 19 and Figure 20. Though inductor current drops to zero, the minor delay is explained above. The delay can be assumed as fixed when AC is at line peak and zero. Near AC line peak, the inductor current decreasing slope is slow and inductor current slope is also slow during the ZCD delay. The amount of negative current is not much higher than the inductor current peak. Near the AC line zero, inductor current decreasing slope is very high and the amount of negative current is higher than positive inductor current peak because input voltage is almost zero. Negative inductor current creates zero-current distortion and degrades the power factor. Improve this by extending turnon time at the AC line input near the zero cross. Negative auxiliary winding voltage, when the MOSFET is turned on, is linearly proportional to the input voltage. Sourcing current generated by the internal negative clamping circuit is also proportional to sinusoidal input voltage. That current is detected internally and added to the internal sawtooth generator, as shown in Figure 21. Figure 21. ZCD Current and Sawtooth Generator When the AC input voltage is almost zero, no negative current is generated from inside, but sourcing current when input voltage is high is used to raise the sawtooth generator slope and turn-on time is shorter. As a result, turn-on time when AC voltage is zero is longer compared to AC voltage, in peaks shown in Figure 22. Figure 19. Inductor Current at AC Voltage Peak © 2011 Fairchild Semiconductor Corporation Rev. 1.0.0 • 4/20/11 www.fairchildsemi.com 9 AN-9738 APPLICATION NOTE control voltage decreases rapidly. For example, if input voltage doubles, control voltage drops to one quarter. Making control voltage maximum when input voltage is low and at full load is necessary to use the whole control range for the rest of the input voltage conditions. Matching maximum turn-on time needed at low line is calculated in Equation (14) and turn-on time adjustment by RZCD guarantees use of the full control range. RZCD for control range optimization is obtained as: RZCD ≥ Figure 22. THD Improvement 2 ⋅ VLINE ,MIN ⋅ N AUX 28 µs ⋅ [ Ω ] (21) 0.469 mA ⋅ N BOOST t ON ,MAX 1 − t ON ,MAX where: tON,MAX is calculated by Equation (14); tON,MAX1 is maximum on-time programming 1; NBOOST is the winding turns of boost inductor; and NAUX is the auxiliary winding turns. The current that comes from the ZCD pin, when auxiliary voltage is negative, depends on RZCD. The second role of RZCD is also related to improving the Total Harmonic Distortion (THD). The third role of RZCD is making the maximum turn-on time adjustment. Depending on sourcing current from the ZCD pin, the maximum on-time varies as in Figure 23. RZCD calculated by Equation (20) is normally lower than the value calculated in Equation (21). To guarantee the needed turn on-time for the boost inductor to deliver rated power, the RZCD from Equation (20) is normally not suitable. RZCD should be higher than the result of Equation (21) when output voltage drops as a result of low line voltage. When input voltage is high and load is light, not much input current is needed and control voltage of VCOMP touches switching stop level, such as if FL7930B is 1V. However, in some applications, a PFC block is needed to operate normally at light load. To compensate control range correctly, input voltage sensing is necessary, such as with Fairchild’s interleaved PFC controller FAN9612, or special care on sawtooth generator is necessary. To guarantee enough control range at high line, clamping output voltage lower than rated on the minimum input condition can help. Figure 23. Maximum On-Time Variation vs. IZCD With the aid of IZCD, an internal sawtooth generator slope is changed and turn-on time varies as shown in Figure 24. (Design Example) Minimum RZCD for clamping capability is calculated as: N AUX 2 VLINE,MAX − 0.65 V N BOOST RZCD ≥ 3 mA 5 2 ⋅ 277 − 0.65 V 34 = = 18.9 kΩ 3 mA Minimum RZCD for control range is calculated as: R ZCD ≥ = t ON ,MAX1 − t ON ,MAX ⋅ 2 ⋅V LINE ,MIN ⋅ N AUX 0.469 mA ⋅ N BOOST 28 µs 2 ⋅ 85 ⋅ 5 ⋅ = 20.97 kΩ 42 µs −10.9 µs 0.469 mA ⋅ 55 A choice close to the value calculated by the control range is recommended. 39kΩ is chosen in this case. Figure 24. Internal Sawtooth Wave Slope Variation RZCD also influences control range. Because FL7930B doesn’t detect input voltage, voltage-mode control value is determined by the turn-on time to deliver the needed current to boost output voltage. When input voltage increases, © 2011 Fairchild Semiconductor Corporation Rev. 1.0.0 • 4/20/11 28 µs www.fairchildsemi.com 10 AN-9738 APPLICATION NOTE [STEP-5] Output Capacitor Selection (Design Example) With the ripple specification of 8Vp-p, the capacitor should be: The output voltage ripple should be considered when selecting the output capacitor. Figure 25 shows the line frequency ripple on the output voltage. With a given specification of output ripple, the condition for the output capacitor is obtained as: C OUT ≥ I OUT 2 π ⋅ f LINE ⋅ ∆VOUT ,RIPPLE [f] CO ≥ I OUT 2 π ⋅ f LINE ⋅ ∆VOUT ,ripple = 0.465 = 185 [ µF ] 2 π ⋅ 50 ⋅ 8 Since minimum allowable output voltage during one cycle line (20ms) drop-outs is 330V, the capacitor should be: CO ≥ (22) (V OUT 2 × POUT ⋅ t HOLD − 0 .5 ⋅ ∆ V OUT 2 ⋅ 200 ⋅ 20 × 10 −3 ,ripple )2 − V OUT 2 ,MIN where VOUT,RIPPLE is the peak-to-peak output voltage ripple specification. = The output voltage ripple caused by the ESR of the electrolytic capacitor is not as serious as other power converters because output voltage is high and load current is small. Since too much ripple on the output voltage may cause premature OVP during normal operation, the peak-topeak ripple specification should be smaller than 15% of the nominal output voltage. To meet both conditions, the output capacitor must be larger than 140µF. A 240µF capacitor is selected for the output capacitor. 2 ⋅ POUT ⋅ t HOLD (VOUT − 0.5 ⋅ ∆VOUT,RIPPLE) 2 − VOUT,MIN 2 [f] − 0 .5 ⋅ 8 )2 − 330 2 = 110 [ µ F ] The voltage stress of selected capacitor is calculated as: VST ,COUT = The hold-up time should also be considered when determining the output capacitor as: COUT ≥ (430 2.730 VOVP,MAX ⋅ 430 = 469.5 [V ] ⋅VOUT = 2.500 VREF [STEP-6] MOSFET and DIODE Selection Selecting the MOSFET and diode requires extensive knowledge and calculation regarding loss mechanisms and gets more complicated if proper selection of a heatsink is added. Sometimes the loss calculation itself is based on assumptions that may be far from reality. Refer to industry resources regarding these topics. This note shows the voltage rating and switching loss calculations based on a linear approximation. (23) where tHOLD is the required hold-up time and VOUT,MIN is the minimum output voltage during hold-up time. Idiode The voltage stress of the MOSFET is obtained as: VST ,Q = (25) where VDROP,DOUT is the maximum forward-voltage drop of output diode. Idiode,ave Idiode,ave=IOUT(1-cos(4p.fL.t)) After the MOSFET is turned off, the output diode turns on and a large output electrolytic capacitance is shown at the drain pin; thus a drain voltage clamping circuit that is necessary on other topologies is not necessary in PFC. During the turn-off transient, boost inductor current changes the path from MOSFET to output diode. Before the output diode turns on; a minor voltage peak can be shown at drain pin, which is proportional to MOSFET turn-off speed. IOUT VOUT,ripple= IOUT 2p.fL.COUT VOUT t MOSFET loss can be divided into three parts: conduction loss, turn-off loss, and discharge loss. Boundary mode guarantees Zero Current Switching (ZCS) of the MOSFET when turned on, so turn-on loss is negligible. Figure 25. Output Voltage Ripple The voltage rating of capacitor can be obtained as: VST ,COUT = VOVP ,MAX ⋅ VOUT + VDROP ,DOUT [ V ] VREF VOVP ,MAX ⋅ VOUT [ V ] VREF The MOSFET RMS current and conduction loss are obtained as: (24) where VOVP,MAX and VREF are the maximum tolerance specifications of over-voltage protection triggering voltage and reference voltage at error amplifier, respectively. I Q,RMS = I L,PK ⋅ ( 1 4 2 ⋅ VLINE − [ A] 6 9 π ⋅ VOUT ) PQ ,CON = I Q ,RMS 2 ⋅ RDS ,ON [ W ] © 2011 Fairchild Semiconductor Corporation Rev. 1.0.0 • 4/20/11 (26) (27) www.fairchildsemi.com 11 AN-9738 APPLICATION NOTE where IQ,RMS is the RMS value of MOSFET current, PQ,CON is the conduction loss caused by MOSFET current, and RDS,ON is the ON resistance of the MOSFET. The average diode current and power loss are obtained as: On resistance is described as “static on resistance” and varies depending on junction temperature. That variation information is normally supplied as a graph in the datasheet and may vary by manufacturer. When calculating conduction loss, generally multiply three by the RDS,ON for more accurate estimation. 1 ⋅VOUT ⋅ I L ⋅ tOFF ⋅ f SW [W ] 2 = 2.73 ⋅ 430 + 2.1 = 471.6 [V ] 2.50 1 4 2 ⋅ 85 = 7.392 ⋅ − 6 9 π ⋅ 430 PQ ,SWOFF = = = 2 ( ) ⋅ RDS,ON 2 ⋅ (0.34) = 2.23 [W ] 1 ⋅VOUT ⋅ I L ⋅ t OFF ⋅ f SW 2 1 ⋅ 430 ⋅ 2.613 ⋅ 50 ns ⋅ ( 50 k / 0.8 ) =1.755 [ W ] 2 PQ,DISCHG = Capacitive discharge loss made by effective capacitance shown at drain and source, which includes MOSFET COSS, an externally added capacitor to reduce dv/dt and parasitic capacitance shown at drain pin, is also dissipated at MOSFET. That loss is calculated as: 1 2 ⋅ (COSS + C EXT + C PAR ) ⋅VOUT ⋅ f SW 2 1 ⋅ 32 p ⋅ 430 2 ⋅ ( 50 k / 0.8 ) = 0.184 [ W ] 2 Diode average current and forward-voltage drop loss as: I DOUT,AVE = (29) I OUT 0.5 = = 0.56 [ A ] 0.9 η PDOUT ,LOSS = VDOUT ,FOR ⋅ I DOUT ,AVE = 2.1 ⋅ 0.56 = 1.46 [ W ] where: COSS is the output capacitance of MOSFET; CEXT is an externally added capacitance at drain and source of MOSFET; and CPAR is the parasitic capacitance shown at drain pin. [STEP-7] Determine Current-Sense Resistor It is typical to set pulse-by-pulse current limit level a little higher than the maximum inductor current calculated by Equation (10). For 10% margin, the current-sensing resistor is selected as: Because the COSS is a function of the drain and source voltage, it is necessary to refer to graph data showing the relationship between COSS and voltage. RCS = Estimate the total power dissipation of MOSFET as the sum of three losses: VCS,LIM I L,PK ⋅1.1 [ Ω] (33) Once resistance is calculated, its power loss at low line is calculated as: (30) PRCS = IQ2,RMS⋅ RCS [W ] Diode voltage stress is the same as the output capacitor stress calculated in Equation (24). © 2011 Fairchild Semiconductor Corporation Rev. 1.0.0 • 4/20/11 VOVP,MAX ⋅VOUT +VDROP,DIODE VREF 1 4 2 ⋅VLINE PQ,CON = I L,PK ⋅ − 6 9 π ⋅VOUT Individual loss portions are changed according to the input voltage; maximum conduction loss appears at low line because of high input current; and maximum switching off loss appears at high line because of the high switching frequency. The resulting loss is always lower than the summation of the two losses calculated above. PQ = PQ,CON + PQ,SWOFF+ PQ,DISCHG[W ] (32) VST,Q = (28) Boundary Mode PFC inductor current and switching frequency vary at every switching moment. RMS inductor current and average switching frequency over one AC period can be used instead of instantaneous values. 1 2 (COSS + CEXT + CPAR) ⋅VOUT ⋅ f SW [W ] 2 PDOUT = VDROP,DOUT⋅ I DOUT,AVE [W ] (Design Example) Internal reference at the feedback pin is 2.5V and maximum tolerance of OVP trigger voltage is 2.730V. If Fairchild’s FDPF17N60NT MOSFET and FFPF08H60S diode are selected, VD,FOR is 2.1V at 8A, 25°C, maximum RDS,ON is 0.34Ω at drain current is 17A, and maximum COSS is 32pF at drain-source voltage is 480V. where tOFF is the turn-off time and fSW is the switching frequency. PQ,DISCHG= (31) where VDROP,DOUT is the forward voltage drop of diode. The precise turn-off loss calculation is difficult because of the nonlinear characteristics of MOSFET turn-off. When piecewise linear current and voltage of MOSFET during turn-off and inductive load are assumed, MOSFET turn-off loss is obtained as: PQ,SWOFF = I OUT [ A] η I DOUT ,AVE = (34) Power rating of the sensing resistor is recommended a twice the power rating calculated in Equation (34). www.fairchildsemi.com 12 AN-9738 APPLICATION NOTE ∧ (Design Example) Maximum inductor current is 4.889A and sensing resistor is calculated as: RCS = VCS ,LIM pk Iind ⋅1.1 = v OUT ∧ = K SAW ⋅ (VLINE )2 RL ⋅ v COMP 0.8 = 0.098 [ Ω ] 7.392 ⋅1.1 where fp = 4 VOUT ⋅ L 1 1+ 2 2 π ⋅ RL COUT s (36) 2π f p and RL is the output load resistance in a Choosing 0.1Ω as RCS, power loss is calculated as: given load condition. PRCS,LOSS = I Q2,RMS ⋅ RCS = 2.4362 ⋅0.098 = 0.58 [W ] Figure 27 and Figure 28 show the variation of the controlto-output transfer function for different input voltages and different loads. Since DC gain and crossover frequency increase as input voltage increases, and DC gain increases as load decreases, high input voltage and light load is the worst condition for feedback loop design. Recommended power rating of sensing resistor is 1.19W. [STEP-8] Design Compensation Network The boost PFC power stage can be modeled as shown in Figure 26 MOSFET and diode can be changed to loss-free resistor model and then modeled as a voltage-controlled current source supplying RC network. Figure 27. Control-to-Output Transfer Function for Different Input Voltages Figure 28. Control-to-Output Transfer Function for Different Loads Figure 26. Small Signal Modeling of the Power Stage Proportional and integration (PI) control with highfrequency pole is typically used for compensation, as shown in Figure 29. The compensation zero (fCZ) introduces phase boost, while the high-frequency compensation pole (fCP) attenuates the switching ripple. By averaging the diode current during the half line cycle, the low-frequency behavior of the voltage controlled current source of Figure 26 is obtained as: I DOUT,AVE = K SAW ⋅ 2VLINE 2 VLINE ⋅ [ A] 4VOUT L (35) The transfer function of the compensation network is obtained as: where: L is the boost inductance; VOUT is the output voltage; and KSAW is the internal gain of sawtooth generator (that of FL7930B is 8.496×10-6). ∧ v COMP ∧ v OUT = 2 π fI s 1+ ⋅ 1+ s 2 π f CZ s 2 π f CP (37) Then the low-frequency, small-signal, control-to-output transfer function is obtained as: © 2011 Fairchild Semiconductor Corporation Rev. 1.0.0 • 4/20/11 www.fairchildsemi.com 13 AN-9738 APPLICATION NOTE fI = 2.5 115 µmho ⋅ VOUT 2 π ⋅ CCOMP, LF + CCOMP, HF ( where fCZ = fCP = Typically, high RFB1 is used to reduce power consumption and CFB can be added to raise the noise immunity. The maximum CFB currently used is several nano farads. Adding a capacitor at the feedback loop introduces a pole as: ) 1 2 π ⋅ RCOMP ⋅ CCOMP, LF 1 2 π ⋅ (RFB1 // RFB2 ) ⋅ CFB 1 ≅ [ Hz] 2 π ⋅ RFB2 ⋅ CFB 1 f FP = CCOMP, LF ⋅ CCOMP, HF 2 π ⋅ RCOMP ⋅ CCOMP, LF + CCOMP, HF If CCOMP,LF is much larger than CCOMP,HF, fI and fCP can be simplified as: fI ≅ 2.5 f CP ≅ where (R FB1 // R FB 2 ) = R FB1 ⋅ R FB 2 R FB1 + R FB 2 . 115 µmho ⋅ [ Hz ] VOUT 2 π ⋅ CCOMP, LF 1 [ Hz ] 2 π ⋅ RCOMP ⋅ CCOMP, HF (40) Though RFB1 is high, pole frequency made by the synthesized total resistance and several nano farads is several kilo hertz and rarely affects control-loop response (38) The procedure to design the feedback loop is: a. G M = 115 µmho Determine the crossover frequency (fC) around 1/10 ~ 1/5 of line frequency. Since the control-to-output transfer function of the power stage has -20dB/dec slope and -90o phase at the crossover frequency; it is required to place the zero of the compensation network (fCZ) around the crossover frequency so 45° phase margin is obtained. The capacitor CCOMP,LF is determined as: CCOMP, LF ≅ KSAW (VLINE)2 2.5 ⋅115 µ mho 2 ⋅ VOUT2 ⋅ L ⋅ COUT (2 π f C )2 [f] (41) To place the compensation zero at the crossover frequency, the compensation resistor is obtained as: RCOMP = b. 1 [ Ω] 2 π ⋅ f C ⋅ CCOMP,LF Place this compensator high-frequency pole (fCP) at least a decade higher than fC to ensure that it does not interfere with the phase margin of the voltage regulation loop at its crossover frequency. It should also be sufficiently lower than the switching frequency of the converter for noise to be effectively attenuated. The capacitor CCOMP,HF is determined as: CCOMP,HF = Figure 29. Compensation Network (42) 1 [ Ω] 2 π ⋅ f CP ⋅ RCOMP (43) The feedback resistor is chosen to scale down the output voltage to meet the internal reference voltage: RFB1 ⋅ VOUT = 2.5 V RFB1 + RFB2 © 2011 Fairchild Semiconductor Corporation Rev. 1.0.0 • 4/20/11 (39) www.fairchildsemi.com 14 AN-9738 APPLICATION NOTE [STEP-9] Line Filter Capacitor Selection (Design Example) If RFB1 is 11.7MΩ, then RFB2 is: RFB2 = It is typical to use small bypass capacitors across the bridge rectifier output stage to filter the switching current ripple, as shown in Figure 30. Since the impedance of the line filter inductor at line frequency is negligible compared to the impedance of the capacitors, the line frequency behavior of the line filter stage can be modeled, as shown in Figure 30. Even though the bypass capacitors absorb switching ripple current, they also generate circulating capacitor current, which leads the line voltage by 90o, as shown in Figure 31. The circulating current through the capacitor is added to the load current and generates displacement between line voltage and current. 2.5V 2.5 RFB1 = 11.7 × 106 = 68kΩ VOUT − 2.5V 430 − 2.5 Choosing the crossover frequency (control bandwidth) at 15Hz, CCOMP,LF is obtained as: K SAW (V LINE ) 2.5 ⋅ 115 µ mho 2 C COMP , LF ≅ 2 ⋅ VOUT ⋅ L ⋅ C OUT (2π f C ) 2 2 8.496 × 10 −6 (230 ) 2.5 ⋅115 × 10 − 6 = 823 nF 2 2 ⋅ 430 2 ⋅199 × 10 − 6 ⋅ 240 × 10 −6 (2π 15 ) 2 = Actual CCOMP,LF is determined as 1000nF since it is the closest value among the off-the-shelf capacitors. RCOMP is obtained as: RCOMP = The displacement angle is given by: 2 η⋅ (V LINE) ⋅ 2 π ⋅ f LINE ⋅ CEQ θ = tan−1 POUT 1 1 = = 12.8kΩ 2π ⋅ f C ⋅ CCOMP,LF 2π ⋅15 ⋅ 823×10−9 Selecting the high-frequency pole as 150Hz, CCOMP,HF is obtained as: CCOMP,HF = (44) where CEQ is the equivalent capacitance that appears across the AC line (CEQ=CF1+CF2+CHF). 1 1 = = 82nF 2π ⋅ f CP ⋅ RCOMP 2π ⋅150⋅12.8 ×103 The resultant displacement factor is: DF = cos(θ) These components result in a control loop with a bandwidth of 19.5Hz and phase margin of 45.6°. The actual bandwidth is a little larger than the asymptotic design. (45) Since the displacement factor is related to power factor, the capacitors in the line filter stage should be selected carefully. With a given minimum displacement factor (DFMIN) at full-load condition, the allowable effective input capacitance is obtained as: CEA < POUT η ⋅ (VLINE )2 ⋅ 2 π ⋅ f LINE ( ) ⋅ tan cos−1 (DFMN ) [ F ] (46) One way to determine if the input capacitor is too high or PFC control routine has problems is to check Power Factor (PF) and Total Harmonic Distortion (THD). PF is the degree to which input energy is effectively transferred to the load by the multiplication of displacement factor and THD that is input current shape deterioration ratio. PFC control loop rarely has no relation to displacement factor and input capacitor rarely has no impact on the input current shape. If PF is low (high is preferable), but THD is quite good (low is preferable), it can be concluded that input capacitance is too high and PFC controller is fine. (Design Example) Assuming the minimum displacement factor at full load is 0.98, the equivalent input capacitance is obtained as: CEA < < POUT η ⋅ (VLINE ) ⋅ 2 π ⋅ f LINE 2 ( ( ) ⋅ tan cos−1 (DFMN ) ) 200 ⋅ tan cos −1 (0.98 ) = 1.6 µF 2 0.9 ⋅ (277 ) ⋅ 2 π ⋅ 50 Thus, the sum of the capacitors on the input side should be smaller than 2.0µF. © 2011 Fairchild Semiconductor Corporation Rev. 1.0.0 • 4/20/11 www.fairchildsemi.com 15 AN-9738 APPLICATION NOTE [STEP-10] Define System Specifications Estimated Efficiency (Eff): The power conversion efficiency must be estimated to calculate the maximum input power with a given maximum output power. If no reference data is available, use Eff = 0.88~0.92 for lowvoltage output applications and Eff = 0.92~0.96 for highvoltage output applications. With the estimated efficiency, the maximum input power is given as: Pin = Po (47) E ff Input Voltage Range (Vinmin and Vinmax): The maximum input voltage would be the nominal PFC output voltage as: Vin max = VO . PFC (48) Even though the input voltage is regulated as constant by PFC pre-regulator, it drops during the hold-up time. The minimum input voltage considering the hold-up time requirement is given as: Figure 30. Equivalent Circuit of Line Filter Stage Vin min = VO.PFC 2 − 2 PinTHU CDL (49) where VO.PFC is the nominal PFC output voltage, THU is a hold-up time, and CDL is the DC link bulk capacitor. (Design Example) Assuming the efficiency is 92%, Pin = Vin min Po 150 = = 163W E ff 0.92 = VO. PFC − = 4302 − 2 2 PinTHU C DL 2 ⋅ 163 ⋅ 30 × 10−3 = 379V 240 × 10−6 [STEP-11] Determine Maximum and Minimum Voltage Gains of the Resonant Network As discussed in the previous section, it is typical to operate the LLC resonant converter around the resonant frequency (fo) to minimize switching frequency variation. Since the input of the LLC resonant converter is supplied from PFC output voltage, the converter should be designed to operate at fo for the nominal PFC output voltage. θ Figure 31. Line Current Displacement 3.2 LLC SRC Section In this section, a design procedure is presented using the schematic in Figure 1 as a reference. An integrated transformer with center tap, secondary side is used and input is supplied from Power Factor Correction (PFC) preregulator. A DC-DC converter with 150W/103V output is selected as a design example. The design specifications are: As observed in Equation (9), the gain at fo is a function of m (m=Lp/Lr). The gain at fo is determined by choosing that value of m. While a higher peak gain can be obtained with a small m value, too small m value results in poor coupling of the transformer and deteriorates the efficiency. It is typical to set m to be 3~7, which results in a voltage gain of 1.1~1.2 at the resonant frequency (fo). Nominal input voltage: 400VDC (output of PFC stage) Output: 103V/1.46A (150W) Hold-up time requirement: 30ms (50Hz line freq.) DC link capacitor of PFC output: 240µF © 2011 Fairchild Semiconductor Corporation Rev. 1.0.0 • 4/20/11 With the chosen m value, the voltage gain for the nominal PFC output voltage is obtained as: www.fairchildsemi.com 16 AN-9738 APPLICATION NOTE m m − 1 @f=fo M min = Rac = The maximum voltage gain is given as: M (51) With the m value chosen in STEP-11, read the proper Q value from the peak gain curves in Figure 33 that allows enough peak gain. Considering the load transient and stable zero-voltage-switching (ZVS) operation, 10~20% margin should be introduced on the maximum gain when determining the peak gain. Once the Q value is determined, the resonant parameters are obtained as: (Design Example) The ratio (m) between Lp and Lr is chosen as 5. The minimum and maximum gains are obtained as: M max = V RO Vin max V in = m = m −1 V in min m min = Gain (M) 400 ⋅ 1.12 = 1.31 341 Peak Gain (Available Maximum Gain) 1.31 Mmax M 5 = 1.12 5 −1 2 max Cr = 1 2π Q ⋅ f o ⋅ Rac (54) Lr = 1 (2π f o )2 Cr (55) L p = m ⋅ Lr (56) for VINmin 1.12 min M = 8n 2 (Vo + VF ) 2 8 ⋅1.932 ⋅103.9 2 = = 217 Ω π2 Po π 2 ⋅150 [STEP-14] Design the Resonant Network V max = in min M min Vin M min = (53) (Design Example) which would be the minimum gain because the nominal PFC output voltage is the maximum input voltage (Vinmax). max 8n2 Vo 2 π 2 Po Rac = (50) (Design Example) As calculated in STEP-11, the maximum voltage gain (M max) for the minimum input voltage (Vinmin) is 1.31. With 15% margin, a peak gain of 1.51 is required. m has been chosen as 5 in STEP-11 and Q is obtained as 0.38 from the peak gain curves in Figure 33. By selecting the resonant frequency as 100kHz, the resonant components are determined as: for VINmax ( VO.PFC ) m = 1.12 m −1 fo fs Figure 32. Maximum Gain / Minimum Gain [STEP-12] Determine the Transformer Turns Ratio (n=Np/Ns) Cr = 1 1 = = 19 nF 2 πQ ⋅ f o ⋅ Rac 2 π ⋅ 0.38 ⋅100 ×10 3 ⋅ 217 Lr = = = 133 µH ( 2 πf o ) 2 C r ( 2 π ×100 ×10 3 ) 2 ⋅19 ×10 −9 1 1 L p = m ⋅ Lr = 665 µH With the minimum gain (Mmin) obtained in STEP-11, the transformer turns ratio is given as: n= Np Ns = Vin max ⋅ M min 2(Vo + VF ) (52) where VF is the secondary-side rectifier diode voltage drop. (Design Example) assuming VF is 0.9V: max Np Vin 430 n= = ⋅ M min = ⋅ 1.12 = 2.06 N s 2(VO + VF ) 2(103 + 0.9) [STEP-13] Calculate Equivalent Load Resistance Figure 33. Resonant Network Design Using the Peak Gain (Attainable Maximum Gain) Curve for m=5 With the transformer turns ratio obtained from Equation (52), the equivalent load resistance is obtained as: © 2011 Fairchild Semiconductor Corporation Rev. 1.0.0 • 4/20/11 www.fairchildsemi.com 17 AN-9738 APPLICATION NOTE [STEP-15] Design the Transformer The worst case for the transformer design is the minimum switching frequency condition, which occurs at the minimum input voltage and full-load condition. To obtain the minimum switching frequency, plot the gain curve using gain Equation (8) and read the minimum switching frequency. The minimum number of turns for the transformer primary-side is obtained as: N p min = n(Vo + VF ) 2 f s ⋅ M V ⋅ ∆B ⋅ Ae (57) min where Ae is the cross-sectional area of the transformer core in m2 and ∆B is the maximum flux density swing in Tesla, as shown in Figure 34. If there is no reference data, use ∆B =0.3~0.4 T. n (Vo+VF)/MV Figure 35. Gain Curve VRI 1/(2fs) [STEP-16] Transformer Construction Parameters Lp and Lr of the transformer were determined in STEP-14. Lp and Lr can be measured in the primary side with the secondary-side winding open circuited and short circuited, respectively. Since LLC converter design requires a relatively large Lr, a sectional bobbin is typically used, as shown in Figure 36, to obtain the desired Lr value. For a sectional bobbin, the number of turns and winding configuration are the major factors determining the value of Lr, while the gap length of the core does not affect Lr much. Lp can be controlled by adjusting the gap length. Table 1. shows measured Lp and Lr values with different gap lengths. A gap length of 0.05mm obtains values for Lp and Lr closest to the designed parameters. -n (Vo+VF)/MV ∆B B Figure 34. Flux Density Swing Choose the proper number of turns for the secondary side that results in primary-side turns larger than Npmin as: N p = n ⋅ N s > N p min (58) Np 2 N s2 (Design Example) EER3542 core (Ae=107mm ) is selected for the transformer. From the gain curve of Figure 35, the minimum switching frequency is obtained as 82KHz. The minimum primary-side turns of the transformer is given as: n(Vo + VF ) min Np = min 2 f s ∆B ⋅1.11⋅ Ae 1.93 ×103.9 = = 26 turns 2 × 82 ×103 ⋅ 0.4 ⋅1.11⋅107 ×10 −6 N s1 Figure 36. Sectional Bobbin Choose Ns so that the resultant Np is larger than Npmin: N p = n ⋅ N s = 1.93 × 14 = 27 < N p min Table 1. Measured Lp and Lr with Different Gap Lengths N p = n ⋅ N s = 1.93 × 15 = 29 < N p min N p = n ⋅ N s = 1.93 × 16 = 31 > N p min N p = n ⋅ N s = 1.93 × 17 = 33 > N p min N p = n ⋅ N s = 1.93 × 18 = 35 > N p min N p = n ⋅ N s = 1.93 × 19 = 37 > N p min © 2011 Fairchild Semiconductor Corporation Rev. 1.0.0 • 4/20/11 Gap Length Lp Lr 0.0mm 2,295µH 123µH 0.05mm 943µH 122µH 0.10mm 630µH 118µH 0.15mm 488µH 117µH 0.20mm 419µH 115µH 0.25mm 366µH 114µH www.fairchildsemi.com 18 AN-9738 APPLICATION NOTE The nominal voltage of the resonant capacitor in normal operation is given as: (Design Example) Final Resonant Network Design VCr nom ≅ Even though the integrated transformer approach in LLC resonant converter design can implement the magnetic components in a single core and save one magnetic component, the value of Lr is not easy to control in real transformer design. Resonant network design sometimes requires iteration with a resultant Lr value after the transformer is built. The resonant capacitor value is also changed since it should be selected among off-the-shelf capacitors. The final resonant network design is summarized in Table 2. and the new gain curves are shown in Figure 37. Initial Design Final Design Lp 665µH 691µH Lr 133H 122µH (60) However, the resonant capacitor voltage increases higher than this at overload condition or load transient. Actual capacitor selection should be based on the Over-Current Protection (OCP) trip point. With the OCP current, IOCP, the maximum resonant capacitor voltage is obtained as: VCr nom ≅ Table 2. Final Resonant Network Design Parameters Parameters Vin max 2 ⋅ I Cr RMS + 2 2 ⋅ π ⋅ f o ⋅ Cr Vin max I OCP + 2 2 ⋅ π ⋅ f o ⋅ Cr (61) (Design Example) I Cr RMS ≅ 1 E ff [ πI O 2 2n ]2 + [ n(Vo + VF ) 4 2 f o M v ( L p − Lr ) ]2 Cr 19nF 22nF fo 100kHz 96kHz m 5 5 Q 0.38 0.3 =1.12A M at fo 1.12 1.12 Minimum Frequency 75kHz 74.4kHz The peak current in the primary side in normal operation is: peak rms I Cr = 2 ⋅ I Cr = 1.58 A = 1 1.93(103 + 0.9) π ⋅1.4 2 [ ] +[ ]2 3 6 − 0.92 2 2 ⋅1.93 4 2 ⋅ 96 ×10 ⋅1.12 ⋅ 500 × 10 OCP level is set to 2.5A with 50% margin on ICrpeak: RMS VCr nom ≅ = 430 2 ⋅1.18 + = 340V 2 2 ⋅ π ⋅ 96 ×103 ⋅ 22 ×10 −9 VCr max ≅ = 2 ⋅ I Cr Vin max + 2 2 ⋅ π ⋅ f o ⋅ Cr Vin max I OCP + 2 2 ⋅ π ⋅ f o ⋅ Cr 430 2.5 + = 403.3V 2 2 ⋅ π ⋅ 96 ×103 ⋅ 22 ×10−9 A 630V rated low-ESR film capacitor is selected for the resonant capacitor. [STEP-18] Rectifier Network Design When the center tap winding is used in the transformer secondary side, the diode voltage stress is twice of the output voltage expressed as: Figure 37. Gain Curve of the Final Resonant Network Design [STEP-17] Select the Resonant Capacitor VD = 2(Vo + VF ) When choosing the resonant capacitor, the current rating should be considered because a considerable amount of current flows through the capacitor. The RMS current through the resonant capacitor is given as: I Cr RMS 1 ≅ E ff π Io n(Vo + VF ) [ ] +[ ]2 2 2n 4 2 f o MV ( Lp − Lr ) 2 © 2011 Fairchild Semiconductor Corporation Rev. 1.0.0 • 4/20/11 (62) The RMS value of the current flowing through each rectifier diode is given as: I D RMS = (59) π 4 Io (63) www.fairchildsemi.com 19 AN-9738 APPLICATION NOTE Meanwhile, the ripple current flowing through output capacitor is given as: I Co RMS = ( π Io 2 2 )2 − I o 2 = π2 −8 8 Io (64) The voltage ripple of the output capacitor is: ∆Vo = π 2 I o ⋅ RC (65) where RC is the effective series resistance (ESR) of the output capacitor and the power dissipation is the output capacitor is: PLoss.Co = ( I Co RMS ) 2 ⋅ RC (66) (Design Example) The voltage stress and current stress of the rectifier diode are: Figure 38. Typical Circuit Configuration for RT Pin Soft-start prevents excessive inrush current and overshoot of output voltage during startup, increases the voltage gain of the resonant converter progressively. Since the voltage gain of the resonant converter is reversely proportional to the switching frequency, soft-start is implemented by sweeping down the switching frequency from an initial high frequency (f ISS) until the output voltage is established, as illustrated in Figure 39. The soft-start circuit is made by connecting RC series network on the RT pin as shown in Figure 38. FAN7621S also has an internal soft-start for 3ms to reduce the current overshoot during the initial cycles, which adds 40KHz to the initial frequency of the external soft-start circuit, as shown in Figure 39. The actual initial frequency of the soft-start is given as: VD = 2(Vo + VF ) = 2(103 + 0.9) = 207.8V π RMS ID = I o = 1.14 A 4 The 600V/8A ultra-fast recovery diode is selected for the rectifier, considering the voltage overshoot caused by the stray inductance. The RMS current of the output capacitor is: πI o 2 π 2 −8 RMS 2 I Co = ( 2 2 ) − Io = 8 I o = 0.584 A When two electrolytic capacitors with ESR of 100mΩ are used in parallel, the output voltage ripple is given as: π π 0.1 ∆Vo = I o ⋅ RC = ⋅1.46 ⋅ ( ) = 0.114V 2 2 2 The loss in electrolytic capacitors is: RMS PLoss,Co = ( I Co ) 2 ⋅ RC = 0.5842 ⋅ 0.05 = 0.017W f ISS = ( 5.2k Ω 5.2k Ω + ) × 100 + 40 (kHz ) Rmin RSS It is typical to set the initial frequency of soft-start (f 2~3 times of the resonant frequency (fo). t SS = 3 ~ 4 ( R SS • C SS ) Figure 38 shows the typical circuit configuration for the RT pin of FAN7621S, where the opto-coupler transistor is connected to the RT pin to control the switching frequency. The minimum switching frequency occurs when the optocoupler transistor is fully tuned off, which is given as: 5.2k Ω × 100(kHz ) Rmin ISS ) at The soft-start time is determined by the RC time constant: [STEP-19] Control Circuit Configuration f min = (69) (70) (67) Assuming the saturation voltage of opto-coupler transistor is 0.2V, the maximum switching frequency is determined as: f max = ( 5.2k Ω 4.68k Ω + ) × 100(kHz ) Rmin Rmax (68) Figure 39. Frequency Sweep of the Soft-Start © 2011 Fairchild Semiconductor Corporation Rev. 1.0.0 • 4/20/11 www.fairchildsemi.com 20 AN-9738 APPLICATION NOTE (Design Example) The minimum frequency is 75kHz in STEP-15. Rmin is determined as: Rmin = (Design Example) Since the OCP level is determined as 2.5A in STEP-17 and the OCP threshold voltage is -0.6V, a sensing resistor of 0.24Ω is used. The RC time constant is set to 100ns (1/100 of switching period) with 1kΩ resistor and 100pF capacitor. 100 KHz × 5.2 KΩ = 6.93KΩ f min Considering the output voltage overshoot during transient (10%) and the controllability of the feedback loop, the maximum frequency is set as 140kHz. Rmax is determined as: Rmax = = [STEP-21] Voltage and Current Feedback Power supplies for LED lighting must be controlled by Constant Current (CC) Mode as well as a Constant Voltage (CV) Mode. Because the forward-voltage drop of LED varies with the junction temperature and the current also increases greatly consequently, devices can be damaged. 4.68KΩ f o × 1.40 5.2 KΩ − ( ) 100 KHz Rmin 4.68 KΩ = 7.88 KΩ 96 KHz × 1.40 5.2 KΩ ( − ) 100 KHz 6.93KΩ Figure 42 shows an example of a CC and CV Mode feedback circuit for single-output LED power supply. During normal operation, CC Mode is dominant and the CV control circuit does not activate as long as the feedback voltage is lower than reference voltage, which means that CV control circuit only acts as OVP for abnormal modes. Setting the initial frequency of soft-start as 250kHz (2.5 times of the resonant frequency), the soft-start resistor RSS is given as: R SS = = 5 .2 KΩ f ISS − 40 KHz 5.2 KΩ ( − ) 100 KHz Rmin (Design Example) The output voltage (VO) is 103V in design target. VO is determined as: 5.2 KΩ = 3.85 KΩ 250 KHz − 40 KHz 5.2 KΩ ( − ) 100 KHz 6.93KΩ Vo = 2.5(1 + R FU ) R FL Set the upper-side feedback resistance (RFU) as 330KΩ. RFL is determined as: [STEP-20] Current Sensing and Protection FAN7621S senses low-side MOSFET drain current as a negative voltage, as shown in Figure 40. and Figure 41. Half-wave sensing allows low power dissipation in the sensing resistor, while full-wave sensing has less switching noise in the sensing signal. Typically, an RC low-pass filter is used to filter out the switching noise in the sensing signal. The RC time constant of the low-pass filter should be 1/100~1/20 of the switching period. RFL = 2.5 × RFU 2.5 × 330 KΩ = = 8 .2 K Ω (Vo − 2.5) (103 − 2.5) The output current (ILED) is 1.46A in design target. Assuming the sensing resistor (RSENSE) of 0.1Ω and feedback resistor (R202) of 47KΩ are used, the input resistor R203 is determined as: VSENSE × R 202 ( RSENSE × I LED ) × R202 = 0.36 0.36 (0.1×1.46) × 47KΩ = = 19KΩ 0.36 R203 = Figure 40. Half-Wave Sensing Figure 42. Example of CC and CV Feedback Circuit Figure 41. Full-Wave Sensing © 2011 Fairchild Semiconductor Corporation Rev. 1.0.0 • 4/20/11 www.fairchildsemi.com 21 DS3 LL4148 7 OUT 8 4 LM358/ON 8 - DS2 LL4148 + V+ U6A V- + V+ U6B 2 47k CS6 33uF/25V 3 CS25 RS56 220nF 47k RS35 13k VLED ISENSE VAUX VFB RS40 100k RS41 4.7k RS55 120k VAUX 22 RS49 1k RS42 RS44 N.C R46 N.C 0.1 CN1 CON3 2 1 CP9 0.1uF 68K/2W 24K CP14 1uF 5.2K RP27 FS101 F1 RP12 ZNR1 CP10 1uF RS1M DP3 6 3 5 8 3 9 5 7 4 6 1M RS3 1M RS2 1M RS1 GND COMP ZCD VCC FAN7930B CS3 470nF OVP INV CS OUT 1 8 PFC 2 10 U1 3 1 2 1 4 7 LF1 10mH CP11 470pF 4 2 U3 MMBT2907A FG CS10 4.7nF 3 1 RP33 0.1/5W CS9 4.7nF RP30 10K DP1 LF2 10mH RP29 75K RP20 4.3M 4 2 RP31 75K RP21 4.3M CP15 1nF CS11 220nF CP16 1nF 4 - CP4 CP5 CP8 120uF/450V120uF/450V120uF/450V RP14 4.3M 4.3M 4.3M RP13 4.3M RP4 RP3 FFPF08H60S M1 FCPF11N65 RP18 4.7 CS4 470nF DP4 RP16 LL4148 27 EER3019N TM1 RP6 0 1 RP5 CP21 33uF/25V VDC 1 2 1 V- 3 4 LM358/ON + 2 BD1 PC1B PS2561 CP6 33uF/25V DP2 RS1M 0 2k 0.68uF/630V CP20 3 4 VDC 0 8.2k RP24 0 CP18 12n ZDP1 MMSZ5248 Q1 MMBT2222A RP23 RP10 33k RP7 0 0 1k RP37 10uF/16V CP17 2.7k RP25 CP2 33uF/25V 0 CP19 100p 0 CP7 680p RP38A 0.2 CP22 0 6.8uF/50V RP11 10k 9.CS 6.A/R 8.RT RP8 10k 0 ZDP2 MMSZ5235 Q3 MMBT2222A Q2 MMBT2907A RP1 390k 12.LVcc 220nF 0 10.SG © 2011 Fairchild Semiconductor Corporation Rev. 1.0.0 • 4/20/11 CS19 FAN7621S 14.LO 2.CTR 3.HO 1.HVcc 16.PG RP35 3 DP7 RP34 LL4148 10 RP28 3 DP6 RP22 LL4148 10 C1 100nF U5 MMBT2907A RP36 10k RP32 10k U4 MMBT2907A M3 FDPF7N60NZ M2 FDPF7N60NZ 0 C2 3.3n 9 8 11 10 12 6 7 5 0 FAN7621S U2 14 3 13 15 2 4 DP5 RS1M 16 1 47k RP17 10 TM2 EER3543 RP15 RP9 1M RP2 1M CP1 22nF/630V D2 CS7 47uF CS6 47uF CS5 47uF CP13 33uF/25V RP26 33k DS1 RS1M RP19 10 FFPF20UA60DN 0 D1 FFPF20UA60DN CS8 47uF CS2 47uF ZDP3 MMSZ5248 MMBT2222A Q4 CS1 47uF CON2 J2 2 1 2 1 PC1A PS2561 VLED ISENSE VAUX VFB FB 1 2 3 4 5 6 7 8 9 10 11 12 CON12 J1 AN-9738 APPLICATION NOTE 4. Schematic of the Evaluation Board RS33 1 2 3 4 5 6 7 8 9 10 11 12 J6 U7 TL431 CON12 RS57 330k OUT 6 5 RS59 8.2k Figure 43. Evaluation Board Schematic www.fairchildsemi.com AN-9738 APPLICATION NOTE Dimensions: 240 (W) × 80 (H) [mm] Figure 44. Top View of Evaluation Board Figure 45. Bottom View of Evaluation Board 5. Bill of Materials Item No. Qty Reference Part Reference Description (Manufacturer) 1 1 BD1 600V/8A Bridge Diode (Fairchild Semiconductor) 2 1 CN1 3PIN Connector 3 1 CP1 630V22nF Film Capacitor 4 5 CP2,CP6,CP13,CP21 33µF/25V SMD Tantal Capacitor 5 3 CP4,CP5,CP8 120µF/450V Electrolytic Capacitor 6 1 CP7 680p/25V SMD Capacitor 2012 7 1 CP9 0.1µF/25V SMD Capacitor 2012 8 2 CP10,CP14 1µF/25V SMD Capacitor 2012 9 1 CP11 470pF/25V SMD Capacitor 2012 10 2 CP15,CP16 33µF/25V SMD Capacitor 2012 11 1 CP17 10µF/16V Electrolytic Capacitor 12 1 CP18 12nF/25V SMD Capacitor 2012 13 1 CP19 100pF/26V SMD Capacitor 2012 14 1 CP20 0.68µF/630V Film Capacitor 15 1 CP22 100p/25V SMD Capacitor 2012 16 6 CS1,CS2,CS5,CS6,CS7,CS8 47µF/200V Electrolytic Capacitor 17 2 CS3,CS4 470nF/400V Film Capacitor CS19,CS25 220nF/25V SMD Capacitor 2012 © 2011 Fairchild Semiconductor Corporation Rev. 1.0.0 • 4/20/11 www.fairchildsemi.com 23 AN-9738 APPLICATION NOTE Item No. Qty Reference Part Reference Description (Manufacturer) 18 2 CS9,CS10 220p/400V Ceramic Capacitor 19 3 CS11 220nF/400V Film Capacitor 20 1 C1 100nF/50V SMD Capacitor 3216 21 1 C2 4.7µF/400V Ceramic Capacitor 22 1 DP1 600V/8A Hyperfast2 Diode 23 4 DS1,DP2,DP3,DP5 1000V/1A Fast Rectifier Diode 24 5 DS2,DS3,DP4,DP6,DP7 100V/200mA SMD General Purpose Diode 25 2 D1,D2 600V/20A Ultra-Fast Diode 26 1 F1 FS101 Fuse 27 2 J1,J6 12PIN Connector 28 1 J2 2PIN Connector 29 2 LF1,LF2 10mH/2.3A Common-Mode Filter 30 1 M1 650V/11A MOSFET 31 2 M2,M3 600V/7A MOSFET 32 1 PC1 Photo Copuler Photo Coupler 33 3 Q1,Q3,Q4 40V/1A SMD NPN Transitor 34 4 Q2,U3,U4,U5 40V/200mA SMD PNP Transitor 35 1 RP1 390kΩ/25V SMD Resistor 2012 36 5 RS1,RS2,RP2,RS3,RP9 1M/Ω50V SMD Resistor 3216 37 6 RP3,RP4,RP13,RP14,RP20,RP21 4.3MΩ/50V SMD Resistor 3216 38 1 RP5 68KΩ/2W Watt Resistor 39 2 RP6,RP7 0Ω/50V SMD Resistor 3216 40 5 RP8,RP11 10kΩ/25V SMD Resistor 2012 RP30,RP32,RP36 10kΩ/50V SMD Resistor 3216 41 2 RP10,RP26 33kΩ/25V SMD Resistor 2012 42 1 RP12 24kΩ/50V SMD Resistor 3216 43 3 RP15,RS33,RS56 47kΩ/25V SMD Resistor 2012 44 1 RP16 2.7Ω/25V SMD Resistor 2012 45 4 RP17,RP19 10Ω/50V SMD Resistor 3216 RP22,RP34 10Ω/25V SMD Resistor 2012 46 1 RP18 4.7Ω/25V SMD Resistor 2012 47 1 RP23 10kΩ/25V SMD Resistor 2012 48 2 RP24,RS59 8.2kΩ/25V SMD Resistor 2012 49 1 RP25 1.8KΩ/25V SMD Resistor 2012 50 1 RP27 5.1kΩ/25V SMD Resistor 2012 51 2 RP28,RP35 3Ω/25V SMD Resistor 2012 52 2 RP29,RP31 75kΩ/50V SMD Resistor 3216 53 1 RP33 0.1Ω/5W Watt Resistor 54 2 RP37,RS49 1kΩ/50V SMD Resistor 3216 55 1 RP38A 0.1Ω/1W Watt Resistor 56 1 RS35 13kΩ/25V SMD Resistor 2012 57 1 RS40 100kΩ/25V SMD Resistor 2012 58 1 RS41 4.7kΩ/25V SMD Resistor 2013 59 1 RS42 0.1Ω/2W Watt Resistor © 2011 Fairchild Semiconductor Corporation Rev. 1.0.0 • 4/20/11 www.fairchildsemi.com 24 AN-9738 APPLICATION NOTE Item No. Qty Reference Part Reference Description (Manufacturer) 60 2 RS44,R46 NC NC 61 1 RS55 120kΩ/25V SMD Resistor 2012 62 1 RS57 330kΩ/25V SMD Resistor 2012 63 1 TM1 EER3019N-10 PFC Inductor 64 1 TM2 EER3543-16 LLC Transformer 65 1 U1 FL7930B CRM PFC Controller 66 1 U2 FAN7621S LLC Resonant Controller 67 1 U6 LM358 OP-AMP 68 1 U7 KA431 Shunt Regulator 69 2 ZDP1,ZDP3 MMSZ5248 Zener Diode 18V 70 1 ZDP2 MMSZ5235 Zener Diode 6.8V 71 1 ZNR1 10D471 Varistor 470V Related Datasheets FL7930B — Single-Stage Flyback and Boundary Mode PFC Controller for Lighting FAN7621S — Controller for Resonant Half Bridge FDPF17N60NT — 600V N-Channel MOSFET, UniFET™2 FDPF7N60NZ — 600V N-Channel MOSFET, UniFET™2 Author WonSeok, Kang Power Conversion Korea Senior System and Application Engineer [email protected] DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION, OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, or (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in significant injury to the user. © 2011 Fairchild Semiconductor Corporation Rev. 1.0.0 • 4/20/11 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com 25

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