ETC PI74ALVCH16825

PI74ALVCH32374
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32-Bit Edge Triggered D-Type Flip-Flop
with 3-State Outputs
Product Features
Product Description
• PI74ALVCH32374 is designed for low voltage operation
• VCC = 2.3V to 3.6V
• Typical VOLP (Output Ground Bounce)
< 0.8V at VCC = 3.3V, TA = 25°C
• Typical VOHV (Output VOH Undershoot)
> 2.0V at VCC = 3.3V, TA = 25°C
• Bus Hold retains last active bus state during 3-State
eliminating the need for external pullup resistors
• Industrial operation at –40°C to +85°C
• Packages available:
– 96-ball, 13.5mm x 5.5mm x 1.4mm low profile fine
pitch ball grid array, LFBGA (NB)
Pericom Semiconductor’s PI74ALVCH series of logic circuits are
produced using the Company’s advanced 0.5 micron CMOS
technology, achieving industry leading speed.
This 32-bit edge-triggered D-type flip-flop is designed for 2.3V to
3.6V VCC operation.
The PI74ALVCH32374 is particularly suitable for implementing
buffer registers, I/O ports, bidirectional bus drivers, and working
registers. This device can be used as four 8-bit flip-flops or two
16-bit flip-flops or one 32-Bit flip-flop. On the positive transition of
the Clock (CLK) input, the Q outputs of the flip-flop take on the logic
levels set up at the data (D) inputs. OE can be used to place the eight
outputs in either a normal logic state (high or low logic levels) or a
high-impedance state. In that state, the outputs neither load nor
drive the bus lines significantly. The high-impedance state and the
increased drive provide the capability to drive bus lines without
need for interface or pullup components. OE does not affect internal
operations of the flip-flop. Old data can be retained or new data can
be entered while the outputs are in the high-impedance state.
To ensure the high-impedance state during power up or power
down, OE should be tied to VCC through a pullup resistor; the
minimum value of the resistor is determined by the current-sinking
capability of the driver.
Active bus-hold circuitry is provided to hold unused or floating
data inputs at a valid logic level.
Logic Block Diagram
1OE
1CLK
A3
2OE
A4
2CLK
H3
H4
C1
C1
A2
1D1
A5
E2
1Q1
2D1
1D
E5
To Seven Other Channels
To Seven Other Channels
3OE
3CLK
J3
4OE
J4
4CLK
T3
T4
C1
C1
J2
3D1
J5
1D
2Q1
1D
N2
3Q1
4D1
N5
4Q1
1D
To Seven Other Channels
To Seven Other Channels
1
PS8439
10/14/99
PI74ALVCH32374
32-Bit Edge Triggered D-Type Flip-Flop
with 3-State Outputs
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Product Pin Description
Pin Name
OE
CLK
Dx
Qx
GND
VCC
Truth Table(1)
Description
Output Enable Input (Active LOW)
Clock Input (Active HIGH)
Data Inputs
3-State Outputs
Ground
Power
Inputs
Outputs
OE
CLK
D
Q
L
­
H
H
L
­
L
L
L
H or L
X
Q0
H
X
X
Z
Notes:
1. H = High Signal Level
L = Low Signal Level
X = Irrelevant
Z = High Impedance
↑ = LOW to HIGH Transition
n = 1,2
NB Package (Top View)
6
5
4
3
2
1
A B C D E F G H J K L MN P R T
Terminal Assignments
6
1D2
1D4
1D6
1D8
2D2
2D4
2D6
2D7
3D2
3D4
3D6
3D8
4D2
4D4
4D6
4D7
5
1D1
1D3
1D5
1D7
2D1
2D3
2D5
2D8
3D1
3D3
3D5
3D7
4D1
4D3
4D5
4D8
4
1CLK
GND
V CC
GND
GND
V CC
GND
2CLK
3CLK
GND
V CC
GND
GND
V CC
GND
4CLK
3
1OE
GND
V CC
GND
GND
V CC
GND
2OE
3OE
GND
V CC
GND
GND
V CC
GND
4OE
2
1Q1
1Q3
1Q5
1Q7
2Q1
2Q3
2Q5
2Q8
3Q1
3Q3
3Q5
3Q7
4Q1
4Q3
4Q5
4Q8
1
1Q2
1Q4
1Q6
1Q8
2Q2
2Q4
2Q6
2Q7
3Q2
3Q4
3Q6
3Q8
4Q2
4Q4
4Q6
4Q7
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
2
PS8439
10/14/99
PI74ALVCH32374
32-Bit Edge Triggered D-Type Flip-Flop
with 3-State Outputs
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Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.)
Supply Voltage Range,VCC ............................................................... –0.5V to 4.6V
Input Voltage Range, VI: Except I/O ports (1) .............................. –0.5V to 4.6V
I/O ports (1,2) ........................... –0.5V to VCC + 0.5V
Output Voltage Range, VO (1,2) ............................................ –0.5V to VCC +0.5V
Input Clamp Current, IIK (VI <0) ........................................................ –50mA
Output Clamp Current, IOK (VO <0) .................................................. –50mA
Continuous Output Current, IO ................................................................... ±50mA
Continuous Current through each VCC or GND ............................... ±100mA
Package Thermal Impedance, θJA(3) ............................................................. 40ºC/W
Storage Temperature Range, TSTG ............................................... –65ºC to 150ºC
Note:
Stresses greater than those listed under MAXIMUM
RATINGS may cause permanent damage to the device.
This is a stress rating only and functional operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions
for extended periods may affect reliability.
Note:
1. The input negative voltage and output voltage ratings may be exceeded
if the input and output current ratings are observed.
2. This value is limited to 4.6V maximum.
3. The package thermal impedance is calculated in accordance with JESD 51.
Recommended Operating Conditions(1)
Parame te rs
D e s cription
VCC
Supply Voltage
VIH
Input HIGH Voltage
VIL
Input LO W Voltage
VIN
Input Voltage
0
VCC
VOUT
O utput Voltage
0
VCC
IOH
O utput
HIGH
Current
IOL
O utput
LO W
Current
Te s t Conditions
M in.
2.3
VCC = 2.3V to 2.7V
1.7
VCC = 2.7V to 3.6V
2.0
Typ.
M ax.
Units
3.6
V
VCC = 2.3V to 2.7V
0.7
VCC = 2.7V to 3.6V
0.8
VCC = 2.3V
–12
VCC = 2.7V
–12
VCC = 3.0V
–24
VCC = 2.3V
12
VCC = 2.7V
12
VCC = 3.0V
24
mA
∆t/∆V
Input Transition Rise or Fall Rate
0
10
ns/V
TA
O perating Free- Air Temperature
–40
85
°C
Note 1: All unused inputs must be held at VCC or GND to ensure proper device operation
3
PS8439
10/14/99
PI74ALVCH32374
32-Bit Edge Triggered D-Type Flip-Flop
with 3-State Outputs
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DC Electrical Characteristics (Over the Operating Range, TA = –40°C to +85°C, VCC = 3.3V ±10%)
Te s t Conditions (1)
Parame te rs D e s cription
VOH
VOL
IIN
IIN (HOLD)
O utput HIGH Voltage
O utput LO W Voltage
Input Current
Input Hold
Current
M in.
IOH = - 100µA, VCC = Min. to Max.
VCC- 0.2
VIH = 1.7V, IOH = - 6mA, VCC = 2.3V
2.0
VIH = 1.7V, IOH = - 12mA, VCC = 2.3V
1.7
VIH = 2.0V, IOH = - 12mA, VCC = 2.7V
2.2
VIH = 2.0V, IOH = - 12mA, VCC =3.0V
2.4
VIH = 2.0V, IOH = - 24mA, VCC =3.0V
2.0
Typ.(2)
M ax.
V
IOL = - 100µA, VIL = Min. to Max.
0.2
VIL = 0.7V, IOL = 6mA, VCC = 2.3V
0.4
VIL = 0.7V, IOL = 12mA, VCC = 2.3V
0.7
VIL = 0.8V, IOL = 12mA, VCC = 2.7V
0.4
VIL = 0.8V, IOL = 24mA, VCC =3.0V
0.55
VIN = VCC or GND, VCC = 3.6V
±5
VIN = 0.7V, VCC = 2.3V
45
VIN = 1.7V, VCC = 2.3V
–45
VIN = 0.8V, VCC = 3.0V
75
VIN = 2.0V, VCC = 3.0V
–75
VIN = 0 to 3.6V, VCC = 3.6V(3)
±500
IOZ
O utput Current (3- State O utputs)
VOUT = VCC or GND, VCC = 3.6V
±10
ICC
Supply Current
VCC = 3.6V, IOUT = 0µA,
VIN = GND or VCC
40
∆ICC
Supply Current per Input
@ TTL HIGH
VCC = 3.0V to 3.6V
O ne Input at VCC - 0.6V
O ther Inputs at VCC or GND
750
CI
CO
Control Inputs
Data Inputs
O utputs
VIN = VCC or GND, VCC = 3.3V
VO = VCC or GND, VCC = 3.3V
Units
µA
3
6
pF
7
Notes:
1. For Min. or Max conditions, use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at VCC = 3.3V, +25°C ambient and maximum loading.
3. This is the bushold maximum dynamic current. It is the mimum overdrive current necessary to switch the input from one
state to another.
4
PS8439
10/14/99
PI74ALVCH32374
32-Bit Edge Triggered D-Type Flip-Flop
with 3-State Outputs
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Timing Requirements over Operating Range
Parame te rs
D e s cription
fCLOCK
VCC = 2.5V ±0.2V
VCC = 2.7V
VCC = 3.3V ±0.3V
M in.
M ax.
M in.
M ax.
M in.
M ax.
Clock Frequency
0
150
0
150
0
150
tW
Pulse Duration
CLK HIGH or
LO W
3.3
3.3
3.3
tSU
Setup Time Data
Before CLK ↑
2.1
2.2
1.9
tH
Hold Time Data
After CLK ↑
0.6
0.5
0.5
Units
MHz
ns
Switching Characteristics over Operating Range(1)
Parame te rs
From (IN PUT)
To (OUTPUT)
fMAX
V CC = 2 . 5 V
±0.2V
M in.(2)
M ax.
150
tPD
CLK
tEN
OE
tDIS
OE
Q
V CC = 2 . 7 V
M in.
M ax.
150
V CC = 3 . 3 V
±0.3V
M in.(2)
Units
M ax.
150
MHz
1.0
5.3
4.9
1.0
4.2
1.0
6.2
5.9
1.0
4.8
1.0
5.3
4.7
1.0
4.3
ns
Notes:
1. See test circuit and waveforms, Figures 1 and 2.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
Operating Characteristics, TA = 25ºC
Parame te r
CPD Power Dissipation
Capacitance
Te s t Conditions
Outputs Enabled
Outputs Disabled
CL = 50pF, f = 10 MHz
5
VCC = 2.5V ±0.2V
VCC = 3.3V ±0.3V
Typ.
62
60
32
36
Units
pF
PS8439
10/14/99
PI74ALVCH32374
32-Bit Edge Triggered D-Type Flip-Flop
with 3-State Outputs
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PARAMETER MEASUREMENT INFORMATION
VCC = 2.5V ±0.2V
2 x VCC
S1
500Ω
From Output
Under Test
CL = 30pF
Open
GND
500Ω
(See Note A)
Te s t
S1
tpd
tPLZ/tPZH
tPHZ/tPZH
O pen
2 x VCC
GND
Load Circuit
VCC
Timing
tW
VCC/2
Input
VCC
0V
tsu
VCC/2
Input
th
VCC/2
0V
VCC
Data
VCC/2
Input
Voltage Waveforms
Pulse Duration
VCC/2
0V
Voltage Waveforms
Setup and Hold Times
Output
Control
(Low Level
Enabling)
VCC
Input
VCC/2
VCC/2
tPLH
tPHL
VOH
Output
VCC/2
Output
Waveform 2
S1 at GND
(see Note B)
VCC/2
VOL
Voltage Waveforms
Propagation Delay Times
VCC/2
0V
tPZL
Output
Waveform 1
S1 at 2 x VCC
(see Note B) t
PZH
0V
VCC /2
VCC
tPLZ
VCC
VCC/2
VOL +0.15V
VOL
tPHZ
VCC/2
VOH –0.15V
VOH
0V
Voltage Waveforms
Enable and Disable Times
Figure 1. Load Circuit and Voltage Waveforms
Notes:
A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input impulses are supplied by generators having the following characteristics: PRR ≤ MHz, ZO = 50Ω, tR ≤ 2.0ns, tF ≤ 2.0ns.
D. The outputs are measured one at a time with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis
F. tPZL and tPZH are the same as ten
G. tPLH and tPHL are the same as tpd
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PS8439
10/14/99
PI74ALVCH32374
32-Bit Edge Triggered D-Type Flip-Flop
with 3-State Outputs
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PARAMETER MEASUREMENT INFORMATION
VCC = 2.7V and 3.3V ±0.3V
6V
S1
500Ω
From Output
Under Test
CL = 50pF
Open
GND
500Ω
(See Note A)
Te s t
S1
tpd
tPLZ/tPZH
tPHZ/tPZH
O pen
6V
GND
Load Circuit
2.7V
Timing
tW
1.5V
Input
2.7V
0V
tsu
1.5V
Input
0V
th
Voltage Waveforms
Pulse Duration
2.7V
Data
1.5V
Input
1.5V
1.5V
0V
Voltage Waveforms
Setup and Hold Times
Output
Control
(Low Level
Enabling)
Input
0V
tPLH
tPHL
Output
Waveform 2
S1 at GND
(see Note B)
VOH
Output
1.5V
1.5V
1.5V
VOL
Voltage Waveforms
Propagation Delay Times
1.5V
0V
tPZL
Output
Waveform 1
S1 at 6V
(see Note B) t
PZH
2.7V
1.5V
1.5V
2.7V
tPLZ
3V
1.5V
VOL +0.3V
VOL
tPHZ
1.5V
VOH –0.3V
VOH
0V
Voltage Waveforms
Enable and Disable Times
Figure 2. Load Circuit and Voltage Waveforms
Notes:
A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input impulses are supplied by generators having the following characteristics: PRR ≤ MHz, ZO = 50Ω, tR ≤ 2.5ns, tF ≤ 2.5ns.
D. The outputs are measured one at a time with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis
F. tPZL and tPZH are the same as ten
G. tPLH and tPHL are the same as tpd
Pericom Semiconductor Corporation
2380 Bering Drive • San Jose, CA 95131 • 1-800-435-2336 • Fax (408) 435-1100 • http://www.pericom.com
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PS8439
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