AD AD7376AR10

a
FEATURES
128 Position
Potentiometer Replacement
10 kV, 50 kV, 100 kV, 1 MV
Power Shutdown: Less than 1 mA
3-Wire SPI Compatible Serial Data Input
+5 V to +30 V Single Supply Operation
65 V to 615 V Dual Supply Operation
Midscale Preset
615 V Operation
Digital Potentiometer
AD7376*
FUNCTIONAL BLOCK DIAGRAM
AD7376
SDO
VDD
Q
7-BIT
SERIAL
REGISTER
SDI
D
7
7-BIT
LATCH
A
7
W
B
R
CK
SHDN
VSS
CLK
CS
APPLICATIONS
Mechanical Potentiometer Replacement
Instrumentation: Gain, Offset Adjustment
Programmable Voltage-to-Current Conversion
Programmable Filters, Delays, Time Constants
Line Impedance Matching
Power Supply Adjustment
GENERAL DESCRIPTION
The AD7376 provides a single channel, 128-position digitallycontrolled variable resistor (VR) device. This device performs the
same electronic adjustment function as a potentiometer or variable resistor. These products were optimized for instrument and
test equipment applications where a combination of high voltage
with a choice between bandwidth or power dissipation are available as a result of the wide selection of end-to-end terminal resistance values. The AD7376 contains a fixed resistor with a wiper
contact that taps the fixed resistor value at a point determined by
a digital code loaded into the SPI-compatible serial-input register. The resistance between the wiper and either endpoint of the
fixed resistor varies linearly with respect to the digital code transferred into the VR latch. The variable resistor offers a completely
programmable value of resistance between the A terminal and the
wiper or the B terminal and the wiper. The fixed A to B terminal
resistance of 10 kΩ, 50 kΩ, 100 kΩ or 1 MΩ has a nominal temperature coefficient of –300 ppm/°C.
GND
RS
SHDN
to an end-to-end open circuit condition on the A terminal and
shorts the wiper to the B terminal, achieving a microwatt power
shutdown state. When shutdown is returned to logic high, the
previous latch settings put the wiper in the same resistance
setting prior to shutdown as long as power to VDD is not removed. The digital interface is still active in shutdown so that
code changes can be made that will produce a new wiper position when the device is taken out of shutdown.
The AD7376 is available in both surface mount (SOL-16) and
the 14-lead plastic DIP package. For ultracompact solutions
selected models are available in the thin TSSOP package. All
parts are guaranteed to operate over the extended industrial
temperature range of –40°C to +85°C. For operation at lower
supply voltages (+3 V to +5 V), see the AD8400/AD8402/
AD8403 products.
SDI
(DATA IN)
1
DX
DX
0
t DS
t DH
SDO
(DATA OUT)
1
D'X
D'X
0
t PD_MAX
t CH
1
The VR has its own VR latch which holds its programmed resistance value. The VR latch is updated from an internal serial-toparallel shift register which is loaded from a standard 3-wire
serial-input digital interface. Seven data bits make up the data
word clocked into the serial data input register (SDI). Only the
last seven bits of the data word loaded are transferred into the
7-bit VR latch when the CS strobe is returned to logic high. A
serial data output pin (SDO) at the opposite end of the serial
register allows simple daisy-chaining in multiple VR applications
without additional external decoding logic.
The reset (RS) pin forces the wiper to the midscale position by
loading 40H into the VR latch. The SHDN pin forces the resistor
*Patent Number: 5495245
t CS1
CLK
0
t CSH0
1
CS
t CL
t CSS
t CSH
t CSW
0
tS
VOUT
VDD
0V
61 LSB ERROR BAND
61 LSB
Figure 1. Detail Timing Diagram
The last seven data bits clocked into the serial input register will
be transferred to the VR 7-bit latch when CS returns to logic
high. Extra data bits are ignored.
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 1997
AD7376–SPECIFICATIONS
(VDD/VSS = 615 V 6 10% or 6 5 V 6 10%, VA = +VDD, VB = VSS/0 V, –408C < TA < +858C
ELECTRICAL CHARACTERISTICS unless otherwise noted.)
Parameter
Symbol
Conditions
DC CHARACTERISTICS RHEOSTAT MODE (Specifications Apply to All VRs)
Resistor Differential NL2
R-DNL
RWB, VA = NC
Resistor Nonlinearity2
R-INL
RWB, VA = NC
Nominal Resistor Tolerance
∆R
TA = +25°C
Resistance Temperature Coefficient
RAB/∆T
VAB = VDD, Wiper = No Connect
Wiper Resistance
RW
IW = ± 15 V/RNOMINAL
Wiper Resistance
RW
IW = ± 5 V/RNOMINAL
DC CHARACTERISTICS POTENTIOMETER DIVIDER MODE (Specifications Apply to All VRs)
Resolution
N
Integral Nonlinearity3
INL
Differential Nonlinearity3
DNL
Voltage Divider Temperature Coefficient
∆VW/∆T
Code = 40H
Full-Scale Error
VWFSE
Code = 7FH
Zero-Scale Error
VWZSE
Code = 00H
RESISTOR TERMINALS
Voltage Range4
Capacitance5 A, B
Capacitance5 W
Shutdown Supply Current6
Shutdown Wiper Resistance
Common-Mode Leakage
VA, B, W
CA, B
CW
IA_SD
RW_SD
ICM
DIGITAL INPUTS AND OUTPUTS
Input Logic High
Input Logic Low
Output Logic High
Output Logic Low7
Input Current
Input Capacitance5
VIH
VIL
VOH
VOL
IIL
CIL
VDD = +5 V or +15 V
VDD = +5 V or +15 V
RL = 2.2 kΩ to +5 V
IOL = 1.6 mA, VLOGIC = +5 V, VDD = +15 V
VIN = 0 V or +15 V
VDD/VSS
VDD
IDD
IDD
ISS
PDISS
PSS
PSS
Dual Supply Range
Single Supply Range, VSS = 0
VIH = +5 V or VIL = 0 V, VDD = +5 V
VIH = +5 V or VIL = 0 V, VDD = +15 V
VIH = +5 V or VIL = 0 V, VSS = –5 V or –15 V
VIH = +5 V or VIL = 0 V, VDD = +15 V, VSS = –15 V
∆VDD = +5 V ± 10%, or ∆VSS = –5 V ± 10%
∆VDD = +15 V ± 10% or ∆VSS = –15 V ± 10%
BW_10K
BW_50K
BW_100K
THDW
tS
eN_WB
RAB = 10 kΩ, Code = 40H
RAB = 50 kΩ, Code = 40H
RAB = 100 kΩ, Code = 40H
VA = 1 V rms, VB = 0 V, f = 1 kHz
VA = 10 V, VB = 0 V, ± 1 LSB Error Band
RWB = 25 kΩ, f = 1 kHz, RS = 0
POWER SUPPLIES
Power Supply Range
Power Supply Range
Supply Current
Supply Current
Supply Current
Power Dissipation8
Power Supply Sensitivity
DYNAMIC CHARACTERISTICS5, 9, 10
Bandwidth –3 dB
Bandwidth –3 dB
Bandwidth –3 dB
Total Harmonic Distortion
VW Settling Time
Resistor Noise Voltage
Min
Typ1
Max
Units
–1
–1
–30
± 0.25
± 0.5
+1
+1
30
LSB
LSB
%
ppm/°C
Ω
Ω
–300
120
200
7
–1
–1
–2
0
± 0.5
± 0.1
5
–0.5
+0.5
VSS
f = 1 MHz, Measured to GND, Code = 40H
f = 1 MHz, Measured to GND, Code = 40H
VA = VDD, VB = 0 V, SHDN = 0
VA = VDD, VB = 0 V, SHDN = 0, VDD = +15 V
VA = VB = VW
INTERFACE TIMING CHARACTERISTICS (Applies to All Parts [Notes 5, 11])
Input Clock Pulsewidth
tCH, tCL
Clock Level High or Low
Data Setup Time
tDS
Data Hold Time
tDH
CLK to SDO Propagation Delay12
tPD
RL = 2.2 kΩ, CL < 20 pF
CS Setup Time
tCSS
CS High Pulsewidth
tCSW
Reset Pulsewidth
tRS
CLK Rise to CS Rise Hold Time
tCSH
CS Rise to Clock Rise Setup
tCS1
–2–
200
+1
+1
+0
+1
VDD
45
60
0.01
170
1
1
400
2.4
5
± 16.5
28
0.0001 0.01
0.75
2
0.02
0.1
11
30
0.05
0.15
0.01
0.02
V
V
mA
mA
mA
mW
%/%
%/%
520
125
60
0.005
4
14
kHz
kHz
kHz
%
µs
nV√Hz
4.9
0.4
±1
120
30
20
10
120
150
120
120
120
V
pF
pF
µA
Ω
nA
V
V
V
V
µA
pF
0.8
± 4.5
4.5
Bits
LSB
LSB
ppm/°C
LSB
LSB
100
ns
ns
ns
ns
ns
ns
ns
ns
ns
REV. 0
AD7376
NOTES
11
Typicals represent average readings at +25°C, VDD = +15 V, and V SS = –15 V.
12
Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper positions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic. See Figure 27. Test Circuit.
13
INL and DNL are measured at V W with the RDAC configured as a potentiometer divider similar to a voltage output D/A converter. V A = VDD and VB = 0 V. DNL
specification limits of ± 1 LSB maximum are Guaranteed Monotonic operating conditions. See Figure 26. Test Circuit.
14
Resistor terminals A, B, W have no limitations on polarity with respect to each other.
15
Guaranteed by design and not subject to production test.
16
Measured at the A terminal. A terminal is open circuit in shutdown mode.
17
IOL = 200 µA for the 50 kΩ version operating at V DD = +5 V.
18
PDISS is calculated from (IDD × VDD). CMOS logic level inputs result in minimum power dissipation.
19
Bandwidth, noise and settling time are dependent on the terminal resistance value chosen. The lowest R value results in the fastest settling time and highest bandwidth. The highest R value results in the minimum overall power consumption.
10
All dynamic characteristics use V DD = +15 V and V SS = –15 V.
11
See timing diagram for location of measured values. All input control voltages are specified with t R = tF = 1 ns (10% to 90% of V DD) and timed from a voltage level
of 1.6 V. Switching characteristics are measured using both V DD = +5 V or +15 V.
12
Propagation delay depends on value of V DD, RL and CL see Applications section.
Specifications subject to change without notice.
PIN CONFIGURATIONS
ABSOLUTE MAXIMUM RATINGS
(TA = +25°C, unless otherwise noted)
PDIP & TSSOP-14
VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V, +30 V
VSS to GND . . . . . . . . . . . . . . . . . . . . . . . . . . +0.3 V, –16.5 V
VDD to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V, +44 V
VA, VB, VW to GND . . . . . . . . . . . . . . . . . . . . . . . . . . VSS, VDD
AX – BX, AX – WX, BX – WX . . . . . . . . . . . . . . . . . . . ± 20 mA
Digital Input Voltages to GND . . . . . . . . . . 0 V, VDD + 0.3 V
Digital Output Voltage to GND . . . . . . . . . . . . . . 0 V, +30 V
Operating Temperature Range . . . . . . . . . . . –40°C to +85°C
Maximum Junction Temperature (TJ MAX) . . . . . . . +150°C
Storage Temperature . . . . . . . . . . . . . . . . . . –65°C to +150°C
Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . +300°C
Package Power Dissipation . . . . . . . . . . . . (TJ MAX – TA)/θJA
Thermal Resistance θJA
P-DIP (N-14) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92°C/W
SOIC (SOL-16) . . . . . . . . . . . . . . . . . . . . . . . . . . 120°C/W
TSSOP-14 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240°C/W
SOL-16
A 1
14 W
A 1
16 W
B 2
13 NC
B 2
15 NC
VSS 3
GND 4
CS 5
AD7376
TOP VIEW
(Not to Scale)
RS 6
CLK 7
12 VDD
VSS 3
11 SDO
GND 4
10 SHDN
14 VDD
AD7376
13 SDO
TOP VIEW
CS 5 (Not to Scale) 12 SHDN
9 SDI
RS 6
11 SDI
8 NC
CLK 7
10 NC
NC 8
9 NC
NC = NO CONNECT
NC = NO CONNECT
ORDERING GUIDE
Model
kV
Temperature
Range
AD7376AN10
10
–40°C to +85°C
AD7376AR10
10
–40°C to +85°C
AD7376ARU10
10
–40°C to +85°C
AD7376AN50
50
–40°C to +85°C
AD7376AR50
50
–40°C to +85°C
AD7376ARU50
50
–40°C to +85°C
AD7376AN100
100
–40°C to +85°C
AD7376AR100
100
–40°C to +85°C
AD7376ARU100
100
–40°C to +85°C
AD7376AN1M
1,000
–40°C to +85°C
AD7376AR1M
1,000
–40°C to +85°C
AD7376ARU1M
1,000
–40°C to +85°C
Die Size: 101.6 mil × 127.6 mil, 2.58 mm × 3.24 mm
Number Transistors: 840
Package
Description
Package
Options
PDIP-14
SOL-16
TSSOP-14
PDIP-14
SOL-16
TSSOP-14
PDIP-14
SOL-16
TSSOP-14
PDIP-14
SOL-16
TSSOP-14
N-14
R-16
RU-14
N-14
R-16
RU-14
N-14
R-16
RU-14
N-14
R-16
RU-14
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD7376 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
REV. 0
–3–
WARNING!
ESD SENSITIVE DEVICE
AD7376–Typical Performance Characteristics
0.5
50
0.2
0.1
TA = +858C
0
VDD = +15V
VSS = –15V
VA = 2.5V
VB = 0V
RAB = 50kV
–0.1
–0.2
25
–0.3
RWB
0
RWA
32
64
96
CODE – Decimal
128
0.15
R-DNL ERROR – LSB
75
Figure 2. Wiper To End Terminal
Percent Resistance vs. Code
0.05
0
–0.05
–0.20
32
48
64 80
96
CODE – Decimal
VDD = +15V
VSS = –15V
RAB = 50kV
–0.15
–0.25
16
TA = +858C
–0.10
–0.4
0
TA = –558C
TA = +258C
0.10
–0.5
112 128
Figure 3. Resistance Step Position
Nonlinearity Error vs. Code
0
16
32
48
64 80
96
CODE – Decimal
112 128
Figure 4. Relative Resistance Step
Change from Ideal vs. Code
1.5
50
14
VDD = +15V
VSS = –15V
RAB = 50kV NOMINAL
47
10H
12
1.2
20H
10
40H
8
6
4
CODE = 70H
46
2
45
–55 –35 –15
0
0.6
0.4
0.2
0.25
0.5 0.75 1 1.25 1.5 1.75
IWA – mA
10
15
20
25
30
SUPPLY VOLTAGE (VDD - VSS) – Volts
Figure 8. Potentiometer Divider
Nonlinearity Error vs. Supply
Voltage
0
2
5
1000
15
900
10
5
0
–5
VDD = +15V
VSS = –15V
VA = +2.5V
VB = 0V
–558C < TA < +858C
RAB = 50kV
–10
–15
–20
–30
0
16
32
48 64
80
96
CODE – Decimal
112 128
Figure 9. ∆VWB/∆T Potentiometer
Mode Tempco
–4–
10
15
20
25
30
SUPPLY VOLTAGE (VDD - VSS) – Volts
Figure 7. Resistance Nonlinearity
Error vs. Supply Voltage
20
–25
0
0.6
0.3
Figure 6. Resistance Linearity vs.
Conduction Current
DVWB/DT POTENTIOMETER
MODE TEMPCO – ppm/8C
VA = 2.5V
VB = 0V
CODE = 40H
RAB = 50kV
0.9
7FH
1.0
5
TA = +258C
VDD = +15V
VSS = –15V
RAB = 50kV
0
5
25 45 65 85 105 125
TEMPERATURE – 8C
Figure 5. Nominal Resistance vs.
Temperature
0.8
R_INL – LSB
48
I w = 100mA, TA = +258C
DATA = 40H
01H
WIPER CONTACT RESISTANCE – V
49
VWA – V
NOMINAL END-TO-END RESISTANCE – kV
0.20
TA = –558C
TA = +258C
0.3
0
INL – LSB
0.25
0.4
R-INL ERROR – LSB
PERCENT OF NOMINAL
END-TO-END RESISTANCE – % RAB
100
RAB = 50kV
800
700
VDD = +5V
VSS = 0V
600
500
400
300
200
VDD = +5V
VSS = –5V
100
0
–55 –35 –15
VDD = +15V
VSS = –15V
5
25 45 65 85
TEMPERATURE – 8C
105 125
Figure 10. Wiper Contact
Resistance vs. Temperature
REV. 0
0.25
0.20
0.20
0.15
TA = +258C
0.10
0.10
TA = –558C
0.05
0
–0.05
VDD = +15V
VSS = –15V
VA = +2.5V
VB = 0V
RAB = 50kV
–0.10
–0.15
–0.20
–0.25
0
16
32
48
64
80
96
CODE – Decimal
112 128
CODE = 02H
CODE = 01H
A
–48
W
OP275
B
10k
100k
FREQUENCY – Hz
1k
CODE = 40H
–6
–24
AMP = 50mV
VDD = +15V
VSS = –15V
RL = 1MV
–30
–36
–54
1k
128kHz
32
48
64 80
96
CODE – Decimal
112 128
Figure 13. ∆RWB/∆T Rheostat Mode
Tempco
RAB = 1MV
259.8 ms
VDD = +15V
VSS = —15V
CODE = 3FH
VA = 2.5V
VB = 0V
f = 100 kHz
OP275
100
B
Lw
50m
1k
10k
FREQUENCY – Hz
40H
3FH
HO5ms
5mS/DIV
100k
Figure 15. 1 MΩ Gain vs. Frequency
vs. Code
Figure 16. Midscale Transition Glitch
1.6 V
DLY
27.08 ms
12
CODE = 3FH
VA = 12V
VB = 0V
f = 1 MHz
0
04H
02H
VDD = +15V
VSS = –15V
0
5V
OP275
0.1
NON-INVERTING
MODE TEST
CKT FIG 36
VDD = +15V
VSS = –15V
VA = 610V p–p
CODE = 40H
RAB = 50kV
0.010
5
01H
5V
B
Lw
HO2ms
2mS/DIV
1M
Figure 17. 50 kΩ Gain vs. Frequency
vs. Code
REV. 0
16
1.0
08H
10k
100k
FREQUENCY – Hz
0
VDD = +15V
VSS = –15V
VAMPL = 50mVrms
RAB = 1MV
W
A2
A
B
112 128
CODE = 01H
A
10H
–18
0
–5
CODE = 02H
B
20H
–12
5
CODE = 04H
–30
CODE = 7FH RAB = 50kV
0
10
CODE = 08H
–24
–48
Figure 14. 10 kΩ Gain vs. Frequency
vs. Code
15
CODE = 10H
–18
1M
20
CODE = 20H
–42
VDD = +15V
VSS = –15V
VAMPL = 50mVrms
25
CODE = 40H
–36
CODE = 00H
–42
48
64 80
96
CODE – Decimal
CODE = 7FH
–6
CODE = 04H
–30
32
–12
CODE = 08H
–24
16
0
GAIN – dB
GAIN – dB
RAB = 10kV
30
–10
0
Figure 12. Potentiometer Divider
Differential Nonlinearity Error
vs. Code
CODE = 10H
–36
GAIN – dB
–0.25
CODE = 20H
–18
VDD = +15V
VSS = –15V
VA = +2.5V
VB = 0V
RAB = 50kV
–0.15
CODE = 40H
–6
–48
–0.05
–0.20
CODE = 7FH
–12
–42
0
–0.10
TA = +858C
Figure 11. Potentiometer Divider
Nonlinearity Error vs. Code
0
0.05
VDD = +15V
VSS = –15V
RAB = 50kV
35
THD – %
0.15
40
RHEOSTAT MODE TEMPCO – ppm/8C
0.25
DNL – LSB
INL NONLINEARITY ERROR – LSB
AD7376
0.001
0.0005
10
Figure 18. Large Signal Settling Time
–5–
NON-INVERTING
MODE TEST
CKT FIG 35
100
1k
10k
FREQUENCY – Hz
200k
Figure 19. Total Harmonic Distortion
Plus Noise vs. Frequency
AD7376
CODE = 7FH
0
A2
0
2.9 V
DLY
s
235.2
40H
–6
–6
GAIN – dB
08H
–24
04H
–30
–18
10kV
VDD = +15V
VSS = –15V
VAMPL = 50mVrms
CODE = 40H
–24
–30
02H
–36
–36
A
W
B
OP275
RAB = 1MV
–42
VDD = +15V
VSS = –15V
VAMPL = 50mVrms
RAB = 100kV
A
–48
10k
100k
FREQUENCY – Hz
1k
1M
B
100k
10k
FREQUENCY – Hz
70
50kV
–0.2
100kV
–0.3
VDD = +15V
VSS = –15V
VAMPL = 50mVrms
CODE = 40H
60
40
A
OP275
100
200
100
50
10
10k
1k
FREQUENCY – Hz
100k
10
1M
Figure 23. Gain Flatness vs Frequency vs. Nominal Resistance RAB
100
1k
10k
FREQUENCY – Hz
0
–15
100k
Figure 24. Power Supply Rejection
vs. Frequency
10
0.010
[email protected] = +5V, VLOGIC = +0.8V
[email protected] = +5V, VLOGIC = +5V
VDD = +15V
VSS = –15V
–5
0
5
VB – Volts
10
15
0.1
0.010
3.5
SUPPLY CURRENT – mA
[email protected] = –15V, VLOGIC = +15V
SHUTDOWN CURRENT – mA
SUPPLY CURRENT – mA
1.0
–10
4.0
1.0
[email protected] = +15V, VLOGIC = 0V
SEE FIGURE 38 TEST CIRCUIT
Figure 25. Incremental Wiper
Contact Resistance vs.
Common-Mode Voltage
[email protected] = +15V, VLOGIC = +5V
0.1
VDD = +15V
VSS = –15V
250
+PSRR
VDD = +5V610%
VSS = –5V
20
W
B
300
150
30
–0.7
–0.8
VDD = +5V
VSS = –5V
350
–PSRR
VDD = +5V
VSS = –5V610%
50
TA = +258C
400
–PSRR
VDD = +15V
VSS = –15V610%
1MV
PSRR – dB
GAIN – dB
Figure 22. Clock Feedthrough
+PSRR
VDD = +15V610%
VSS = –15V
80
–0.1
–0.9
10
1M
90
RAB = 10kV
0
–0.6
HO2 s
OP275
Figure 21. –3 dB Bandwidth vs.
Nominal Resistance
0.1
B
Lw
20m
W
–54
1k
Figure 20. 100 kΩ Gain vs. Frequency
vs. Code
–0.4
100kV
01H
–42
–0.5
50kV
RON– V
GAIN – dB
–12
10H
–18
–48
VDD = +15V
VSS = –15V
20H
–12
3.0
2.5
VDD = +15V,
VSS = –15V
VA = +2.5V
VB = 0
TA = +258C
DATA = 55H
2.0
1.5
DATA = 3FH
1.0
0.5
RAB = 50kV
0.001
–55 –35 –15
5 25 45 65 85 105 125
TEMPERATURE – 8C
Figure 26. Supply Current (IDD, ISS)
vs. Temperature
0.001
–55 –35 –15
5 25 45 65 85 105 125
TEMPERATURE – 8C
Figure 27. IA_SD Shutdown Current vs.
Temperature
–6–
0.0
1k
10k
100k
1M
CLOCK FREQUENCY – Hz
10M
Figure 28. IDD Supply Current vs.
Input Clock Frequency
REV. 0
AD7376
3.5
IMS
INPUT LOGIC THRESHOLD
VOLTAGE – Volts
3.0
DUT
2.5
A
VW
W
V+
B
2.0
V+
VMS
VA = +5V
VB = 0V
VSS = 0V
1.5
IW = 1V/RNOMINAL
VDD
RW = VW2 - (VW1 + IW [RAW||RBW])
IW
WHERE VW1 = VMS WHEN IW = 0
AND VW2 = VMS WHEN IW = 1/R
1.0
Figure 33. Wiper Resistance Test Circuit
0.5
0
5
10
15
20
25
SUPPLY VOLTAGE (VDD) – Volts
30
VA
Figure 29. Input Logic Threshold Voltage vs.
VDD Supply Voltage
VDD
V+ = VDD 610% OR VSS 610%
A
W
V+
PSRR (dB) = 20LOG
B
VMS
PSS (%/%) =
(DDVV+MS (
DVMS%
DV+%
1600
Figure 34. Power Supply Sensitivity Test Circuit
(PSS, PSRR)
IDD – mA
1200
800
VDD = +15V
VSS = –15V
A
B
DUT
+18V
W
400
VIN
OP275
VDD = +5V
VSS = 0V OR –5V
0
0
5
10
VOUT
–18V
15
VLOGIC
Figure 35. Inverting Programmable Gain Test Circuit
Figure 30. Supply Current (IDD) vs. Logic Voltage
+18V
PARAMETRIC TEST CIRCUITS
A
DUT
W
V+
OP275
V+ = VDD
1LSB = V+/128
B
VIN
VOUT
W
–18V
VMS
A
DUT
B
Figure 36. Noninverting Programmable Gain Test Circuit
Figure 31. Potentiometer Divider Nonlinearity Error Test
Circuit (INL, DNL)
NO CONNECT
A
DUT
IW
A
VIN
W
B
+18V
W
DUT
B
OP275
VOUT
VMS
–18V
Figure 32. Resistor Position Nonlinearity Error (Rheostat
Operation; R-INL, R-DNL)
REV. 0
Figure 37. Gain vs. Frequency Test Circuit
–7–
AD7376
RSW =
DUT
CODE = OOH
W
B
PROGRAMMING THE VARIABLE RESISTOR
Rheostat Operation
0.1V
ISW
ISW
The nominal resistance of the RDAC between terminals A and
B are available with values of 10 kΩ, 50 kΩ, 100 kΩ and 1 MΩ.
The final three characters of the part number determine the
nominal resistance value, e.g., 10 kΩ = 10; 50 kΩ = 50; 100 kΩ
= 100; 1 MΩ = 1M. The nominal resistance (RAB) of the VR
has 128 contact points accessed by the wiper terminal, plus the
B terminal contact. The 7-bit data word in the RDAC latch is
decoded to select one of the 128 possible settings. The wiper’s first
connection starts at the B terminal for data 00H. This B–terminal connection has a wiper contact resistance of 120 Ω. The
second connection (10 kΩ part) is the first tap point located
at 198 Ω (= RBA [nominal resistance]/128 + RW = 78 Ω + 120 Ω)
for data 01H. The third connection is the next tap point representing 156 + 120 = 276 Ω for data 02H. Each LSB data value
increase moves the wiper up the resistor ladder until the last tap
point is reached at 10041 Ω. The wiper does not directly connect to the B terminal. See Figure 40 for a simplified diagram of
the equivalent RDAC circuit.
0.1V
VSS TO VDD
Figure 38. Incremental ON Resistance Test Circuit
NC
VDD
DUT
A
VSS GND
B
W
ICM
VCM
NC
Figure 39. Common-Mode Leakage Current Test Circuit
The general transfer equation that determines the digitally programmed output resistance between W and B is:
RWB(D) = (D)/128 × RBA + RW
OPERATION
where D is the data contained in the 7-bit VR latch, and RBA is
the nominal end-to-end resistance.
The AD7376 provides a 128-position digitally-controlled variable resistor (VR) device. Changing the programmed VR settings is accomplished by clocking in a 7-bit serial data word into
the SDI (Serial Data Input) pin, while CS is active low. When
CS returns high the last seven bits are transferred into the RDAC
latch setting the new wiper position. The exact timing requirements are shown in Figure 1.
For example, when VB = 0 V and A–terminal is open circuit, the
following output resistance values will be set for the following
VR latch codes (applies to the 10 kΩ potentiometer).
Table I.
The AD7376 resets to a midscale by asserting the RS pin, simplifying initial conditions at power-up. Both parts have a power
shutdown SHDN pin which places the RDAC in a zero power
consumption state where terminal A is open circuited and the
wiper W is connected to B, resulting in only leakage currents
being consumed in the VR structure. In shutdown mode the
VR latch settings are maintained so that, returning to operational mode from power shutdown, the VR settings return to
their previous resistance values.
RS
RS
RWB
(V)
Output State
127
64
1
0
10041
5120
276
198
Full-Scale
Midscale (RS = 0 Condition)
1 LSB
Zero-Scale (Wiper Contact Resistance)
Like the mechanical potentiometer the RDAC replaces, it is
totally symmetrical. The resistance between the wiper W and
terminal A also produces a digitally controlled resistance RWA.
When these terminals are used the B–terminal should be tied to
the wiper. Setting the resistance value for RWA starts at a maximum value of resistance and decreases as the data loaded in the
latch is increased in value. The general transfer equation for this
operation is:
RS
D6
D5
D4
D3
D2
D1
D0
D
(DEC)
Note that in the zero-scale condition a finite wiper resistance of
120 Ω is present. Care should be taken to limit the current flow
between W and B in this state to a maximum value of 5 mA to
avoid degradation or possible destruction of the internal switch
contact.
A
SHDN
(1)
W
RWA(D) = (128-D)/128 × RBA + RW
RDAC
LATCH
&
DECODER
(2)
where D is the data contained in the 7-bit RDAC latch, and RBA
is the nominal end-to-end resistance. For example, when VA = 0 V
and B–terminal is tied to the wiper W the following output
resistance values will be set for the following RDAC latch codes.
RS
B
R S = R NOMINAL /128
Figure 40. AD7376 Equivalent RDAC Circuit
–8–
REV. 0
AD7376
clean transitions to avoid clocking incorrect data into the serial
input register. Standard logic families work well. If mechanical
switches are used for product evaluation they should be debounced by a flip-flop or other suitable means. When CS is
taken active low the clock loads data into the serial register on
each positive clock edge, see Table III. The last seven bits
clocked into the serial register will be transferred to the 7-bit
RDAC latch, see Figure 41. Extra data bits are ignored. The
serial-data-output (SDO) pin contains an open drain n-channel
FET. This output requires a pull-up resistor in order to transfer
data to the next package’s SDI pin. This allows for daisy chaining several RDACs from a single processor serial data line.
Clock period needs to be increased when using a pull-up resistor
to the SDI pin of the following device in the series. Capacitive
loading at the daisy chain node SDO-SDI between devices must
be accounted for to successfully transfer data. When daisy
chaining is used, the CS should be kept low until all the bits of
every package are clocked into their respective serial registers
insuring that the data bits are in the proper decoding location.
This would require 14 bits of data when two AD7376 RDACs
are daisy chained. During shutdown (SHDN) the SDO output
pin is forced to the off (logic high state) to disable power dissipation in the pull up resistor. See Figure 42 for equivalent SDO
output circuit schematic.
Table II.
D
(DEC)
RWA
(V)
Output State
127
64
1
0
74
5035
9996
10035
Full-Scale
Midscale (RS = 0 Condition)
1 LSB
Zero-Scale
The typical distribution of RBA from device to device matching
is process lot dependent having a ±30% variation. The change
in RBA with temperature has a –300 ppm/°C temperature
coefficient.
PROGRAMMING THE POTENTIOMETER DIVIDER
Voltage Output Operation
The digital potentiometer easily generates an output voltage
proportional to the input voltage applied to a given terminal.
For example connecting A–terminal to +5 V and B–terminal to
ground produces an output voltage at the wiper which can be
any value starting at zero volts up to 1 LSB less than +5 V. Each
LSB of voltage is equal to the voltage applied across terminal
AB divided by the 128-position resolution of the potentiometer
divider. The general equation defining the output voltage with
respect to ground for any given input voltage applied to terminals AB is:
Table III. Input Logic Control Truth Table
VW (D) = D/128 × VAB + VB
Operation of the digital potentiometer in the divider mode
results in more accurate operation over temperature. Here the
output voltage is dependent on the ratio of the internal resistors, not the absolute value; therefore, the drift improves to
5 ppm/°C.
AD7376
SDO
Q
D
CK
7
7-BIT
RDAC
LATCH
A
7
W
B
R
SHDN
RS
SHDN Register Activity
L
L
H
H
Enables SR, enables SDO pin.
P
L
H
H
Shifts one bit in from the SDI
pin. The seventh previously
entered bit is shifted out of the
SDO pin.
X
P
H
H
Loads SR data into 7-bit RDAC
latch.
X
H
H
H
No Operation.
X
X
L
H
Sets 7-bit RDAC latch to midscale, wiper centered, and SDO
latch cleared.
X
H
P
H
Latches 7-bit RDAC latch to
40H.
X
H
H
L
Opens circuits resistor A–terminal,
connects W to B, turns off SDO
output transistor.
VSS
CLK
CS
GND
RS
SHDN
Figure 41. Block Diagram
DIGITAL INTERFACING
The AD7376 contains a standard three-wire serial input control
interface. The three inputs are clock (CLK), CS and serial data
input (SDI). The positive-edge sensitive CLK input requires
REV. 0
CS
VDD
7-BIT
SERIAL
REGISTER
SDI
CLK
NOTE
P = positive edge, X = don’t care, SR = shift register.
–9–
AD7376
The data setup and data hold times in the specification table
determine the data valid time requirements. The last seven bits
of the data word entered into the serial register are held when
CS returns high. At the same time CS goes high it transfers the
7-bit data to the VR latch.
VDD
100V
LOGIC
Figure 43. Equivalent ESD Protection Circuit
SHDN
CS
SDI
SDO
SERIAL
REGISTER
D
VDD
Q
A,B,W
CK RS
VSS
CLK
RS
Figure 44. Equivalent ESD Protection Analog Pins
Figure 42. Detail SDO Output Schematic of the AD7376
All digital inputs are protected with a series input resistor and
parallel Zener ESD structure shown in Figure 43. Applies to
digital input pins CS, SDI, SDO, RS, SHDN, CLK
–10–
REV. 0
AD7376
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
14-Lead Plastic DIP
(N-14)
14-Lead TSSOP
(RU-14)
0.795 (20.19)
0.725 (18.42)
0.201 (5.10)
0.193 (4.90)
1
7
PIN 1
0.210 (5.33)
MAX
0.160 (4.06)
0.115 (2.93)
0.022 (0.558)
0.014 (0.356)
0.280 (7.11)
0.240 (6.10)
0.060 (1.52)
0.015 (0.38)
14
0.325 (8.25)
0.300 (7.62) 0.195 (4.95)
0.115 (2.93)
1
0.130
(3.30)
MIN
0.100 0.070 (1.77)
(2.54) 0.045 (1.15)
BSC
8
0.256 (6.50)
0.246 (6.25)
8
0.177 (4.50)
0.169 (4.30)
14
0.015 (0.381)
0.008 (0.204)
SEATING
PLANE
7
PIN 1
0.006 (0.15)
0.002 (0.05)
SEATING
PLANE
0.0433
(1.10)
MAX
0.0256
(0.65)
BSC
0.0118 (0.30)
0.0075 (0.19)
16-Lead Wide Body SOIC
(R-16)
9
1
8
PIN 1
0.0118 (0.30)
0.0040 (0.10)
0.0500
(1.27)
BSC
REV. 0
0.4193 (10.65)
0.3937 (10.00)
16
0.2992 (7.60)
0.2914 (7.40)
0.4133 (10.50)
0.3977 (10.00)
0.1043 (2.65)
0.0926 (2.35)
0.0291 (0.74)
x 45°
0.0098 (0.25)
8°
0.0192 (0.49)
SEATING 0.0125 (0.32) 0°
0.0138 (0.35) PLANE
0.0091 (0.23)
–11–
0.0500 (1.27)
0.0157 (0.40)
0.0079 (0.20)
0.0035 (0.090)
8°
0°
0.028 (0.70)
0.020 (0.50)
–12–
PRINTED IN U.S.A.
C3163–8–10/97