ETC 522976X

LT1366/LT1367
LT1368/LT1369
Dual and Quad Precision
Rail-to-Rail Input and Output
Op Amps
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DESCRIPTION
FEATURES
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Input Common Mode Range Includes Both Rails
Output Swings Rail-to-Rail
Low Input Offset Voltage: 150µV
High Common Mode Rejection Ratio: 90dB
High AVOL: >1V/µV Driving 10kΩ Load
Low Input Bias Current: 10nA
Wide Supply Range: 1.8V to ±15V
Low Supply Current: 375µA per Amplifier
High Output Drive: 30mA
400kHz Gain-Bandwidth Product
Slew Rate: 0.13V/µs
Stable for Capacitive Loads up to 1000pF
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APPLICATIONS
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Rail-to-Rail Buffer Amplifiers
Low Voltage Signal Processing
Supply Current Sensing at Either Rail
Driving A/D Converters
The LT ®1366/LT1367/LT1368/LT1369 are dual and quad
bipolar op amps which combine rail-to-rail input and
output operation with precision specifications. These op
amps maintain their characteristics over a supply range of
1.8V to 36V. Operation is specified for 3V, 5V and ±15V
supplies. Input offset voltage is typically 150µV, with an
open-loop gain AVOL of 1 million while driving a 10k load.
Common mode rejection is typically 90dB over the full railto-rail input range, and supply rejection is 110dB.
The LT1366/LT1367 have conventional compensation
which assures stability for capacitive loads of 1000pF or
less. The LT1368/LT1369 have compensation that
requires a 0.1µF output capacitor, which improves the
amplifier’s supply rejection and reduces output impedance at high frequencies. The output capacitor’s filtering
action reduces high frequency noise, which is beneficial
when driving A/D converters.
The LT1366/LT1368 are available in plastic 8-pin PDIP and
8-lead SO packages with the standard dual op amp pinout.
The LT1367/LT1369 feature the standard quad pinout,
which is available in a plastic 14-lead SO package. These
devices can be used as plug-in replacements for many
standard op amps to improve input/output range and
precision.
, LTC and LT are registered trademarks of Linear Technology Corporation.
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TYPICAL APPLICATION
Output Saturation Voltage vs Load Current
Positive Supply Rail Current Sense
VCC
1000
R1
200Ω
Rs
0.2Ω
–
–
Q1
TP0610L
1/2 LT1366
+
ILOAD
LOAD
R2
20k
1/2 LT1366
+
( )
R2
VO = ILOAD • RS
R1
= ILOAD • 20Ω
1366 TA01
SATURATION VOLTAGE (mV)
VOUT – VS
■
100
POSITIVE
RAIL
NEGATIVE
RAIL
10
1
0.001
0.01
0.1
1
LOAD CURRENT (mA)
10
1366 TA02
1
LT1366/LT1367
LT1368/LT1369
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ABSOLUTE MAXIMUM RATINGS
Total Supply Voltage (V + to V – ) ............................. 36V
Input Current ..................................................... ±15mA
Output Short-Circuit Duration (Note 1) ........ Continuous
Operating Temperature Range .............. –40°C to 85°C
Junction Temperature.......................................... 150°C
Storage Temperature Range ................ – 65°C to 150°C
Lead Temperature (Soldering, 10 sec)................. 300°C
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PACKAGE/ORDER INFORMATION
ORDER PART
NUMBER
TOP VIEW
OUT A 1
8 V+
– IN A 2
7 OUT B
LT1366CN8
LT1366CS8
LT1368CN8
LT1368CS8
A
+IN A 3
V
–
B
6 – IN B
5 +IN B
4
N8 PACKAGE
8-LEAD PDIP
S8 PART MARKING
S8 PACKAGE
8-LEAD PLASTIC SO
1366
1368
TJMAX = 150°C, θJA = 130°C/ W (N8)
TJMAX = 150°C, θJA = 190°C/ W (S8)
ORDER PART
NUMBER
TOP VIEW
14 OUT D
OUT A 1
–IN A 2
A
D
LT1367CS
LT1369CS
12 +IN D
+IN A 3
V+ 4
11 V –
10 +IN C
+IN B 5
–IN B 6
13 – IN D
B
OUT B 7
C
9 – IN C
8 OUT C
S PACKAGE
14-LEAD PLASTIC SO
TJMAX = 150°C, θJA = 150°C/ W
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AVAILABLE OPTIO S
ORDER PART NUMBER
PRODUCT NUMBER
NUMBER OF OP AMPS
LOAD CAPACITANCE
MAX VOS (25°C)
AT VS = 5V, 0V
PLASTIC (N)
SURFACE MOUNT(S)
LT1366
2
OpF < CL < 1000pF
475µV
LT1366CN8
LT1366CS8
LT1367
4
OpF < CL < 1000pF
800µV
LT1368
2
CL = 0.1µF
475µV
LT1369
4
CL = 0.1µF
800µV
LT1367CS
LT1368CN8
LT1368CS8
LT1369CS
ELECTRICAL CHARACTERISTICS
TA = 25°C, VS = 5V, 0V, VCM = 2.5V, VO = 2.5V, unless otherwise noted.
SYMBOL PARAMETER
CONDITIONS
VOS
Input Offset Voltage (LT1366/LT1368)
TYP
MAX
UNITS
VCM = VCC
VCM = VEE
150
150
475
475
µV
µV
Input Offset Voltage (LT1367/LT1369)
VCM = VCC
VCM = VEE
150
150
800
700
µV
µV
Input Offset Voltage Shift (LT1366/LT1368)
Input Offset Voltage Match (Channel to Channel)
VCM = VEE to VCC
VCM = VEE, VCC (Notes 3, 4)
150
250
400
700
µV
µV
Input Offset Voltage Shift (LT1367/LT1369)
Input Offset Voltage Match (Channel to Channel)
VCM = VEE to VCC
VCM = VEE, VCC (Notes 3, 4)
150
250
650
1600
µV
µV
IB
Input Bias Current
VCM = VCC
VCM = VEE
10
–10
35
0
nA
nA
∆IB
Input Bias Current Shift
VCM = VEE to VCC
20
70
nA
∆VOS
2
MIN
0
–35
LT1366/LT1367
LT1368/LT1369
ELECTRICAL CHARACTERISTICS
TA = 25°C, VS = 5V, 0V, VCM = 2.5V, VO = 2.5V, unless otherwise noted.
SYMBOL PARAMETER
CONDITIONS
IOS
Input Offset Current
VCM = VCC
VCM = VEE
MIN
∆IOS
Input Offset Current Shift
VCM = VEE to VCC
Input Bias Current Match (Channel to Channel)
VCM = VCC (Note 3)
VCM = VEE (Note 3)
en
Input Noise Voltage Density
f = 1kHz
29
nV/√Hz
in
Input Noise Current Density
f = 1kHz
0.07
pA/√Hz
CIN
Input Capacitance
0
0
TYP
MAX
1
0.3
12
12
nA
nA
1
12
nA
1
1
12
12
nA
nA
12
UNITS
pF
A VOL
Large-Signal Voltage Gain
VO = 50mV to 4.8V, RL = 10k
250
2000
CMRR
Common Mode Rejection Ratio (LT1366/LT1368)
CMRR Match (Channel to Channel)
VCM = VEE to VCC
VCM = VEE to VCC (Note 3)
81
75
90
90
dB
dB
Common Mode Rejection Ratio (LT1367/LT1369)
CMRR Match (Channel to Channel)
VCM = VEE to VCC
VCM = VEE to VCC (Note 3)
77
71
90
90
dB
dB
PSRR
Power Supply Rejection Ratio
PSRR Match (Channel to Channel) (Note 3)
VS = 2.0V to 12V, VCM = VO = 0.5V
VS = 2.0V to 12V, VCM = VO = 0.5V
90
84
105
100
dB
dB
V OL
Output Voltage Swing LOW
No Load
ISINK = 0.5mA
ISINK = 2.5mA
V OH
Output Voltage Swing HIGH
No Load
ISOURCE = 0.5mA
ISOURCE = 2.5mA
ISC
Short-Circuit Current
(Note 1)
6
40
110
V/mV
12
70
200
VCC – 0.012 VCC – 0.004
VCC – 0.100 VCC – 0.050
VCC – 0.250 VCC – 0.150
±15
V
V
V
±30
IS
Supply Current per Amplifier
GBW
Gain-Bandwidth Product (LT1366/LT1367)
Gain-Bandwidth Product (LT1368/LT1369)
AV = 1000
AV = 1000
340
0.4
0.16
tS
Settling Time (LT1366/LT1367)
AV = 1, VSTEP = 4V to 0.1%
30
mV
mV
mV
mA
520
µA
MHz
MHz
µs
0°C < TA < 70°C, VS = 5V, 0V, VCM = 2.5V, VO = 2.5V, unless otherwise noted.
SYMBOL PARAMETER
CONDITIONS
TYP
MAX
UNITS
VOS
Input Offset Voltage (LT1366/LT1368)
VCM = VCC
VCM = VEE
●
●
MIN
200
200
575
575
µV
µV
Input Offset Voltage (LT1367/LT1369)
VCM = VCC
VCM = VEE
●
●
200
200
950
900
µV
µV
VOS TC
Input Offset Voltage Drift
(Note 2)
●
2
6
∆VOS
Input Offset Voltage Shift (LT1366/LT1368)
Input Offset Voltage Match (Channel to Channel)
VCM = VEE to VCC
VCM = VEE, VCC (Notes 3, 4)
●
●
200
250
425
900
µV
µV
Input Offset Voltage Shift (LT1367/LT1369)
Input Offset Voltage Match (Channel to Channel)
VCM = VEE to VCC
VCM = VEE, VCC (Notes 3, 4)
●
●
200
250
675
1900
µV
µV
IB
Input Bias Current
VCM = VCC
VCM = VEE
●
●
15
–10
45
0
nA
nA
∆IB
Input Bias Current Shift
VCM = VEE to VCC
●
25
90
nA
IOS
Input Offset Current
VCM = VCC
VCM = VEE
●
●
2
1
15
15
nA
nA
∆IOS
Input Offset Current Shift
VCM = VEE to VCC
●
2
15
nA
Input Bias Current Match (Channel to Channel)
VCM = VCC (Note 3)
VCM = VEE (Note 3)
●
●
2
1
15
15
nA
nA
0
–45
0
0
µV/°C
3
LT1366/LT1367
LT1368/LT1369
ELECTRICAL CHARACTERISTICS
0°C < TA < 70°C, VS = 5V, 0V, VCM = 2.5V, VO = 2.5V, unless otherwise noted.
SYMBOL PARAMETER
CONDITIONS
MIN
TYP
AVOL
Large-Signal Voltage Gain
VO = 50mV to 4.8V, RL = 10k
●
250
2000
CMRR
Common Mode Rejection Ratio (LT1366/LT1368)
CMRR Match (Channel to Channel)
VCM = VEE to VCC
VCM = VEE to VCC (Note 3)
●
●
80
74
87
87
dB
dB
Common Mode Rejection Ratio (LT1367/LT1369)
CMRR Match (Channel to Channel)
VCM = VEE to VCC
VCM = VEE to VCC (Note 3)
●
●
77
71
87
87
dB
dB
PSRR
Power Supply Rejection Ratio
PSRR Match (Channel to Channel) (Note 3)
VS = 2.3V to 12V, VCM = VO = 0.5V
VS = 2.3V to 12V, VCM = VO = 0.5V
●
●
88
82
105
100
dB
dB
VOL
Output Voltage Swing LOW
No Load
ISINK = 0.5mA
ISINK = 2.5mA
●
●
●
VOH
Output Voltage Swing HIGH
No Load
ISOURCE = 0.5mA
ISOURCE = 2.5mA
● VCC – 0.014 VCC – 0.005
● VCC – 0.110 VCC – 0.055
● VCC – 0.300 VCC – 0.180
ISC
Short-Circuit Current
(Note 1)
●
IS
Supply Current per Amplifier
9
45
120
MAX
V/mV
14
80
230
mV
mV
mV
V
V
V
±12.5
●
UNITS
mA
385
540
µA
TA = 25°C, VS = 3V, 0V, VCM = 1.5V, VO = 1.5V, unless otherwise noted.
SYMBOL PARAMETER
CONDITIONS
TYP
MAX
UNITS
VOS
Input Offset Voltage (LT1366/LT1368)
VCM = VCC
VCM = VEE
150
150
475
475
µV
µV
Input Offset Voltage (LT1367/LT1369)
VCM = VCC
VCM = VEE
150
150
850
750
µV
µV
Input Offset Voltage Shift (LT1366/LT1368)
Input Offset Voltage Match (Channel to Channel)
VCM = VEE to VCC
VCM = VEE, VCC (Notes 3, 4)
150
250
400
700
µV
µV
Input Offset Voltage Shift (LT1367/LT1369)
Input Offset Voltage Match (Channel to Channel)
VCM = VEE to VCC
VCM = VEE, VCC (Notes 3, 4)
150
250
650
1700
µV
µV
IB
Input Bias Current
VCM = VCC
VCM = VEE
10
–10
35
0
nA
nA
∆IB
Input Bias Current Shift
VCM = VEE to VCC
20
70
nA
IOS
Input Offset Current
VCM = VCC
VCM = VEE
1.0
0.3
12
12
nA
nA
∆IOS
Input Offset Current Shift
VCM = VEE to VCC
1
12
nA
Input Bias Current Match (Channel to Channel)
VCM = VCC (Note 3)
VCM = VEE (Note 3)
0
0
1
1
12
12
nA
nA
AVOL
Large-Signal Voltage Gain
VO = 50mV to 2.8V, RL = 10k
250
1500
CMRR
Common Mode Rejection Ratio (LT1366/LT1368)
CMRR Match (Channel to Channel)
VCM = VEE to VCC
VCM = VEE to VCC (Note 3)
77
71
86
86
dB
dB
Common Mode Rejection Ratio (LT1367/LT1369)
CMRR Match (Channel to Channel)
VCM = VEE to VCC
VCM = VEE to VCC (Note 3)
73
67
86
86
dB
dB
VOL
Output Voltage Swing LOW
No Load
ISINK = 0.5mA
ISINK = 2.5mA
VOH
Output Voltage Swing HIGH
No Load
ISOURCE = 0.5mA
ISOURCE = 2.5mA
ISC
Short-Circuit Current
(Note 1)
IS
Supply Current per Amplifier
∆VOS
4
MIN
0
– 35
6
40
110
V/mV
12
70
200
VCC – 0.012 VCC – 0.004
VCC – 0.100 VCC – 0.050
VCC – 0.250 VCC – 0.150
±10
V
V
V
±20
330
mV
mV
mV
mA
500
µA
LT1366/LT1367
LT1368/LT1369
ELECTRICAL CHARACTERISTICS
0°C < TA < 70°C, VS = 3V, 0V, VCM = 1.5V, VO = 1.5V, unless otherwise noted.
SYMBOL PARAMETER
CONDITIONS
TYP
MAX
UNITS
VOS
Input Offset Voltage (LT1366/LT1368)
VCM = VCC
VCM = VEE
●
●
200
200
575
575
µV
µV
Input Offset Voltage (LT1367/LT1369)
VCM = VCC
VCM = VEE
●
●
200
200
950
900
µV
µV
Input Offset Voltage Shift (LT1366/LT1368)
Input Offset Voltage Match (Channel to Channel)
VCM = VEE to VCC
VCM = VEE, VCC (Notes 3, 4)
●
●
200
250
425
900
µV
µV
Input Offset Voltage Shift (LT1367/LT1369)
Input Offset Voltage Match (Channel to Channel)
VCM = VEE to VCC
VCM = VEE, VCC (Notes 3, 4)
●
●
200
250
675
1900
µV
µV
VOS TC
Input Offset Voltage Drift
(Note 2)
●
2
6
µV/°C
IB
Input Bias Current
VCM = VCC
VCM = VEE
●
●
15
–10
45
0
nA
nA
∆IB
Input Bias Current Shift
VCM = VEE to VCC
●
25
90
nA
IOS
Input Offset Current
VCM = VCC
VCM = VEE
●
●
2
1
15
15
nA
nA
∆IOS
Input Offset Current Shift
VCM = VEE to VCC
●
2
15
nA
Input Bias Current Match (Channel to Channel)
VCM = VCC (Note 3)
VCM = VEE (Note 3)
●
●
0
0
2
1
15
15
nA
nA
∆VOS
MIN
0
–45
A VOL
Large-Signal Voltage Gain
VO = 50mV to 2.8V, RL = 10k
●
150
1500
CMRR
Common Mode Rejection Ratio (LT1366/LT1368)
CMRR Match (Channel to Channel)
VCM = VEE to VCC
VCM = VEE to VCC (Note 3)
●
●
76
70
83
83
dB
dB
●
●
72
66
83
83
dB
dB
V OL
Common Mode Rejection Ratio (LT1367 /LT1369) VCM = VEE to VCC
CMRR Match (Channel to Channel)
VCM = VEE to VCC (Note 3)
Output Voltage Swing LOW
No Load
ISINK = 0.5mA
ISINK = 2.5mA
V OH
Output Voltage Swing HIGH
No Load
ISOURCE = 0.5mA
ISOURCE = 2.5mA
● VCC – 0.014 VCC – 0.005
● VCC – 0.110 VCC – 0.055
● VCC – 0.300 VCC – 0.180
ISC
Short-Circuit Current
(Note 1)
●
IS
Supply Current per Amplifier
9
45
120
●
●
●
●
V/mV
14
80
230
mV
mV
mV
V
V
V
±10
mA
375
520
µA
5
LT1366/LT1367
LT1368/LT1369
ELECTRICAL CHARACTERISTICS
TA = 25°C, VS = ± 15V, VCM = 0V, VO = 0V, unless otherwise noted.
SYMBOL PARAMETER
CONDITIONS
TYP
MAX
UNITS
VOS
Input Offset Voltage (LT1366/LT1368)
VCM = VCC
VCM = VEE
200
200
700
700
µV
µV
Input Offset Voltage (LT1367/LT1369)
VCM = VCC
VCM = VEE
200
200
1000
900
µV
µV
Input Offset Voltage Shift (LT1366/LT1368)
Input Offset Voltage Match (Channel to Channel)
VCM = VEE to VCC
VCM = VEE, VCC (Notes 3, 4)
150
300
500
1300
µV
µV
Input Offset Voltage Shift (LT1367/LT1369)
Input Offset Voltage Match (Channel to Channel)
VCM = VEE to VCC
VCM = VEE, VCC (Notes 3, 4)
150
300
650
2000
µV
µV
IB
Input Bias Current
VCM = VCC
VCM = VEE
10
–10
35
0
nA
nA
∆IB
Input Bias Current Shift
VCM = VEE to VCC
20
70
nA
IOS
Input Offset Current
VCM = VCC
VCM = VEE
1.0
0.3
12
12
nA
nA
∆IOS
Input Offset Current Shift
VCM = VEE to VCC
1
12
nA
Input Bias Current Match (Channel to Channel)
VCM = VCC (Note 3)
VCM = VEE (Note 3)
1
1
12
12
nA
nA
∆VOS
MIN
0
– 35
0
0
CIN
Input Capacitance
AVOL
Large-Signal Voltage Gain
VO = –14.7V to 14.7V, RL = 10k
VO = –10V to 10V, RL = 2k
1000
500
10000
10000
Channel Separation
VO = –10V to 10V, RL = 2k
120
135
dB
Slew Rate (LT1366/LT1367)
AV = –1, RL = Open, VO = ±10V,
Measured at VO = ± 5V
0.13
V/µs
Slew Rate (LT1368/LT1369)
AV = –1, RL = Open, VO = ±10V,
Measured at VO = ±5V
0.065
V/µs
Common Mode Rejection Ratio (LT1366/LT1368)
CMRR Match (Channel to Channel)
VCM = VEE to VCC
VCM = VEE to VCC (Note 3)
95
89
106
106
dB
dB
Common Mode Rejection Ratio (LT1367/LT1369)
CMRR Match (Channel to Channel)
VCM = VEE to VCC
VCM = VEE to VCC (Note 3)
93
87
106
106
dB
dB
PSRR
Power Supply Rejection Ratio
PSRR Match (Channel to Channel)
VS = ±5V to ±15V
VS = ±5V to ±15V (Note 3)
90
84
110
105
dB
dB
VOL
Output Voltage Swing LOW
No Load
ISINK = 0.5mA
ISINK = 10mA
VOH
Output Voltage Swing HIGH
No Load
ISOURCE = 0.5mA
ISOURCE = 10mA
ISC
Short-Circuit Current
(Note 1)
IS
Supply Current per Amplifier
SR
CMRR
6
7.1
pF
V/mV
V/mV
VEE + 0.006 VEE + 0.012
VEE + 0.040 VEE + 0.070
VEE + 0.240 VEE + 0.500
VCC – 0.012 VCC – 0.004
VCC – 0.100 VCC – 0.050
VCC – 0.800 VCC – 0.400
±30
V
V
V
±75
370
V
V
V
mA
550
µA
LT1366/LT1367
LT1368/LT1369
ELECTRICAL CHARACTERISTICS
0°C < TA < 70°C, VS = ±15V, VCM = 0V, VO = 0V, unless otherwise noted.
SYMBOL PARAMETER
CONDITIONS
TYP
MAX
UNITS
VOS
Input Offset Voltage (LT1366/LT1368)
VCM = VCC
VCM = VEE
●
●
250
250
850
850
µV
µV
Input Offset Voltage (LT1367/LT1369)
VCM = VCC
VCM = VEE
●
●
250
250
1150
1000
µV
µV
Input Offset Voltage Shift (LT1366/LT1368)
Input Offset Voltage Match (Channel to Channel)
VCM = VEE to VCC
VCM = VEE, VCC (Notes 3, 4)
●
●
200
300
525
1500
µV
µV
Input Offset Voltage Shift (LT1367/LT1369)
Input Offset Voltage Match (Channel to Channel)
VCM = VEE to VCC
VCM = VEE, VCC (Notes 3, 4)
●
●
200
300
750
2300
µV
µV
VOS TC
Input Offset Voltage Drift
(Note 2)
●
IB
Input Bias Current
VCM = VCC
VCM = VEE
●
●
∆IB
Input Bias Current Shift
VCM = VEE to VCC
IOS
Input Offset Current
∆IOS
∆VOS
MIN
2
8
µV/°C
15
–10
45
0
nA
nA
●
25
90
nA
VCM = VCC
VCM = VEE
●
●
2
1
15
15
nA
nA
Input Offset Current Shift
VCM = VEE to VCC
●
2
15
nA
Input Bias Current Match (Channel to Channel)
VCM = VCC (Note 3)
VCM = VEE (Note 3)
●
●
0
0
2
1
15
15
nA
nA
Large-Signal Voltage Gain
VO = – 14.7V to 14.7V, RL = 10k
VO = – 10V to 10V, RL = 2k
●
●
750
500
6000
6000
V/mV
V/mV
Channel Separation
VO = – 10V to 10V, RL = 2k
●
110
135
dB
Common Mode Rejection Ratio (LT1366/LT1368)
CMRR Match (Channel to Channel)
VCM = VEE to VCC
VCM = VEE to VCC (Note 3)
●
●
95
89
103
103
dB
dB
Common Mode Rejection Ratio (LT1367/LT1369)
CMRR Match (Channel to Channel)
VCM = VEE to VCC
VCM = VEE to VCC (Note 3)
●
●
92
86
103
103
dB
dB
PSRR
Power Supply Rejection Ratio
PSRR Match (Channel to Channel)
VS = ±5V to ±15V
VS = ±5V to ±15V (Note 3)
●
●
80
75
105
100
dB
dB
V OL
Output Voltage Swing LOW
No Load
ISINK = 0.5mA
ISINK = 10mA
●
●
●
V OH
Output Voltage Swing HIGH
No Load
ISOURCE = 0.5mA
ISOURCE = 10mA
● VCC – 0.014 VCC – 0.005
● VCC – 0.11 VCC – 0.055
● VCC – 0.95 VCC – 0.500
ISC
Short-Circuit Current
(Note 1)
●
IS
Supply Current per Amplifier
A VOL
CMRR
The ● denotes specifications that apply over the full operating temperature
range.
Note 1: Applies to short circuits to ground for all split supplies and for
single supplies less than 20V. Short circuits to either supply for supplies
greater than 20V total may permanently damage the part. A heat sink may
be required to keep the junction temperature below the absolute maximum
rating when the output is shorted indefinitely.
●
0
–45
VEE + 0.009 VEE + 0.014
VEE + 0.045 VEE + 0.080
VEE + 0.300 VEE + 0.600
V
V
V
V
V
V
±30
mA
415
575
µA
Note 2: This parameter is not 100% tested.
Note 3: Matching parameters are the difference between amplifiers A and
D and between B and C on the LT1367/LT1369; between the two amplifiers
on the LT1366/LT1368.
Note 4: Input offset voltage match is the difference in offset voltage
between amplifiers measured at both VCM = VEE and VCM = VCC.
7
LT1366/LT1367
LT1368/LT1369
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TYPICAL PERFORMANCE CHARACTERISTICS
(The data presented here applies to the LT1366/LT1367/LT1368/LT1369 unless otherwise noted.)
30
30
N-PACKAGE
VS = 5V, 0V
VCM = 0V
30
N-PACKAGE
VS = 5V, 0V
VCM = 5V
20
15
10
5
20
15
10
5
0
–350 –250 –150 – 50 50 150 250
INPUT OFFSET VOLTAGE (µV)
LT1366 TPC03
300
200
100
0
–50 –35 –20 – 5 10 25 40 55 70 85 100
TEMPERATURE (°C)
Input Bias Current vs
Common Mode Voltage
20
VS = 5V, 0V
15
500
TA = 125°C
400
TA = 25°C
300
TA = –55°C
200
100
TA = –55°C
10
5
TA = 25°C
0
–5
TA = 125°C
–10
–15
–20
–2
0
0
4
8 12 16 20 24 28 32
TOTAL SUPPLY VOLTAGE (V)
36
–1
0
4
3
5
2
1
COMMON MODE VOLTAGE (V)
LT1366 TPC04
Output Saturation Voltage vs
Load Current (Output HIGH)
Output Saturation Voltage vs
Load Current (Output LOW)
1000
50
6
LT1366 TPC06
LT1366 TPC05
Input Bias Current
vs Temperature
350
LT1366 TPC01
INPUT BIAS CURRENT (nA)
SUPPLY CURRENT PER AMPLIFIER (µA)
SUPPLY CURRENT PER AMPLIFIER (µA)
0
–350 –250 –150 – 50 50 150 250
INPUT OFFSET VOLTAGE (µV)
350
600
VS = 5V, 0V
10
Supply Current vs Supply Voltage
500
VS = ±15V
15
LT1366 TPC02
Supply Current vs Temperature
400
20
5
0
–350 –250 –150 – 50 50 150 250
INPUT OFFSET VOLTAGE (µV)
350
N-PACKAGE
VS = 5V, 0V
VCM = 0V TO 5V
25
PERCENT OF UNITS (%)
25
PERCENT OF UNITS (%)
PERCENT OF UNITS (%)
25
∆VOS-Shift Between PNP and NPN
Stages (LT1366/LT1368)
NPN Stage VOS Distribution
(LT1366/LT1368)
PNP Stage VOS Distribution
(LT1366/LT1368)
1000
20
VS = 5V, 0V, VCM = 5V
10
VS = ±15V, VCM = 15V
0
VS = 5V, 0V, VCM = 0V
– 10
– 20
VS = ±15V, VCM = –15V
– 30
SATURATION VOLTAGE (mV)
30
SATURATION VOLTAGE (mV)
INPUT BIAS CURRENT (nA)
40
100
TA = 85°C
10
TA = 25°C
TA = –55°C
100
TA = 85°C
TA = 25°C
10
TA = – 55°C
– 40
– 50
–50 –35 –20 – 5 10 25 40 55 70 85 100
TEMPERATURE (°C)
LT1366 TPC07
8
1
0.001
0.01
0.1
1
LOAD CURRENT (mA)
10
LT1366 TPC08
1
0.001
0.01
0.1
1
LOAD CURRENT (mA)
10
LT1366 TPC09
LT1366/LT1367
LT1368/LT1369
U W
TYPICAL PERFORMANCE CHARACTERISTICS
(The data presented here applies to the LT1366/LT1367/LT1368/LT1369 unless otherwise noted.)
0.1Hz to 10Hz
Output Voltage Noise
Minimum Supply Voltage
Noise Voltage Spectrum
70
TA = 70°C
TA = 85°C
100
50
TA = 25°C
0
TA = – 55°C
VS = 5V, 0V
60
NOISE VOLTAGE nV/√Hz
150
VS = ±2.5V
VCM = 0V
OUTPUT VOLTAGE (200nV/DIV)
CHANGE IN OFFSET VOLTAGE (µV)
200
50
40
VCM = 4V
30
VCM = 2.5V
20
10
NONFUNCTIONAL
0
3
2
4
TOTAL SUPPLY VOLTAGE (V)
5
1
TIME (1s/DIV)
LT1366 TPC10
0.8
50
VCM = 2.5V
0.3
0.2
VCM = 4V
0.1
0
1
10
100
FREQUENCY (Hz)
1000
PHASE
40
30
50
120
40
100
30
100
80
20
80
60
GAIN
20
40
10
20
0
0
140
VS = ±2.5V
CL = 0.1µF
10
60
PHASE
0
20
–20
– 30
–20
–20
– 40
– 40
–40
–30
– 60
10M
– 50
10k
1k
100k
1M
FREQUENCY (Hz)
LT1366 TPC15
PSRR vs Frequency
(LT1368/LT1369)
120
80
70
60
50
40
30
120
VS = ±2.5V
POWER SUPPLY REJECTION RATIO (dB)
POWER SUPPLY REJECTION RATIO (dB)
90
100
80
POSITIVE SUPPLY
60
40
20
NEGATIVE SUPPLY
0
20
10k
100k
FREQUENCY (Hz)
1M
LT1366 TPC16
–60
10M
100k
1M
FREQUENCY (Hz)
LT1366 TPC14
120
1k
10k
1k
PSRR vs Frequency
(LT1366/LT1367)
100
0
GAIN
–20
CMRR vs Frequency
(LT1366 and LT1367)
110
40
–10
–10
LT1366 TPC13
VS = ±2.5V
120
PHASE SHIFT (DEG)
VOLTAGE GAIN (dB)
0.6
140
PHASE SHIFT (DEG)
CURRENT NOISE (pA/√Hz)
VS = ±2.5V
60
0.7
COMMON-MODE REJECTION RATIO (dB)
Gain and Phase Shift vs
Frequency (LT1368/LT1369)
70
VS = 5V, 0V
0.4
1000
LT1366 TPC12
Gain and Phase Shift vs
Frequency (LT1366/LT1367)
Noise Current Spectrum
0.5
10
100
FREQUENCY (Hz)
LT1366 TPC11
VOLTAGE GAIN (dB)
1
VS = ±2.5V
100
80
POSITIVE SUPPLY
60
40
20
NEGATIVE SUPPLY
0
1k
10k
100k
FREQUENCY (Hz)
1M
LT1366 TPC17
1k
10k
100k
FREQUENCY (Hz)
1M
LT1366 TPC18
9
LT1366/LT1367
LT1368/LT1369
U W
TYPICAL PERFORMANCE CHARACTERISTICS
(The data presented here applies to the LT1366/LT1367/LT1368/LT1369 unless otherwise noted.)
Gain-Bandwidth and Phase
Margin vs Supply Voltage
(LT1366/LT1367)
Channel Separation vs Frequency
– 50
450
54
– 60
48
– 70
GBW
PHASE MARGIN
350
42
PHASE MARGIN (DEG)
– 90
36
250
30
200
24
150
18
100
12
50
6
–140
0
30
–150
0
5
25
15
20
10
SUPPLY VOLTAGE (V)
LT1368/LT1369
–100
–110
–120
RL = 2k
5
0
RL = 10k
–5
–15
100
1k
FREQUENCY (Hz)
10
–20
5
–20 –15 –10 –5 0
10
OUTPUT VOLTAGE (V)
10k
LT1366 TPC20
80
Overshoot vs Load Current
(LT1368/LT1369)
60
60
VS = ±2.5V
AV = 1
VS = 5V, 0V
50
VS = ±15V
AV = 1
50
CL = 0.22µF
OVERSHOOT (%)
60
50
AV = 1
40
AV = 5
30
20
15
LT1366 TPC21
Overshoot vs Load Current
(LT1368/LT1369)
Capacitive Load Handling
(LT1366/LT1367)
OVERSHOOT (%)
10
–10
LT1366/LT1367
–130
LT1366 TPC19
70
VS = ±15V
15
– 80
300
0
VS = ±15V
VOUT = ±1VP-P
RL = 2k
40
OVERSHOOT (%)
FREQUENCY (kHz)
400
Open-Loop Gain
20
INPUT VOLTAGE (µV)
60
CHANNEL SEPARATION (dB)
500
CL = 0.047µF
CL = 0.1µF
30
20
CL = 0.22µF
40
CL = 0.047µF
30
CL = 0.1µF
20
20
0
100
1k
10k
CAPACITIVE LOAD (pF)
10
10
10
AV = 10
0
–10
100k
–5
0
5
LOAD CURRENT (mA)
LT1366 TPC22
CHANGE IN OFFSET VOLTAGE (µV)
SLEW RATE (V/µs)
0.16
0.14
0.12
0.10
0
4
8 12 16 20 24 28 32
TOTAL SUPPLY VOLTAGE (V)
36
LT1366 TPC25
10
THD + Noise vs
Peak-to-Peak Voltage
80
AV = –1
10
60
f = 1kHz
RL = 10k
(ALL CURVES)
S8 PACKAGE
VS = ±15V
1
40
S8 PACKAGE
VS = ±2.5V
20
0
–20
N8 PACKAGE
VS = ±2.5V
–40
0.1
VS = ±1.5V
AV = 1
0.01
VS = ±1.5V
AV = –1
N8 PACKAGE
VS = ±15V
–60
–80
10
LT1366 TPC24
Warm-Up Drift vs Time
0.18
–5
0
5
LOAD CURRENT (mA)
LT1366 TPC23
Slew Rate vs Supply Voltage
0.20
0
–10
10
THD + NOISE (%)
10
0
15 30 45 60 75 90 105 120 135 150
TIME AFTER POWER-UP (SEC)
LT1366 TPC26
0.001
0
1
2
3
VIN(P-P) (V)
VS = ±2.5V
AV = 1
VS = ±2.5V
AV = –1
4
5
LT1366 TPC27
LT1366/LT1367
LT1368/LT1369
U W
TYPICAL PERFORMANCE CHARACTERISTICS
(The data presented here applies to the LT1366/LT1367/LT1368/LT1369 unless otherwise noted.)
Large-Signal Response
(LT1366/LT1367)
THD + Noise vs Frequency
0.1
5mV/DIV
VS = ± 1.5V
VIN = 2VP-P
RL = 10k
5V/DIV
THD + NOISE (%)
1
Small-Signal Response
(LT1366/LT1367)
0V
AV = 1
0.01
AV = –1
VS = ±15V
UNITY-GAIN
0.001
0.01
0.1
1
FREQUENCY (kHz)
VS = ±15V
UNITY-GAIN
100µs/DIV
LT1366 TPC29
2µs/DIV
LT1366 TPC30
10
LT1366 TPC28
U
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APPLICATIONS INFORMATION
Rail-to-Rail Operation
different portions of the input common mode range.
Lateral devices are used in both input stages, eliminating
the need for clamps across the input pins. Each input stage
is trimmed for offset voltage. A complementary output
configuration (Q23 through Q26) is employed to create an
output stage with rail-to-rail swing. The amplifier is fabri-
The LT1366 family differs from conventional op amps in
the design of both the input and output stages. Figure 1
shows a simplified schematic of the amplifier. The input
stage consists of two differential amplifiers, a PNP stage
Q1/Q2 and an NPN stage Q3/Q4, which are active over
V+
D4
I1
D7
D6
D5
Q21
Q17
Q10
Q11
Q5
Q16
V–
V–
V–
V–
IN+
V+
Q1 Q2
D1
IN –
V+
C1
OUT
C2
V+
D2
Q3 Q4
Q6
Q9
Q25
Q26
Q22
Q18
Q13
D3
Q20
Q14 Q15
Q7
Q12
– 300mV
V+
CC
Q8
V+
Q24
Q23
Q19
D8
D7
V–
LT1366 FO1
Figure 1. LT1366 Simplified Schematic Diagram
11
LT1366/LT1367
LT1368/LT1369
U
W
U
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APPLICATIONS INFORMATION
cated on Linear Technology’s proprietary complementary
bipolar process, which ensures very similar DC and AC
characteristics for the output devices Q24 and Q26.
A simple comparator Q5 steers current from current
source I1 between the two input stages. When the input
common mode voltage VCM is near the negative supply,
Q5 is reverse biased, and I1 becomes the tail current for
the PNP differential pair Q1/Q2. At the other extreme,
when VCM is within about 1.3V from the positive supply,
Q5 diverts I1 to the current mirror D3/Q6, which furnishes
the tail current for the NPN differential pair Q3/Q4.
When overdriven, the amplifier draws input current that
exceeds the normal input bias current. Figures 2 and 3
show some typical overdrive currents as a function of
input voltage. The input current must be less than 1mA of
positive overdrive or less than 7mA of negative overdrive,
for the phase reversal protection to work properly. When
the amplifier is severely overdriven, an external resistor
should be used to limit the overdrive current. In addition
to overdrive protection, the amplifier is protected against
ESD strokes up to 4kV on all pins.
110
MEASURED AS A
FOLLOWER
100
90
INPUT BIAS CURRENT (nA)
The collector currents of the two input pairs are combined
in the second stage, consisting of Q7 through Q11. Most
of the voltage gain in the amplifier is contained in this
stage. Differential amplifier Q14/Q15 buffers the output of
the second stage, converting the output voltage to differential currents. The differential currents pass through
current mirrors D4/Q17 and D5/Q16, and are converted to
differential voltages by Q18 and Q19. These voltages are
also buffered and applied to the output Darlington pairs
Q23/Q24 and Q25/Q26. Capacitors C1 and C2 form local
feedback loops around the output devices, lowering the
output impedance at high frequencies.
+
80
–
70
T = 25°C
60
50
T = 85°C
40
T = –55°C
T = 70°C
30
20
10
0
–500
–300
–100 VS 100
300
500
COMMON MODE VOLTAGE RELATIVE TO
POSITIVE SUPPLY (mV)
LT1366 F02
Since the amplifier has two input stages, the input offset
voltage changes depending upon which stage is active.
The input offsets are random, but bounded voltages.
When the amplifier switches between stages, offset voltages may go up, down, or remain flat; but will not exceed
the guaranteed limits. This behavior is illustrated in three
distribution plots of input offset voltage in the Typical
Performance Characteristics section.
Overdrive Protection
Two circuits prevent the output from reversing polarity
when the input voltage exceeds the common mode range.
When the noninverting input exceeds the positive supply
by approximately 300mV, the clamp transistor Q12 (Figure 1) turns on, pulling the output of the second stage low,
which forces the output high. For inputs below the negative supply, diodes D1 and D2 turn on, overcoming the
saturation of the input pair Q1/Q2.
12
Figure 2. Input Bias Current vs Common Mode Voltage
0
–10
INPUT BIAS CURRENT (nA)
Input Offset Voltage
MEASURED AS A FOLLOWER
+
–20
–
–30
–40
–50
T = – 55°C T = 25°C
–60
T = 70°C
T = 85°C
–70
– 80
– 90
–100
–110
–800
–600
– 400
–200
200
VS
COMMON MODE VOLTAGE RELATIVE TO
NEGATIVE SUPPLY (mV)
LT1366 F03
Figure 3. Input Bias Current vs Common Mode Voltage
LT1366/LT1367
LT1368/LT1369
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W
U
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APPLICATIONS INFORMATION
Improved Supply Rejection in the LT1368/LT1369
100mV/DIV
V+
(AC)
100mV/DIV
V+
(AC)
VOUT
20mV/DIV
The tolerance of the external compensation capacitor is
not critical. The plots of Overshoot vs Load Current in the
Typical Performance Characteristics section illustrate the
effect of a capacitive load.
100mV/DIV
The LT1368/LT1369 are variations of the LT1366/LT1367
offering greater supply rejection and lower high frequency
output impedance. The LT1368/LT1369 require a 0.1µF
load capacitance for compensation. The output capacitance forms a filter, which reduces pickup from the supply
and lowers the output impedance. This additional filtering
is helpful in mixed analog/digital systems with common
supplies, or systems employing switching supplies. Filtering also reduces high frequency noise, which may be
beneficial when driving A/D converters.
Figure 4 shows the outputs of the LT1366/LT1368 perturbed by a 200mVP-P 50kHz square wave added to the
positive supply. The LT1368’s power supply rejection is
about ten times greater than that of the LT1366 at 50kHz.
Note the 5-to-1 scale change in the output voltage traces.
VOUT
2µs/DIV
2µs/DIV
LT1366 F04a
Figure 4a. LT1366 Power Supply Rejection Test
LT1366 F04b
Figure 4b. LT1368 Power Supply Rejection Test
U
TYPICAL APPLICATIONS
VCC
Buffering A/D Converters
Figure 5 shows the LT1368 driving an LTC ®1288
2-channel micropower A/D Converter (ADC). The LTC1288
can accommodate voltage references and input signals
equal to the supply rails. The sampling nature of this ADC
eliminates the need for an external sample-and-hold, but
may call for a drive amplifier because of the ADC’s 12µs
settling requirement. The LT1368’s rail-to-rail operation
and low input offset voltage make it well-suited for low
power, low frequency A/D applications. Either the LT1366
or LT1368 could be used for this application. However, for
low frequencies (f < 1kHz) the LT1368 provides better
supply rejection.
1µF
0.1µF
V0
+
1/2 LT1368
–
0.1µF
CS/SHDN
VCC (REF)
CH0
CLK
TO µP
LTC1288
V1
+
CH1
DOUT
GND
DIN
1/2 LT1368
–
0.1µF
LT1366 FO5
Figure 5. 2-Channel Low Power A/D Converter
13
LT1366/LT1367
LT1368/LT1369
U
TYPICAL APPLICATIONS
Precision Low Dropout Regulator
Microprocessors and complex digital circuits frequently
specify tight control of power supply characteristics. The
circuit shown in Figure 6 provides a precise 3.6V, 1A
output from a minimum 3.8V input voltage. The circuit's
nominal operating voltage is 4.75V ±5%. The voltage
reference and resistor ratios determine output voltage
accuracy, while the LT1366’s high gain enforces 0.2% line
and load regulation. Quiescent current is about 1mA and
does not change appreciably with supply or load. All
components are available in surface mount packages.
The regulator’s main loop consists of A1 and a logic level
FET, Q1. The output is fed back to the op amp’s positive
input because of the phase inversion through Q1. The
regulator’s frequency response is limited by Q1’s roll-off
and the phase lead introduced by the output capacitor’s
effective series resistance (ESR). Two pole-zero networks
compensate for these effects. The pole formed with R5
and C2 rolls off the gain set with the feedback network,
while the pole formed with R7 and C3 rolls off A1’s gain
directly, which is the dominant influence on settling time.
The zeros formed with R6 and C2, and R8 and C3 provide
phase boost near the unity-gain crossover, which in-
creases the regulator’s phase margin. Although not directly part of the compensation, R9 decouples the op
amp’s output from Q1’s large gate capacitance.
A second loop provides a foldback current limit. A2
compares the sense voltage across R1 with 50mV referenced to the positive rail. When the sense voltage exceeds
the reference, A2’s output drives Q1’s gate positive via A1.
In current limit, the output voltage collapses and the
current limit LED (D1) turns on causing about 30mV to
drop across R3. A2 regulates Q1’s drain current so that the
deficit between the 50mV reference and the voltage across
R3 is made up across the sense resistor. The reduced
sense voltage is 20mV, which sets the current limit to
about 400mA. As the supply voltage increases, the voltage
across R3 increases, and the current limit folds back to a
lower level. The current limit loop deactivates when the
load current drops below the regulated output current.
When the supply turns on rapidly, C1 bypasses the fold
back circuit allowing the regulator to start-up into a heavy
load.
Q1 does not require a heat sink. When mounted on a type
FR4 PC board, Q1 has a thermal resistance of 50°C/W. At
1.4W worst case dissipation, Q1 can operate up to 80°C.
VIN = 4.75V ±5%
R8
2k
10k
C3
6.8nF
R3
20Ω
R7
13k
–
A1
1/2 LT1366
R9
100Ω
Q1
Si9433DY
1.5k
+
+
50mV
–
C1
10µF
R1
0.05Ω
+
R2
2k
+
R4
10k
C5
47µF
0.1µF
–
A2
1/2 LT1366
D1
+
D2
1N4148
5k
38.5k*
C4
1µF
LT1004-1.2
R5*
20k
C2
6.8nF
R6
6.2k
VOUT = 3.6V
AT 1A
RMIN
1k
+
**
CLOAD
10µF
Q2
2N3904
23.2k
4.75V TO 3.6V LDO AT 1A
*1% METAL FILM
**SET RMIN BASED ON LOAD CHARACTERISTICS
Figure 6. Precision 3.6V, 1A Low Dropout Regulator
14
LT1366 F06
LT1366/LT1367
LT1368/LT1369
U
TYPICAL APPLICATIONS
High-Side Current Source
The wide-compliance current source shown in Figure 7
takes advantage of the LT1366’s ability to measure small
signals near the positive supply rail. The LT1366 adjusts
Q1’s gate voltage to force the voltage across the sense
resistor (RSENSE) to equal the voltage from the supply to
the potentiometer’s wiper. A rail-to-rail op amp is needed
because the voltage across the sense resistor must drop
to zero when the divided reference voltage is set to zero.
Q2 acts as a constant current sink to minimize error in the
reference voltage when the supply voltage varies.
VCC
RSENSE
0.2Ω
0.0033µF
–
100Ω
1/2 LT1366
RP
10k
The circuit delivers 1A at 200mV of sense voltage. With a
5V input supply, the power dissipation is 5W. For operation at 70°C ambient temperature, the MOSFET’s heat sink
must have a thermal resistance of:
θHS = θJA SYSTEM – θJC FET
= (125°C – 70°C)/5W – 1.25°C/W
= 11°C/W –1.25°C/W
= 9.75°C/W
which is easily achievable with a small heat sink. Input
voltages greater than 5V require the use of a larger heat
sink or a reduction of the output current.
1k
LT1004-1.2
input voltage, circuit operation is limited by the LT1366’s
absolute maximum ratings and the output power requirements.
Q1
MTP23P06
+
ILOAD
40k
5V < VCC < 30V
0A < ILOAD < 1A AT VCC = 5V
0mA < ILOAD < 160mA AT VCC = 30V
Q2
2N4340
The circuit’s supply regulation is about 0.03%/V. The
output impedance is equal to the MOSFET’s output impedance multiplied by the op amp’s open-loop gain. Degradations in current-source compliance occur when the voltage across the MOSFET’s on-resistance and the sense
resistor drops below the voltage required to maintain the
desired output current. This condition occurs when
[VCC – VOUT] < [ILOAD • (RSENSE + RON)].
LT1366 F07
Single Supply, 1kHz, 4th Order Butterworth Filter
Figure 7. High-Side Current Source
The circuit can operate over a wide supply range
(5V < VCC < 30V). At low input voltage, circuit operation is
limited by the MOSFET’s gate drive requirements. At high
C1
10,000pF
R1*
29.5k
VIN
An LT1367 is used in Figure 8 to form a 4th order
Butterworth filter. The filter is a simplified state variable
architecture consisting of two cascaded 2nd order sections. Each section uses the 360 degree phase shift around
C2
10,000pF
10,000pF
–
A1
1/4 LT1367
R2*
8.6k
–
A2
1/4 LT1367
+
+
10,000pF
11.8k*
–
A3
1/4 LT1367
21.5k*
–
A4
1/4 LT1367
+
29.5k*
VOUT
+
10k
3.3V
11.8k*
10k
1µF
*1% RESISTORS
LT1366 F08
Figure 8. 4-Pole 1kHz, 3.3V Single Supply, State Variable Filter Using the LT1367
15
LT1366/LT1367
LT1368/LT1369
U
TYPICAL APPLICATIONS
10k
the 2 op amp loop to create a negative summing junction
at A1’s positive input1. The circuit has low sensitivities for
center frequency and Q, which are set with the following
equations:
ω02 = 1/(R1 • C1 • R2 • C2)
V+
2
–
1
1/2 LT1366
3
VIN
+
VOUT
SIGNAL AMP
where,
R1 = 1/(ω0 • Q • C1) and R2 = Q/(ω0 • C2).
1M
+
The DC bias applied to A2 and A4, half supply, is not
needed when split supplies are available. The circuit
swings rail-to-rail in the passband making it an excellent
anti-aliasing filter for ADCs. The amplitude response is flat
to 1kHz then rolls off at 80dB/decade.
7
5
CANCELLATION AMP
1/2 LT1366
–
22pF
1M
6
1366 F10
1James Hahn, “State Variable Filter Trims Predecessor’s Component Count,” Electronics, April
Figure 10. Input Bias Current Cancellation
21, 1982.
180
0
GAIN
144
PHASE
108
72
36
–40
0
–36
–60
–80
100
PHASE (DEG)
GAIN (dB)
–20
VCC
1/2 LT1366
–108
–
RL
–180
10k
1366 F09
Figure 9. Frequency Response of 4th Order Butterworth Filter
16
+
–72
–144
1k
FREQUENCY (Hz)
RP
10k
1366 F11
Figure 11. Rail-to-Rail Potentiometer Buffer
LT1366/LT1367
LT1368/LT1369
U
PACKAGE DESCRIPTION
Dimensions in inches (millimeters) unless otherwise noted.
N8 Package
8-Lead PDIP (Narrow 0.300)
(LTC DWG # 05-08-1510)
0.400*
(10.160)
MAX
8
7
6
5
1
2
3
4
0.255 ± 0.015*
(6.477 ± 0.381)
0.300 – 0.325
(7.620 – 8.255)
0.009 – 0.015
(0.229 – 0.381)
(
+0.035
0.325 –0.015
8.255
+0.889
–0.381
)
0.045 – 0.065
(1.143 – 1.651)
0.130 ± 0.005
(3.302 ± 0.127)
0.065
(1.651)
TYP
0.100 ± 0.010
(2.540 ± 0.254)
0.125
(3.175) 0.020
MIN (0.508)
MIN
0.018 ± 0.003
(0.457 ± 0.076)
N8 1197
*THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.
MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.010 INCH (0.254mm)
17
LT1366/LT1367
LT1368/LT1369
U
PACKAGE DESCRIPTION
Dimensions in inches (millimeters) unless otherwise noted.
S8 Package
8-Lead Plastic Small Outline (Narrow 0.150)
(LTC DWG # 05-08-1610)
0.189 – 0.197*
(4.801 – 5.004)
8
7
6
5
0.150 – 0.157**
(3.810 – 3.988)
0.228 – 0.244
(5.791 – 6.197)
1
0.010 – 0.020
× 45°
(0.254 – 0.508)
0.008 – 0.010
(0.203 – 0.254)
0.053 – 0.069
(1.346 – 1.752)
0°– 8° TYP
0.016 – 0.050
0.406 – 1.270
0.014 – 0.019
(0.355 – 0.483)
*DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
**DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
18
2
3
4
0.004 – 0.010
(0.101 – 0.254)
0.050
(1.270)
TYP
SO8 0996
LT1366/LT1367
LT1368/LT1369
U
PACKAGE DESCRIPTION Dimensions in inches (millimeters) unless otherwise noted.
S Package
14-Lead Plastic Small Outline (Narrow 0.150)
(LTC DWG # 05-08-1610)
0.337 – 0.344*
(8.560 – 8.738)
14
13
12
11
10
9
8
0.228 – 0.244
(5.791 – 6.197)
0.150 – 0.157**
(3.810 – 3.988)
1
0.010 – 0.020
× 45°
(0.254 – 0.508)
0.008 – 0.010
(0.203 – 0.254)
2
3
4
5
6
0.053 – 0.069
(1.346 – 1.752)
0.004 – 0.010
(0.101 – 0.254)
0° – 8° TYP
0.016 – 0.050
0.406 – 1.270
0.014 – 0.019
(0.355 – 0.483)
7
0.050
(1.270)
TYP
*DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
**DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
S14 0695
19
LT1366/LT1367
LT1368/LT1369
U
TYPICAL APPLICATION
Instrumentation Amplifier
V+
0.1µF
+
10M
GUARD
1/4
LT1367
A1A
100k
10k
–
RF
102k
+
RG
11.3k
+
+
1/4
LT1367
A1C
1/4
LT1367
A1B
200Ω
INPUTS
OUTPUT
–
–
10M
–
RG
11.3k
10M
22pF
GUARD
( )
R
GAIN = 10 1 + F = 100
RG
BW = 30kHz
–
1/4
LT1367
A1D
RF
102k
10k
100k
1366 TA03
+
RELATED PARTS
PART
DESCRIPTION
COMMENTS
LT1078/LT1079
Dual/Quad 55µA Max, Single Supply, Precision Op Amps
Input/Output Common Mode Includes Ground, 70µV VOS(MAX)
and 2.5µV/°C Drift (Max), 200kHz GBW, 0.07V/µs Slew Rate
LTC1152
Rail-to-Rail Input, Rail-to-Rail Output, Zero-Drift Amplifier
High DC Accuracy, 10µV VOS(MAX), 100nV/°C Drift, 1MHz
GBW, 1V/µs Slew Rate, Supply Current 2.2mA (Max),
Single Supply, Can Be Configured for C-LoadTM Operation
LT1178/LT1179
Dual/Quad 17µA Max, Single Supply, Precision Op Amps
Input/Output Common Mode Includes Ground, 70µV VOS(MAX)
and 4µV/°C Drift (Max), 85kHz GBW, 0.04V/µs Slew Rate
LT1211/LT1212
Dual/Quad 14MHz, 7V/µs, Single Supply, Precision Op Amps
Input Common Mode Includes Ground, 275µV VOS(MAX) and
6µV/°C Drift (Max), Supply Current 1.8mA per Op Amp (Max)
LT1495/LT1496
1.5µA, Rail-to-Rail Input/Output Dual/Quad
375µV VOS(MAX), 2µV/°C Drift (Max), “Over-the-Top” Input
C-Load is a trademark of Linear Technology Corporation
20
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417 ● (408) 432-1900
FAX: (408) 434-0507● TELEX: 499-3977 ● www.linear-tech.com
1366fa LT/TP 0298 REV A 2K • PRINTED IN USA
 LINEAR TECHNOLOGY CORPORATION 1995