ETC OV3630

Omni
ision
Advanced Information
Preliminary Datasheet
®
OV3630 Color CMOS QXGA (3.2 MPixel) CAMERACHIPTM with OmniPixel® Technology
General Description
Applications
The OV3630 (color) CAMERACHIPTM is a high performance
3.2 mega-pixel CMOS image sensors for digital still image
and video/still camera products.
The device incorporates a 2048 x 1536 (QXGA) image
array and an on-chip 10-bit A/D converter capable of
operating at up to 15 frames per second (fps) in full
resolution mode. Proprietary sensor technology utilizes
advanced algorithms to cancel Fixed Pattern Noise
(FPN), eliminate smearing, and drastically reduce
blooming. The control registers allow for flexible control of
timing, polarity, and CameraChip operation, which, in turn,
allows the engineer a great deal of freedom in product
design.
Pb
Note: The OV3630 uses a lead-free
package.
Features
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Optical black level calibration
Line optical black level output capability
Video or snapshot operations
Programmable/Auto Exposure and Gain Control
Programmable/Auto White Balance Control
Horizontal and vertical sub-sampling (4:2 and 4:2)
High frame rate output for auto focus mode
Programmable image windowing
Zooming and panning functions
Variable frame rate control
On-chip R/G/B Channel and Luminance Average
Counter
Internal/External frame synchronization
SCCB slave interface
Power-on reset and power-down modes
Ordering Information
Product
OV03630-VL5A (Color, Lead-free)
Version 1.2, August 4, 2005
Package
36-pin CSP2
•
•
•
•
•
•
•
Cellular phones
Digital still cameras
PC camera/dual mode
Video conference equipment
Machine vision
Security cameras
Biometrics
Key Specifications
QXGA
XGA
HF
Analog
Core
Power Supply
I/O
Power
Active
Standby
Requirements
QXGA
Electronics
XGA
Exposure
HF
Output Format
Lens Size
Chief Ray Angle (CRA)
QXGA
Maximum
Image
XGA
Transfer Rate
HF
Sensitivity
S/N Ratio
Dynamic Range
Scan Mode
Pixel Size
Dark Current
Fixed Pattern Noise
Image Area
Package Dimensions
Array Size
2048 x 1536
1024 x 768
1024 x 192
2.8VDC + 5%
1.8VDC + 5%
1.7 ~ 3.3V
TBD
TBD
Up to 1567:1
Up to 799:1
Up to 223:1
10-bit digital RGB Raw data
1/3"
TBD
15 fps
30 fps
90 fps
TBD
TBD
TBD
Progressive
2.2 µm x 2.2 µm
TBD
TBD
4.54 mm x 3.41 mm
6085µm X 6315µm
Figure 1 OV3630 Pin Diagram (Top View)
A1
A2
A3
A4
A5
A6
PWDN
HVDD
SGND
OGND
SIO_C
HREF
B5
B6
B1
B2
B3
B4
RESET
NVDD
SVDD
OVDD
C1
C2
SIO_D VSYNC
C5
FREX EXP_STB
C6
DOVDD PCLK
OV3630
D1
D2
D5
D6
D0
D1
D9
D8
E1
E2
E5
E6
D2
NC
D7
D6
F1
F2
F3
F4
F5
F6
D3
NC
EGND
XVCLK
DVDD
D5
G4
G5
G6
G1
G2
G3
EVDD
NC
NC
PVDD DOGND
Proprietary to OmniVision Technologies
D4
1
Color CMOS QXGA (3.2 MPixel) OmniPixel® CAMERACHIP™
OV3630
Omni
ision
Functional Description
Figure 2 shows the functional block diagram of the OV3630 image sensor. The OV3630 includes:
•
Image Sensor Array (2064 x 1560 active image array)
•
Analog Amplifier
•
•
– Gain Control
10-Bit A/D Converter
Channel Balance
•
•
– Balance Control
Black Level Compensation
Timing Generator and Control Logic
–
Frame Exposure Mode Timing
–
Frame Rate Timing
– Frame Rate Adjust
SCCB Interface
Channel Average Calculator
Digital Video Port
•
•
•
Figure 2 Functional Block Diagram
D[9:0]
10-Bit
A/D
AMP
Column Sample/Hold
Channel
Balance
Black Level
Compensation
Digital
Video
Port
PCLK
HREF
Row Select
VSYNC
Image Array
(2064 x 1560)
Gain
Control
Balance
Control
Control
Register
Bank
PLL
XVCLK
2
Timing Generator and Control Logic
RESET
PWDN
FREX
Proprietary to OmniVision Technologies
EXP_STB
SCCB Slave
Interface
SIO_C
SIO_D
Version 1.2, August 4, 2005
Omni
Functional Description
ision
Image Sensor Array
10-Bit A/D Converter
The OV3630 sensor is a 1/3-inch CMOS imaging device.
The sensor contains 3,219,840 pixels. Figure 3 shows the
color filter layout.
1 G R G R
G R
B G B G
G R
2063
2061
2062
2060
2059
5
4
3
2
1
0
Column
R
o 0 B G B G B G
w
2058
Figure 3 Sensor Array Region Color Filter Layout
The signal is then digitized by the on-chip 10-bit ADC. It
can operate at 28 MHz and is fully synchronous to the
pixel clock. The actual conversion rate is determined by
the frame rate.
Channel Balance
B G
Dummy
G R G R
Dummy
2 B G B
G B G
B
G B G B
G
Dummy
3 G R G
R G R
G
R G R G
R
Dummy
4
The digitized signals are then balanced with a channel
balance block. In this block, the Red/Blue channel gain is
increased or decreased to match Green channel
luminance level.
5
6
7
Optical
Black
8
Balance Control
Channel balance can be done manually by the user or by
the internal automatic white balance (AWB) controller.
9
10
11
12 B G
B G B G
13 G R G R
14 B G B
G R
B G B G
G R
B G
G R G R
G B G
B
G B G B
15 G R G
R G R
G
16 B G B
G B G
B
17 G R G
R G R
G
R G R G
R
Dummy
Dummy
G
Dummy
R G R G
R
Dummy
G B G B
G
1540
Active
Lines
1554
B G
1555
G R G R
B G B G
1556
B G
1557
G R G R
1558
B G
1559
G R G R
G R
B G B G
G R
B G B G
G R
B G B G
G R
B G B G
G R
B G
Dummy
G R G R
Dummy
B G B G
G R
B G
G R G R
B G
Dummy
G R G R
Dummy
The color filters are in a Bayer pattern. The primary color
BG/GR array is arranged in line-alternating fashion. Of the
3,219,840 pixels, 3,170,352 are active. The other pixels
are used for black level calibration and interpolation.
The sensor array design is based on a field integration
read-out system with line-by-line transfer and an
electronic shutter with a synchronous pixel read-out
scheme.
Analog Amplifier
Black Level Compensation
After the pixel data has been channel balanced, black
level calibration can be applied before the data is output.
The black level calibration block subtracts the average
signal level of optical black pixels to compensate for the
dark current in the pixel output. Black level calibration can
be disabled by the user.
Windowing
The OV3630 allows the user to define window size or
region of interest (ROI), as required by the application.
Window size setting (in pixels) ranges from 2 x 4 to
2056 x 1542 (QXGA), 2 x 2 to 1028 x 774 (XGA), or
1028 x 192 (HF), and can be anywhere inside the
2056 x 1542 boundary. Note that modifying window size
or window position does not alter the frame or pixel rate.
The windowing control merely alters the assertion of the
HREF signal to be consistent with the programmed
horizontal and vertical ROI. The default window size is
2048 x 1536. Refer to Figure 4 and registers HREFST,
HREFEND, VSTRT, VEND, COM1, and REG32 for
details.
When the column sample/hold circuit has sampled one
row of pixels, the pixel data will shift out one-by-one into
an analog amplifier.
Gain Control
The amplifier gain can either be programmed by the user
or controlled by the internal automatic gain control circuit
(AGC).
Version 1.2, August 4, 2005
Proprietary to OmniVision Technologies
3
Color CMOS QXGA (3.2 MPixel) OmniPixel® CAMERACHIP™
OV3630
Figure 4 Windowing
Omni
ision
High Frame (HF) Rate Mode
Column
Start
Column
End
HREF
R Column
o
w
HREF
Row Start
Display
Window
The OV3630 image array sensor can also operate at a
High Frame rate (HF) mode. In this mode, the OV3630
averages the B and G pixels (see Figure 6) in lines 1 and
3 to output line 1, G and R pixels of lines 10 and 12 to
output line 2, B and G pixels of lines 17 and 19 to output
line 3, G and R pixels of lines 26 and 28 to output line 4,
etc.
This mode enables up to 90 fps output using a 27.3 MHz
system clock so it is effective for high frame rate
application.
Row End
Sensor Array
Boundary
Figure 6 High Frame Rate Sub-Sampling Mode
Zooming and Panning
The OV3630 provides zooming and panning modes. The
user can select this mode under XGA/HF mode timing.
Zoom ratio for XGA is 2:1 of QXGA. Zoom ratio for HF is
2:1 of QXGA in the horizontal direction and 8:1 of QXGA
in the vertical direction. Register ZOOMSH (0x49) and
ZOOMSL[1:0] (0x48) defines the vertical line start point.
Register ZOOMW[2:0] (0x34) defines the horizontal start
point.
Sub-sampling Mode
The OV3630 supports two sub-sampling modes. Each
sub-sampling mode has different resolution and maximum
frame rate. These modes are described in the following
sections.
XGA Mode
The OV3630 can be programmed to output 1024 x 768
(XGA) sized images for applications where higher
resolution image capture is not required. In this mode,
both horizontal and vertical pixels will be sub-sampled
with an aspect ratio of 4:2 as shown in Figure 5.
Figure 5 XGA Sub-Sampling Mode
i+8
i+7
i+6
i+4
i+5
i+3
i+2
G B
33
B
32
G R G R
G B
31
B
30
G R G R
G B
B
28
G R G R
G B
G B
27
B
26
G R G R
G B
G B
25
B
24
G R G R
G B
G B
23
B
22
G R G R
G B
G B
21
B
20
G R G R
19
B
18
G R G R
G B
G B
G B
G B
17
B
16
G R G R
G B
G B
15
B
14
G R G R
G B
G B
13
B
12
G R G R
G B
G B
G B
11
B
10
G R G R
G B
G B
9
B
G R G R
G B
B
G
B G
B G
7
B
G R
G R
G R
6
G R G R
5
B
4
G R G R
3
B
2
G R G R
1
B
n+3
n+4
B
G
B G
B G
n+5
G R
G R
G R
n+6
n+7
Skipped Pixels
Proprietary to OmniVision Technologies
G B
G B
G B
G B
G B
G B
Line 2
G
G
G
G R
G B
G R
G B
G
G R
G B
G R
G B
G
G R
G B
G R
G
G R
G B
G R
G
G R
G B
G R
Line 3
G R
G B
G R
G
G R
G B
G R
G
G R
G B
G R
G
G R
G B
G R
G
G R
G B
G R
Line 4
G R
G B
G R
G
G R
G B
G R
G
G R
G B
G R
G
G R
G B
G R
G
G R
G B
G R
G
G R
G B
G R
G B
29
G B
G R
G B
8
n+2
4
G B
i+9
n+1
G R G R
i
Row n
B
34
i+1
Column
35
G
G R
G B
Line 1
G
Data Out
Version 1.2, August 4, 2005
Omni
Functional Description
ision
Maximum Exposure Line Limits
OV3630 maximum exposure line values are:
•
QXGA - 1567 lines
Register setting: 0x61E = {REG45[5:0] (0x45),
AEC[7:0] (0x10), REG04[1:0] (0x04)}, meaning
REG45[5:0] (0x45) = 0x01, AEC[7:0] (0x10) = 0x87,
REG04[1:0] (0x04)= 0x03
•
XGA - 799 lines
Register setting: 0x31E = {REG45[5:0] (0x45),
AEC[7:0] (0x10), REG04[1:0] (0x04)}, meaning
REG45[5:0] (0x45) = 0x00, AEC[7:0] (0x10) = 0xC7,
REG04[1:0] (0x04)= 0x03
•
HF - 223 lines
Register setting: 0xDE = {REG45[5:0] (0x45),
AEC[7:0] (0x10), REG04[1:0] (0x04)}, meaning
REG45[5:0] (0x45) = 0x00, AEC[7:0] (0x10) = 0x37,
REG04[1:0] (0x04)= 0x03
Timing Generator and Control Logic
In general, the timing generator controls the following:
•
Frame Exposure Mode Timing
•
Frame Rate Timing
•
Frame Rate Adjust
Frame Exposure Mode Timing
The OV3630 supports frame exposure mode. Typically,
the frame exposure mode must work with the aid of an
external shutter.
The frame exposure pin, FREX (pin C1), is the frame
exposure mode enable pin and the EXP_STB pin (pin C2)
serves as the sensor's exposure start trigger. When the
external master device asserts the FREX pin high, the
sensor array is quickly pre-charged and stays in reset
mode until the EXP_STB pin goes low (sensor exposure
time can be defined as the period between EXP_STB low
and shutter close). After the FREX pin is pulled low, the
video data stream is then clocked to the output port in a
line-by-line manner. After completing one frame of data
output, the OV3630 will output continuous live video data
unless in single frame transfer mode. Figure 21 shows the
detailed timing and Table 11 shows the timing
specifications for this mode.
Frame Rate Timing
Default frame timing is illustrated in Figure 14, Figure 15
(if PIDL = 0x30), Figure 16 (if PIDL ≠ 0x30), Figure 17,
Figure 18 (if PIDL = 0x30), Figure 19 (if PIDL ≠ 0x30), and
Figure 20. Refer to Table 1 for the actual pixel rate at
different frame rates.
Version 1.2, August 4, 2005
Table 1
Frame/Pixel Rates in QXGA Mode
Frame Rate (fps)
PCLK (MHz)
15
10
5
2.5
55.2
36.8
18.4
9.2
Frame Rate Adjust
The OV3630 offers three methods for frame rate
adjustment:
•
Clock prescaler: (see “CLKRC” on page 20)
By changing the system clock divide ratio, the frame
rate and pixel rate will change together. This method
can be used for dividing the frame/pixel rate by: 1/2,
1/3, 1/4 … 1/64 of the input clock rate.
•
Line adjustment: (see “REG2A” on page 23 and see
“FRARL” on page 23)
By adding a dummy pixel timing in each line after
active pixel output, the frame rate can be changed
while leaving the pixel rate as is.
•
Vertical sync adjustment:
By adding dummy line periods to the vertical sync
period (see “ADDVSL” on page 23 and see
“ADDVSH” on page 23), the frame rate can be
altered while the pixel rate remains the same.
SCCB Interface
The OV3630 provides an on-chip SCCB serial control port
that allows access to all internal registers, for complete
control and monitoring of OV3630 operation.
Refer to OmniVision Technologies Serial Camera Control
Bus (SCCB) Specification for detailed usage of the serial
control port.
Slave Operation Mode
The OV3630 can be programmed to operate in slave
mode (default is master mode).
When used as a slave device, COM7[3], CLKRC[6], and
COM2[2] register bits should be set to "1" and the OV3630
will use PWDN and RESET pins as vertical and horizontal
synchronization triggers supplied by a master device. The
master device must provide the following signals:
1.
System clock MCLK to XVCLK pin
2.
Horizontal sync MHSYNC to RESET pin
3.
Vertical frame sync MVSYNC to PWDN pin
See Figure 7 for slave mode connections and Figure 8 for
detailed timing considerations.
Proprietary to OmniVision Technologies
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OV3630
Color CMOS QXGA (3.2 MPixel) OmniPixel® CAMERACHIP™
Figure 7 Slave Mode Connection
Omni
ision
To initiate hardware power-down, the PWDN pin (pin A1)
must be tied to high (+2.8VDC). When this occurs, the
OV3630 internal device clock is halted and all internal
counters are reset.
D[9:0]
SLHS
MHSYNC
SLVS
MVSYNC
XVCLK
Executing a software power-down through the SCCB
interface suspends internal circuit activity but does not
halt the device clock. All register content is maintained in
this mode.
MCLK
OV3630
Digital Video Port
Master
Device
Figure 8 Slave Mode Timing
MSB/LSB Swap
T frame
MVSYNC
T VS
T line
MHSYNC
T HS
Tclk
MCLK
NOTE:
1) THS > 6 TCLK, Tvs > TLINE
2) TLINE = 2320 x TCLK (QXGA); TLINE = 1332 x TCLK (XGA);
TLINE = 1332 x TCLK (HF)
3) TFRAME = 1568 x TLINE (QXGA); TFRAME = 800 x TLINE (XGA)
TFRAME = 224 x TLINE (HF)
Channel Average Calculator
The OV3630 provides average output level data for the
R/G/B channels along with frame-averaged luminance
level. Access to the data is provided via the SCCB
interface.
Reset
The OV3630 includes a RESET pin (pin B1) that forces a
complete hardware reset when it is pulled high
(+2.8VDC). The OV3630 clears all registers and resets
them to their default values when a hardware reset
occurs. A reset can also be initiated through the SCCB
interface.
Power Down Mode
The OV3630 has a 10-bit digital video port. The MSB and
LSB can be swapped with the control registers. Figure 9
shows some examples of connections with external
devices.
Figure 9 Connection Examples
MSB D9
D8
D7
D6
D5
D4
D3
D2
D1
LSB D0
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
LSB D9
D8
D7
D6
D5
D4
D3
D2
D1
MSB D0
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
OV3630
External
Device
OV3630
External
Device
Default 10-bit Connection
Swap 10-bit Connection
MSB D9
D8
D7
D6
D5
D4
D3
D2
D1
LSB D0
D7
D6
D5
D4
D3
D2
D1
D0
LSB D9
D8
D7
D6
D5
D4
D3
D2
D1
MSB D0
OV3630
External
Device
OV3630
Default 8-bit Connection
D0
D1
D2
D3
D4
D5
D6
D7
External
Device
Swap 8-bit Connection
Two methods are available to place the OV3630 into
power-down mode: hardware power-down and SCCB
software power-down.
6
Proprietary to OmniVision Technologies
Version 1.2, August 4, 2005
Omni
Functional Description
ision
Line/Pixel Timing
The specifications shown in Table 10 apply for
DVDD = +1.8 V, DOVDD = +2.8 V, TA = 25°C, sensor
working at 15 fps in QXGA resolution, external loading =
30 pF.
The OV3630 digital video port can be programmed to
work in either master or slave mode.
In both master and slave modes, pixel data output is
synchronous with PCLK (or XVCLK if port is a slave),
HREF, and VSYNC. The default PCLK edge for updated
data is the negative edge but may be programmed using
register COM10[4] for the positive edge. Basic line/pixel
output timing and pixel timing specifications are shown in
Figure 13 and Table 10.
Also, using register COM10[5] (0x15), PCLK output can
be gated by the active video period defined by the HREF
signal. See Figure 10 for details.
Figure 10 PCLK Output Only at Valid Pixels
PCLK
Data updated on falling edge,
latch data at next rising edge
of PCLK
HREF
PCLK
Data updated on rising edge,
latch data at next falling edge
of PCLK
VSYNC
Version 1.2, August 4, 2005
Pixel Output Pattern
Table 2 shows the output data order from the OV3630.
The data output sequence following the first HREF and
after VSYNC is: B0,0 G0,1 B0,2 G0,3… B0,2046 G0,2047.
After the second HREF the output is G1,0 R1,1 G1,2 R1,3…
G1,2046 R1,2047…, etc.
Table 2
Data Pattern
R/C
0
1
2
3
...
2046
2047
0
B0,0
G0,1
B0,2
G0,3
...
B0,2046
G0,2047
1
G1,0
R1,1
G1,2
R1,3
...
G1,2046
R1,2047
2
B2,0
G2,1
B2,2
G2,3
...
B2,2046
G2,2047
3
G3,0
R3,1
G3,2
R3,3
...
G3,2046
R3,2047
.
.
.
.
1534 B1534,0 G1534,1 B1534,2 G1534,3
B1534,2046 G1534,2047
1535 G1535,0 R1535,1 G1535,2 R1535,3
G1535,2046 R1535,2047
Proprietary to OmniVision Technologies
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OV3630
Color CMOS QXGA (3.2 MPixel) OmniPixel® CAMERACHIP™
Omni
ision
Pin Description
Table 3
8
Pin Description
Pin Number
(see Table 4)
Name
Pin Type
Function/Description
A1
PWDN
Input (0)a
A2
HVDD
Analog
Sensor high reference - connect to ground using a 0.1 µF capacitor
A3
SGND
Power
Ground for sensor array
A4
OGND
Power
Ground for internal regulator
A5
SIO_C
Input
SCCB serial interface clock input
A6
HREF
Output
B1
RESET
Input (0)
B2
NVDD
Analog
Sensor low reference - connect to ground using a 0.1 µF capacitor
B3
SVDD
Analog
Sensor internal reference - connect to ground using a 0.1 µF capacitor
B4
OVDD
Power
2.8 V supply for the internal regulator
B5
SIO_D
I/O
SCCB serial interface data I/O
Vertical synchronization output
Power down mode enable, active high
Horizontal reference output
Chip reset, active high
B6
VSYNC
Output
C1
FREX
Input (0)
Snapshot trigger - use to activate a snapshot sequence
C2
EXP_STB
Input (0)
Snapshot Exposure Start Trigger
0:
Sensor starts exposure (only effective in snapshot mode)
1:
Sensor stays in reset mode
C5
DOVDD
Power
2.8 V supplyb for digital video port
C6
PCLK
Output
Pixel clock output
D1
D0
Output
Video port output bit[0]
D2
D1
Output
Video port output bit[1]
D5
D9
Output
Video port output bit[9]
D6
D8
Output
Video port output bit[8]
E1
D2
Output
Video port output bit[2]
E2
NC
–
E5
D7
Output
Video port output bit[7]
E6
D6
Output
Video port output bit[6]
F1
D3
Output
Video port output bit[3]
F2
NC
–
F3
EGND
Power
F4
XVCLK
Input
F5
DVDD
Analog
Digital internal reference - connect to ground using a 0.1 µF capacitor
F6
D5
Output
Video port output bit[5]
G1
EVDD
Power
1.8 V supply
G2
NC
–
No connect
No connect
No connect
No connect
Ground
System clock input
G3
NC
–
G4
PVDD
Analog
PLL internal reference - connect to ground using a 0.1 µF capacitor
G5
DOGND
Power
Ground for digital video port
G6
D4
Output
Video port output bit[4]
a.
Input (0) represents an internal pull-down resistor.
b.
Contact your local OmniVision FAE for 1.8V I/O support.
Proprietary to OmniVision Technologies
Version 1.2, August 4, 2005
Omni
Pin Description
ision
Figure 11 Pinout Diagram
A1
A2
A3
A4
A5
A6
PWDN
HVDD
SGND
OGND
SIO_C
HREF
B5
B6
B1
B2
B3
B4
RESET
NVDD
SVDD
OVDD
C1
C2
C5
FREX EXP_STB
Table 4
D1
D2
D0
D1
SIO_D VSYNC
C6
DOVDD PCLK
OV3630
D5
D6
D9
D8
E1
E2
E5
E6
D2
NC
D7
D6
F1
F2
F3
F4
F5
F6
D3
NC
EGND
XVCLK
DVDD
D5
G4
G5
G6
G1
G2
G3
EVDD
NC
NC
PVDD DOGND
D4
Ball Matrix
1
2
3
4
5
6
A
PWDN
HVDD
SGND
OGND
SIO_C
HREF
B
RESET
NVDD
SVDD
OVDD
SIO_D
VSYNC
C
FREX
EXP_STB
DOVDD
PCLK
D
D0
D1
D9
D8
E
D2
NC
D7
D6
F
D3
NC
EGND
XVCLK
DVDD
D5
G
EVDD
NC
NC
PVDD
DOGND
D4
Version 1.2, August 4, 2005
Proprietary to OmniVision Technologies
9
Color CMOS QXGA (3.2 MPixel) OmniPixel® CAMERACHIP™
OV3630
Omni
ision
Electrical Characteristics
Table 5
Absolute Maximum Ratings
Ambient Storage Temperature
-40ºC to +95ºC
Supply Voltages (with respect to Ground)
VDD-A
4.5V
VDD-C
3V
VDD-IO
4.5V
All Input/Output Voltages (with respect to Ground)
-0.3V to VDD-IO+0.5V
Lead-free Temperature, Surface-mount process
245ºC
ESD Rating, Human Body model
2000V
NOTE:
Exceeding the Absolute Maximum ratings shown above invalidates all AC and DC electrical specifications and may
result in permanent device damage.
Table 6
DC Characteristics (-20°C < TA < 70°C)
Symbol
Parameter
Min
Typ
Max
Unit
Supply
VDD-A
Supply voltage (OVDD)
2.66
2.8
2.94
V
VDD-C
Supply voltage (EVDD)
1.71
1.8
1.89
V
VDD-IO
Supply voltage (DOVDD)a
1.7
2.8
3.3
V
IDDA-A
Active (Operating) Current (OVDD)b
TBD
mA
IDDA-C
Active (Operating) Current (EVDD)b
TBD
mA
TBD
mA
TBD
mA
IDDA-IO
IDDS-SCCB
IDDS-PWDN
Active (Operating) Current
(DOVDD)b
Standby Currentb
TBD
TBD
µA
0.8
V
Digital Inputs
VIL
Input voltage LOW
VIH
Input voltage HIGH
CIN
Input capacitor
2
V
10
pF
Digital Outputs (standard loading 25 pF, 1.2 KΩ to 2.8 V)
VOH
Output voltage HIGH
VOL
Output voltage LOW
2.2
V
0.6
V
Serial Interface Inputs
10
VIL
SIO_C and SIO_D
-0.5
0
1
V
VIH
SIO_C and SIO_D
2.5
2.8
VDD-IO + 0.5
V
a.
1.8V I/O is supported. Contact your OmniVision FAE for further details.
b.
VDD-A = 2.8V, VDD-C = 1.8V, and VDD-IO = 2.8V
IDDS-SCCB refers to a SCCB-initiated Standby, while IDDS-PWDN refers to a PWDN pin-initiated Standby
Proprietary to OmniVision Technologies
Version 1.2, August 4, 2005
Omni
Electrical Characteristics
ision
Table 7
AC Characteristics (TA = 25°C, VDD-A = 2.8V)
Symbol
Parameter
Min
Typ
Max
Unit
ADC Parameters
B
Analog bandwidth
28
MHz
DLE
DC differential linearity error
0.5
LSB
ILE
DC integral linearity error
1
LSB
Settling time for hardware reset
<1
ms
Settling time for software reset
<1
ms
Settling time for XGA/QXGA mode change
<1
ms
<300
ms
Settling time for register setting
Table 8
Timing Characteristics
Symbol
Parameter
Min
Typ
6
24
Max
Unit
Oscillator and Clock Input
fOSC
Frequency (XVCLK)
tr, tf
Clock input rise/fall time
Clock input duty cycle
Version 1.2, August 4, 2005
45
50
Proprietary to OmniVision Technologies
MHz
5
ns
55
%
11
Color CMOS QXGA (3.2 MPixel) OmniPixel® CAMERACHIP™
OV3630
Omni
ision
Timing Specifications
Figure 12 SCCB Timing Diagram
tF
t HIGH
tR
t HD:DAT
t SU:DAT
t LOW
SIO_C
t SU:STA
t HD:STA
tSU:STO
SIO_D
IN
t BUF
tAA
t DH
SIO_D
OUT
Table 9
SCCB Timing Specifications
Symbol
12
Parameter
Min
Typ
Max
Unit
400
KHz
fSIO_C
Clock Frequency
tLOW
Clock Low Period
1.3
µs
tHIGH
Clock High Period
600
ns
tAA
SIO_C low to Data Out valid
100
tBUF
Bus free time before new START
1.3
µs
tHD:STA
START condition Hold time
600
ns
tSU:STA
START condition Setup time
600
ns
tHD:DAT
Data-in Hold time
0
µs
tSU:DAT
Data-in Setup time
100
ns
tSU:STO
STOP condition Setup time
600
ns
tR, tF
SCCB Rise/Fall times
tDH
Data-out Hold time
Proprietary to OmniVision Technologies
900
300
50
ns
ns
ns
Version 1.2, August 4, 2005
Omni
Timing Specifications
ision
Figure 13 QXGA, XGA, and HF Mode Line/Pixel Output Timing
tp
t pr
t pf
PCLK or
MCLK
t dphf
t dphr
HREF
t hd
t su
D[9:0]
P 1023/2047
Invalid
Data
P0
P1
P2
P 1022/2046
P 1023/2047
t dpd
Table 10
Pixel Timing Specification
Symbol
Parameter
Min
Typ
Max
Unit
tp
PCLK period
18.3
ns
tpr
PCLK rising time
3.5
ns
tpf
PCLK falling time
2.2
ns
tdphr
PCLK negative edge to HREF rising edge
0
5
ns
tdphf
PCLK negative edge to HREF negative edge
0
5
ns
tdpd
PCLK negative edge to data output delay
0
5
ns
tsu
Data bus setup time
15
ns
thd
Data bus hold time
8
ns
Version 1.2, August 4, 2005
Proprietary to OmniVision Technologies
13
OV3630
Color CMOS QXGA (3.2 MPixel) OmniPixel® CAMERACHIP™
Omni
ision
Figure 14 QXGA Frame Timing
1568 x tLINE
VSYNC
4 x tLINE
32760 tP
tLINE = 2320 tP
32472 tP
272 tP
HREF
2048 tP
184 tP
80 tP
HSYNC
D[9:0]
Invalid Data
P0 - P2047
Row 0
Row 1
Row 2
Row 1535
Figure 15 XGA Frame Timing (if PIDL = 0x30)
800 x tLINE
VSYNC
4 x tLINE
7106 tP
tLINE = 1160 tP
25510 tP
136 tP
HREF
1024 tP
98 tP
40 tP
HSYNC
D[9:0]
Invalid Data
P0 - P1023
Row 0
Row 1
Row 2
Row 767
Figure 16 XGA Frame Timing (if PIDL ≠ 0x30)
790 x tLINE
VSYNC
4 x tLINE
7060 tP
tLINE = 1152 tP
13804 tP
128 tP
HREF
1024 tP
100 tP
48 tP
HSYNC
D[9:0]
Invalid Data
P0 - P1023
Row 0
14
Proprietary to OmniVision Technologies
Row 1
Row 2
Row 767
Version 1.2, August 4, 2005
Omni
Timing Specifications
ision
Figure 17 XGA Zoom Frame Timing
800 x tLINE
VSYNC
4 x tLINE
8262 tP
tLINE = 1332 tP
29342 tP
308 tP
HREF
1024 tP
184 tP
80 tP
HSYNC
D[9:0]
Invalid Data
P0 - P1023
Row 0
Row 1
Row 2
Row 767
Figure 18 HF Mode Frame Timing (if PIDL = 0x30)
224 x tLINE
VSYNC
4 x tLINE
7106 tP
tLINE = 1160 tP
25510 tP
136 tP
HREF
1024 tP
98 tP
40 tP
HSYNC
D[9:0]
Invalid Data
P0 - P1023
Row 0
Version 1.2, August 4, 2005
Row 1
Row 2
Row 191
Proprietary to OmniVision Technologies
15
OV3630
Color CMOS QXGA (3.2 MPixel) OmniPixel® CAMERACHIP™
Omni
ision
Figure 19 HF Mode Frame Timing (if PIDL ≠ 0x30)
224 x tLINE
VSYNC
4 x tLINE
7060 tP
tLINE = 1152 tP
25324 tP
128 tP
HREF
1024 tP
100 tP
48 tP
HSYNC
D[9:0]
Invalid Data
P0 - P1023
Row 0
Row 1
Row 2
Row 191
Figure 20 HF Mode Zoom Frame Timing
224 x tLINE
VSYNC
4 x tLINE
8262 tP
tLINE = 1332 tP
29342 tP
308 tP
HREF
1024 tP
184 tP
80 tP
HSYNC
D[9:0]
Invalid Data
P0 - P1023
Row 0
16
Proprietary to OmniVision Technologies
Row 1
Row 2
Row 191
Version 1.2, August 4, 2005
Omni
Timing Specifications
ision
Figure 21 Frame Exposure Mode Timing with EXP_STB Asserted
Shutter Open
Shutter
FREX
t des
tdef
EXP_STB
t pre
Exposure Time
Sensor
Precharge
Sensor Timing
t dfvr
Turn ON Flash
t dfvf
t dvsc
VSYNC
t dvh
tdhv
HREF
D[9:0]
Row X
Table 11
Row 0
Row 1
No following live video
frame if set to transfer
single frame
Row 1535
Frame Exposure Timing Specifications
Symbol
Min
Typ
Max
Unit
2320 (QXGA)
tp
tline
1160 (XGA) (if PIDL = 0x30)
1152 (XGA) (if PIDL ≠ 0x30)
tp
tvs
4
tline
tdfvr
8
9
tp
tdfvf
4
tline
tdvsc
2
tline
tdhv
tdvh
32472 (QXGA)
tp
29342 (XGA)
tp
32760 (QXGA)
tp
8262 (XGA)
tp
tdhso
0
ns
tdef
20
tp
tdes
NOTE
2300 (QXGA)
tp
1300 (XGA)
tp
1) FREX must stay high long enough to ensure the entire sensor has been reset.
2) Shutter must be closed no later then 4640 tp (2664 tp for XGA) after VSYNC falling edge.
Version 1.2, August 4, 2005
Proprietary to OmniVision Technologies
17
Color CMOS QXGA (3.2 MPixel) OmniPixel® CAMERACHIP™
OV3630
Omni
ision
Register Set
Table 12 provides a list and description of the Device Control registers contained in the OV3630. The device slave addresses
for the OV3630 are 60 for write and 61 for read.
Table 12
Address
(Hex)
Device Control Register List
Register
Name
Default
(Hex)
R/W
Description
AGC Gain Control
Bit[7:0]: Gain setting
• Range: 1x to 32x
00
GAIN
00
RW
Gain = (Bit[7]+1) x (Bit[6]+1) x (Bit[5]+1) x (Bit[4]+1) x
(1+Bit[3:0]/16)
Note: Set COM8[2] = 0 to disable AGC.
01
BLUE
80
RW
02
RED
80
RW
Digital AWB Blue Gain Control
• Range: 0 to 2x ([00] to [FF])
Digital AWB Red Gain Control
• Range: 0 to 2x ([00] to [FF])
Common Control 1
Bit[7:6]:
03
COM1
0F
(0A in XGA,
06 in HF)
RW
Bit[5:4]:
Bit[3:2]:
Bit[1:0]:
Dummy frame control
00: Not used
01: Allow 1 dummy frame
10: Allow 3 dummy frames
11: Allow 7 dummy frames
Reserved
Vertical window end line control 2 LSBs
Vertical window start line control 2 LSBs
Register 04
18
Bit[7]:
Bit[6]:
Bit[5]:
Bit[4]:
Bit[3]:
Bit[2]:
Bit[1:0]:
Horizontal mirror
Vertical flip
Reserved
VREF[0]
HREF[0]
Reserved
AEC lower 2 bits – AEC[1:0]
04
REG04
00
RW
05
BAVG
00
RW
B Channel Average
06
GbAVG
00
RW
G Channel Average - Picked G pixels in the same line with B pixels.
07
GrAVG
00
RW
G Channel Average - Picked G pixels in the same line with R pixels.
08
RAVG
00
RW
R Channel Average
Proprietary to OmniVision Technologies
Version 1.2, August 4, 2005
Omni
Register Set
ision
Table 12
Address
(Hex)
Device Control Register List
Register
Name
Default
(Hex)
R/W
Description
Common Control 2
Bit[7:5]:
Bit[4]:
Bit[3]:
Bit[2]:
Bit[1:0]:
Reserved
Sleep mode enable
0: Normal mode
1: Sleep mode
Reserved
Pin PWDN/RESET used as SLVS/SLHS
Output drive current select
00: Weakest
01: Double capability
10: Double capability
11: Triple drive current
09
COM2
01
RW
0A
PIDH
36
R
Product ID Number MSB (Read only)
0B
PIDL
30
R
Product ID Number LSB (Read only)
Common Control 3
0C
COM3
38
RW
Bit[7]:
Bit[6]:
Bit[5:1]:
Bit[0]:
Reserved
Swap MSB and LSB at the output port
Reserved
Snapshot option
0: Enable live video output after snapshot
sequence
1:
Output single frame only
Common Control 4
0D
COM4
06
RW
Bit[7:3]:
Bit[2]:
Reserved
Clock output power-down pin status
0: Tri-state data output pin at power-down
1: Data output pin hold at last status before
power-down
Bit[1]:
Data output pin status selection at power-down
0: Tri-state VSYNC, PCLK, HREF and HSYNC
pins upon power-down
1:
Bit[0]:
VSYNC, PCLK, HREF and HSYNC hold on last
states before power-down
Reserved
Common Control 5
0E
COM5
Version 1.2, August 4, 2005
01
RW
Bit[7]:
Bit[6:0]:
Reserved - always set to "1"
Reserved
Proprietary to OmniVision Technologies
19
OV3630
Table 12
Address
(Hex)
Color CMOS QXGA (3.2 MPixel) OmniPixel® CAMERACHIP™
Omni
ision
Device Control Register List
Register
Name
Default
(Hex)
R/W
Description
Common Control 6
Bit[7:4]:
Bit[3]:
0F
COM6
43
RW
Bit[2]:
Bit[1]:
Bit[0]:
Reserved
Night mode enable
0: Disable
1: Enable
Reserved
Reset enable/disable when sensor working mode
changes
0: Sensor timing not reset when mode changes
1: Sensor timing resets when mode changes
Reserved
Automatic Exposure Control - AEC[9:2]
MSB 6 bits, AEC[15:10], is in REG45[5:0] and LSB 2 bits, AEC[1:0],
is in register REG04[1:0].
10
AEC
43
RW
AEC[15:0]:Exposure time
TEX = tLINE x AEC[15:0]
Note: The maximum exposure time is 1 frame period even if TEX
is longer than 1 frame period.
Clock Rate Control
11
CLKRC
00
RW
Bit[7:6]:
Bit[5:0]:
Reserved
Clock divider
CLK = XVCLK/(decimal value of CLKRC[5:0] + 1)
Common Control 7
12
COM7
00
Bit[7]:
SRST
1: Initiates soft reset. All register are set to factory
default values after which the chip resumes
normal operation
Bit[6:4]:
Resolution selection
000: QXGA (full size) mode
001: High Frame rate (HF) mode
100: XGA mode
Master/Slave mode selection
0: Master mode
1: Slave mode
Zoom mode
Reserved
RW
Bit[3]:
Bit[2]:
Bit[1:0]:
20
Proprietary to OmniVision Technologies
Version 1.2, August 4, 2005
Omni
Register Set
ision
Table 12
Address
(Hex)
Device Control Register List
Register
Name
Default
(Hex)
R/W
Description
Common Control 8
Bit[7]:
Bit[6:3]:
Bit[2]:
13
COM8
C7
RW
Bit[1]:
Bit[0]:
AEC speed selection
0: Normal
1: Faster AEC correction
Reserved
AGC auto/manual control selection
0: Manual
1: Auto
AWB auto/manual control selection
0: Manual
1: Auto
Exposure control
0: Manual
1: Auto
Common Control 9
Bit[7:5]:
14
COM9
40
RW
Bit[4:3]:
Bit[2]:
Bit[1]:
Bit[0]:
Version 1.2, August 4, 2005
AGC gain ceiling
000: 2x
001: 4x
010: 8x
011: 16x
100: 32x
101: Reserved
110: Reserved
111: Reserved
Reserved
VSYNC drop option
0: VSYNC is always output
1: VSYNC is dropped if frame data is dropped
Frame data drop
0: Disable data drop
1: Drop frame data if exposure is not within
tolerance. In AEC mode, data is normally
dropped when data is out of range.
Reserved
Proprietary to OmniVision Technologies
21
OV3630
Table 12
Address
(Hex)
Color CMOS QXGA (3.2 MPixel) OmniPixel® CAMERACHIP™
Omni
ision
Device Control Register List
Register
Name
Default
(Hex)
R/W
Description
Common Control 10
Bit[7]:
Bit[6]:
Bit[5]:
Bit[4]:
15
COM10
00
RW
Bit[3]:
Bit2]:
Bit[1]:
Bit[0]:
16
GREEN
80
RW
17
HREFST
10
RW
18
HREFEND
90
(50 in XGA, HF)
RW
19
VSTRT
01
(00 in XGA, HF)
RW
1A
VEND
C1
(60 in XGA,
18 in HF)
RW
Reserved
HREF pin output swap
0: HREF
1: HSYNC
PCLK output selection
0: PCLK always output
1: PCLK output qualified by HREF
PCLK edge selection
0: Data is updated at the falling edge of PCLK
(user can latch data at the next rising edge of
PCLK)
1: Data is updated at the rising edge of PCLK
(user can latch data at the next falling edge of
PCLK)
HREF output polarity
0: Output positive HREF
1: Output negative HREF, HREF negative for valid
data
Reserved
VSYNC polarity
0: Positive
1: Negative
HSYNC polarity
0: Positive
1: Negative
Digital AWB Green Gain Control
• Range: 0 to 2x ([00] to [FF])
Horizontal Window Start 8 MSBs (3 LSBs in REG32[2:0])
Bit[10:0]: Select beginning of horizontal window, each LSB
represents two pixels
Horizontal Window End 8 MSBs (3 LSBs in REG32[5:3])
Bit[10:0]: Select end of horizontal window, each LSB
represents two pixels
Vertical Window Line Start 8 MSBs (2 LSBs in register COM1[1:0])
Bit[9:0]:
Selects the start of the vertical window, each LSB
represents two scan lines.
Vertical Window Line End 8 MSBs (2 LSBs in register COM1[3:2])
Bit[9:0]:
Selects the end of the vertical window, each LSB
represents two scan lines.
Pixel Shift
Bit[7:0]:
22
1B
PSHFT
00
RW
1C
MIDH
7F
R
Proprietary to OmniVision Technologies
Pixel delay count - provides a method to fine tune the
output timing of the pixel data relative to the HREF
pulse. It physically shifts the video data output time
in units of pixel clock counts. The largest delay count
is [FF] and is equal to 255 x PCLK.
Manufacturer ID Byte – High
(Read only = 0x7F)
Version 1.2, August 4, 2005
Omni
Register Set
ision
Table 12
Device Control Register List
Address
(Hex)
Register
Name
Default
(Hex)
R/W
1D
MIDL
A2
R
Manufacturer ID Byte – Low
1E-23
RSVD
XX
–
Reserved
24
AEW
78
RW
Luminance Signal High Range for AEC/AGC operation
AEC/AGC value decreases in auto mode when average luminance
is greater than AEW[7:0]
25
AEB
68
RW
Luminance Signal Low Range for AEC/AGC operation
AEC/AGC value increases in auto mode when average luminance
is less than AEB[7:0]
Description
(Read only = 0xA2)
Fast Mode Large Step Range Thresholds - effective only in
AEC/AGC fast mode
26
VV
D4
RW
27-29
RSVD
XX
–
Bit[7:4]: 4 MSBs of high threshold
Bit[3:0]: 4 MSBs of low threshold
AEC/AGC may change in larger steps when the luminance average
is greater than the high threshold or less than the low threshold.
Reserved
Register 2A
Bit[7:4]:
2A
REG2A
00
RW
Bit[3:2]:
Bit[1:0]:
Line interval adjust value MSB 4 bits, LSBs in
register FRARL[7:0]
HSYNC timing end point adjustment MSB 2 bits
HSYNC timing start point adjustment MSB 2 bits
Line Interval Adjustment Value LSB 8 bits
2B
FRARL
00
RW
2C
RSVD
XX
–
The frame rate will be adjusted by changing the line interval. Each
LSB will add 1/2320 Tframe in QXGA. Each 2 LSBs will add 1/1160
Tframe in XGA and HF modes (if PIDL = 0x30) or 1/1152 Tframe in
XGA and HF modes (if PIDL ≠ 0x30) to the frame period.
Reserved
VSYNC Pulse Width LSB 8 bits
2D
ADDVSL
00
RW
Bit[7:0]:
Line periods added to VSYNC width. Default
VSYNC output width is 4 x tline. Each LSB count will
add 1 x tline to the VSYNC active period.
VSYNC Pulse width MSB 8 bits
2E
ADDVSH
00
RW
Bit[7:0]:
Line periods added to VSYNC width. Default
VSYNC output width is 4 x tline. Each MSB count will
add 256 x tline to the VSYNC active period.
2F
YAVG
00
RW
Luminance Average - this register will auto update
Average luminance is calculated from the B/Gb/Gr/R channel
average as follows:
B/Gb/Gr/R channel average =
(BAVG[7:0] + GbAVG[7:0] + GrAVG[7:0] +RAVG[7:0]) x 0.25
30
HSDY
08
RW
HSYNC Position and Width Start LSB 8 bits
This register and REG2A[1:0] define the HSYNC start position.
Each LSB will shift HSYNC starting point by a 2 pixel period.
Version 1.2, August 4, 2005
Proprietary to OmniVision Technologies
23
OV3630
Table 12
Color CMOS QXGA (3.2 MPixel) OmniPixel® CAMERACHIP™
Omni
ision
Device Control Register List
Address
(Hex)
Register
Name
Default
(Hex)
R/W
31
HEDY
30
RW
Description
HSYNC Position and Width End LSB 8 bits
This register and REG2A[3:2] define the HSYNC end position.
Each LSB will shift HSYNC end point by a 2 pixel period.
Register 32
Bit[7:6]:
32
REG32
36
(09 in XGA, HF)
RW
Bit[5:3]:
Bit[2:0]:
Pixel clock divide option
00: No effect on PCLK
01: No effect on PCLK
10: PCLK frequency divide by 2
11: PCLK frequency divide by 4
Horizontal window end position LSBs
Horizontal window start position LSBs
33
RSVD
XX
–
Reserved
34
ZOOMW
00
RW
35-44
RSVD
XX
–
45
REG45
00
RW
46
FLL
00
RW
Frame Length Adjustment LSBs
Each bit will add 1 horizontal line timing in frame
47
FLH
00
RW
Frame Length Adjustment MSBs
Each bit will add 256 horizontal line timing in frame
Zoom Horizontal Start Point
Bit[7:3]:
Bit[2:0]:
Reserved
Zoom horizontal start point
Reserved
REG45
Bit[7:6]:
Bit[5:0]:
Reserved
AEC[15:10], AEC MSBs
Common Control 19
48
ZOOMSL
00
–
49
ZOOMSH
00
RW
4A-74
RSVD
00
–
Bit[7:2]:
Bit[1:0]:
Reserved
Zoom mode vertical start window 2 LSBs (see
register ZOOMSH[7:0] (0x49) for 8 MSBs)
Zoom Mode Vertical Window Start Point 8 MSBs
Reserved
NOTE: All other registers are factory-reserved. Please contact OmniVision Technologies for reference register settings.
24
Proprietary to OmniVision Technologies
Version 1.2, August 4, 2005
Omni
Package Specifications
ision
Package Specifications
The OV3630 uses a 36-pin Chip Scale Package 2 (CSP2). Refer to Figure 22 for package information, Table 13 for package
dimensions and Figure 23 for the array center on the chip.
Note: For OVT devices that are lead-free, all part marking letters are
lower case. Underlining the last digit of the lot number indicates CSP2 is
used.
Figure 22 OV3630 Package Specifications
A
1
2
3
S1
4
5
J1
6
S2
6
5
4
3
2
1
A
A
B
B
J2
C
C
wxyz
abcd
D
B
E
E
F
F
G
G
Center of BGA (die) =
Center of the package
Top View (Bumps Down)
D
Bottom View (Bumps Up)
Glass
Part Marking Code:
- OVT Product Version
w
- Year the part is assembled
x
- Month the part is assembled
y
- Wafer number
z
abcd - Last four digits of lot number
Die
C3
C2
C
C1
Table 13
CSP2 Package Dimensions
Parameter
Symbol
Min
Nominal
Max
Unit
Package Body Dimension X
A
6060
6085
6110
µm
Package Body Dimension Y
B
6290
6315
6340
µm
Package Height
C
845
905
965
µm
Ball Height
C1
150
180
210
µm
Package Body Thickness
C2
680
725
770
µm
Thickness of Glass Surface to Wafer
C3
425
445
465
µm
Ball Diameter
D
320
350
380
µm
Total Pin Count
N
36 (4 NC)
Pin Count X-axis
N1
6
Pin Count Y-axis
N2
7
Pins Pitch X-axis
J1
800
µm
Pins Pitch Y-axis
J2
800
µm
Edge-to-Pin Center Distance Analog X
S1
1013
1043
1073
µm
Edge-to-Pin Center Distance Analog Y
S2
728
758
788
µm
Version 1.2, August 4, 2005
Proprietary to OmniVision Technologies
25
OV3630
Color CMOS QXGA (3.2 MPixel) OmniPixel® CAMERACHIP™
Omni
ision
Sensor Array Center
Figure 23 OV3630 Sensor Array Center
A1
A2
A3
A4
A5
A6
Array Center
(31.4 µm, 283.8 µm)
4540.8 µm
3405.6 µm
Sensor
Array
OV3630
Package Center
(0, 0)
TOP VIEW
NOTES: 1. This drawing is not to scale and is for reference only.
2. As most optical assemblies invert and mirror the image, the chip is typically mounted
with pins A1 to A6 oriented down on the PCB.
26
Proprietary to OmniVision Technologies
Version 1.2, August 4, 2005
Omni
Package Specifications
ision
IR Reflow Ramp Rate Requirements
OV3630 Lead-Free Packaged Devices
Note: For OVT devices that are lead-free, all part marking letters are
lower case
Figure 24 IR Reflow Ramp Rate Requirements
300.0
Z1
Z2
Z3
Z4
Z5
Z6
Z7
end
280.0
260.0
240.0
220.0
Temperature (∞C )
200.0
180.0
160.0
140.0
120.0
100.0
80.0
60.0
40.0
20.0
0.0
0.0
-22
-2
0.6
18
38
1.1
58
78
1.6
98
118
2.2
138
158
2.8
178
198
3.3
218
238
258
3.9
278
298
318
338
358 369
Time (sec)
Table 14
Reflow Conditions
Condition
Exposure
Average Ramp-up Rate (30°C to 217°C)
Less than 3°C per second
> 100°C
Between 330 - 600 seconds
> 150°C
At least 210 seconds
> 217°C
At least 30 seconds (30 ~ 120 seconds)
Peak Temperature
Greater than or equal to 245°C
Cool-down Rate (Peak to 50°C)
Less than 6°C per second
Time from 30°C to 255°C
No greater than 390 seconds
Version 1.2, August 4, 2005
Proprietary to OmniVision Technologies
27
OV3630
Color CMOS QXGA (3.2 MPixel) OmniPixel® CAMERACHIP™
Omni
ision
Note:
•
All information shown herein is current as of the revision and publication date. Please refer
to the OmniVision web site (http://www.ovt.com) to obtain the current versions of all
documentation.
•
OmniVision Technologies, Inc. reserves the right to make changes to their products or to
discontinue any product or service without further notice (It is advisable to obtain current product
documentation prior to placing orders).
•
Reproduction of information in OmniVision product documentation and specifications is
permissible only if reproduction is without alteration and is accompanied by all associated
warranties, conditions, limitations and notices. In such cases, OmniVision is not responsible
or liable for any information reproduced.
•
This document is provided with no warranties whatsoever, including any warranty of
merchantability, non-infringement, fitness for any particular purpose, or any warranty
otherwise arising out of any proposal, specification or sample. Furthermore, OmniVision
Technologies Inc. disclaims all liability, including liability for infringement of any proprietary
rights, relating to use of information in this document. No license, expressed or implied, by
estoppels or otherwise, to any intellectual property rights is granted herein.
•
‘OmniVision’ and ‘OmniPixel’ are trademarks of OmniVision Technologies, Inc. All other trade,
product or service names referenced in this release may be trademarks or registered trademarks of
their respective holders. Third-party brands, names, and trademarks are the property of their
respective owners.
For further information, please feel free to contact OmniVision at [email protected]
OmniVision Technologies, Inc.
1341 Orleans Drive
Sunnyvale, CA USA
(408) 542-3000
28
Proprietary to OmniVision Technologies
Version 1.2, August 4, 2005
Omni
ision
TM
REVISION CHANGE LIST
Document Title:
OV3630 Datasheet
Version: 1.0
DESCRIPTION OF CHANGES
Initial Release
Omni
ision
TM
REVISION CHANGE LIST
Document Title:
OV3630 Datasheet
Version: 1.1
DESCRIPTION OF CHANGES
The glass of the CSP2 package used was changed from 500µm to 400µm. As a result, the following changes were made to version 1.0:
•
In Table 13 on page 23, changed Min, Nominal, and Max specifications for the Package
Height (C) parameter to “845”, “905”, and “965”, respectively.
•
In Table 13 on page 23, changed Min, Nominal, and Max specifications for the Package
Body Thickness (C2) parameter to “680”, “725”, and “770”, respectively.
•
In Table 13 on page 23, changed Min, Nominal, and Max specifications for the Thickness
of Glass Surface to Wafer (C3) parameter to “425”, “445”, and “465”, respectively.
•
In Table 6 on page 10, changed Min and Max specifications for Supply Voltage
(DOVDD)a parameter from “2.5” and “VDD-A+0.3V” to “1.7” and “3.3”, respectively.
•
In the table under Key Specifications on page 1, changed the specification for Power
Supply (I/O) from “2.8VDC + 5%” to “1.7 ~ 3.3V”
Omni
ision
TM
REVISION CHANGE LIST
Document Title:
OV3630 Datasheet
Version: 1.2
DESCRIPTION OF CHANGES
The following changes were made to version 1.1:
•
In the Channel Balance section on page 3, changed the first line from “The amplified
signals are then ...” to “The digitized signals are then ...”
•
In the Channel Balance section on page 3, deleted “and gamma correction is performed”
from the last line of the paragraph.
•
In the Black Level Compensation section on page 3, changed the first line from “After the
pixel data has been digitized, black level ...” to “After the pixel data has been channel
balanced, black level ...”
•
Under Power Down Mode section (2nd column) on page 6, changed the last line of the last
paragraph of the section from “... All register content is maintained in mode” to “... All
register content is maintained in this mode”
•
In Table 12 on page 19, changed description of register bit COM4[1] from:
Bit[1]:
Data output pin status selection at power-down
0: Tri-state VSYNC, PCLK, HREF and CHSYNC pins upon power-down
1:
VSYNC, PCLK, HREF and CHSYNC hold on last states before power-down
to:
Bit[1]:
Data output pin status selection at power-down
0: Tri-state VSYNC, PCLK, HREF and HSYNC pins upon power-down
1:
•
VSYNC, PCLK, HREF and HSYNC hold on last states before power-down
In Table 12 on page 23, changed description for register VV (0x26) from:
Fast Mode Large Step Range Thresholds - effective only in AEC/AGC fast mode
Bit[7:4]: High threshold
Bit[3:0]: Low threshold
to:
Fast Mode Large Step Range Thresholds - effective only in AEC/AGC fast mode
Bit[7:4]: 4 MSBs of high threshold
Bit[3:0]: 4 MSBs of low threshold
•
In Table 12 on page 22, changed description for register bit COM10[6] (0x15) from
Reserved to:
Bit[6]:
•
HREF pin output swap
0:
HREF
1:
HSYNC
On page 14, changed title of Figure 15 from “XGA Frame Timing” to “XGA Frame
Timing (if PIDL = 0x30)
Omni
ision
TM
DESCRIPTION OF CHANGES (CONTINUED)
•
On page 14, changed the following callouts in Figure 15: “8262 tP” to “7106 tP”,
“1332 tP” to “1160 tP”, “29342 tP” to “25510 tP”, “184 tP” to “98 tP”, “308 tP” to “136 tP”,
and “80 tP” to “40 tP”
•
On page 14, added Figure 16, XGA Frame Timing (if PIDL ≠ 0x30)
•
On page 15, added Figure 17, XGA Zoom Frame Timing
•
On page 15, changed title of Figure 18 (previously Figure 16) from “HF Frame Timing” to
“HF Frame Timing (if PIDL = 0x30)”
•
On page 15, changed the following callouts in Figure 18: “8262 tP” to “7106 tP”,
“1332 tP” to “1160 tP”, “29342 tP” to “25510 tP”, “184 tP” to “98 tP”, “308 tP” to “136 tP”,
and “80 tP” to “40 tP”
•
On page 16, added Figure 19, HF Mode Frame Timing (if PIDL ≠ 0x30)”
•
On page 16, added Figure 20, HF Mode Zoom Frame Timing
•
Under Frame Rate Timing subsection in column 1 on page 5, changed the first sentence
from “Default frame timing is illustrated in Figure 14, Figure 15, and Figure 16” to
“Default frame timing is illustrated in Figure 14, Figure 15 (if PIDL = 0x30), Figure 16 (if
PIDL ≠ 0x30), Figure 17, Figure 18 (if PIDL = 0x30), Figure 19 (if PIDL ≠ 0x30), and
Figure 20”
•
In Table 12 on page 22, changed last line in the description of register VV (0x26) from
“AEC/AGC may change in larger steps when luminance average is greater than VV[7:4]
or less than VV[3:0]” to “AEC/AGC may change in larger steps when the luminance
average is greater than the high threshold or less than the low threshold.”
•
Under Windowing section on page 3, changed text from “... Window size setting (in
pixels) ranges from 2 x 4 to 2064 x 1540 (QXGA), 2 x 2 to 1032 x 772 (XGA), or
1032 x 192 (HF), and can be anywhere inside the 2064 x 1540 boundary” to “Window
size setting (in pixels) ranges from 2 x 4 to 2056 x 1542 (QXGA), 2 x 2 to 1028 x 774
(XGA), or 1028 x 192 (HF), and can be anywhere inside the 2056 x 1542 boundary”
•
In Table 12 on page 20, changed description for register CLKRC (0x11) from:
Bit[7]:
Bit[6]:
Reserved
Digital video port master/slave selection
0:
Master mode, sensor provides PCLK
1:
Slave mode, external PCLK input from XCLK1 pin
to:
Bit[7:6]: Reserved
Omni
ision
TM
DESCRIPTION OF CHANGES (CONTINUED)
•
In Table 12 on page 23, changed description for register FRAFL (0x2B) from:
to:
The frame rate will be adjusted by changing the line interval. Each LSB will add 1/2320 Tframe in
QXGA and 1/1332 Tframe in XGA mode to the frame period.
The frame rate will be adjusted by changing the line interval. Each LSB will add 1/2320 Tframe in
QXGA. Each 2 LSBs will add 1/1160 Tframe in XGA and HF modes (if PIDL = 0x30) or 1/1152 Tframe
in XGA and HF modes (if PIDL ≠ 0x30) to the frame period.
•
In Table 11 on page 17, changed Typ specification for tline from “1332 (XGA)” to “1160
(XGA) (if PIDL = 0x30) 1152 (XGA) (if PIDL ≠ 30)
•
Under Key Specifications on page 1, changed specifications for Active Power
Requirements from “< 110 mWa” to “TBD”
•
Under Key Specifications on page 1, changed specifications for Standby Power
Requirements from “10µA” to “TBD”
•
Under Key Specifications on page 1, deleted table footnote “@ 15 fps, QXGA, without I/
O power consumption - needs to be verified”
•
In Power Down Mode subsection on page 6 (second column), deleted “The current draw is
less than 10 µA in this mode” and “The current requirements drop to less than 1 mA in this
mode.”
•
In Table 6 on page 10, changed Typ specifications for Active Operating Current (IDDA-A),
Active Operating Current (IDDA-C), Active Operating Current (IDDA-IO), and Standby
Current (IDDS-SCCB and IDDS-PWDN) to “TBD”
•
In Table 6 on page 10, changed Max specification for Standby Current (IDDS-SCCB and
IDDS-PWDN) to “TBD”