ETC CS5361/D

CS5361
Battery Charger
Buck Controller
Features
• Switching Regulator Controller
– Synchronous Buck Regulator Topology for High Efficiency
– Top Side P–Channel Allows High Input Voltage and
Requires No Charge Pump
– Pulse–by–Pulse Inner Control Loop for Fast Response
– Programmable Peak Current Limit
– True Current Soft Start
– Clamped Gate–to–Source Voltage
• Oscillator
– Constant Frequency Design
– 100 kHz to 500 kHz Adjustable Frequency
• System Power Management
– Programmable UVLO
– 2.0 µA Sleep Mode Current (Typical)
– Bias Mode Uses Top Switch to Connect Battery to Load
– 4.2 V ± 0.8% Reference Output
– Thermal Shutdown
 Semiconductor Components Industries, LLC, 2001
May, 2001 – Rev. 8
1
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SO–16
D SUFFIX
CASE 751B
16
1
PIN CONNECTIONS AND
MARKING DIAGRAM
1
ENABLE/UVLO
OSC
VREF(IN)
LGND
ICOMP
VREF
IAVG
VCOMP
16
5361
YYWWA
The CS5361 is a high voltage step down controller that provides a
simple way to build a battery charger suited for various types of
batteries. With an operating range of up to 40 V, it can be used to
charge a multiple number of cells from a DC voltage, as is supplied by
high AC–DC adapter voltages. Proprietary I2 architecture ensures full
control over both Average and Peak charging currents. Independent
voltage loop allows for precision regulation of the battery voltage.
Average current outer control loop provides tight regulation and easy
loop compensation while pulse by pulse inner control provides for fast
response.
The CS5361 is designed to provide a high performance,
full–featured battery charger that is simple to use. A 4.2 V reference
with 0.8% tolerance can be used to implement 1.0% accurate output
voltages. It also features an additional pulse–by–pulse current limit
input to allow for fast output current control.
The CS5361 operates over a 7.0 V to 40 V range and is available in a
16 lead surface mount narrow body.
GATE(H)
VCC
GATE(L)
PGND
IS+
IS–
IPEAK
VFB
A
= Assembly Location
YY, Y
= Year
WW, W = Work Week
ORDERING INFORMATION
Device
Package
Shipping
CS5361GD16
SO–16
48 Units/Rail
CS5361GDR16
SO–16
2500 Tape & Reel
Publication Order Number:
CS5361/D
CS5361
Q3
VIN
18.5 V
to 24.5 V
CIN
10 µ
1.0 µF
R3
40.2 k 1%
C5
R7
VCC
OSC
330 k C3
Rc
0.1 µ
C1
VOUT
16.8 V
GATE(H)
Q1
ICOMP
0.022 µ
CS5361
L1
RSENSE
33 µH
0.05 Ω ± 1%
1.0 k
C2
100 p
VCOMP
Q2
GATE(L)
D1
R4
C4
VREF(IN)
0.1 µ
R5
4.12 k ± 1%
R6
6.04 k 1%
VREF
EN/UVL
12.7 k 1%
IS+
R1
75 k
± 0.1%
IS–
IAVG
IPEAK
CO
10 µ
VFB
R2
24.9 k
± 0.1%
Shutdown
Figure 1. Application Diagram, 16.8 V/2.0 A Four Cell Lithium–Ion Battery Charger with High Side Current Sensing
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2
CS5361
ABSOLUTE MAXIMUM RATINGS*
Rating
Operating Junction Temperature
Lead Temperature Soldering:
Reflow: (SMD styles only) (Note 1.)
Storage Temperature Range
ESD Susceptibility (Human Body Model)
Value
Unit
150
°C
230 peak
°C
–65 to +150
°C
2.0
kV
1. 60 second maximum above 183°C.
*The maximum package power dissipation must be observed.
ABSOLUTE MAXIMUM RATINGS
Pin Name
Pin Symbol
VMAX
VMIN
ISOURCE
ISINK
IC Power Input
VCC
40 V
–0.3 V
N/A
2.0 A Peak
50 mA DC
Positive Current Sense Input
IS+
40 V
–0.3 V
1.0 mA
1.0 mA
Negative Current Sense Input
IS–
40 V
–0.3 V
1.0 mA
1.0 mA
Shutdown and UVLO Input
Enable/UVLO
6.0 V
–0.3 V
1.0 mA
10 mA
Average Current Loop Set Point
IAVG
6.0 V
–0.3 V
1.0 mA
1.0 mA
Peak Current Loop Set Point
IPEAK
6.0 V
–0.3 V
1.0 mA
1.0 mA
Voltage Feedback Input
VFB
6.0 V
–0.3 V
1.0 mA
1.0 mA
Reference Voltage Input
VREF(IN)
6.0 V
–0.3 V
1.0 mA
1.0 mA
Voltage Loop Compensation Pin
VCOMP
6.0 V
–0.3 V
1.0 mA
1.0 mA
High–Side FET Driver
GATE(H)
40 V
–0.3 V
–2.0 V for 50 ns
2.0 A Peak
200 mA DC
2.0 A Peak
200 mA DC
Low–Side FET Driver
GATE(L)
15 V
–0.3 V
–2.0 V for 50 ns
2.0 A Peak
200 mA DC
2.0 A Peak
200 mA DC
Current Loop Compensation Pin
ICOMP
6.0 V
–0.3 V
1.0 mA
1.0 mA
Power Ground
PGND
0V
0V
2.0 A Peak
200 mA DC
N/A
Logic Ground
LGND
0V
0V
200 mA DC
N/A
Reference Voltage Output
VREF
6.0 V
–0.3 V
50 mA
50 mA
Oscillator Pin
OSC
6.0 V
–0.3 V
10 mA
10 mA
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3
CS5361
ELECTRICAL CHARACTERISTICS (0°C < TA < 70°C; 0°C < TJ < 125°C; 7.0 V < VCC < 30 V; CGATE(H) = CGATE(L) =
1.0 nF, CREF = 0.1 µF, CVCC = 0.1 µF, CICOMP = 0.1 µF; unless otherwise specified.)
Test Conditions
Characteristic
Min
Typ
Max
Unit
Voltage Error Amplifier
VFB Bias Current
VFB = 0 V
–
0.1
0.27
µA
VCOMP Source Current
VCOMP = 0.2 V to 3.3 V; VFB = 0.9 V
68
100
170
µA
VCOMP Sink Current
VCOMP = 0. 8 to 3.3 V; VFB = 1.1 V
60
100
160
µA
Open Loop DC Gain
Note 2.
60
80
100
dB
0.6
1.2
2.1
mA/V
Transconductance (Gm)
–
Output Impedance
Note 2.
1.4
8.3
47.6
MΩ
PSRR @ 1.0 kHz
Note 2.
60
85
–
dB
CMRR @ 1.0 kHz
Note 2.
80
110
–
dB
Input Voltage Offset
1.0 V to 5.0 V
–5.0
–
6.5
mV
VCOMP Max Voltage
VREF(IN) = 3.3 V, VFB = 3.2 V
3.9
5.0
6.5
V
VCOMP Min Voltage
VREF(IN) = 3.3 V, VFB = 3.4 V
–
0.1
0.2
V
GATE(H) and GATE(L)
High Voltage (AC)
Note 2.
VCC – 0.5
VCC
–
V
Low Voltage (AC)
Note 2.
–
0
0.5
V
Rise Time
For VCC > 10 V: Note 2.
1.0 V < GATE(L) < 3.0 V,
VCC – 8.0 V < GATE(H) < VCC – 1.0 V;
For 7.0 V < VCC < 10 V:
1.0 V < GATE(L) < VCC – 1.0 V,
1.0 V < GATE(H) < VCC 1.0 V
–
40
80
ns
Fall Time
For VCC > 10 V: Note 2.
3.0 V > GATE(L) > 1.0 V,
VCC – 1.0 V > GATE(H) < VCC – 8.0 V;
For 7.0 V < VCC < 10 V:
VCC – 1.0 V > GATE(L) < 1.0 V,
VCC – 1.0 V > GATE(H) > 1.0 V
–
40
80
ns
GATE(H) to GATE(L) Delay
VCC – GATE(H) < 2.0 V, GATE(L) > 2.0 V
Note 2.
40
80
110
ns
GATE(L) to GATE(H) Delay
GATE(L) < 2.0 V, VCC – GATE(H) > 2.0 V
Note 2.
15
60
80
ns
GATE(L) Clamp to GND
–
4.0
5.0
6.0
V
GATE(H) Clamp to VCC
–
–14
–12
–10
V
–
VCC – 0.7
VCC – 1.0
V
20
50
100
kΩ
GATE(H) Sleep Clamp
IGATE(H) = 100 µA
GATE(L) Resistance to GND
–
GATE(H) Bias Clamp
IGATE(H) = 10 µA to GND in Bias mode
13
16
20
V
GATE(H) Bias Current
GATE(H) = VCC – 5.0 V
3.0
10
20
µA
2. Guaranteed by design, not 100% production tested.
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CS5361
ELECTRICAL CHARACTERISTICS (continued) (0°C < TA < 70°C; 0°C < TJ < 125°C; 7.0 V < VCC < 30 V; CGATE(H) = CGATE(L) =
1.0 nF, CREF = 0.1 µF, CVCC = 0.1 µF, CICOMP = 0.1 µF; unless otherwise specified.)
Characteristic
Test Conditions
Min
Typ
Max
Unit
Oscillator
Switching Frequency
960 kΩ from OSC to GND
85
100
115
kHz
Switching Frequency
330 kΩ from OSC to GND
255
300
345
kHz
Switching Frequency
185 kΩ from OSC to GND
425
500
575
kHz
Bias Threshold Positive
–
2.5
2.75
3.0
V
Bias Threshold Negative
–
2.25
2.5
2.75
V
Bias Threshold Hysteresis
–
150
250
350
mV
OSC = 5.0 V
–
–
1.0
µA
IAVG Bias Current
IAVG = 0 V
–
0.2
1.0
µA
ICOMP Source Current
ICOMP = 0.2 V to 3.3 V
18
25
37
µA
ICOMP Sink Current
ICOMP = 0.8 to 3.3 V
18
25
36
µA
Set Point
IAVG = 0.25V, 7.0 V < VCC < 24 V
IAVG = 2.5 V, 7.0 V < VCC < 24 V
3.5
90
10
100
16.5
110
mV
mV
Open Loop DC Gain
Note 3.
60
80
100
dB
Transconductance (Gm)
Note 3.
0.2
0.3
0.7
mA/V
Output Impedance
Note 3.
5.0
33
143
MΩ
PSRR @ 1.0 kHz
Note 3.
60
80
–
dB
ICOMP Max Voltage
VI(AVG) = 3.3 V, IS+ = IS– = 0V
3.9
5.0
6.5
V
ICOMP Min Voltage
VI(AVG) = 0 V, IS+ = 0.2 V, IS– = 0 V
–
0.1
0.2
V
IS+, IS– Bias Current
IS– = IS+ = 0 V to VCC (20 V max)
–5.0
1.0
5.0
µA
Input Offset
IS– = 0 to VCC
–6.6
–
6.6
mV
DC Gain
IS– = 1.0 V to VCC
23
25
27
V/V
Gain Bandwidth (–3.0 dB)
Note 3.
3.5
5.5
–
MHz
Propagation Delay
Note 3.
–
70
105
ns
PSRR @ 1.0 kHz
Note 3.
60
85
–
dB
CMRR @ 1.0 kHz
Note 3.
80
100
–
dB
0
–
VCC
V
Note 3.
0
–
125
mV
Set Point
IPEAK = 3.0 V, Duty Cycle = 50%
93
100
107
mV
IPEAK Bias Current
IPEAK = 0 V
–
0.3
1.0
µA
Bias Input Current
Average Current Error Amplifier
Current Sense Amplifier
Input Common Mode Range
Input Differential Mode Range
–
Peak Current Comparator
3. Guaranteed by design, not 100% production tested.
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CS5361
ELECTRICAL CHARACTERISTICS (0°C < TA < 70°C; 0°C < TJ < 125°C; 7.0 V < VCC < 30 V; CGATE(H) = CGATE(L) =
1.0 nF, CREF = 0.1 µF, CVCC = 0.1 µF, CICOMP = 0.1 µF; unless otherwise specified.)
Test Conditions
Characteristic
Min
Typ
Max
Unit
–
50
–
ns
200
500
800
Ω
PWM Comparator
Transient Response
Note 4.
ICOMP Input Resistance
–
Slope Compensation
Note 4.
0.8
1.0
1.2
V
Oscillator Duty Cycle
Note 4.
85
90
95
%
Minimum Pulse Width
Note 4.
–
150
200
ns
2.25
2.5
2.75
V
Enable/UVLO Management
Enable Input Threshold
–
Input Resistance
Note 4.
10
50
80
kΩ
Input Bias Current
VENABLE/UVLO = 2.75 V
–
0.1
1.0
µA
VREF Output Voltage
0 mA < IV(REF) < 1.0 mA
4.166
4.2
4.234
V
VREF Short Circuit Current
VREF = 0V
3.0
6.0
10
mA
Over Temperature Trip Point
Note 4.
125
150
175
°C
Thermal Shutdown Hysteresis
Note 4.
–
25
–
°C
VCC Operating Current
(Non–Switching)
VCOMP = ICOMP = 0 V
–
17
30
mA
VCC Sleep Current
ENABLE/UVLO = 0V; 7.0 V < VCC < 20 V
–
2.0
5.0
µA
VCC Bias Mode Current
ENABLE/UVLO = 0 V
–
50
75
µA
Reference Output
Thermal Protection
General Electrical Specifications
4. Guaranteed by design, not 100% production tested.
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CS5361
PACKAGE PIN DESCRIPTION
Package Pin #
SO–16
Pin Symbol
1
ENABLE/UVLO
2
OSC
Oscillator pin. Place resistor to GND to set the switching frequency. Enters bias mode when
pulled above 2.75 V and the ENABLE/UVLO Input is low (PFET turned ON).
3
VREF(IN)
Reference input of the voltage error amplifier. Connect to the built–in or external reference.
4
LGND
Logic Ground. IC Substrate Connection.
5
ICOMP
Current feedback compensation network.
6
VREF
4.2 V Reference output voltage. Capable of sourcing 3.0 mA.
7
IAVG
Average current control loop input. Voltage at this pin sets average output current.
8
VCOMP
9
VFB
Voltage feedback pin. Connect a resistor divider between output and this pin to set output
voltage.
10
IPEAK
Peak current control loop input. This input is used to set peak value of the inductor ripple
current. This pin can override average current loop setting. It can be used for fast current
control.
11
IS–
Negative input of the current sense amplifier.
12
IS+
Positive input of the current sense amplifier.
13
PGND
14
GATE(L)
15
VCC
16
GATE(H)
Function
Shutdown input. Connect to VIN through a resistor divider to program minimum operating
voltage. Pull below 2.5 V to shut down the IC.
Voltage feedback compensation network.
Power Ground.
Low–Side FET Driver. This pin is capable of delivering peak currents of 1.0 A.
Input power supply pin or VCC bias.
High–Side FET Driver. This pin is capable of delivering peak currents of 1.0 A.
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CS5361
Reset Dominant
PULSE
S
OSC Negative RAMP
OSC
GATE(H)
QN
NONOVR
R
GATE(L)
Thermal
Shutdown
VCOMP
PGND
VREF(IN)
SUM
+
–
VFB
+
–
Voltage Error Amp.
Bias COMP
2.5 V
VCC
ICOMP
IAVG
500 k
+
–
SUM
–
–
+
IS–
IPEAK
Rail–to–Rail
Low Vos.
High Speed
–
+
+
–
VREF
PWM
Comp
Avg. Current Amp.
IS+
EN V
REF =4.2 V
+
–
× 25
50 k
ENABLE/
UVLO
2.5 V
Current Sense Amp.
2.5 V +
–
×1
LGND
Peak Current Buffer Amp.
Figure 2. Block Diagram
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CS5361
APPLICATIONS INFORMATION
THEORY OF OPERATION
–
PWM
+
Overview
The CS5361 battery charger controller has been designed
with the flexibility to charge several types of batteries, such
as Lithium Ion, Nickel Cadmium, Nickel Metal Hydride and
Lead Acid. The differences in chemistry between different
battery types result in differing charge requirements.
Lithium Ion batteries are charged with a constant voltage,
current limit supply. When the battery voltage is low, the
charger operates in constant current mode. When the battery
voltage reaches 4.2 V, the current begins to taper off and the
charger enters into constant voltage mode until the current
essentially reaches zero. Nickel Cadmium and Nickel Metal
Hydride batteries can be charged with a constant current
profile. Lead Acid batteries are charged with a constant
voltage, current limiting supply or with a constant–current
supply.
For a battery charger with the capability to charge all those
battery types, at least two operation modes are required:
constant current mode and constant voltage mode.
Synchronous operation enables designs with greater than
94% efficiency to be realized.
GATE(H)
GATE(L)
RAMP
Inductor
Current
Current
Sense
+
Error
–
+
IAVG
–
Sense
Resistor
Figure 3. I2 Control Scheme
2. Voltage Control
Current mode voltage control method is used to regulate
the voltage. The VFB pin monitors the battery voltage. A
resistor divider is used to scale the voltage down to the
reference level set at the VREF(IN) pin. CS5361 provides a
4.2 V ± 0.8%reference voltage which can obviate the need
for a resistor network if charging a single 4.2 V cell. VFB and
VREF(IN) are the two inputs of the Voltage Error Amplifier.
The output VCOMP is compared with the ramp signal, which
is generated from the inductor current, to adjust the duty
cycle. Similar to ICOMP, VCOMP provides user with
compensation capability.
Control Method
1. Current Control
I2 control scheme is employed to regulate the charging
current. The sense resistor senses the inductor current. A low
offset, high speed Current Sense amplifier with rail–to–rail
inputs amplifies the voltage across the sense resistor. The
output of the amplifier (ISENSE), which is proportional to the
inductor current, is used as feedback for two control loops.
The DC level is used by the outer loop and is fed to the
Average Current Error Amplifier. The Error Amplifier
compares ISENSE to an externally set reference voltage IAVG
and generates a PWM control voltage ICOMP. Charger
designers can use the ICOMP pin to design the compensation
for the Average Current Amplifier. The current ripple is used
as the ramp signal of the PWM comparator. I2 control has
inherent compensation for duty cycle in response to line
voltage or load changes. Changes in line and load conditions
affect the inductor current. Because the ramp signal of the
PWM comparator is generated from the inductor current, the
duty cycle can be adjusted on a pulse by pulse basis. Since
the fast PWM control loop handles transient response, a high
gain, low bandwidth error amplifier can be used to improve
DC accuracy, stability and noise immunity.
Start–Up
CS5361 provides a controlled startup of regulator output
current and voltage through the Error Amplifiers and
external compensation networks. The capacitor at the ICOMP
output provides true current soft start. As the capacitor
charges up, the Average Current Error Amplifier signal
increases. The output current of the regulator ramps up in a
controlled manner. The compensation network at VCOMP
has the similar function, which will prevent instantaneous
switching of the output voltage.
Oscillator
The battery charger controller is designed for constant
frequency operation. The user can adjust the switching
frequency from 100 kHz to 500 kHz by connecting a resistor
from the OSC pin to GND. This function simplifies the
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CS5361
Error Amplifier Compensation
selection of external components and allows the user
freedom to choose switching frequency.
The outputs of the Average Current Error Amplifier and
the Voltage Error Amplifier are available to users. Users
have the freedom to design the compensation network to
improve the dynamic characteristics such as transient
response time, over/undershoot, and loop stability.
Gate Drivers GATE(H) and GATE(L)
In synchronous buck operation, GATE(H) and GATE(L)
drive the high–side P–channel MOSFET and the low–side
N–channel MOSFET respectively. The advantage of this
circuit is that no charge pump is required. The low–side FET
(the synchronous rectifier) behaves like a diode but has a
smaller voltage drop and improves the efficiency. A 60 ns
nonoverlap dead time is added between the time when the
high–side FET is turned off and when the synchronous
rectifier is turned on, and vice versa. This function
effectively prevents crowbar currents during switching
transitions.
Enable/Under–Voltage Lockout
The input voltage of the charger must remain above a
certain level in order to work. Control is required to ensure
that the charger will not start to operate without sufficient
voltage. Under–Voltage Lockout provides this protection
with a comparator, which compares the input to 2.5 V. The
output of the comparator enables the charger’s reference
voltage, which in turn controls startup of the charger. The
comparator’s output also controls the high–side MOSFET
so that the batteries will power the load when the charger is
shut off. This pin also provides the function of manual
shutdown by bringing the pin below 2.5 V. Chip current in
the shutdown mode is only 2.0 µA.
Gate Voltage Clamps
Internal clamps prevent driving the external power
MOSFET gate voltages to levels higher than required for
complete enhancement. This improves converter efficiency
by reducing gate rise time, fall time, and the losses
associated with the charge and discharge of gate
capacitance.
Peak Current Control
The Peak Current Buffer Amplifier compares the current
control signal (the output of the Average Current Error
Amplifier) with a preset reference voltage, which can be set
externally at pin IPEAK. When output of the Error Amplifier
exceeds the limit, the output of the Peak Current Buffer
Amplifier goes low and clamps current control signal.
Therefore, the peak current control can override the average
current control. In laptop computer systems, fast reducing
the charge current is required to prevent overloading the
input supply when the computer switches into active mode
from sleep mode. On the other hand, a trickle charging mode
is required in many battery chargers either to prevent
over–discharged or fully charged cells from being damaged
by constant–current charging. The current for trickle
charging is usually much lower than that of constant–current
charging. The Peak Current Control can be utilized to
implement trickle charging mode without changing the
setting of the average charging current.
Bias Mode
When the battery is fully charged, the charger can be shut
down externally by pulling the ENABLE/UVLO pin low.
When the part is off and the OSC pin is pulled above 2.75 V,
the charger will enter into Bias Mode. In Bias mode, the
high–side PFET turns on and connect the battery to the load
so that the battery starts discharging to the load.
100% Duty Cycle
The maximum duty cycle of the CS5361 is 100%. This
feature is useful when the input voltage is marginally higher
than the output voltage. If the battery voltage is very close
to the input line voltage, the controller will simply go to
100% duty cycle.
Slope Compensation
In both current and voltage controls, the sensed inductor
current signal is used as the ramp of the PWM comparator
to afford fast response to line and load variations. An
artificial ramp signal with negative slope generated by the
oscillator is added to the two negative inputs (VCOMP and
ICOMP) of the PWM comparator to be compared with the
ramp generated by the inductor current. The output of the
PWM comparator is used to control the duty cycle. This
method helps stabilize the system over the whole operation
duty cycle range as well as minimize response time to output
current changes.
Input Current Limiting
An input current limiting function can be implemented
externally using a dual op–amp, a sense resistor and several
resistors and capacitors. The first op–amp is configured into
a differential amplifier. The second op–amp compares the
amplified input current signal with a reference voltage. The
output is used to clamp the ICOMP pin voltage when input
current exceeds the limit. See Figure 9 for detailed
implementation.
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CS5361
Constant Current
VCC
Constant Voltage
Shutoff
Bias Mode
4.2 V
VREF
Battery
Voltage
16.8 V
Battery
Current
2.0 A
0A
VCOMP
ICOMP
Inductor
Current
GATE(H)
δ
δ
GATE(L)
ENABLE/
UVLO
2.5 V
2.5 V
2.5 V
OSC
δ: Nonoverlap Time
Figure 4. Key Operation Waveforms
DESIGN GUIDELINES
The peak current should not saturate the core of the
inductor.
1. Selection of the Output Inductor
The value of the output inductor can be calculated based
on the inductor ripple current requirement:
T V
L (1.0 D) S OUT
IL
2. Selection of Output Capacitor
Both the output voltage ripple and the inductor current
ripple determine the value of the output capacitance. The
required minimum is given by:
(1)
C 0.125 where VOUT is the output voltage; TS is the period of one
switching cycle; ∆IL is the peak–to–peak inductor ripple
current given by design specification; and D is the duty
cycle. Because both duty cycle and the output voltage
change during charging operation, the designer should
determine the maximum product of (1.0 – D) and VOUT to
calculate the inductance. The peak inductor current is given
by:
I
IL,PEAK IO L
2.0
ILTS
VOUT
(3)
The capacitor ESR (Equivalent Series Resistance) of the
capacitor also needs to be small enough to meet the ripple
requirement.
ESRMAX VOUT
IL
(4)
If the ESR obtained from the above equation is smaller
than the ESR specified in the capacitor manufacturer’s data
(2)
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11
CS5361
RSENSE 125 mV
IPEAK
sheet; several capacitors should be paralleled. The number
of capacitors is determined by:
Number of Capacitors ESRPER CAP
ESRMAX
(8)
After the value of current sense resistor is determined, the
resistor divider for current setting can be designed.
(5)
R6
IOUT RSENSE 25
R5 R6
4.2 V
3. Design of Resistor Divider for Voltage Sensing
Because the internal reference voltage is 4.2 V, which is
equal to the voltage of one Lithium Ion battery cell, we have:
where IOUT is the target value of the output current.
The maximum bias current of the Current Error Amplifier
is 1.0 mA. The voltage across the resistor divider is 4.2 V. If
we choose R5 + R6 = 10 kΩ, we have
1.0
R2
R1 R2
Cell Count
The maximum input bias current of the Voltage Error
Amplifier is 1.0 µA, the resistor divider current should be
much higher than that to ensure that there is sufficient bias
current. For 4–cell charger, the output voltage is 16.8 V. If
we choose R1 + R2 = 100 kΩ, then
42 420 A >> 1.0 A
10 k
Therefore,
R
R6 10 k 25 IOUT SENSE ,
4.2 V
R5 10 k R6
16.8 V 168 A >> 1.0 A
100 k
Therefore,
(9)
6. Design of Average Current Compensation Network
R2 100 k , R1 100 k R2
Cell Count
As mentioned before, there are two feedback loops in the
I2 control scheme. The slow outer loop provides tight
regulation and easy loop compensation. The fast inner loop
handles the transient response on a pulse–by–pulse basis.
The design of the compensation network is based on the
control–to–output transfer function with closed inner
current feedback loop. In this case, “control” is the output of
the Average Current Error Amplifier (ICOMP) and “output”
is the inductor current.
The approximate control–to–output transfer function for
the Buck converter is given by:
(6)
R1 and R2 must be ± 0.1% precise resistors to meet the
± 1.0% overall charge voltage accuracy.
4. Design of Resistor Divider for Enable/Under–Voltage
Lockout
The resistor divider should be so designed that the
controller can be enabled at the required minimum input
voltage.
R4
2.5 V
R3 R4
VIN,MIN
1.0 sC (ESR R)
IL
ICOMP
RI(1.0 sCR)1.0 s(nQ) s2n2
The maximum bias current for this pin is also 1.0 µA. The
sum of R3 and R4 can also be chosen as 100 kΩ, so
R4 100 k 2.5 V , R3 100 k R4
VIN,MIN
(10)
where RI is the current sense gain, ωn is half of the switching
frequency and
(7)
Q
5. Selection of Current Sense Resistor and Resistor
Divider for Current Setting
1.0
[(1.0 SeSn) (1.0 D) 0.5]
(11)
where Se is the slope of the external ramp signal and Sn is
the inductor current up slope.
The transfer function is a third–order system with a double
pole at half of the switching frequency and a low frequency
pole. Because ESR of the output capacitor is usually very
small compared to load resistor R, the zero and the low
frequency pole can cancel out each other. The system
degrades to second–order.
The compensation design for such a system becomes very
easy. A single integrator pole gives the system high DC gain
and makes it crossover with –1.0 slope. The Bode plot of the
The tolerance of the current sense resistor affects the
accuracy of current regulation, so a sense resistor with ± 1.0%
tolerance should be used. Since the Current Sense Amplifier
is a high–speed, low voltage rail–to–rail amplifier, the value
of the current sensing resistor should satisfy the following
condition:
IPEAK RSENSE 125 mV
where 125 mV is the differential mode input range of the
Current Sense Amplifier.
Therefore,
http://onsemi.com
12
CS5361
R(1.0 sC ESR)
VOUT
(15)
VCOMP
RI(1.0 sCR)1.0 s(nQ) s2n2
closed loop control–to–output transfer function without and
with compensation is shown in Figure 5.
Compare the above expression with equation (9), the
transfer function of current mode voltage control has same
poles as I2 control. The difference is the zero. For I2 control,
the zero is determined by both ESR of the output capacitor
and the load resistor and can be cancel out the low frequency
pole. But for current mode voltage control, the zero is a high
frequency ESR zero. The low frequency pole cannot be
cancelled. So the system is third–order. The Bode plot of the
control–to–output transfer function with closed current loop
is illustrated in Figure 6
dB
Without Compensation
–1
fs/2
–2
f
dB
With Compensation
–3
Double Pole
–1
Figure 5. Bode Plot of Control–to–Output
Transfer Function
Low Freq. Pole
ESR Zero
If a transconductance amplifier is used as the error
amplifier, the integrator pole can be implemented by
connecting a capacitor from the amplifier output to the
ground. The compensation gain is given by:
FC(s) G
(sCCOMP)
–2
Figure 6. Bode Plot
For a transconductance error amplifier, a possible
compensation network is shown in Figure 7. The
compensation network has two poles and one zero.
(12)
where G is the transconductance of the amplifier.
The total loop gain is
T(s) f
G
(13)
RI sCCOMP1.0 s(nQ) s2n2
VFB
–
VREF(IN)
+
The value of the compensation capacitor CCOMP can be
calculated if the crossover frequency is known. Generally,
the crossover frequency should be chosen well below the
switching frequency.
We can choose
VCOMP
R1
C2
C1
Figure 7. Compensation Network
fCO 16 fS
The compensation gain is given by:
So
CCOMP G
RI 2.0fCO
F(s) (14)
G (1.0 sR1C1)
(16)
(C1 C2) s[1.0 sR1C1C2(C1 C2)]
The integrator pole will give the system high DC gain. Use
the zero to compensate the excessive phase delay caused by
the low frequency pole of the control–to–output transfer
function. The other pole of the compensation network
should be placed around the ESR zero to make sure the
amplitude decrease fast after the 0 dB crossover.
7. Design of Voltage Compensation Network
For voltage, “control” is referred to the output of the
Voltage Error Amplifier (VCOMP) and “output” is the output
voltage. The control–to–output transfer function with
closed current loop is given by:
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13
CS5361
Q3
VIN 18.5
to 24.5 V
C5
10 µ
VCC
R7
OSC
330 k C3 0.1 µ
R8
C1 0.1 µ
VOUT
16.8 V
R3
40.2 k
GATE(H)
Q1
ICOMP
L1
10 µH
VCOMP
1.0 k
CS5361
GATE(L)
C2 1000 p
Q2
D1
R4
C4 0.1 µ
VREF(IN)
VREF
12.7 k
C7
10 µ
IS+
R5
69.8 k 1%
R6
29.4 k 1%
EN/UVL
R1
75 k
1%
Li_Ion
Battery
Pack
IS–
IAVG
IPEAK
PGND
C6
10 µ
VFB
R2
24.9 k
1%
LGND
R11
0.025 1%
VIN_RTN
R9
R10
430 k
70 k
Q4
NPN
Q5
NPN
VOUT_RTN
R12
Shutdown
470
R13
IPEAK
470
5.0 V
D2
Bias
Diode
Figure 8. Additional Application Diagram, 16.8 V/2.0 A Four Cell Lithium–Ion Battery Charger
with Low Side Current Sensing
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14
CS5361
C8 1.0 µF
Load
R15
500
VIN 18.5
to 24.5 V
R16
500
D2
R14
C5
10 µ
0.025
D3
C7 1.0 µ
R3
40.2 k
U1
VCC
R7
OSC
330 k C3 0.1 µ
R8 C1 0.1 µ
VOUT
16.8 V
GATE(H)
Q1
ICOMP
L1
R11
VCOMP
33 µH
0.05
1.0 k
CS5361
GATE(L)
C2 1000 p
Q2
D1
R4
VREF(IN)
C4 0.1 µ
Bias
IS+
R5
41.2 k 1%
R6
60.4 k 1%
VIN_RTN
12.7 k
VREF
+5.0 V
R1
75 k
1%
EN/UVL
Li_Ion
Battery
Pack
IS–
IAVG
IPEAK
PGND
R9
R10
430 k
70 k
VFB
R2
24.9 k
1%
LGND
C6
10 µ
VOUT_RT
R13
Q5
NPN
R12
Q4
NPN
470
470
Shutdown
IPEAK
R19
560 k
R17 10 k
R18 10 k
R20
560 k
+
-
U1A
R21
10 k
+
-
R22
10 k
U1B
LM2903
D4
LM2903
R23
560 k
C9 1.0 nF
Figure 9. Additional Application Diagram, 16.8 V/2.0 A Four Cell Lithium–Ion Battery Charger
with High Side Current Sensing and Input Current Limiting
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15
CS5361
PACKAGE DIMENSIONS
SO–16
D SUFFIX
CASE 751B–05
ISSUE J
–A–
16
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
9
–B–
1
P
8 PL
0.25 (0.010)
8
M
B
S
G
R
K
F
X 45 C
–T–
SEATING
PLANE
J
M
D
16 PL
0.25 (0.010)
M
T B
S
A
S
DIM
A
B
C
D
F
G
J
K
M
P
R
MILLIMETERS
MIN
MAX
9.80
10.00
3.80
4.00
1.35
1.75
0.35
0.49
0.40
1.25
1.27 BSC
0.19
0.25
0.10
0.25
0
7
5.80
6.20
0.25
0.50
INCHES
MIN
MAX
0.386
0.393
0.150
0.157
0.054
0.068
0.014
0.019
0.016
0.049
0.050 BSC
0.008
0.009
0.004
0.009
0
7
0.229
0.244
0.010
0.019
PACKAGE THERMAL DATA
Parameter
SO–16
Unit
RΘJC
Typical
28
°C/W
RΘJA
Typical
115
°C/W
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes
without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular
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16
CS5361/D