HM62256B Series 32,768-word × 8-bit High Speed CMOS Static RAM ADE-203-135D (Z) Rev. 4.0 Nov. 29, 1995 Description The Hitachi HM62256B is a CMOS static RAM organized 32-kword × 8-bit. It realizes higher performance and low power consumption by employing 0.8 µm Hi-CMOS process technology. The device, packaged in 8 × 14 mm TSOP, 8 × 13.4 mm TSOP with thickness of 1.2 mm, 450-mil SOP (foot print pitch width), 600-mil plastic DIP, or 300-mil plastic DIP, is available for high density mounting. It offers low power standby power dissipation; therefore, it is suitable for battery back-up systems. Features • • • • • • • • High speed Fast access time: 45/55/70/85 ns (max) Low power Standby: 1.0 µW (typ) Operation: 25 mW (typ) (f = 1 MHz) Single 5 V supply Completely static memory No clock or timing strobe required Equal access and cycle times Common data input and output Three state output Directly TTL compatible All inputs and outputs Capability of battery back up operation HM62256B Series Ordering Information Type No. Access Time Package HM62256BLP-7 70 ns HM62256BLP-7SL 70 ns HM62256BLSP-7 70 ns HM62256BLSP-7SL 70 ns HM62256BLFP-7T 70 ns *1 HM62256BLFP-4SLT HM62256BLFP-5SLT HM62256BLFP-7SLT 45 ns 55 ns 70 ns HM62256BLFP-7ULT 70 ns HM62256BLT-8 85 ns HM62256BLT-7SL 70 ns HM62256BLTM-8 85 ns *1 HM62256BLTM-4SL HM62256BLTM-5SL HM62256BLTM-7SL 45 ns 55 ns 70 ns HM62256BLTM-7UL 70 ns Note: 600-mil 28-pin plastic DIP (DP-28) 300-mil 28-pin plastic DIP (DP-28NA) 450-mil 28-pin plastic SOP (FP-28DA) 8 mm × 14 mm 32-pin TSOP (TFP-32DA) 8 mm × 13.4 mm 28-pin TSOP (TFP-28DA) 1. Under development 2 HM62256B Series Pin Arrangement HM62256BLP/BLFP/BLSP Series HM62256BLT Series OE A11 NC A9 A8 A13 WE VCC A14 A12 A7 A6 A5 NC A4 A3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 A14 1 28 VCC A12 2 27 WE A7 3 26 A13 A6 4 25 A8 A5 5 24 A9 A4 6 23 A11 A3 7 22 OE A2 8 21 A10 A1 9 20 CS A0 10 19 I/O7 I/O0 11 18 I/O6 I/O1 12 17 I/O5 (Top View) I/O2 13 16 I/O4 HM62256BLTM Series VSS 14 15 I/O3 (Top View) OE A11 A9 A8 A13 WE VCC A14 A12 A7 A6 A5 A4 A3 22 23 24 25 26 27 28 1 2 3 4 5 6 7 (Top View) Pin Description Symbol Function A0 – A14 Address I/O0 – I/O7 Input/output CS Chip select WE Write enable OE Output enable NC No connection VCC Power supply VSS Ground 3 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 A10 CS NC I/O7 I/O6 I/O5 I/O4 I/O3 VSS I/O2 I/O1 I/O0 A0 NC A1 A2 21 20 19 18 17 16 15 14 13 12 11 10 9 8 A10 CS I/O7 I/O6 I/O5 I/O4 I/O3 V SS I/O2 I/O1 I/O0 A0 A1 A2 HM62256B Series Block Diagram V CC (MSB) A12 V SS A5 A7 • • • A6 Row Decoder • • A8 • A13 A14 Memory Matrix 512 × 512 • • • • A4 (LSB) A3 I/O0 • • • Column I/O • • • • Input Data Control • • • • • • Column Decoder • • I/O7 • • A2 A1 A0 A10 A9 A11 (LSB) • (MSB) • • • Timing Pulse Generator CS Read/Write Control WE OE Function Table WE CS OE Mode VCC Current I/O Pin Ref. Cycle X H X Not selected I SB , I SB1 High-Z — H L H Output disable I CC High-Z — H L L Read I CC Dout Read cycle (1)–(3) L L H Write I CC Din Write cycle (1) L L L Write I CC Din Write cycle (2) Note: X: H or L 4 HM62256B Series Absolute Maximum Ratings Parameter Power supply voltage *1 Symbol Value VCC –0.5 to +7.0 V *1 VT –0.5* to VCC + 0.3 V Power dissipation PT 1.0 W Operating temperature Topr 0 to + 70 °C Storage temperature Tstg –55 to +125 °C Storage temperature under bias Tbias –10 to +85 °C Terminal voltage 2 Unit *3 Notes: 1. Relative to VSS 2. VT min: –3.0 V for pulse half-width ≤ 50 ns 3. Maximum voltage is 7.0 V Recommended DC Operating Conditions (Ta = 0 to +70°C) Parameter Symbol Min Typ Max Unit Supply voltage VCC 4.5 5.0 5.5 V VSS 0 0 0 V VIH 2.2 — VCC+0.3 V — 0.8 V Input high (logic 1) voltage Input low (logic 0) voltage Note: VIL –0.5 1. VIL min: –3.0 V for pulse half-width ≤ 50 ns 5 *1 HM62256B Series DC Characteristics (Ta = 0 to +70°C, VCC = 5 V ±10%, VSS = 0 V) Parameter Symbol Min Typ*1 Max Unit Test Conditions Input leakage current |ILI| — — 1 µA Vin = VSS to V CC Output leakage current |ILO | — — 1 µA CS = VIH or OE = VIH or WE = VIL, VSS ≤ VI/O ≤ VCC Operating power supply current I CC — 6 15 mA CS = VIL, others = VIH/VIL I I/O = 0 mA Average operating HM62256B-4 I CC1 power supply current — — 70 mA min cycle, duty = 100 %, II/O = 0 mA CS = VIL, others = VIH/VIL HM62256B-5 I CC1 — — 60 HM62256B-7 I CC1 — 33 60 HM62256B-8 I CC1 — 29 50 I CC2 — 5 15 mA Cycle time = 1 µs, II/O = 0 mA CS = VIL, V IH = VCC, VIL = 0 I SB — 0.3 2 mA CS = VIH I SB1 — 0.2 µA Vin ≥ 0 V, CS ≥ V CC – 0.2 V, 0.4 V I OL = 2.1 mA — V I OH = –1.0 mA Standby power supply current — 100 0.2 *2 50 0.2 *3 10*3 Output low voltage VOL — Output high voltage VOH 2.4 — — *2 Notes: 1. Typical values are at VCC = 5.0 V, Ta = +25°C and not guaranteed. 2. This characteristics is guaranteed only for L-SL version. 3. This characteristics is guaranteed only for L-UL version. Capacitance (Ta = 25°C, f = 1.0 MHz)*1 Parameter Input capacitance *1 Input/output capacitance Note: *1 Symbol Min Typ Max Unit Test Conditions Cin — — 8 pF Vin = 0 V CI/O — — 10 pF VI/O = 0 V 1. This parameter is sampled and not 100% tested. 6 HM62256B Series AC Characteristics (Ta = 0 to +70°C, VCC = 5 V ± 10%, unless otherwise noted.) Test Conditions • • • • Input pulse levels: 0.8 V to 2.4 V Input rise and fall times: 5 ns Input and output timing reference level: 1.5 V Output load: HM62256B-4: 1 TTL Gate + C L (30 pF)(Including scope & jig) HM62256B-5: 1 TTL Gate + C L (50 pF)(Including scope & jig) HM62256B-7/8: 1 TTL Gate + C L (100 pF)(Including scope & jig) Read Cycle HM62256B -4 -5 -7 -8 Parameter Symbol Min Max Min Max Min Max Min Max Unit Notes Read cycle time t RC 45 — 55 — 70 — 85 — ns Address access time t AA — 45 — 55 — 70 — 85 ns Chip select access time t ACS — 45 — 55 — 70 — 85 ns Output enable to output valid t OE 30 — 35 — 40 — 45 ns Chip selection to output in low-Z t CLZ 5 — 5 — 10 — 10 — ns 2 Output enable to output in low-Z t OLZ 5 — 5 — 5 — 5 — ns 2 Chip deselection in to output in high-Z t CHZ 0 20 0 20 0 25 0 30 ns 1, 2 Output disable to output in high-Z t OHZ 0 20 0 20 0 25 0 30 ns 1, 2 Output hold from address change t OH 5 — 5 — 5 — 10 — ns Notes: 1. t CHZ and tOHZ defined as the time at which the outputs achieve the open circuit conditions and are not referred to output voltage levels. 2. This parameter is sampled and not 100% tested. 7 HM62256B Series Read Timing Waveform (1) (WE=VIH) t RC Address Valid address t AA t ACS CS t OH t OE t OLZ OE t OHZ t CHZ Dout High impedance Valid data Read Timing Waveform (2) (WE =VIH, CS=VIL , OE=VIL ) t RC Valid address Address tAA t OH t OH Dout Valid data 8 HM62256B Series Read Timing Waveform (3) (WE =VIH, OE=VIL )*1 t ACS CS t CLZ Dout t CHZ High impedance Valid data Note: 1. Address must be valid prior to or simultaneously with CS going low. 9 HM62256B Series Write Cycle HM62256B -4 -5 -7 -8 Parameter Symbol Min Max Min Max Min Max Min Max Unit Notes Write cycle time t WC 45 — 55 — 70 — 85 — ns Chip selection to end of write t CW 35 — 40 — 60 — 75 — ns 4 Address setup time t AS 0 — 0 — 0 — 0 — ns 5 Address valid to end of write t AW 35 — 40 — 60 — 75 — ns Write pulse width t WP 30 — 35 — 50 — 55 — ns 3, 8 Write recovery time t WR 0 — 0 — 0 — 0 — ns 6 WE to output in high-Z t WHZ 0 20 0 20 0 25 0 40 ns 1, 2, 7 Data to write time overlap t DW 20 — 25 — 30 — 35 — ns Data hold from write time t DH 0 — 0 — 0 — 0 — ns Output active from end of write t OW 5 — 5 — 5 — 5 — ns 2 Output disable to output in high-Z t OHZ 0 20 0 20 0 25 0 40 ns 1, 2, 7 Notes: 1. t OHZ and t WHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referred to output voltage levels. 2. This parameter is sampled and not 100% tested. 3. A write occurs during the overlap (tWP) of a low CS and a low WE. A write begins at the later transition of CS going low or WE going low. A write ends at the earlier transition of CS going high or WE going high. tWP is measured from the beginning of write to the end of write. 4. t CW is measured from CS going low to the end of write. 5. t AS is measured from the address valid to the beginning of write. 6. t WR is measured from the earlier of WE or CS going high to the end of write cycle. 7. Durng this period, I/O pins are in the output state so that the input signals of the opposite phase to the outputs must not be applied. 8. In the write cycle with OE low fixed, tWP must satisfy the following equation to avoid a problem of data bus contention, tWP ≥ tWHZ max + tDW min. 10 HM62256B Series Write Timing Waveform (1) (OE Clock) t WC Address Valid address t AW t WR OE t CW CS *1 t WP t AS WE t OHZ High impedance Dout t DW Din High impedance t DH Valid data Note: 1. If CS goes low simultaneously with WE going low or after WE going low, the outputs remain in the high impedance state. 11 HM62256B Series Write Timing Waveform (2) (OE Low Fixed) (OE = VIL ) t WC Address Valid address t WR t CW CS *1 t AW t OH tWP WE tAS t WHZ t OW *2 Dout t DW t DH *4 Din High impedance Valid data Notes: 1. If CS goes low simultaneously with WE going low or after WE going low, the outputs remain in the high impedance state. 2. Dout is the same phase of the write data of this write cycle. 3. Dout is the read data of next address. 4. If CS is low during this period, I/O pins are in the output state. Therefore, the input signals of theopposite phase to the output must not be applied to them. 12 *3 HM62256B Series Low VCC Data Retention Characteristics (Ta = 0 to +70°C) Parameter Symbol Min Typ*1 Max Unit Test Conditions*6 VCC for data retention VDR 2.0 — 5.5 V CS ≥ V CC –0.2 V, Vin ≥ 0 V Data retention current I CCDR — 0.05 30*2 µA VCC = 3.0 V, Vin ≥ 0 V 0.05 *3 10 0.05 *4 3 — — ns — — ns — — Chip deselect to data retention time t CDR Operation recovery time Notes: 1. 2. 3. 4. 5. 6. tR 0 *5 t RC CS ≥ V CC –0.2 V, See retention waveform Typical values are at VCC = 3.0 V, Ta = 25°C and not guaranteed. 10 µA max at Ta = 0 to + 40°C. This characteristics guaranteed for only L-SL version. 3 µA max at Ta = 0 to +40°C. This characteristics guaranteed for only L-UL version. 0.6 µA max at Ta = 0 to +40°C. t RC = read cycle time. CS controls address buffer, WE buffer, OE buffer, and Din buffer. If CS controls data retention mode, other input levels (address, WE, OE, I/O) can be in the high impedance state. Low V CC Data Retention Timing Waveform Data retention mode VCC 4.5V t CDR tR 2.2V VDR CS 0V CS > VCC - 0.2V 13 HM62256B Series Package Dimensions HM62256BLP Series (DP-28) Unit: mm 35.60 36.50 Max 15 13.40 14.60 Max 28 14 1.20 2.54 ± 0.25 0.51 Min 1.90 Max 0.48 ± 0.10 15.24 2.54 Min 5.70 Max 1 + 0.11 0.25 – 0.05 0° – 15° HM62256BLSP Series (DP-28NA) Unit: mm 36.0 37.32 Max 14 5.08 Max 1.3 2.54 ± 0.25 0.51 Min 2.2 Max 0.48 ± 0.10 14 2.54 Min 1 7.37 Max 15 7.1 28 7.62 + 0.11 0.25 – 0.05 0° – 15° HM62256B Series HM62256BLFP Series (FP-28DA) Unit: mm 18.00 18.75 Max 15 1.27 Max 11.80 ± 0.30 1.70 0 – 10 ° 0.20 ± 0.10 + 0.10 0.40 – 0.05 1.27 ± 0.10 + 0.08 – 0.07 14 0.17 1 3.00 Max 8.40 28 1.00 ± 0.20 HM62256BLT Series (TFP-32DA) Unit: mm 8.00 8.20 Max 17 1 16 12.40 32 0.50 0.08 M 14.00 ± 0.20 0.10 0.17 ± 0.05 1.20 Max 0.45 Max 0.80 0–5° 0.50 ± 0.10 0.13 ± 0.05 0.20 ± 0.10 15