Industrial Current/Voltage Output Driver with Programmable Ranges AD5748 FEATURES Current output ranges: 4 mA to 21 mA, 0 mA to 21 mA ±0.15% FSR total unadjusted error (TUE) ±5 ppm/°C FSR typical output drift Voltage output ranges: 0 V to 5 V, 0 V to 10.5 V, ±10.5 V ±0.05% FSR total unadjusted error (TUE) ±3 ppm/°C FSR output drift Flexible serial digital interface On-chip output fault detection PEC error checking Asynchronous CLEAR function Flexible power-up condition to 0 V or tristate Power supply range AVDD: +12 V (± 10%) to +24 V (± 10%) AVSS: −12 V (± 10%) to −24 V (± 10%) Output loop compliance to AVDD − 2.75 V Temperature range: −40°C to +105°C 32-lead, 5 mm × 5 mm LFCSP package APPLICATIONS Process control Actuator control PLCs GENERAL DESCRIPTION The AD5748 is a single-channel, low cost, precision, voltage/ current output driver with hardware or software programmable output ranges. The software ranges are configured via an SPI-/ MICROWIRE™-compatible serial interface. The AD5748 targets applications in PLC and industrial process control. The analog input to the AD5748 is provided from a low voltage, single-supply, digital-to-analog converter (DAC) and is internally conditioned to provide the desired output current/voltage range. The analog input range is 0 V to 4.096 V. The output current range is programmable across two current ranges: 4 mA to 21 mA and 0 mA to 21 mA. Voltage output is provided from a separate pin that can be configured to provide 0 V to 5 V, 0 V to 10.5 V, or ±10.5 V output range. Analog outputs are short-circuit and open-circuit protected and can drive capacitive loads of 2 μF and inductive loads of 0.1 H. The device is specified to operate with a power supply range from ±12 V to ±24 V. Output loop compliance is 0 V to AVDD − 2.75 V. The flexible serial interface is SPI- and MICROWIRE-compatible and can be operated in 3-wire mode to minimize the digital isolation required in isolated applications. The interface also features an optional PEC error checking feature using CRC-8 error checking, useful in industrial environments where data communication corruption can occur. The device also includes a power-on-reset function, ensuring that the device powers up in a known state (0 V or tristate), and a asynchronous CLEAR pin that sets the outputs to zero scale/midscale voltage output or the low end of the selected current range. An HW SELECT pin is used to configure the part for hardware or software mode on power-up. Note that the plots in the Typical Performance Characteristics section of this data sheet contain information on the standard ranges, as released in the AD5750/AD5750-1 data sheet. Although the overranges have been tested, new plots were not generated and substitution data was used for plotting purposes. Table 1. Related Device Part Number AD5422 Description Single-channel, 16-bit, serial input current source and voltage output DAC Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2010 Analog Devices, Inc. All rights reserved. AD5748 TABLE OF CONTENTS Features .............................................................................................. 1 Reset Function ............................................................................ 25 Applications ....................................................................................... 1 OUTEN........................................................................................ 25 General Description ......................................................................... 1 Software Control ........................................................................ 25 Revision History ............................................................................... 2 Hardware Control ...................................................................... 27 Functional Block Diagram .............................................................. 3 Transfer Function ....................................................................... 27 Specifications..................................................................................... 4 Detailed Description of Features .................................................. 28 Timing Characteristics ................................................................ 7 Output Fault Alert—Software Mode ....................................... 28 Absolute Maximum Ratings............................................................ 9 Output Fault Alert—Hardware Mode ..................................... 28 ESD Caution .................................................................................. 9 Voltage Output Short-Circuit Protection ................................ 28 Pin Configuration and Function Descriptions ........................... 10 Asynchronous Clear (CLEAR) ................................................. 28 Typical Performance Characteristics ........................................... 12 Current Setting Resistor ............................................................ 29 Voltage Output ............................................................................ 12 Packet Error Checking ............................................................... 29 Current Output ........................................................................... 16 Applications Information .............................................................. 30 Terminology .................................................................................... 21 Transient Voltage Protection .................................................... 30 Theory of Operation ...................................................................... 22 Thermal Considerations............................................................ 30 Software Mode ............................................................................ 22 Layout Guidelines....................................................................... 30 Current Output Architecture .................................................... 24 Galvanically Isolated Interface ................................................. 31 Driving Inductive Loads ............................................................ 24 Microprocessor Interfacing ....................................................... 31 Power-On State of the AD5748 ................................................ 24 Outline Dimensions ....................................................................... 32 Default Registers at Power-On ................................................. 25 Ordering Guide .......................................................................... 32 REVISION HISTORY 3/10—Revision 0: Initial Version Rev. 0 | Page 2 of 32 AD5748 FUNCTIONAL BLOCK DIAGRAM DVCC GND AVDD GND COMP1 COMP2 AD5748 CLEAR CLRSEL SCLK/OUTEN* SDIN/R0* SYNC/RSET* SDO/VFAULT* HW SELECT VSENSE+ INPUT SHIFT REGISTER AND CONTROL LOGIC VOUT RANGE SCALING VOUT VOUT SHORT FAULT STATUS REGISTER VSENSE– AVDD VIN R2 VREF R3 REXT1 REXT2 IOUT RESET IOUT RANGE SCALING RSET OVERTEMP NC/IFAULT* VOUT SHORT FAULT IOUT OPEN FAULT PEC ERROR AD2/R1* AD1/R2* POWERON RESET AD0/R3* IOUT OPEN FAULT AVSS * DENOTES SHARED PIN. SOFTWARE MODE DENOTED BY REGULAR TEXT, HARDWARE MODE DENOTED BY ITALIC TEXT. FOR EXAMPLE, FOR FAULT/TEMP PIN, IN SOFTWARE MODE, THIS PIN TAKES ON FAULT FUNCTION. IN HARDWARE MODE, THIS PIN TAKES ON TEMP FUNCTION. Figure 1. Rev. 0 | Page 3 of 32 08922-001 FAULT/TEMP* AD5748 SPECIFICATIONS AVDD/AVSS = ±12 V (± 10%) to ±24 V (± 10%), DVCC = 2.7 V to 5.5 V, GND = 0 V. IOUT: RLOAD = 300 Ω. All specifications TMIN to TMAX, unless otherwise noted. Table 2. Parameter1 INPUT VOLTAGE RANGE VIN Input Leakage Current REFERENCE INPUT Reference Input Voltage Input Leakage Current VOLTAGE OUTPUT, VOUT Output Voltage Ranges Accuracy Total Unadjusted Error (TUE)2 Relative Accuracy (INL) Bipolar Zero Error (Offset at Midscale) Min Zero-Scale Error TC3 Zero-Scale/Offset Error Offset Error TC3 Gain Error Gain Error TC3 Full-Scale Error Full-Scale Error TC3 VOLTAGE OUTPUT CHARACTERISTICS3 Headroom Short-Circuit Current Load Capacitive Load Stability RLOAD = ∞ RLOAD = 2 kΩ RLOAD = ∞ DC Output Impedance 0 V to 5 V range, ¼ to ¾ Step 0 V to 5 V range, 40 mV Input Step Slew Rate Output Noise Max Unit +1 V μA 0 to 4.096 −1 4.096 V −1 +1 μA 0 0 5 10.5 V V −10.5 +10.5 V +0.3 +0.1 +0.02 +10 % FSR % FSR % FSR mV +8 mV ppm FSR/°C mV mV ppm FSR/°C mV mV mV mV ppm FSR/°C % FSR % FSR ppm FSR/°C % FSR % FSR ppm FSR/°C −0.3 −0.1 −0.02 −10 −8 Bipolar Zero Error TC3 Zero-Scale Error Typ −10 −8 −5 −4 −3 −2.2 −0.05 −0.04 −0.05 −0.04 ±0.05 ±0.005 ±0.5 ±1.5 +10 +8 ±0.5 ±1 +5 +4 +3 +2.2 ±0.5 ±0.3 ±2 ±0.015 ±0.5 ±0.015 ±1.5 +0.05 +0.04 +0.05 +0.04 1.3 V mA kΩ 1 1 2 nF nF μF 15 1 Test Conditions/Comments Output unloaded External reference needs to be exactly as stated; otherwise, accuracy errors show up as error in output AVDD must have minimum 1.3 V headroom AVDD/AVSS must have minimum 1.3 V headroom TA = 25°C ±10.5 V range TA = 25°C, ±10.5 V range ±10.5 V range ±10.5 V range TA = 25°C, ±10.5 V range ±10.5 V range 0 V to 10.5 V range TA = 25°C, 0 V to 10.5 V range 0 V to 5 V range TA = 25°C, 0 V to 5 V range All ranges TA = 25°C All ranges TA = 25°C Output unloaded TA = 25°C 0.12 7 4.5 2 2.5 45.5 Ω μs μs V/μs μV rms μV rms Rev. 0 | Page 4 of 32 External compensation capacitor required; see the Driving Inductive Loads section Specified with 2 kΩ || 220 pF, ±0.05% Specified with 2 kΩ || 220 pF, ±0.05% Specified with 2 kΩ || 220 pF 0.1 Hz to 10 Hz bandwidth 100 kHz bandwidth AD5748 Parameter1 Output Noise Spectral Density Min AC PSRR DC PSRR CURRENT OUTPUT, IOUT Output Current Ranges Accuracy, Internal RSET4 Total Unadjusted Error (TUE)2 Relative Accuracy (INL) Offset Error Offset Error TC3 Gain Error Gain TC3 Full-Scale Error Full-Scale TC3 Accuracy, External RSET4 Total Unadjusted Error (TUE)2 Relative Accuracy (INL) Offset Error Offset Error TC3 Gain Error Gain TC Full-Scale Error Full-Scale TC3 CURRENT OUTPUT CHARACTERISTICS3 Current Loop Compliance Voltage Resistive Load Max −0.5 −0.3 −0.02 −16 −10 −0.2 −0.03 −0.2 −0.125 −0.3 −0.1 −0.02 −14 −11 −0.08 −0.07 −0.1 −0.07 Unit nV/√Hz −65 dB 10 μV/V 0 4 ±0.15 ±0.01 +5 ±3 ±0.006 ±8 mA mA +0.5 +0.3 +0.02 +16 +10 % FSR % FSR % FSR μA μA ppm FSR/°C % FSR % FSR ppm FSR/°C % FSR % FSR ppm FSR/°C TA = 25°C 4 mA to 21 mA, 0 mA to 21 mA 4 mA to 21 mA, 0 mA to 21 mA TA = 25°C 4 mA to 21 mA, 0 mA to 21 mA 4 mA to 21 mA, 0 mA to 21 mA TA = 25°C 4 mA to 21 mA, 0 mA to 21 mA 4 mA to 21 mA, 0 mA to 21 mA TA = 25°C 4 mA to 21 mA, 0 mA to 21 mA % FSR % FSR % FSR μA μA ppm FSR/°C % FSR % FSR ppm FSR/°C % FSR % FSR ppm FSR/°C TA = 25°C 4 mA to 21 mA, 0 mA to 21 mA 4 mA to 21 mA, 0 mA to 21 mA TA = 25°C 4 mA to 21 mA, 0 mA to 21 mA 4 mA to 21 mA, 0 mA to 21 mA TA = 25°C 4 mA to 21 mA, 0 mA to 21 mA 4 mA to 21 mA, 0 mA to 21 mA TA = 25°C 4 mA to 21 mA, 0 mA to 21 mA +0.2 +0.03 +0.3 +0.1 +0.02 +14 +11 ±0.02 ±0.01 +5 ±2 +0.08 +0.07 ±0.02 ±1 +0.1 +0.07 ±0.02 ±2 AVDD − 2.75 V See comments Chosen so that compliance is not exceeded Needs appropriate capacitor at higher inductance values; see the Driving Inductive Loads section See comments 8.5 1.2 Test Conditions/Comments Measured at 10 kHz; specified with 2 kΩ || 220 pF 200 mV, 50 Hz/60 Hz sine wave superimposed on power supply voltage Outputs unloaded 21 21 +0.2 +0.125 ±0.02 ±4 0 Inductive Load Settling Time 4 mA to 21 mA, Full-Scale Step 120 μA Step, 4 mA to 21 mA Range DC PSRR Output Impedance DIGITAL INPUT Input High Voltage, VIH Input Low Voltage, VIL Input Current Pin Capacitance DIGITAL OUTPUTS3 FAULT, IFAULT, TEMP, VFAULT Output Low Voltage, VOL Output Low Voltage, VOL Output High Voltage, VOH Typ 165 Ą 1 130 μs μs μA/V MΩ 250 Ω load 250 Ω load 0.8 +1 5 V V μA pF Per pin Per pin V V V 10 kΩ pull-up resistor to DVCC At 2.5 mA 10 kΩ pull-up resistor to DVCC JEDEC compliant 2 −1 0.4 0.6 3.6 Rev. 0 | Page 5 of 32 AD5748 Parameter1 SDO Output Low Voltage, VOL Output High Voltage, VOH High Impedance Output Capacitance High Impedance Leakage Current POWER REQUIREMENTS Min Typ Max 0.5 DVCC − 0.5 0.5 DVCC − 0.5 3 Unit Test Conditions/Comments V V pF Sinking 200 μA Sourcing 200 μA −1 +1 μA 12 −12 24 −24 V V 4.4 5.5 5.2 V mA AISS 5.2 5.2 2.0 6.2 6.2 2.5 mA mA mA DICC Power Dissipation 2.5 2.5 0.3 108 3 3 1 mA mA mA mW Positive Analog Supply, AVDD Negative Analog Supply, AVSS Digital Power Supply, DVCC Input Voltage AIDD 2.7 1 Temperature range: −40°C to +105°C; typical at +25°C. Specification includes gain and offset errors over temperature, and drift after 1000 hours, TA = 125°C. Guaranteed by characterization, but not production tested. 4 See the Current Setting Resistor section. 2 3 Rev. 0 | Page 6 of 32 ±10% ±10% Output unloaded, output disabled, R3, R2, R1, R0 = 0, 1, 0, 1 Current output enabled Voltage output enabled Output unloaded, output disabled, R3, R2, R1, R0 = 0, 1, 0, 1 Current output enabled Voltage output enabled VIH = DVCC, VIL = GND AVDD/AVSS = ±24 V, outputs unloaded AD5748 TIMING CHARACTERISTICS AVDD/AVSS = ±12 V (± 10%) to ±24 V (± 10%), DVCC = 2.7 V to 5.5 V, GND = 0 V. VOUT: RLOAD = 2 kΩ, CL = 200 pF, IOUT: RLOAD = 300 Ω. All specifications TMIN to TMAX, unless otherwise noted. Table 3. Parameter 1, 2 t1 t2 t3 t4 t5 t6 t7 t8 t9, t10 t11 t12 t13 1 2 Limit at TMIN, TMAX 20 8 8 5 10 5 5 5 1.5 5 40 10 Unit ns min ns min ns min ns min ns min ns min ns min ns min μs max ns min ns max ns min Description SCLK cycle time SCLK high time SCLK low time SYNC falling edge to SCLK falling edge setup time 16th SCLK falling edge to SYNC rising edge (on 24th SCLK falling edge if using PEC) Minimum SYNC high time (write mode) Data setup time Data hold time CLEAR pulse low/high activation time Minimum SYNC high time (read mode) SCLK rising edge to SDO valid (SDO CL = 15 pF) RESET pulse low time Guaranteed by characterization, but not production tested. All input signals are specified with tR = tF = 5 ns (10% to 90% of DVCC) and timed from a voltage level of 1.2 V. Rev. 0 | Page 7 of 32 AD5748 Timing Diagrams t1 SCLK 1 2 16 t3 t6 t2 t4 t5 SYNC t8 t7 SDIN D15 D0 CLEAR t10 t9 VOUT 08922-002 RESET t13 Figure 2. Write Mode Timing Diagram 1 2 A2 A1 16 SCLK SYNC SDIN t11 A0 R=1 0 X X X X X X X X X X X SDO X X X X X R3 R2 R1 R0 CLRSEL OUTEN Figure 3. Readback Mode Timing Diagram Rev. 0 | Page 8 of 32 RSET PEC ERROR OVER TEMP IOUT FAULT VOUT FAULT 08922-003 t12 AD5748 ABSOLUTE MAXIMUM RATINGS TA = 25°C unless otherwise noted. Transient currents of up to 100 mA do not cause SCR latch-up. Table 4. Parameter AVDD to GND AVSS to GND AVDD to AVSS DVCC to GND VSENSE+ to GND VSENSE− to GND Digital Inputs to GND Digital Outputs to GND VREF to GND VIN to GND VOUT, IOUT to GND Operating Temperature Range, Industrial Storage Temperature Range Junction Temperature (TJ max) 32-Lead LFCSP Package θJA Thermal Impedance Lead Temperature Soldering ESD (Human Body Model) Rating −0.3 V to +30 V +0.3 V to −28 V −0.3 V to +58 V −0.3 V to +7 V AVSS to AVDD ±5.0 V −0.3 V to DVCC + 0.3 V or 7 V (whichever is less) −0.3 V to DVCC + 0.3 V or 7 V (whichever is less) −0.3 V to +7 V −0.3 V to +7 V AVSS to AVDD −40°C to +105°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ESD CAUTION −65°C to +150°C 125°C 28°C/W JEDEC industry standard J-STD-020 3 kV Rev. 0 | Page 9 of 32 AD5748 32 31 30 29 28 27 26 25 NC/IFAULT FAULT/TEMP RESET HW SELECT NC NC NC NC PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 1 2 3 4 5 6 7 8 PIN 1 INDICATOR AD5748 TOP VIEW (Not to Scale) 24 23 22 21 20 19 18 17 VSENSE+ VOUT VSENSE– AVSS COMP1 COMP2 IOUT AVDD NOTES 1. NC = NO CONNECT. 2. THE EXPOSED PADDLE IS TIED TO AVSS. 08922-004 AD2/R1 AD1/R2 AD0/R3 REXT2 REXT1 VREF VIN GND 9 10 11 12 13 14 15 16 SDO/VFAULT CLRSEL CLEAR DVCC GND SYNC/RSET SCLK/OUTEN SDIN/R0 Figure 4. Pin Configuration Table 4. Pin Function Descriptions Pin No. 1 Mnemonic SDO/VFAULT 2 CLRSEL 3 CLEAR 4 5 6 DVCC GND SYNC/RSET 7 SCLK/OUTEN 8 SDIN/R0 9 AD2/R1 10 AD1/R2 Description Serial Data Output (SDO). In software mode, this pin is used to clock data from the input shift register in readback mode. Data is clocked out on the rising edge of SCLK and is valid on the falling edge of SCLK. This pin is a CMOS output. Short-Circuit Fault Alert (VFAULT). In hardware mode, this pin acts as a short-circuit fault alert pin and is asserted low when a short-circuit error is detected. This pin is an open-drain output and must be connected to a pull-up resistor. In hardware or software mode, this pin selects the clear value, either zero-scale or midscale code. In software mode, this pin is implemented as a logic OR with the internal CLRSEL bit. Active High Input. Asserting this pin sets the output current/voltage to zero-scale code or midscale code of the range selected (user-selectable). CLEAR is a logic OR with the internal clear bit. In software mode, during power-up, the CLEAR pin level determines the power-on condition of the voltage channel, which can be active 0 V or tristate. See the Asynchronous Clear (CLEAR) section for more details. Digital Power Supply. Ground Connection. Positive Edge-Sensitive Latch (SYNC). In software mode, a rising edge parallel loads the input shift register data into the AD5748, also updating the output. Resistor Select (RSET). In hardware mode, this pin chooses whether the internal or the external current sense resistor is used. If RSET = 0, the external sense resistor is chosen. If RSET = 1, the internal sense resistor is chosen. Serial Clock Input (SCLK). In software mode, data is clocked into the input shift register on the falling edge of SCLK. This pin operates at clock speeds of up to 50 MHz. Output Enable (OUTEN). In hardware mode, this pin acts as an output enable pin. Serial Data Input (SDIN). In software mode, data must be valid on the falling edge of SCLK. Range Decode Bit (R0). In hardware mode, this pin, in conjunction with R1, R2, and R3, selects the output current/voltage range setting on the part. Device Addressing Bit (AD2). In software mode, this pin, in conjunction with AD1 and AD0, allows up to eight devices to be addressed on one bus. Range Decode Bit (R1). In hardware mode, this pin, in conjunction with R0, R2, and R3, selects the output current/voltage range setting on the part. Device Addressing Bit (AD1). In software mode, this pin, in conjunction with AD2 and AD0 allows up to eight devices to be addressed on one bus. Range Decode Bit (R2). In hardware mode, this pin, in conjunction with R0, R1, and R3, selects the output current/voltage range setting on the part. Rev. 0 | Page 10 of 32 AD5748 Pin No. 11 Mnemonic AD0/R3 12, 13 REXT2, REXT1 14 15 16 17 18 19, 20 VREF VIN GND AVDD IOUT COMP2, COMP1 21 22 AVSS VSENSE− 23 24 25, 26, 27, 28 29 VOUT VSENSE+ NC 30 31 RESET FAULT/TEMP 32 NC/IFAULT 33 (EPAD) Exposed paddle HW SELECT Description Device Addressing Bit (AD0). In software mode, this pin, in conjunction with AD1 and AD2, allows up to eight devices to be addressed on one bus. Range Decode Bit (R3). In hardware mode, this pin, in conjunction with, R0, R1, and R2, selects the output current/voltage range setting on the part. A 15 kΩ external current setting resistor can be connected between the REXT1 and REXT2 pins to improve the IOUT temperature drift performance. Buffered Reference Input. Buffered Analog Input (0 V to 4.096 V). Ground Connection. Positive Analog Supply Pin. Current Output Pin. Optional Compensation Capacitor Connections for the Voltage Output Buffer. These are used to drive higher capacitive loads on the output. These pins also reduce overshoot on the output. Care should be taken when choosing the value of the capacitor connected between the COMP1 and COMP2 pins because it has a direct influence on the settling time of the output. See the Driving Large Capacitive Loads section for further details. Negative Analog Supply Pin. Sense Connection for the Negative Voltage Output Load Connection. This pin must stay within ±3.0 V of ground for correct operation. Buffered Analog Output Voltage. Sense Connection for the Positive Voltage Output Load Connection. No Connect. Can be tied to GND. This pin is used to configure the part to hardware or software mode. HW SELECT = 0 selects software control. HW SELECT = 1 selects hardware control. Resets the part to its power-on state. Fault Alert (FAULT). In software mode, this pin acts as a general fault alert pin. It is asserted low when an open circuit, short circuit, overtemperature error, or PEC interface error is detected. This pin is an open-drain output and must be connected to a pull-up resistor. Overtemperature Fault (TEMP). In hardware mode, this pin acts as an overtemperature fault pin. It is asserted low when an overtemperature error is detected. This pin is an open-drain output and must be connected to a pull-up resistor. No Connect (NC). In software mode, this pin is a no connect. Instead, tie this pin to GND. Open-Circuit Fault Alert (IFAULT). In hardware mode, this pin acts as an open-circuit fault alert pin. It is asserted low when an open-circuit error is detected. This pin is an open-drain output and must be connected to a pullup resistor. The exposed paddle is tied to AVSS. Rev. 0 | Page 11 of 32 AD5748 TYPICAL PERFORMANCE CHARACTERISTICS VOLTAGE OUTPUT 0.0020 0.10 0.08 0.06 0.0005 0.04 0 –0.0005 –0.0010 0.02 0 –0.02 –0.0015 –0.04 –0.0020 –0.06 +5V +10V ±10V –0.0025 –0.08 –0.0030 0 0.585 1.170 1.755 2.341 2.926 3.511 4.096 VIN (V) –0.10 –40 105 Figure 8. Total Unadjusted Error vs. Temperature 0.03 +5V LINEARITY, NO LOAD +10V LINEARITY, NO LOAD ±10V LINEARITY, NO LOAD AVDD = +24V 0.004 AVSS = –24V 0.02 FULL-SCALE ERROR (%FSR) 0.003 0.002 0.001 0 –0.001 –0.002 –0.003 0.01 0 –0.01 –0.02 –0.03 –0.004 –40 25 –0.04 08922-006 –0.005 105 TEMPERATURE (°C) +5V RANGE, FULL-SCALE ERROR +10V RANGE, FULL-SCALE ERROR ±10V RANGE, FULL-SCALE ERROR –40 25 Figure 9. Full-Scale Error vs. Temperature Figure 6. Integral Nonlinearity Error vs. Temperature 2.5 0.006 AVDD = +24V AVSS = –24V 0.002 0 –0.002 –0.004 +5V +10V ±10V –0.006 AVDD = +24V AVSS = –24V 2.0 BIPOLAR ZERO ERROR (mV) 0.004 105 TEMPERATURE (°C) 08922-009 0.005 –0.008 1.5 1.0 ±10V ZERO ERROR 0.5 0 –0.5 –1.0 –1.5 –2.0 0 0.585 1.170 1.755 2.341 2.926 3.511 VIN (V) 4.096 08922-007 –2.5 –0.010 –40 25 105 TEMPERATURE (°C) Figure 10. Bipolar Zero Error vs. Temperature Figure 7. Total Unadjusted Error vs. VIN Rev. 0 | Page 12 of 32 08922-010 INL (%FSR) 25 TEMPERATURE (°C) Figure 5. Integral Nonlinearity Error vs. VIN TUE (%FSR) +5V POSITIVE TUE, NO LOAD +10V POSITIVE TUE, NO LOAD ±10V POSITIVE TUE, NO LOAD +5V NEGATIVE TUE, NO LOAD +10V NEGATIVE TUE, NO LOAD ±10V NEGATIVE TUE, NO LOAD 08922-008 TUE (%FSR) 0.0010 08922-005 INL (%FSR) AVDD = +24V 0.0015 AVSS = –24V AD5748 0.020 0.10 AVDD = +24V AVSS = –24V 0.015 0.08 0.06 0.04 0.005 TUE (%FSR) 0 –0.005 –0.010 –0.02 –0.06 +5V GAIN, NO LOAD +10V GAIN, NO LOAD ±10V GAIN, NO LOAD 25 105 TEMPERATURE (°C) –0.10 ±24.0 ±26.4 Figure 14. Total Unadjusted Error vs. Supply Voltages 2.5 1.2 AVDD = +24V 2.0 AVSS = –24V OUTPUT UNLOADED 1.5 1.0 1.0 HEADROOM (V) 0.5 0 –0.5 –1.0 0.8 ±10V AV DD HEADROOM, LOAD OFF 0.6 0.4 –1.5 –2.5 –3.0 0.2 +5V RANGE +10V RANGE ±10V RANGE –40 25 105 TEMPERATURE (°C) Figure 12. Zero-Scale Error (Offset Error) vs. Temperature 0.002 –40 25 105 TEMPERATURE (°C) Figure 15. AVDD Headroom, ±10 V Range, Output Set to 10 V, Load Off 0.05 +5V LINEARITY, NO LOAD +10V LINEARITY, NO LOAD ±10V LINEARITY, NO LOAD 0.04 OUTPUT VOLTAGE DELTA (V) 0.003 0 08922-015 –2.0 08922-012 ZERO-SCALE ERROR (mV) ±15.0 SUPPLY VOLTAGES (AVDD/AVSS) Figure 11. Gain Error vs. Temperature 0.001 0 –0.001 –0.002 +5V RANGE ±10V RANGE 0.03 0.02 0.01 0 –0.01 –0.02 –0.03 –0.04 –0.003 +11.2/–10.8 ±15.0 ±24.0 ±26.4 SUPPLY VOLTAGES (AVDD/AVSS) 08922-013 INL (%FSR) +11.2/–10.8 08922-014 –40 –0.08 08922-011 –0.025 0 –0.04 –0.015 –0.020 0.02 Figure 13. Integral Nonlinearity Error vs. Supply Voltage –0.05 –15 –13 –11 –9 –7 –5 –3 –1 1 3 5 7 9 11 13 15 SOURCE/SINK CURRENT (mA) Figure 16. Source and Sink Capability of Output Amplifier Rev. 0 | Page 13 of 32 08922-016 GAIN ERROR (%FSR) 0.010 +5V POSITIVE TUE, NO LOAD +10V POSITIVE TUE, NO LOAD ±10V POSITIVE TUE, NO LOAD +5V NEGATIVE TUE, NO LOAD +10V NEGATIVE TUE, NO LOAD ±10V NEGATIVE TUE, NO LOAD AD5748 12 10 1 VOLTAGE (V) 8 6 4 2 –3 2 7 12 17 22 27 TIME (µs) CH1 5.00V CH2 20.0mV BW M1.0µs A CH1 08922-020 0 –8 08922-017 2 3.00V Figure 20. VOUT Enable Glitch, Load = 2 kΩ || 1 nF Figure 17. Full-Scale Positive Step 12 10 VOLTAGE (V) 8 6 2 –3 2 7 12 17 22 1s/DIV 08922-018 5µV/DIV 0 –8 08922-021 4 27 TIME (µs) Figure 21. Peak-to-Peak Noise (0.1 Hz to 10 Hz Bandwidth) Figure 18. Full-Scale Negative Step 40 35 30 20 15 10 0 –5 –1.0 100µV/DIV –0.5 0 0.5 1.0 1.5 2.0 TIME (ms) 2.5 1s/DIV Figure 22. Peak-to-Peak Noise (100 kHz Bandwidth) Figure 19. VOUT vs. Time on Power-Up, Load = 2 kΩ || 200 pF Rev. 0 | Page 14 of 32 08922-022 5 08922-019 VOUT (mV) 25 AD5748 1.0 4.0 3.5 0.8 3.0 AVDD 0.6 0.4 VOUT (V) 2.0 1.5 0.2 1.0 VOUT 0 0.5 0 –1.5 –1.0 –0.5 0 0.5 1.0 1.5 TIME (ms) –0.2 2.0 08922-023 AVDD (V) 2.5 Figure 23. AVDD and VOUT vs. Time on Power-Up Rev. 0 | Page 15 of 32 AD5748 CURRENT OUTPUT 0.004 0.010 +4mA TO +20mA 0mA TO +20mA +4mA TO +20mA INTERNAL RSET LINEARITY 0mA TO +20mA INTERNAL R SET LINEARITY 0.008 0.002 0.006 0.004 INL (%FSR) INL (%FSR) 0 –0.002 –0.004 0.002 0 –0.002 –0.004 –0.006 –0.006 –0.008 0.585 1.170 1.755 2.341 2.926 3.511 4.096 VIN (V) –0.010 08922-024 0 +11.2/–10.8 ±26.4 Figure 27. Integral Nonlinearity Error Current Mode, Internal RSET Sense Resistor 0.010 AVDD = +24V AVSS = –24V 0.002 ±24.0 SUPPLY VOLTAGES (AVDD/AVSS) Figure 24. Integral Nonlinearity Error vs. VIN, External RSET Resistor 0.004 ±15.0 08922-027 –0.008 AVDD = +24V AVSS = –24V –0.010 +4mA TO +20mA 0mA TO +20mA 0.008 0.006 0 TUE (%FSR) –0.004 –0.006 –0.004 –0.006 +4mA TO +20mA 0mA TO +20mA 0 0.585 1.170 1.755 2.341 2.926 3.511 4.096 VIN (V) 0 0.585 1.170 1.755 2.341 2.926 3.511 4.096 VIN (V) Figure 28. Total Unadjusted Error vs. VIN, External RSET Resistor Figure 25. Integral Nonlinearity Error vs. VIN, Internal RSET Resistor 0.015 +4mA TO +20mA EXTERNAL R SET LINEARITY 0mA TO +20mA EXTERNAL R SET LINEARITY +4mA TO +20mA 0mA TO +20mA AVDD = +24V AVSS = –24V 0.010 0.006 0.004 TUE (%FSR) 0.005 0.002 0 –0.002 0 –0.005 –0.004 –0.006 –0.010 –0.008 –0.010 –0.015 +11.2/–10.8 ±15.0 ±24.0 ±26.4 SUPPLY VOLTAGES (AVDD/AVSS) 08922-026 INL (%FSR) AVDD = +24V AVSS = –24V –0.008 08922-025 –0.012 08922-028 –0.010 0.008 0 –0.002 –0.008 0.010 0.002 0 0.585 1.170 1.755 2.341 2.926 3.511 4.096 VIN (V) Figure 29. Total Unadjusted Error vs. VIN, Internal RSET Resistor Figure 26. Integral Nonlinearity Error, Current Mode, External RSET Sense Resistor Rev. 0 | Page 16 of 32 08922-029 INL (%FSR) 0.004 –0.002 AD5748 0.10 0.004 0.02 0.002 0 –0.02 –0.002 –0.04 –0.004 –0.06 –0.006 –0.08 –0.008 AVDD = +24V AVSS = –24V –0.010 –40 +11.2/–10.8 ±15.0 ±24.0 ±26.4 SUPPLY VOLTAGES (AVDD/AVSS) 0.10 +4mA TO +20mA INTERNAL RSET POSITIVE TUE 0mA TO +20mA INTERNAL R SET POSITIVE TUE +4mA TO +20mA INTERNAL RSET NEGATIVE TUE 0mA TO +20mA INTERNAL R SET NEGATIVE TUE 0.08 0.06 0.04 0.04 TUE (%FSR) 0.02 0 –0.02 0.02 0 –0.02 –0.04 –0.04 –0.06 –0.06 –0.08 –0.08 +11.2/–10.8 ±15.0 ±24.0 ±26.4 SUPPLY VOLTAGES (AVDD/AVSS) –0.10 08922-031 –0.10 Figure 31. Total Unadjusted Error Current Mode, Internal RSET Sense Resistor –40 25 105 TEMPERATURE (°C) Figure 34. Total Unadjusted Error vs. Temperature, Internal RSET Sense Resistor 0.10 0.010 0.008 +4mA TO +20mA INTERNAL R SET POSITIVE TUE 0mA TO +20mA INTERNAL RSET POSITIVE TUE +4mA TO +20mA INTERNAL R SET NEGATIVE TUE 0mA TO +20mA INTERNAL RSET NEGATIVE TUE 08922-034 0.06 105 Figure 33. INL vs. Temperature, External RSET Sense Resistor 0.10 0.08 25 TEMPERATURE (°C) Figure 30. Total Unadjusted Error Current Mode, External RSET Sense Resistor TUE (%FSR) 0 08922-033 INL (%FSR) 0.04 –0.10 +4mA TO +20mA INTERNAL RSET LINEARITY 0mA TO +20mA INTERNAL R SET LINEARITY 0.08 0.06 0.004 0.04 TUE (%FSR) 0.006 0.002 0 –0.002 0 –0.02 –0.04 –0.006 –0.06 –0.008 AVDD = +24V AVSS = –24V –0.010 –40 –0.08 25 105 TEMPERATURE (°C) Figure 32. INL vs. Temperature, Internal RSET Sense Resistor +4mA TO +20mA EXTERNAL R SET POSITIVE TUE 0mA TO +20mA EXTERNAL R SET POSITIVE TUE +4mA TO +20mA EXTERNAL R SET NEGATIVE TUE 0mA TO +20mA EXTERNAL R SET NEGATIVE TUE 0.02 –0.004 –0.10 08922-032 INL (%FSR) +4mA TO +20mA EXTERNAL R SET LINEARITY 0mA TO +20mA EXTERNAL RSET LINEARITY 0.006 08922-030 TUE (%FSR) 0.06 0.008 –40 25 TEMPERATURE (°C) 105 08922-035 0.08 0.010 +4mA TO +20mA EXTERNAL R SET POSITIVE TUE 0mA TO +20mA EXTERNAL RSET POSITIVE TUE +4mA TO +20mA EXTERNAL R SET NEGATIVE TUE 0mA TO +20mA EXTERNAL RSET NEGATIVE TUE Figure 35. Total Unadjusted Error vs. Temperature, External RSET Sense Resistor Rev. 0 | Page 17 of 32 AD5748 0.04 +4mA TO +20mA EXTERNAL RSET 0mA TO +20mA EXTERNAL R SET 0.03 FULL-SCALE ERROR (%FSR) 2 0 –2 –4 AVDD = +24V AVSS = –24V 25 105 TEMPERATURE (°C) Figure 36. Zero-Scale Error vs. Temperature, External RSET Sense Resistor –0.03 –0.04 AVDD = +24V AVSS = –24V –40 25 105 TEMPERATURE (°C) Figure 39. Full-Scale Error vs. Temperature, Internal RSET Sense Resistor 0.020 +4mA TO +20mA INTERNAL R SET 0mA TO +20mA INTERNAL RSET +4mA TO +20mA EXTERNAL RSET 0mA TO +20mA EXTERNAL R SET 0.015 GAIN ERROR (%FSR) 10 AVDD = +24V AVSS = –24V 5 0 –5 0.010 0.005 0 –0.005 –10 –40 25 105 TEMPERATURE (°C) –0.015 –40 105 Figure 40. Gain Error vs. Temperature, External RSET Sense Resistor 0.08 +4mA TO +20mA EXTERNAL R SET 0mA TO +20mA EXTERNAL R SET 0.03 25 TEMPERATURE (°C) Figure 37. Zero-Scale Error vs. Temperature, Internal RSET Sense Resistor 0.04 AVDD = +24V AVSS = –24V 08922-042 –20 –0.010 ±20mA INTERNAL R SET ±24mA INTERNAL R SET 08922-037 ZERO-SCALE ERROR (µA) –0.02 15 –15 0.06 +4mA TO +20mA INTERNAL R SET 0mA TO +20mA INTERNAL RSET 0.04 GAIN ERROR (%FSR) 0.02 0.01 0 –0.01 –0.02 0.02 0 –0.02 –0.04 –0.06 –0.03 AV DD = +24V AVSS = –24V –0.08 –0.04 –0.10 –40 25 105 TEMPERATURE (°C) 08922-040 FULL-SCALE ERROR (%FSR) 0 –0.01 –0.06 08922-036 –40 20 0.01 –0.05 –6 25 0.02 AVDD = +24V AVSS = –24V –40 25 105 TEMPERATURE (°C) Figure 41. Gain Error vs. Temperature, Internal RSET Sense Resistor Figure 38. Full-Scale Error vs. Temperature, External RSET Sense Resistor Rev. 0 | Page 18 of 32 08922-043 ZERO-SCALE ERROR (µA) 4 +4mA TO +20mA INTERNAL R SET 0mA TO +20mA INTERNAL RSET 08922-041 6 AD5748 1.4 0.025 1.2 AVDD COMPLIANCE 0.020 CURRENT (A) COMPLIANCE (V) 1.0 0.8 0.6 0.015 0.010 0.4 0.005 –40 25 0 –12 08922-044 0 105 TEMPERATURE (°C) 1 8 14 21 28 34 41 48 54 61 68 TIME (µs) Figure 42. Output Compliance vs. Temperature Tested When IOUT = 10.8 mA Figure 45. 4 mA to 20 mA Output Current Step 3000 0.000010 12 –6 08922-047 0.2 0.000008 10 2500 0.000006 8 0.000004 0 DICC (µA) IOUT (A) IOUT 4 –0.000002 DVCC = 5V 1500 1000 –0.000004 2 –0.000006 0 DVCC = 3V –0.000010 –8 –6 –4 –2 0 2 4 6 08922-045 –2 –10 500 –0.000008 10 8 TIME (ms) 0 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 LOGIC LEVEL (V) Figure 46. DICC vs. Logic Input Voltage Figure 43. Output Current vs. Time on Power-Up 0 –2 –4 –6 –8 –10 –12 –14 –18 –2 –1 0 1 2 3 4 5 6 7 TIME (µs) 8 08922-046 –16 Figure 44. Output Current vs. Time on Output Enable Rev. 0 | Page 19 of 32 4.5 5.0 08922-048 VDD IOUT (V) VDD (V) 2000 0.000002 6 AD5748 6 6 5 5 AIDD 4 3 3 AIDD/AISS (mA) 4 2 1 0 –1 2 1 0 –1 –2 AISS –3 ±10.8 ±15.0 ±24.0 AVDD/AVSS (V) ±26.4 Figure 47. AIDD/AISS vs. AVDD/AVSS, VOUT = 0 V AISS –3 ±10.8 ±15.0 ±24.0 ±26.4 AVDD/AVSS (V) Figure 48. AIDD/AISS vs. AVDD/AVSS, IOUT = 0 mA Rev. 0 | Page 20 of 32 08922-050 –2 08922-049 AIDD/AISS (mA) AIDD AD5748 TERMINOLOGY Zero-Scale Error Zero-scale error is the deviation of the actual zero-scale analog output from the ideal zero-scale output. Zero-scale error is expressed in millivolts (mV). Total Unadjusted Error (TUE) TUE is a measure of the output error taking all the various errors into account: INL error, offset error, gain error, and output drift over supplies, temperature, and time. TUE is expressed as a percentage of full-scale range (% FSR). Relative Accuracy or Integral Nonlinearity (INL) INL is a measure of the maximum deviation, in % FSR, from a straight line passing through the endpoints of the output driver transfer function. A typical INL vs. input voltage plot can be seen in Figure 5. Bipolar Zero Error Bipolar zero error is the deviation of the actual vs. ideal halfscale output of 0 V/0 mA with a bipolar range selected. A plot of bipolar zero error vs. temperature can be seen in Figure 10. Bipolar Zero TC Bipolar zero TC is a measure of the change in the bipolar zero error with a change in temperature. It is expressed in ppm FSR/°C. Full-Scale Error Full-scale error is the deviation of the actual full-scale analog output from the ideal full-scale output. Full-scale error is expressed as a percentage of full-scale range (% FSR). Full-Scale TC Full-scale TC is a measure of the change in the full-scale error with a change in temperature. It is expressed in ppm FSR/°C. Gain Error Gain error is a measure of the span error of the output. It is the deviation in slope of the output transfer characteristic from the ideal expressed in % FSR. A plot of gain error vs. temperature can be seen in Figure 11. Gain Error TC Gain error TC is a measure of the change in gain error with changes in temperature. Gain error TC is expressed in ppm FSR/°C. Zero-Scale TC Zero-scale TC is a measure of the change in zero-scale error with a change in temperature. Zero-scale error TC is expressed in ppm FSR/°C. Offset Error Offset error is a measurement of the difference between VOUT (actual) and VOUT (ideal) expressed in millivolts (mV) in the linear region of the transfer function. It can be negative or positive. Output Voltage Settling Time Output voltage settling time is the amount of time it takes for the output to settle to a specified level for a half-scale input change. Slew Rate The slew rate of a device is a limitation in the rate of change of the output voltage. The output slewing speed is usually limited by the slew rate of the amplifier used at its output. Slew rate is measured from 10% to 90% of the output signal and is expressed in V/μs. Current Loop Voltage Compliance Current loop voltage compliance is the maximum voltage at the IOUT pin for which the output current is equal to the programmed value. Power-On Glitch Energy Power-on glitch energy is the impulse injected into the analog output when the AD5748 is powered on. It is specified as the area of the glitch in nV-sec. Power Supply Rejection Ratio (PSRR) PSRR indicates how the output is affected by changes in the power supply voltage. Rev. 0 | Page 21 of 32 AD5748 THEORY OF OPERATION Figure 49 and Figure 50 show a typical configuration of the AD5748 in software mode and in hardware mode, respectively, in an output module system. The HW SELECT pin selects whether the part is configured in software or hardware mode. The analog input to the AD5748 is provided from a low voltage, single-supply, digital-to-analog converter (DAC) such as the AD506x or AD566x, which provides an output range of 0 V to 4.096 V. The supply and reference for the DAC, as well as the reference for the AD5748, can be supplied from a reference such as the ADR392. The AD5748 can operate from supplies up to ±26.4 V. The AD5748 is a single-channel, precision, voltage/current output driver with hardware or software programmable output ranges. The software ranges are configured via an SPI-/ MICROWIRE-compatible serial interface. The analog input to the AD5748 is provided from a low voltage, single-supply, digital-to-analog converter and is internally conditioned to provide the desired output current/voltage range. The analog input range is 0 V to 4.096 V. The output current range is programmable across two current ranges: 4 mA to 21 mA and 0 mA to 21 mA. The voltage output is provided from a separate pin that can be configured to provide 0 V to 5 V, 0 V to 10.5 V, or ±10.5 V output ranges. The current and voltage outputs are available on separate pins. Only one output can be enabled at one time. The output range is selected by programming the R3 to R0 bits in the control register (see Table 6 and Table 7). SOFTWARE MODE In current mode, software-selectable output ranges include 0 mA to 21 mA, and 4 mA to 21 mA. In voltage mode, software-selectable output ranges include 0 V to 5 V, 0 V to 10.5 V, and ±10.5 V. VDD AGND VSS AD5748 ADR392 SCLK SDI/DIN MCU SDO VDD AVDD GND AVSS VSENSE+ VSENSE– VREF REFIN VOUT RANGE SCALE VOUT 0V TO +5V, 0V TO +10.5V, ±10.5V VIN AD506x AD566x IOUT RANGE SCALE SYNC1 SCLK SDIN SDO SERIAL INTERFACE SYNC IOUT 4mA TO 21mA, 0mA TO 21mA VOUT SHORT FAULT IOUT OPEN FAULT OVERTEMP FAULT PEC ERROR STATUS REGISTER HW SELECT FAULT 08922-051 ADP1720 Figure 49. Typical System Configuration in Software Mode (Pull-Up Resistors Not Shown for Open-Drain Outputs) Rev. 0 | Page 22 of 32 AD5748 VDD AGND VSS ADP1720 AD5748 REFIN VDD VOUT RANGE SCALE SDI/DIN MCU SDO VSENSE+ VSENSE– VREF ADR3192 SCLK AVDD GND AVSS VOUT 0V TO +5V, 0V TO +10.5V, ±10.5V VIN AD506x AD566x SYNC1 IOUT RANGE SCALE DVCC IOUT 4mA TO +21mA, 0mA TO +21mA HW SELECT OUTEN R3 R2 R1 VFAULT IFAULT R0 08922-052 TEMP OUTPUT RANGE SELECT PINS Figure 50. Typical System Configuration in Hardware Mode Using Internal DAC Reference (Pull-Up Resistors Not Shown for Open-Drain Outputs) Table 5. Suggested Parts for Use with AD5748 DAC AD5660 AD5664R AD5668 AD5060 AD5064 AD5662 AD5664 1 2 Reference Internal Internal Internal ADR434 ADR434 ADR3922 ADR3922 Power ADP17201 N/A N/A ADP1720 N/A ADR3922 N/A Accuracy 12-bit INL N/A N/A 16-bit INL N/A 12-bit INL N/A Description Mid end system, single channel, internal reference Mid end system, quad channel, internal reference Mid end system, octal channel, internal reference High end system, single channel, external reference High end system, quad channel, external reference Mid end system, single channel, external reference Mid end system, quad channel, external reference ADP1720 input range up to 28 V. ADR392 input range up to 15 V. Rev. 0 | Page 23 of 32 AD5748 CURRENT OUTPUT ARCHITECTURE Driving Large Capacitive Loads The voltage input from the analog input VIN pin (0 V to 4.096 V) is either converted to a current (see Figure 51), which is then mirrored to the supply rail so that the application simply sees a current source output with respect to an internal reference voltage, or buffered and scaled to output a software-selectable unipolar or bipolar voltage range (see Figure 52). The reference is used to provide internal offsets for range and gain scaling. The selectable output range is programmable through the digital interface. The voltage output amplifier is capable of driving capacitive loads of up to 1 μF with the addition of a nonpolarized compensation capacitor between the COMP1 and COMP2 pins. AVDD RANGEDECODE FROM INTERFACE R2 R3 POWER-ON STATE OF THE AD5748 T2 IOUT RANGE SCALING VREF T1 A2 A1 IOUT 08922-059 VIN RSET Figure 51. Current Output Configuration RANGE DECODE FROM INTERFACE VSENSE+ VREF VOUT RANGE SCALING VOUT VOUT SHORT FAULT VSENSE– 08922-054 VIN (0V TO 4.096V) Without the compensation capacitor, up to 20 nF capacitive loads can be driven. Care should be taken to choose an appropriate value for the CCOMP capacitor. This capacitor, while allowing the AD5748 to drive higher capacitive loads and reduce overshoot, increases the settling time of the part and, therefore, affects the bandwidth of the system. Considered values of this capacitor should be in the range 100 pF to 4 nF depending on the tradeoff required between settling time, overshoot, and bandwidth. Figure 52. Voltage Output DRIVING INDUCTIVE LOADS When driving inductive or poorly defined loads, connect a 0.01 μF capacitor between IOUT and GND. This ensures stability with loads beyond 50 mH. There is no maximum capacitance limit. The capacitive component of the load may cause slower settling. Voltage Output Amplifier The voltage output amplifier is capable of generating both unipolar and bipolar output voltages. It is capable of driving a load of 1 kΩ in parallel with 1.2 μF (with an external compensation capacitor on the COMP1 and COMP2 pins). The source and sink capabilities of the output amplifier can be seen in Figure 16. The slew rate is 2 V/μs. Internal to the device, there is a 2.5 MΩ resistor connected between the VOUT and VSENSE+ pins and similarly between the VSENSE− pin and the internal device ground. Should a fault condition occur, these resistors act to protect the AD5748 by ensuring that the amplifier loop is closed so that the part does not enter into an open-loop condition. On power-up, the AD5748 senses whether hardware or software mode is loaded and sets the power-up conditions accordingly. In software SPI mode, the power-up state of the output is dependent on the state of the CLEAR pin. If the CLEAR pin is pulled high, then the part powers up, driving an active 0 V on the output. If the CLEAR pin is pulled low, then the part powers up with the voltage output channel in tristate mode. In both cases, the current output channel powers up in a tristate condition (0 mA). This allows the voltage and current outputs to be connected together if desired. To put the part into normal operation, the user must set the OUTEN bit in the control register to enable the output and, in the same write, set the output range configuration using the R3 to R0 range bits. If the CLEAR pin is still high (active) during this write, the part automatically clears to its normal clear state as defined by the programmed range and by the CLRSEL pin or CLRSEL bit (see the Asynchronous Clear (CLEAR) section for more details). The CLEAR pin must be taken low to operate the part in normal mode. The CLEAR pin is typically driven directly from a microcontroller. In cases where the power supply for the AD5748 supply may be independent of the microcontroller power supply, the user can connect a weak pull-up resistor to DVCC or a pull-down resistor to ground to ensure that the correct power-up condition is achieved independent of the microcontroller. A 10 kΩ pullup/pull-down resistor on the CLEAR pin should be sufficient for most applications. If hardware mode is selected, the part powers up to the conditions defined by the R3 to R0 range bits and the status of the OUTEN or CLEAR pin. It is recommended to keep the output disabled when powering up the part in hardware mode. The VSENSE− pin can work in a common-mode range of ±3 V with respect to the remote load ground point. The current and voltage are output on separate pins and cannot be output simultaneously. This allows the user to tie both the current and voltage output pins together and configure the end system as a single-channel output. Rev. 0 | Page 24 of 32 AD5748 disabled, both the current and voltage channels go into tristate. The user must set the OUTEN bit to enable the output and simultaneously set the output range configuration. DEFAULT REGISTERS AT POWER-ON The AD5748 power-on reset circuit ensures that all registers are loaded with zero code. In hardware mode, the output can be enabled or disabled using the OUTEN pin. When the output is disabled, both the current and voltage channels both go into tristate. The user must write to the OUTEN pin to enable the output. It is recommended that the output be disabled when changing the ranges. In software SPI mode, the part powers up with all outputs disabled (OUTEN bit = 0). The user must set the OUTEN bit in the control register to enable the output and, in the same write, set the output range configuration using the R3 to R0 bits. If hardware mode is selected, the part powers up to the conditions defined by the R3 to R0 bits and the status of the OUTEN pin. It is recommended to keep the output disabled when powering up the part in hardware mode. SOFTWARE CONTROL Software control is enabled by connecting the HW SELECT pin to ground. In software mode, the AD5748 is controlled over a versatile 3-wire serial interface that operates at clock rates of up to 50 MHz. It is compatible with SPI, QSPI™, MICROWIRE, and DSP standards. RESET FUNCTION In software mode, the part can be reset using the RESET pin (active low) or the reset bit (reset = 1). A reset disables both the current and voltage outputs to their power-on condition. The user must write to the OUTEN bit to enable the output and, in the same write, set the output range configuration. The RESET pin is a level-sensitive input; the part stays in reset mode as long as the RESET pin is low. The reset bit clears to 0 following a reset command to the control register. Input Shift Register OUTEN The input shift register is 16 bits wide. Data is loaded into the device MSB first as a 16-bit word under the control of a serial clock input, SCLK. Data is clocked in on the falling edge of SCLK. The input shift register consists of 16 control bits, as shown in Table 6. The timing diagram for this write operation is shown in Figure 2. The first three bits of the input shift register are used to set the hardware address of the AD5748 device on the printed circuit board (PCB). Up to eight devices can be addressed per board. In software mode, the output can be enabled or disabled using the OUTEN bit in the control register. When the output is Bit D11, Bit D1, and Bit D0 must always be set to 0 during any write sequence. In hardware mode, there is no reset. If using the part in hardware mode, the RESET pin should be tied high. Table 6. Input Shift Register Contents for a Write Operation—Control Register MSB D15 A2 D14 A1 D13 A0 D12 R/W D11 0 D10 R3 D9 R2 D8 R1 D7 R0 D6 CLRSEL D5 OUTEN D4 Clear D3 RSET D2 Reset D1 0 LSB D0 0 Table 7. Input Shift Register Descriptions Bit A2, A1, A0 R/W Description Used in association with the AD2, AD1, and AD0 external pins to determine which part is being addressed by the system controller A2 A1 A0 Function 0 0 0 Addresses part with Pin AD2 = 0, Pin AD1 = 0, Pin AD0 = 0 0 0 1 Addresses part with Pin AD2 = 0, Pin AD1 = 0, Pin AD0 = 1 0 1 0 Addresses part with Pin AD2 = 0, Pin AD1 = 1, Pin AD0 = 0 0 1 1 Addresses part with Pin AD2 = 0, Pin AD1 = 1, Pin AD0 = 1 1 0 0 Addresses part with Pin AD2 = 1, Pin AD1 = 0, Pin AD0 = 0 1 0 1 Addresses part with Pin AD2 = 1, Pin AD1 = 0, Pin AD0 = 1 1 1 0 Addresses part with Pin AD2 = 1, Pin AD1 = 1, Pin AD0 = 0 1 1 1 Addresses part with Pin AD2 = 1, Pin AD1 = 1, Pin AD0 = 1 Indicates a read from or a write to the addressed register Rev. 0 | Page 25 of 32 AD5748 Bit R3, R2, R1, R0 CLRSEL OUTEN Clear RSET Reset Description Selects output configuration in conjunction with RSET RSET R3 R2 R1 R0 Output Configuration 0 0 0 0 0 4 mA to 21 mA (external 15 kΩ current sense resistor) 0 0 0 0 1 0 mA to 21 mA (external 15 kΩ current sense resistor) 0 0 0 1 0 N/A 0 0 0 1 1 N/A 0 0 1 0 0 N/A 0 0 1 0 1 0 V to 5 V 0 0 1 1 0 N/A 0 0 1 1 1 N/A 0 1 0 0 0 N/A 0 1 0 0 1 N/A 0 1 0 1 0 0 V to 10.5 V 0 1 0 1 1 N/A 0 1 1 0 0 ±10.5 V 0 1 1 0 1 N/A 0 1 1 1 0 N/A 0 1 1 1 1 N/A 1 0 0 0 0 4 mA to 21 mA (internal current sense resistor) 1 0 0 0 1 0 mA to 21 mA (internal current sense resistor) 1 0 0 1 0 N/A 1 0 0 1 1 N/A 1 0 1 0 0 N/A 1 0 1 0 1 0 V to 5 V 1 0 1 1 0 N/A 1 0 1 1 1 N/A 1 1 0 0 0 N/A 1 1 0 0 1 N/A 1 1 0 1 0 0 V to 10.5 V 1 1 0 1 1 N/A 1 1 1 0 0 ±10.5 V 1 1 1 0 1 N/A 1 1 1 1 0 N/A 1 1 1 1 1 N/A Sets clear mode to zero scale or midscale. See the Asynchronous Clear (CLEAR) section CLRSEL Function 0 Clear to 0 V 1 Clear to midscale in unipolar mode; clear to zero scale in bipolar mode Output enable bit. This bit must be set to 1 to enable the outputs Software clear bit, active high Select internal/external current sense resistor RSET Function 1 Select internal current sense resistor; used with the R3 to R0 bits to select range 0 Select external current sense resistor; used with the R3 to R0 bits to select range Resets the part to its power-on state Rev. 0 | Page 26 of 32 AD5748 Readback Operation Readback mode is activated by selecting the correct device address (A2, A1, A0) and then setting the R/W bit to 1. By default, the SDO pin is disabled. After having addressed the AD5748 for a read operation, setting R/W to 1 enables the SDO pin and SDO data is clocked out on the 5th rising edge of SCLK. After the data has been clocked out on SDO, a rising edge on SYNC disables (tristate) the SDO pin again. Status register data (see Table 8) and control register data are both available during the same read cycle. The status bits comprise four read-only bits. They are used to notify the user of specific fault conditions that occur, such as an open circuit or short circuit on the output, overtemperature error, or an interface error. If any of these fault conditions occurs, a hardware FAULT is also asserted low, which can be used as a hardware interrupt to the controller. See the Detailed Description of Features section for a full explanation of fault conditions. In hardware mode, there is no status register. The fault conditions (open circuit, short circuit, and overtemperature) are available on Pin IFAULT, Pin VFAULT, and Pin TEMP. If any one of these fault conditions is set, then a low is asserted on the specific fault pin. IFAULT, VFAULT, and TEMP are open-drain outputs and, therefore, can be connected together to allow the user to generate one interrupt to the system controller to communicate a fault. If hardwired in this way, it is not possible to isolate which fault occurred in the system. TRANSFER FUNCTION The AD5748 consists of an internal signal conditioning block that maps the analog input voltage to a programmed output range. The available analog input range is 0 V to 4.096 V. For all ranges, both current and voltage, the AD5748 implements a straight linear mapping function. 0 V maps to the lower end of the selected range; 4.096 V maps to the upper end of the selected range. HARDWARE CONTROL Hardware control is enabled by connecting the HW SELECT pin to DVCC. In this mode, the R3, R2, R1, and R0 pins in conjunction with the RSET pin are used to configure the output range, as per Table 7. Table 8. Input Shift Register Contents for a Read Operation—Status Register MSB D15 A2 D14 A1 D13 A0 D12 1 D11 0 D10 R3 D9 R2 D8 R1 D7 R0 D6 CLRSEL D5 OUTEN D4 RSET D3 PEC error D2 OVER TEMP D1 IOUT fault LSB D0 VOUT fault Table 9. Status Bit Options Bit PEC Error VOUT Fault IOUT Fault OVER TEMP Description This bit is set if there is an interface error detected by CRC-8 error checking. See the Detailed Description of Features section. This bit is set if there is a short circuit on the VOUT pin. This bit is set is there is an open circuit on the IOUT pin. This bit is set if the AD5748 core temperature exceeds approximately 150°C. Rev. 0 | Page 27 of 32 AD5748 DETAILED DESCRIPTION OF FEATURES OUTPUT FAULT ALERT—SOFTWARE MODE In software mode, the AD5748 is equipped with one FAULT pin; this is an open-drain output allowing several AD5748 devices to be connected together to one pull-up resistor for global fault detection. In software mode, the FAULT pin is forced active low by any one of the following fault scenarios: • • • • The voltage at IOUT attempts to rise above the compliance range, due to an open-loop circuit or insufficient power supply voltage. The internal circuitry that develops the fault output avoids using a comparator with window limits because this requires an actual output error before the fault output becomes active. Instead, the signal is generated when the internal amplifier in the output stage has less than approximately 1 V of remaining drive capability. Thus, the fault output activates slightly before the compliance limit is reached. Because the comparison is made within the feedback loop of the output amplifier, the output accuracy is maintained by its open-loop gain, and an output error does not occur before the fault output becomes active. A short is detected on the voltage output pin (VOUT). The short-circuit current is limited to 15 mA. An interface error is detected due to a packet error checking (PEC) failure. See the Packet Error Checking section. If the core temperature of the AD5748 exceeds approximately 150°C. OUTPUT FAULT ALERT—HARDWARE MODE In hardware mode, the AD5748 is equipped with three fault pins: VFAULT, IFAULT, and TEMP. These are open-drain outputs allowing several AD5748 devices to be connected together to one pull-up resistor for global fault detection. In hardware control mode, these fault pins are forced active by any one of the following fault scenarios: • • • output stage has less than approximately 1 V of remaining drive capability. Thus, the fault output activates slightly before the compliance limit is reached. Because the comparison is made within the feedback loop of the output amplifier, the output accuracy is maintained by its open-loop gain, and an output error does not occur before the fault output becomes active. If this fault is detected, the IFAULT pin is forced low. A short is detected on the voltage output pin (VOUT). The short-circuit current is limited to 15 mA. If this fault is detected, the VFAULT pin is forced low. If the core temperature of the AD5748 exceeds approximately 150°C. If this fault is detected, the TEMP pin is forced low. VOLTAGE OUTPUT SHORT-CIRCUIT PROTECTION Under normal operation, the voltage output sinks and sources up to 12 mA and maintains the specified operation. The maximum current that the voltage output delivers is 15 mA; this is the short-circuit current. ASYNCHRONOUS CLEAR (CLEAR) CLEAR is an active high clear that allows the voltage output to be cleared to either zero-scale code or midscale code and is user-selectable via the CLRSEL pin or the CLRSEL bit of the input shift register, as described in Table 7. (The clear select feature is a logical OR function of the CLRSEL pin and the CLRSEL bit.) The current loop output clears to the bottom of its programmed range. When the CLEAR signal is returned low, the output returns to its programmed value or a new value if programmed. A clear operation can also be performed via the clear command in the control register. Table 10. CLRSEL Options Output Clear Value Open-circuit detect. The voltage at IOUT attempts to rise above the compliance range, due to an open-loop circuit or insufficient power supply voltage. The internal circuitry that develops the fault output avoids using a comparator with window limits because this requires an actual output error before the fault output becomes active. Instead, the signal is generated when the internal amplifier in the CLRSEL 0 Unipolar Output Voltage Range 0V 1 Midscale Rev. 0 | Page 28 of 32 Unipolar Current Output Range Zero scale; for example: 4 mA on the 4 mA to 21 mA range 0 mA on the 0 mA to 21 mA range Midscale; for example: 12.5 mA on the 4 mA to 21 mA range 10.5 mA on the 0 mA to 21 mA range AD5748 CURRENT SETTING RESISTOR PACKET ERROR CHECKING Referring to Figure 1, RSET is an internal sense resistor as part of the voltage-to-current conversion circuitry. The nominal value of the internal current sense resistor is 15 kΩ. To allow for overrange capability in current mode, the user can also select the internal current sense resistor to be 14.7 kΩ, giving a nominal 2% overrange capability. This feature is available in the 0 mA to 21 mA and 4 mA to 21 mA current ranges. To verify that data has been received correctly in noisy environments, the AD5748 offers the option of error checking based on an 8-bit (CRC-8) cyclic redundancy check. The device controlling the AD5748 should generate an 8-bit frame check sequence using the following polynomial: The stability of the output current value over temperature is dependent on the stability of the value of RSET. As a method of improving the stability of the output current over temperature, an external low drift resistor can be connected to the REXT1 and REXT2 pins of the AD5748, which can be used instead of the internal resistor. The external resistor is selected via the input shift register. If the external resistor option is not used, the REXT1 and REXT2 pins should be left floating. C(x) = x8 + x2 + x1 + 1 This is added to the end of the data-word, and 24 data bits are sent to the AD5748 before taking SYNC high. If the AD5748 receives a 24-bit data frame, it performs the error check when SYNC goes high. If the check is valid, then the data is written to the selected register. If the error check fails, the FAULT pin goes low and Bit D3 of the status register is set. After reading this register, this error flag is cleared automatically and the FAULT pin goes high again. UPDATE ON SYNC HIGH SYNC SCLK D15 (MSB) D0 (LSB) 16-BIT DATA SDIN 16-BIT DATA TRANSER—NO ERROR CHECKING UPDATE AFTER SYNC HIGH ONLY IF ERROR CHECK PASSED SYNC SCLK SDIN FAULT D8 (LSB) 16-BIT DATA D7 D0 8-BIT FCS FAULT GOES LOW IF ERROR CHECK FAILS 16-BIT DATA TRANSER WITH ERROR CHECKING Figure 53. PEC Error Checking Timing Rev. 0 | Page 29 of 32 08922-055 D23 (MSB) AD5748 APPLICATIONS INFORMATION TRANSIENT VOLTAGE PROTECTION LAYOUT GUIDELINES The AD5748 contains ESD protection diodes that prevent damage from normal handling. The industrial control environment can, however, subject I/O circuits to much higher transients. To protect the AD5748 from excessively high voltage transients, external power diodes and a surge current limiting resistor may be required, as shown in Figure 54. The constraint on the resistor value is that, during normal operation, the output level at IOUT must remain within its voltage compliance limit of AVDD − 2.75 V, and the two protection diodes and resistor must have appropriate power ratings. Further protection can be added with transient voltage suppressors if needed. In any circuit where accuracy is important, careful consideration of the power supply and ground return layout helps to ensure the rated performance. The PCB on which the AD5748 is mounted should be designed so that the AD5748 lies on the analog plane. AVDD AVDD AD5748 IOUT In systems where there are many devices on one board, it is often useful to provide some heat sinking capability to allow the power to dissipate easily. RP 08922-056 RLOAD AVSS The AD5748 should have ample supply bypassing of 10 μF in parallel with 0.1 μF on each supply located as close to the package as possible, ideally right up against the device. The 10 μF capacitors are the tantalum bead type. The 0.1 μF capacitor should have low effective series resistance (ESR) and low effective series inductance (ESI) such as the common ceramic types, which provide a low impedance path to ground at high frequencies to handle transient currents due to internal logic switching. AD5748 Figure 54. Output Transient Voltage Protection THERMAL CONSIDERATIONS It is important to understand the effects of power dissipation on the package and on junction temperature. The internal junction temperature should not exceed 125°C. The AD5748 is packaged in a 32-lead LFCSP 5, 5 mm × 5 mm package. The thermal impedance, θJA, is 28°C/W. It is important that the devices are not operated under conditions that cause the junction temperature to exceed its junction temperature. Worst-case conditions occur when the AD5748 is operated from the maximum AVDD (26.4 V) while driving the maximum current (24 mA) directly to ground. The quiescent current of the AD5748 should also be taken into account, nominally ~4 mA. The following calculations estimate maximum power dissipation under these worst-case conditions, and determine maximum ambient temperature based on the power dissipation: Power Dissipation = 26.4 V × 28 mA = 0.7392 W Temp Increase = 28°C × 0.7392 W = 20.7°C Maximum Ambient Temp = 125°C − 20.7°C = 104.3°C BOARD 08922-057 AVSS PLANE Figure 55. Paddle Connection to Board The AD5748 has an exposed paddle beneath the device. This paddle is connected to the AVSS supply for the part. For optimum performance, special considerations should be used to design the motherboard and to mount the package. For enhanced thermal, electrical, and board level performance, the exposed paddle on the bottom of the package is soldered to the corresponding thermal land paddle on the PCB. Thermal vias are designed into the PCB land paddle area to further improve heat dissipation. The AVSS plane on the device can be increased (as shown in Figure 55) to provide a natural heat sinking effect. These figures assume that proper layout and grounding techniques are followed to minimize power dissipation, as outlined in the Layout Guidelines section. Rev. 0 | Page 30 of 32 AD5748 GALVANICALLY ISOLATED INTERFACE MICROPROCESSOR INTERFACING In many process control applications, it is necessary to provide an isolation barrier between the controller and the unit being controlled to protect and isolate the controlling circuitry from any hazardous common-mode voltages that may occur. The iCoupler® family of products from Analog Devices, Inc., provides voltage isolation in excess of 5.0 kV. The serial loading structure of the AD5748 makes it ideal for isolated interfaces because the number of interface lines is kept to a minimum. Figure 56 shows a 4-channel isolated interface using an ADuM1400. For further information, visit www.analog.com/icouplers. Microprocessor interfacing to the AD5748 is via a serial bus that uses a protocol compatible with microcontrollers and DSP processors. The communications channel is a 3-wire (minimum) interface consisting of a clock signal, a data signal, and a SYNC signal. The AD5748 requires a 16-bit data-word with data valid on the falling edge of SCLK. VID DECODE DECODE 1ADDITIONAL PINS OMITTED FOR CLARITY. VOA TO SCLK VOB TO SDIN VOC TO SYNC VOD TO CLEAR 08922-058 CONTROL OUT VIC DECODE SYNC OUT DECODE VIB ENCODE SERIAL DATA OUT ENCODE SERIAL CLOCK OUT ENCODE ADuM14001 VIA ENCODE CONTROLLER Figure 56. Isolated Interface Rev. 0 | Page 31 of 32 AD5748 OUTLINE DIMENSIONS 0.60 MAX 5.00 BSC SQ 0.60 MAX PIN 1 INDICATOR 0.50 BSC 4.75 BSC SQ 0.50 0.40 0.30 17 16 0.30 0.23 0.18 9 8 0.25 MIN 3.50 REF 0.05 MAX 0.02 NOM SEATING PLANE 3.25 3.10 SQ 2.95 EXPOSED PAD (BOTTOM VIEW) 0.80 MAX 0.65 TYP 12° MAX 1 0.20 REF COPLANARITY 0.08 FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. COMPLIANT TO JEDEC STANDARDS MO-220-VHHD-2 011708-A TOP VIEW 1.00 0.85 0.80 PIN 1 INDICATOR 32 25 24 Figure 57. 32-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 5 mm × 5 mm Body, Very Thin Quad (CP-32-2) Dimensions shown in millimeters ORDERING GUIDE Model 1 AD5748ACPZ AD5748ACPZ-RL7 1 TUE Accuracy ±0.3% VOUT, ±0.5% IOUT ±0.3% VOUT, ±0.5% IOUT Analog Input Range 0 V to 4.096 V 0 V to 4.096 V External Reference 4.096 V 4.096 V Z = RoHS Compliant Part. ©2010 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D08922-0-3/10(0) Rev. 0 | Page 32 of 32 Temperature Range −40°C to +105°C −40°C to +105°C Package Description 32-Lead LFCSP_VQ 32-Lead LFCSP_VQ Package Option CP-32-2 CP-32-2