ETC IBM13N8644HCB-260T

.
IBM13N8644HCC
IBM13N8734HCC
8M x 64/72 One-Bank Unbuffered SDRAM Module
Features
• 168-Pin Unbuffered 8-Byte Dual In-Line Memory
Module
• 8Mx64/72 Synchronous DRAM DIMM
• Three speed sorts:
• -260 and -360 for PC100 applications
• -10 for 66MHz applications (typical)
• Inputs and outputs are LVTTL (3.3V) compatible
• Single 3.3V ± 0.3V Power Supply
• Single Pulsed RAS interface
• SDRAMs have 4 internal banks
• Module has 1 bank
• Fully Synchronous to positive Clock Edge
• Data Mask for Byte Read/Write control
• Auto Refresh (CBR) and Self Refresh
• Automatic and controlled Precharge commands
• Programmable Operation:
- CAS Latency: 2, 3
- Burst Type: Sequential or Interleave
- Burst Length: 1, 2, 4, 8, Full-Page
(Full-Page supports Sequential burst only)
- Operation: Burst Read and Write or Multiple
Burst Read with Single Write
• Suspend Mode and Power Down Mode
• 12/9/2 Addressing (Row/Column/Bank)
• 4096 Refresh cycles distributed across 64ms
• Serial Presence Detect
• Card size: 5.25" x 1.375" x 0.106"
• Gold contacts
• SDRAMs in TSOP Type II Package
Description
IBM13N8644HCC / IBM13N8734HCC are unbuffered 168-pin Synchronous DRAM Dual In-Line
Memory Modules (DIMMs) which are organized as
8Mx64 and 8Mx72 high-speed memory arrays. The
DIMMs use eight (8Mx64) or nine (8Mx72) 8Mx8
SDRAMs in 400mil TSOP II packages. The DIMMs
achieve high-speed data transfer rates of up to
100MHz by employing a prefetch/pipeline hybrid
architecture that supports the JEDEC 1N rule while
allowing very low burst power.
The -10 speed sort DIMMs comply with JEDEC
standards for 168-pin unbuffered SDRAM DIMMs.
The -260 and -360 speed sort DIMMs are compatible with the Intel PC100 SDRAM unbuffered DIMM
specification.
All control, address, and data input/output circuits
are synchronized with the positive edge of the externally supplied clock inputs.
All inputs are sampled at the positive edge of each
externally supplied clock (CK0, CK2). Internal oper-
ating modes are defined by combinations of RAS,
CAS, WE, S0/S2, DQMB, and CKE0 signals. A
command decoder initiates the necessary timings
for each operation. A 14-bit address bus accepts
address information in a row/column multiplexing
arrangement.
Prior to any Access operation, the CAS latency,
burst type, burst length, and Burst operation type
must be programmed into the DIMM by address
inputs A0-A9 during the Mode Register Set cycle.
The DIMM uses serial presence detects implemented via a serial EEPROM using the two-pin IIC
protocol. The first 128 bytes of serial PD data are
used by the DIMM manufacturer. The last 128 bytes
are available to the customer.
All IBM 168-pin DIMMs provide a high-performance,
flexible 8-byte interface in a 5.25" long space-saving
footprint. Related products include both EDO DRAM
and SDRAM unbuffered DIMMs in both non-parity
x64 and ECC-Optimized x72 configurations.
Card Outline
(Front)
(Back)
19L7295.E93875B
12/99
1
85
10 11
94 95
40 41
124 125
84
168
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 1 of 19
IBM13N8644HCC
IBM13N8734HCC
8M x 64/72 One-Bank Unbuffered SDRAM Module
Pin Description
CK0, CK2
Clock Inputs
CK1, CK3
Unused (terminated) Clock Inputs
CKE0
DQ0 - DQ63
CB0 - CB7
Clock Enable
DQMB0 - DQMB7
Data Input/Output
Check Bit Data Input/Output
Data Mask
RAS
Row Address Strobe
VDD
CAS
Column Address Strobe
VSS
Ground
WE
Write Enable
NC
No Connect
S0, S2
Chip Selects
SCL
Serial Presence Detect Clock Input
Address Inputs
SDA
A0 - A9, A11
A10 /AP
Address Input/Autoprecharge
SA0-2
BA0, BA1
SDRAM Bank Address Inputs
WP
Power (3.3V)
Serial Presence Detect Data Input/Output
Serial Presence Detect Address Inputs
Serial Presence Detect Write Protect Input
Pinout
Pin#
Front
Side
Pin#
Back
Side
Pin#
Front
Side
Pin#
Back
Side
Pin#
Front
Side
Pin#
Back
Side
Pin#
Front
Side
Pin#
Back
Side
1
VSS
85
VSS
22
CB1
106
CB5
43
VSS
127
VSS
64
VSS
148
VSS
2
DQ0
86
DQ32
23
VSS
107
VSS
44
NC
128
CKE0
65
DQ21
149
DQ53
3
DQ1
87
DQ33
24
NC
108
NC
45
S2
129
NC
66
DQ22
150
DQ54
4
DQ2
88
DQ34
25
NC
109
NC
46
DQMB2
130
DQMB6
67
DQ23
151
DQ55
5
DQ3
89
DQ35
26
VDD
110
VDD
47
DQMB3
131
DQMB7
68
VSS
152
VSS
6
VDD
90
VDD
27
WE
111
CAS
48
NC
132
NC
69
DQ24
153
DQ56
DQ57
7
DQ4
91
DQ36
28
DQMB0
112
DQMB4
49
VDD
133
VDD
70
DQ25
154
8
DQ5
92
DQ37
29
DQMB1
113
DQMB5
50
NC
134
NC
71
DQ26
155
DQ58
9
DQ6
93
DQ38
30
S0
114
NC
51
NC
135
NC
72
DQ27
156
DQ59
10
DQ7
94
DQ39
31
NC
115
RAS
52
CB2
136
CB6
73
VDD
157
VDD
11
DQ8
95
DQ40
32
VSS
116
VSS
53
CB3
137
CB7
74
DQ28
158
DQ60
12
VSS
96
VSS
33
A0
117
A1
54
VSS
138
VSS
75
DQ29
159
DQ61
13
DQ9
97
DQ41
34
A2
118
A3
55
DQ16
139
DQ48
76
DQ30
160
DQ62
14
DQ10
98
DQ42
35
A4
119
A5
56
DQ17
140
DQ49
77
DQ31
161
DQ63
15
DQ11
99
DQ43
36
A6
120
A7
57
DQ18
141
DQ50
78
VSS
162
VSS
16
DQ12
100
DQ44
37
A8
121
A9
58
DQ19
142
DQ51
79
CK2
163
*CK3
17
DQ13
101
DQ45
38
A10/AP
122
BA0
59
VDD
143
VDD
80
NC
164
NC
BA1
123
A11
WP
165
SA0
18
VDD
102
VDD
39
60
DQ20
144
DQ52
81
19
DQ14
103
DQ46
40
VDD
124
VDD
61
NC
145
NC
82
SDA
166
SA1
DQ47
41
VDD
125
*CK1
62
NC
146
NC
83
SCL
167
SA2
CB4
42
CK0
126
NC
NC
84
VDD
168
VDD
20
21
DQ15
CB0
104
105
63
NC
147
Note: All pin assignments are consistent for all 8-byte unbuffered versions. Check bits (CB0 - CB7) are applicable only to the x72 DIMM; for the x64 DIMM
these pins are no connects (NC). *CK1 and CK3 are terminated.
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 2 of 19
19L7295.E93875B
12/99
IBM13N8644HCC
IBM13N8734HCC
8M x 64/72 One-Bank Unbuffered SDRAM Module
Ordering Information
Part Number
Organization
Clock Cycle
Leads
Dimension
Power
Notes
IBM13N8644HCC-260T
IBM13N8644HCC-360T
8Mx64
IBM13N8644HCC-10T
IBM13N8734HCC-260T
IBM13N8734HCC-360T
8Mx72
IBM13N8734HCC-10T
IBMB3N8644HCB-260T
IBMB3N8644HCB-360T
IBMB3N8734HCB-260T
IBMB3N8734HCB-360T
10ns
Gold
5.25" x 1.375" x 0.106"
3.3V
8Mx64
1
8Mx72
1. Functionally equivalent assembly to IBM13N8644HCB and IBM13N8734HCB, manufactured using SDRAMs from a SDRAM
technology licensee. SPD data reflects the IBM13N8644HCB and IBM13N8734HCB part numbers.
19L7295.E93875B
12/99
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 3 of 19
IBM13N8644HCC
IBM13N8734HCC
8M x 64/72 One-Bank Unbuffered SDRAM Module
8Mx64 SDRAM DIMM Block Diagram (1 Bank, 8Mx8 SDRAMs)
S0
DQMB4
DQMB0
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
*
DQM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
D0
DQMB1
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS
D4
DQMB5
DQM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
D1
DQM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS
DQM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS
D5
S2
DQMB2
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQMB6
DQM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
D2
DQMB3
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
D6
DQMB7
DQM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
D3
DQM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS
D7
Note: Exact DQ wiring may differ from that shown above.
10 Ohm
10pf
A0 - A11
A0-A11: SDRAMs D0 - D7
BA0
A13/BS0: SDRAMs D0 - D7
CK1
10pf
A12/BS1: SDRAMs D0 - D7
BA1
CK3
10 Ohm
VDD
.33µF
VSS
D0 - D7
0.1µF
D0 - D7
CK0
CLK: SDRAMs D0 - D1, D4 - D5, 3.3pF Cap.
CK2
CLK: SDRAMs D2 - D3, D6 - D7, 3.3pF Cap.
RAS
RAS: SDRAMs D0 - D7
CAS
CAS: SDRAMs D0 - D7
CKE0
CKE: SDRAMs D0 - D7
WE
WE: SDRAMs D0 - D7
Serial PD
SCL
WP
SDA
A0
A1
A2
SA0
SA1
SA2
47K
* All resistor values are 10 ohms except as shown.
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 4 of 19
19L7295.E93875B
12/99
IBM13N8644HCC
IBM13N8734HCC
8M x 64/72 One-Bank Unbuffered SDRAM Module
8Mx72 SDRAM DIMM Block Diagram
S0
DQMB0
(1 Bank, 8Mx8 SDRAMs)
DQMB4
DQM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS
CS
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CB0
CB1
CB2
CB3
CB4
CB5
CB6
CB7
DQM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQ0*
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
D0
DQM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS
D5
DQMB5
DQMB1
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
D1
DQM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS
D6
DQMB6
CS
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
D2
CS
D7
DQMB7
S2
DQMB2
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS
D3
DQMB3
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
DQM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS
D8
Note: Exact DQ wiring may differ from that shown above.
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
VDD
.33µF
VSS
DQM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
D4
D0 - D8
0.1µF
D0 - D8
* All resistor values are 10 ohms except as shown.
19L7295.E93875B
12/99
10 Ohm 10pF
CS
CK1
A0 - A11
A0-A11: SDRAMs D0 - D8
BA0
A13/BS0: SDRAMs D0 - D8
BA1
10pF
CK3
10 Ohm
A12/BS1: SDRAMs D0 - D8
CK0
CLK: SDRAMs D0 - D2, D5 - D6
CK2
CLK: SDRAMs D3 - D4, D7 - D8, 3.3pF Cap.
RAS
RAS: SDRAMs D0 - D8
CAS
CAS: SDRAMs D0 - D8
CKE0
CKE: SDRAMs D0 - D8
WE
WE: SDRAMs D0 - D8
Serial PD
SCL
WP
47K
SDA
A0
A1
A2
SA0
SA1
SA2
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 5 of 19
IBM13N8644HCC
IBM13N8734HCC
8M x 64/72 One-Bank Unbuffered SDRAM Module
Input/Output Functional Description
Symbol
Type
Signal
Polarity
Function
CK0, CK2
Input
Pulse
Positive
Edge
The system clock inputs. All of the SDRAM inputs are sampled on the rising edge of their
associated clock.
CKE0
Input
Level
Active
High
Activates the CK0 and CK2 signals when high and deactivates them when low. By deactivating the clocks, CKE0 low initiates the Power Down mode, Suspend mode, or the Self
Refresh mode.
S0,S2
Input
Pulse
Enables the associated SDRAM command decoder when low and disables the command
Active Low decoder when high. When the command decoder is disabled, new commands are
ignored but previous operations continue.
RAS, CAS
WE
Input
Pulse
Active Low
BA0, BA1
Input
Level
—
Selects which SDRAM bank is to be active.
Level
—
During a Bank Activate command cycle, A0-A11 defines the row address (RA0-RA11)
when sampled at the rising clock edge.
During a Read or Write command cycle, A0-A8 defines the column address (CA0-CA8)
when sampled at the rising clock edge. In addition to the column address, AP is used to
invoke Autoprecharge operation at the end of the Burst Read or Write cycle. If AP is high,
autoprecharge is selected and BA0/BA1 define the bank to be precharged. If AP is low,
autoprecharge is disabled.
During a Precharge command cycle, AP is used in conjunction with BA0/BA1 to control
which bank(s) to precharge. If AP is high all 4 banks will be precharged regardless of the
state of BA0/BA1. If AP is low, then BA0/BA1 are used to define which bank to precharge.
Level
—
Data and Check Bit Input/Output pins operate in the same manner as on conventional
DRAMs.
The Data Input/Output mask places the DQ buffers in a high impedance state when sampled high. In Read mode, DQM has a latency of two clock cycles and controls the output
buffers like an output enable. In Write mode, DQM has a latency of zero and operates as
a byte mask by allowing input data to be written if it is low but blocks the Write operation
if DQM is high.
A0 - A9
A10/AP
A11
Input
DQ0 - DQ63, Input
CB0 - CB7
Output
When sampled at the positive rising edge of the clock, CAS, RAS, and WE define the
operation to be executed by the SDRAM.
DQMB0 DQMB7
Input
Pulse
Active
High
SA0 - SA2
Input
Level
—
Address inputs. Connected to either VDD or VSS on the system board to configure the
Serial Presence Detect EEPROM address.
SDA
Input
Output
Level
—
Serial Data. Bidirectional signal used to transfer data into and out of the Serial Presence
Detect EEPROM. Since the SDA signal is Open Drain/Open Collector at the EEPROM, a
pull-up resistor is required on the system board.
SCL
Input
Pulse
—
Serial Clock. Used to clock all Serial Presence Detect data into and out of the EEPROM.
Since the SCL signal is inactive in the “high” state, a pull-up resistor is recommended on
the system board.
WP
Input
Level
Active
High
Hardware Write Protect. When WP is active, writing to the EEPROM array is inhibited.
On the DIMM, this input is connected to the EEPROM Write Protect input and is also tied
to ground through a 47K ohm pull-down resistor.
VDD, VSS
Supply
Power and ground for the module.
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 6 of 19
19L7295.E93875B
12/99
IBM13N8644HCC
IBM13N8734HCC
8M x 64/72 One-Bank Unbuffered SDRAM Module
Serial Presence Detect (Part 1 of 2)
Byte #
Description
SPD Entry Value
Serial PD Data Entry (Hexadecimal)
80
0
Number of Serial PD Bytes Written during Production
128
1
Total Number of Bytes in Serial PD device
256
08
2
Fundamental Memory Type
SDRAM
04
3
Number of Row Addresses on Assembly
12
0C
4
Number of Column Addresses on Assembly
9
09
5
Number of DIMM Banks
6-7
8M x 64
Data Width of Assembly
8M x 72
1
01
x64
4000
x72
4800
8
Voltage Interface Level of this Assembly
LVTTL
01
9
SDRAM Device Cycle Time at CL=3
10.0ns
A0
10
SDRAM Device Access Time from Clock at CL=3
11
DIMM Configuration Type
12
Refresh Rate/Type
13
Primary SDRAM Device Width
-260, -360
6.0ns
60
-10
7.0ns
70
8M x 64
Non-Parity
00
8M x 72
ECC
02
SR/1x(15.625us)
80
8M x 64
x8
08
N/A
00
x8
08
14
Error Checking SDRAM Device Width
15
SDRAM Device Attr: Min Clk Delay, Random Col Access
16
SDRAM Device Attributes: Burst Lengths Supported
17
SDRAM Device Attributes: Number of Device Banks
4
04
18
SDRAM Device Attributes: CAS Latencies Supported
2, 3
06
19
SDRAM Device Attributes: CS Latency
0
01
20
SDRAM Device Attributes: WE Latency
0
01
21
SDRAM Module Attributes
Unbuffered
00
22
SDRAM Device Attributes: General
Wr-1/Rd Burst, Precharge All,
Auto-Precharge, VDD +/- 10%
0E
-260
10.0ns
A0
23
Minimum Clock Cycle at CL=2
-360
15.0ns
F0
-10
15.0ns
F0
-260
6.0ns
60
-360
9.0ns
90
-10
8.0ns
80
N/A
00
N/A
00
24
Maximum Data Access Time (tAC) from Clock at
CL=2
25
Minimum Clock Cycle Time at CL=1
26
Maximum Data Access Time (tAC) from Clock at CL=1
27
Minimum Row Precharge Time (tRP)
28
Minimum Row Active to Row Active delay (tRRD)
29
30
1.
2.
3.
4.
5.
6.
7.
Minimum RAS to CAS delay (tRCD)
Minimum RAS Pulse width (tRAS)
8M x 72
1 Clock
01
1,2,4,8, Full Page
8F
-260, -360
20ns
14
-10
30ns
1E
-260, -360
20ns
14
-10
20ns
14
-260, -360
20ns
14
1E
-10
30ns
-260, -360
50ns
32
-10
60ns
3C
Notes
1
1
See the AC output load circuit in the AC Characteristics section below
cc = Checksum Data byte, 00-FF (Hex)
“R” = Alphanumeric revision code, A-Z, 0-9
rr = ASCII coded revision code byte “R”
yy = Binary coded decimal year code, 00-99 (Decimal) 00-63 (Hex)
ww = Binary coded decimal week code, 01-52 (Decimal) 01-34 (Hex)
ss = Serial number data byte, 00-FF (Hex)
19L7295.E93875B
12/99
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 7 of 19
IBM13N8644HCC
IBM13N8734HCC
8M x 64/72 One-Bank Unbuffered SDRAM Module
Serial Presence Detect (Part 2 of 2)
Byte #
31
Description
Module Bank Density
32
Address and Command Setup Time Before Clock
33
Address and Command Hold Time After Clock
34
Data Input Setup Time Before Clock
35
Data Input Hold Time After Clock
36 - 61
SPD Revision
63
Checksum for bytes 0 - 62
64 - 71
Manufacturers’ JEDEC ID Code
72
Module Manufacturing Location
73 - 90
Module Part Number
91 - 92
Module Revision Code
93 - 94
Module Manufacturing Date
95 - 98
Module Serial Number
127
Module Supports this Clock Frequency
Attributes for Clock Frequency defined in byte 126
10
20
-10
3.0ns
30
-260, -360
1.0ns
10
-10
1.0ns
10
-260, -360
2.0ns
20
-10
3.0ns
30
-260, -360
1.0ns
10
-10
1.0ns
10
-260, -360
-10
Undefined
00
1.2A
12
2
02
Notes
2
Checksum Data
cc
IBM
A400000000000000
Toronto, Canada
91
Vimercate, Italy
53
8M x 64,
-260
ASCII ‘13N8644HC”R”-260T’
31334E383634344843rr
2D32363054202020
8M x 64,
-360
ASCII ‘13N8644HC”R”-360T’
31334E383634344843rr
2D33363054202020
8M x 64,
-10
ASCII ‘13N8644HC”R”-10T’
31334E383634344843rr
2D31305420202020
8M x 72,
-260
ASCII ‘13N8734HC”R”-260T’
31334E383733344843rr
2D32363054202020
8M x 72,
-360
ASCII ‘13N8734HC”R”-360T’
31334E383733344843rr
2D33363054202020
8M x 72,
-10
ASCII ‘13N8734HC”R”-10T’
31334E383733344843rr
2D31305420202020
3, 4
“R” plus ASCII blank
rr20
Year/Week Code
yyww
5, 6
Serial Number
ssssssss
7
Undefined
00
-260, -360
100 MHz
64
-10
66 MHz
66
-260
CK0, CK2, CL3, CL2,
concurrent AP
A7
-360
CK0, CK2, CL3,
concurrent AP
A5
-10
CL3, CL2, concurrent AP
07
Undefined
00
128 - 255 Open for Customer Use
1.
2.
3.
4.
5.
6.
7.
64MB
2.0ns
99 - 125 Reserved
126
Serial PD Data Entry (Hexadecimal)
-260, -360
Reserved
62
SPD Entry Value
See the AC output load circuit in the AC Characteristics section below
cc = Checksum Data byte, 00-FF (Hex)
“R” = Alphanumeric revision code, A-Z, 0-9
rr = ASCII coded revision code byte “R”
yy = Binary coded decimal year code, 00-99 (Decimal) 00-63 (Hex)
ww = Binary coded decimal week code, 01-52 (Decimal) 01-34 (Hex)
ss = Serial number data byte, 00-FF (Hex)
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 8 of 19
19L7295.E93875B
12/99
IBM13N8644HCC
IBM13N8734HCC
8M x 64/72 One-Bank Unbuffered SDRAM Module
Absolute Maximum Ratings
Symbol
Parameter
VDD
Power Supply Voltage
VIN
Input Voltage
VOUT
TA
TSTG
PD
IOUT
Rating
Units Notes
-0.3 to +4.6
SDRAM Devices
-0.3 to VDD+0.3
Serial PD Device
-0.3 to +6.5
SDRAM Devices
-0.3 to VDD+3.3
Serial PD Device
-0.3 to +6.5
Output Voltage
Operating Temperature (ambient)
Storage Temperature
V
1
0 to +70
°C
1
-55 to +125
°C
1
W
1
mA
1
x64
4.0
x72
4.5
Power Dissipation
Short Circuit Output Current
50
1. Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
Recommended DC Operating Conditions
(TA= 0 to 70°C)
Rating
Symbol
Parameter
Min.
Typ.
Max.
Units
Notes
VDD
Supply Voltage
3.0
3.3
3.6
V
1
VIH
Input High Voltage
2.0
—
VDD + 0.3
V
1, 2
VIL
Input Low Voltage
-0.3
—
0.8
V
1, 3
1. All voltages referenced to VSS.
2. VIH(max) = VDD + 1.2V for pulse width ≤ 5ns.
3. VIL(min) = VDD - 1.2V for pulse width ≤ 5ns.
Capacitance (TA= 25°C, f=1MHz, VDD= 3.3V ± 0.3V)
Organization
Symbol
Parameter
Units
x64 Max.
x72 Max.
CI1
Input Capacitance (A0 - A9, A10/AP, A11, BA0, BA1, RAS, CAS, WE)
74
77
pF
CI2
Input Capacitance (CKE0)
54
58
pF
CI3
Input Capacitance (S0, S2)
30
33
pF
CI4
Input Capacitance (CK0 - CK3)
40
40
pF
CI5
Input Capacitance (DQMB0 - DQMB7)
17
21
pF
CI6
Input Capacitance (SA0 - SA2, SCL, WP)
9
9
pF
CIO1
Input/Output Capacitance (DQ0 - DQ63, CB0 - CB7)
10
10
pF
CIO2
Input/Output Capacitance (SDA)
11
11
pF
19L7295.E93875B
12/99
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 9 of 19
IBM13N8644HCC
IBM13N8734HCC
8M x 64/72 One-Bank Unbuffered SDRAM Module
DC Output Load Circuit
3.3 V
1200Ω
VOH (DC) = 2.4V, IOH = -2mA
Output
VOL (DC) = 0.4V, IOL = 2mA
50pF
870Ω
Output Characteristics
(TA= 0 to +70°C, VDD= 3.3V ± 0.3V)
x64
Symbol
II(L)
x72
Parameter
Units Notes
Min.
Max.
Min.
Max.
RAS, CAS, WE, CKE0,
A0-A9, A10/AP, A11, BA0, BA1
-40
+40
-45
+45
CK0
-20
+20
-25
+25
CK2
-20
+20
-20
+20
S0
-20
+20
-25
+25
S2
-20
+20
-20
+20
DQMB1
-5
+5
-10
+10
DQMB0, 2, 3, 4, 5, 6, 7
-5
+5
-5
+5
DQ0 - 63
-5
+5
-5
+5
Input Leakage Current, any input
(0.0V ≤ VIN ≤ VDD), All Other Pins
Not Under Test = 0V
IO(L)
Output Leakage Current
(DOUT is disabled, 0.0V ≤ VOUT ≤ VDD)
VOH
Output Level (LVTTL)
Output “H” Level Voltage (IOUT = -2.0mA)
VOL
Output Level (LVTTL)
Output “L” Level Voltage (IOUT = +2.0mA)
CB0 - 7
0
0
-5
+5
SA0, SA1, SA2, SCL, SDA
-10
+10
-10
+10
WP
-10
+50
-10
+50
DQ0 - 63
-5
+5
-5
+5
CB0 - 7
0
0
-5
+5
SDA
-10
+10
-10
+10
2.4
-
2.4
-
-
0.4
-
0.4
µA
µA
V
1
1. See DC output load circuit.
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 10 of 19
19L7295.E93875B
12/99
IBM13N8644HCC
IBM13N8734HCC
8M x 64/72 One-Bank Unbuffered SDRAM Module
Operating, Standby, and Refresh Currents (TA= 0 to +70°C, VDD= 3.3V ± 0.3V)
Speed/Organization
Parameter
Operating Current
tRC = tRC(min), tCK = min
Active-Precharge command
cycling without Burst operation
Precharge Standby Current in
Power Down Mode
Precharge Standby Current in
Non-Power Down Mode
No Operating Current
(Active state: 4 bank)
Symbol
Test Condition
-260, -360/
x64
-10/x64
560
440
630
Units
Notes
495
mA
1, 2
-260, -360/
-10/x72
x72
ICC1
1 Bank operation
ICC2P
CKE0 ≤ VIL(max), tCK = min,
S0, S2 =VIH(min)
8
8
9
9
mA
ICC2PS
CKE0 ≤ VIL(max), tCK = Infinity,
S0, S2 =VIH(min)
8
8
9
9
mA
ICC2N
CKE0 ≥ VIH(min), tCK = min,
S0, S2 =VIH (min)
200
200
225
225
mA
3
ICC2NS
CKE0 ≥ VIH(min), tCK = Infinity,
S0, S2 =VIH (min)
48
48
54
54
mA
4
ICC3N
CKE0 ≥ VIH(min), tCK = min,
S0, S2 =VIH (min)
240
240
270
270
mA
3
CKE0 ≤ VIL(max), tCK = min,
ICC3P S0, S2 =VIH (min)
(Power Down Mode)
24
24
27
27
mA
5
720
720
810
810
mA
2, 6
1120
880
1260
990
mA
Burst Operating Current
ICC4
tCK = min,
Read/write command cycling,
multiple banks active,
gapless data, BL = 4
Auto (CBR) Refresh Current
ICC5
tCK = min, tRC = tRC(min),
CBR command cycling
Self Refresh Current
ICC6
CKE0 ≤ 0.2V
8
8
9
9
mA
Serial PD Device Standby Current
ISB
VIN = GND or VDD
30
30
30
30
µA
7
Serial PD Device Active Power
Supply Current
ICCA
SCL Clock Frequency =
100KHz
1
1
1
1
mA
8
1. These parameters depend on the cycle rate and are measured with the cycle determined by the minimum value of tCK and tRC.
Input signals are changed up to three times during tRC(min).
2. The specified values are obtained with the output open.
3. Input signals are changed once during three clock cycles.
4. Input signals are stable.
5. Active standby current will be higher if Clock Suspend is entered during a Burst Read cycle (add 1mA per DQ).
6. Input signals are changed once during tck(min).
7. VDD = 3.3V
8. Input pulse levels VDD x 0.1 to VDD x 0.9, input rise and fall times 10ns, input and output timing levels VDD x 0.5, output load 1 TTL
gate and CL=100pf.
19L7295.E93875B
12/99
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 11 of 19
IBM13N8644HCC
IBM13N8734HCC
8M x 64/72 One-Bank Unbuffered SDRAM Module
AC Characteristics (TA= 0 to +70°C, VDD= 3.3V ± 0.3V)
1. An initial pause of 200µs, with DQMB0-7 and CKE0 held high, is required after power-up. A Precharge All
Banks command must be given followed by a minimum of eight Auto (CBR) Refresh cycles before or after
the Mode Register Set operation.
2. The Transition time is measured between VIH and VIL (or between VIL and VIH).
3. In addition to meeting the transition rate specification, the CK0, CK2, and CKE0 signals must transit
between VIH and VIL (or between VIL and VIH) in a monotonic manner.
4. Load Circuit A: AC timing tests have VIL = 0.4 V and VIH = 2.4 V with the timing referenced to the 1.40V
crossover point.
5. Load Circuit A: AC measurements assume tT=1.0 ns.
6. Load Circuit B: AC timing tests have VIL = 0.8 V and VIH = 2.0 V with the timing referenced to the 1.40V
crossover point.
7. Load Circuit B: AC measurements assume tT=1.2 ns.
AC Characteristics Diagrams
tCKH
Clock
Vtt=1.4V
VIH
1.4V
VIL
tCKL
tSETUP
tT
50Ω
Output
Zo = 50Ω
50pF
AC Output Load Circuit (A)
tHOLD
Input
1.4V
Output
tAC
tOH
tLZ
Output
1.4V
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 12 of 19
Zo = 50Ω
50pF
AC Output Load Circuit (B)
19L7295.E93875B
12/99
IBM13N8644HCC
IBM13N8734HCC
8M x 64/72 One-Bank Unbuffered SDRAM Module
Clock and Clock Enable Parameters
-260
Symbol
-360
-10
Parameter
Units Notes
Min.
Max.
Min.
Max.
Min.
Max.
tCK3
Clock Cycle Time, CAS Latency = 3
10
1000
10
1000
10
1000
ns
tCK2
Clock Cycle Time, CAS Latency = 2
10
1000
15
1000
15
1000
ns
1
tAC3 (A) Clock Access Time, CAS Latency = 3
—
—
—
—
—
7
ns
2
tAC2 (A) Clock Access Time, CAS Latency = 2
—
—
—
—
—
8
ns
2
tAC3 (B) Clock Access Time, CAS Latency = 3
—
6
—
6
—
9
ns
3
tAC2 (B) Clock Access Time, CAS Latency = 2
—
6
—
9
—
9
ns
3
tCKH
Clock High Pulse Width
3
—
3
—
3
—
ns
4
tCKL
Clock Low Pulse Width
3
—
3
—
3
—
ns
4
tCES
Clock Enable Set-up Time
2
—
2
—
3
—
ns
tCEH
Clock Enable Hold Time
1
—
1
—
1
—
ns
tSB
Power down mode Entry Time
0
10
0
10
0
10
ns
tT
Transition Time (Rise and Fall)
0.5
10
0.5
10
0.5
10
ns
1.
2.
3.
4.
For -360 sort, 66MHz clock: CAS Latency = 2.
Access time is measured at 1.4V. In AC Characteristics section, see notes 1, 2, 3, 4, and 5, and load circuit A.
Access time is measured at 1.4V. In AC Characteristics section, see notes 1, 2, 3, 6, and 7, and load circuit B.
tCKH is the pulse width of CLK measured from the positive edge to the negative edge referenced to VIH (min). tCKL is the pulse
width of CLK measured from the negative edge to the positive edge referenced to VIL (max).
19L7295.E93875B
12/99
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 13 of 19
IBM13N8644HCC
IBM13N8734HCC
8M x 64/72 One-Bank Unbuffered SDRAM Module
Common Parameters
-260
Symbol
-360
-10
Parameter
Units
Notes
Min.
Max.
Min.
Max.
Min.
Max.
tCS Command Setup Time
2
—
2
—
3
—
ns
tCH Command Hold Time
1
—
1
—
1
—
ns
tAS Address and Bank Select Set-up Time
2
—
2
—
3
—
ns
tAH Address and Bank Select Hold Time
1
—
1
—
1
—
ns
tRCD RAS to CAS Delay
20
—
20
—
30
—
ns
1
tRC Bank Cycle Time
70
—
70
—
90
—
ns
1
tRAS Active Command Period
50
100000
50
100000
60
100000
ns
1
tRP Precharge Time
20
—
20
—
30
—
ns
1
tRRD Bank to Bank Delay Time
20
—
20
—
20
—
ns
1
tCCD CAS to CAS Delay Time
1
—
1
—
1
—
CLK
1. These parameters account for the number of clock cycle and depend on the operating frequency of the clock, as follows:
the number of clock cycles = specified value of timing / clock period (count fractions as a whole number).
Mode Register Set Cycle
-360
-260)
Symbol
tRSC
-10
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
2
—
2
—
2
—
Mode Register Set Cycle Time
Units
Notes
clk
1
1. These parameters account for the number of clock cycle and depend on the operating frequency of the clock, as follows:
the number of clock cycles = specified value of timing / clock period (count fractions as a whole number).
Read Cycle
-260
Symbol
-360
-10
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
2.5
—
2.5
—
2.5
—
3
—
3
Units
Notes
ns
2
ns
3
tOH
Data Out Hold Time
tLZ
Data Out to Low Impedance Time
0
—
0
—
0
—
ns
tHZ3
Data Out to High Impedance Time
3
6
3
6
3
7
ns
1
tHZ2
Data Out to High Impedance Time
3
6
3
8
3
8
ns
1
tDQZ
DQM Data Out Disable Latency
2
—
2
—
2
—
CLK
1
3
1. Referenced to the time at which the output achieves the open circuit condition, not to output voltage levels.
2. AC Output Load Circuit A.
3. AC Output Load Circuit B.
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 14 of 19
19L7295.E93875B
12/99
IBM13N8644HCC
IBM13N8734HCC
8M x 64/72 One-Bank Unbuffered SDRAM Module
Refresh Cycle
Symbol
tREF
tSREX
Parameter
-260
-360
-10
Min.
Max.
Min.
Max.
Min.
Max.
Refresh Period
—
64
—
64
—
64
Self Refresh Exit Time
10
10
Units
Notes
ms
1
10
ns
1. 4096 auto refresh cycles.
Write Cycle
Symbol
-260
Parameter
-360
-10
Min.
Max.
Min.
Max.
Min.
Max.
Units
tDS
Data In Set-up Time
2
—
2
—
3
—
ns
tDH
Data In Hold Time
1
—
1
—
1
—
ns
tDPL
Data input to Precharge
15
—
15
—
15
—
ns
tDAL2
Data In to Active Delay
CAS Latency = 2
5
—
5
—
5
—
CLK
tDAL3
Data In to Active Delay
CAS Latency = 3
4
—
4
—
4
—
CLK
tDQW
DQM Write Mask Latency
0
—
0
—
0
—
CLK
Max.
Units
SCL Clock Frequency
100
kHZ
TI
Noise Suppression Time Constant at SCL, SDA Inputs
100
ns
tAA
SCL Low to SDA Data Out Valid
0.3
3.5
µs
tBUF
Time the Bus Must Be Free before a New Transmission Can Start
4.7
µs
Start Condition Hold Time
4.0
µs
tLOW
Clock Low Period
4.7
µs
tHIGH
Presence Detect Read and Write Cycle
Symbol
fSCL
tHD:STA
Parameter
Min.
Clock High Period
4.0
µs
tSU:STA
Start Condition Setup Time (for a Repeated Start Condition)
4.7
µs
tHD:DAT
Data in Hold Time
0
µs
tSU:DAT
Data in Setup Time
250
ns
tr
SDA and SCL Rise Time
1
µs
tf
SDA and SCL Fall Time
300
ns
Stop Condition Setup Time
4.7
µs
tDH
Data Out Hold Time
300
ns
tWR
Write Cycle Time
tSU:STO
15
ms
Notes
1
1. The Write cycle time (tWR) is the time from a valid stop condition of a write sequence to the end of the internal Erase/Program
cycle. During the Write cycle, the bus interface circuits are disabled, SDA is allowed to remain high per the bus-level pull-up resistor, and the device does not respond to its slave address.
19L7295.E93875B
12/99
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 15 of 19
IBM13N8644HCC
IBM13N8734HCC
8M x 64/72 One-Bank Unbuffered SDRAM Module
Functional Description and Timing Diagrams
Refer to the IBM 64Mb Die Revision C Synchronous DRAM data sheet, document 19L3265.E35856, for the
functional description and timing diagrams for SDRAM operation.
Refer to the IBM Application Notes Serial Presence Detect on Memory DIMMs and SDRAM Presence Detect
Definitions for the Serial Presence Detect functional description and timings.
All AC timing information refers to the timings at the SDRAM devices.
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 16 of 19
19L7295.E93875B
12/99
IBM13N8644HCC
IBM13N8734HCC
8M x 64/72 One-Bank Unbuffered SDRAM Module
Layout Drawing
133.35
5.25
131.35
5.171
127.35
5.014
*
6.35
.250
3.0
.118
1780
.700
(2) 0
3.18
.1255
34.925
1.375
(2x) 4.00
.157
Front
1.27 Pitch
.050
42.18
1.661
1.00 Width
.039
66.68
2.63
See Detail A
* Note: on x72 Module Only
Side
Detail A
Scale 4/1
2.59
0.106 max.
5.95
.234 min.
2.0
.078
3.0
.118
R 1.00
.0393
_ 0.10
1.27 +
_ .004
.050 +
Note: All dimensions are typical unless otherwise stated.
19L7295.E93875B
12/99
Millimeters
Inches
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 17 of 19
IBM13N8644HCC
IBM13N8734HCC
8M x 64/72 One-Bank Unbuffered SDRAM Module
Revision Log
Rev
Contents of Modification
3/99
Initial release.
Reflects PC11 rev 1.2 and Die Rev C 64Mb device specification.
5/99
Updated part number information & ICC2NS in Operating, Standby & Refresh Currents Table.
8/99
Removed Preliminary
12/99
Updated ordering information
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 18 of 19
19L7295.E93875B
12/99

Copyright and Disclaimer
 Copyright International Business Machines Corporation 1999
All Rights Reserved
Printed in the United States of America December 1999
The following are trademarks of International Business Machines Corporation in the United States, or other countries, or both.
IBM
IBM Logo
Other company, product and service names may be trademarks or service marks of others.
All information contained in this document is subject to change without notice. The products described in this document are NOT intended for use in implantation or other life support applications where malfunction may result in injury
or death to persons. The information contained in this document does not affect or change IBM product specifications
or warranties. Nothing in this document shall operate as an express or implied license or indemnity under the intellectual property rights of IBM or third parties. All information contained in this document was obtained in specific environments, and is presented as an illustration. The results obtained in other operating environments may vary.
THE INFORMATION CONTAINED IN THIS DOCUMENT IS PROVIDED ON AN "AS IS" BASIS. In no event will IBM
be liable for damages arising directly or indirectly from any use of the information contained in this document.
IBM Microelectronics Division
1580 Route 52, Bldg. 504
Hopewell Junction,
NY 12533-6351
The IBM home page can be found at
http://www.ibm.com
The IBM Microelectronics Division home page
can be found at http://www.chips.ibm.com
19L7295.E93875B.
12/99