Discontinued (4/1/00 - last order; 7/31/00 - last ship) . IBM13N4644MCB IBM13N4734MCB 4M x 64/72 One-Bank Unbuffered SDRAM Module Features • 168-Pin Unbuffered 8-Byte Dual In-Line Memory Module • 4Mx64/72 Synchronous DRAM DIMM • Three speed sorts: • -260 and -360 for PC100 applications • -10 for 66MHz applications (typical) • Inputs and outputs are LVTTL (3.3V) compatible • Single 3.3V ± 0.3V Power Supply • Single Pulsed RAS interface • SDRAMs have 4 internal banks • Module has 1 bank • Fully Synchronous to positive Clock Edge • Data Mask for Byte Read/Write control • Auto Refresh (CBR) and Self Refresh • Automatic and controlled Precharge commands • Programmable Operation: - CAS Latency: 2, 3 - Burst Type: Sequential or Interleave - Burst Length: 1, 2, 4, 8, Full-Page (FullPage supports Sequential burst only) - Operation: Burst Read and Write or Multiple Burst Read with Single Write • Suspend Mode and Power Down Mode • 12/8/2 Addressing (Row/Column/Bank) • 4096 Refresh cycles distributed across 64ms • Serial Presence Detect • Card size: 5.25" x 1.000" x 0.106" • Gold contacts • SDRAMs in TSOP Type II Package Description IBM13N4644MCB / IBM13N4734MCB are unbuffered 168-pin Synchronous DRAM Dual In-Line Memory Modules (DIMMs) which are organized as 4Mx64 and 4Mx72 high-speed memory arrays. The DIMMs use 4(4Mx64) or 5(4Mx72) 4Mx16 SDRAMs in 400mil TSOP II packages. The DIMMs achieve high-speed data transfer rates of up to 100MHz by employing a prefetch/pipeline hybrid architecture that supports the JEDEC 1N rule while allowing very low burst power. The -10 speed sort DIMMs comply with JEDEC standards for 168-pin unbuffered SDRAM DIMMs. The -360 speed sort DIMMs are compatible with the Intel PC100 SDRAM unbuffered DIMM specification. All control, address, and data input/output circuits are synchronized with the positive edge of the externally supplied clock inputs. All inputs are sampled at the positive edge of each externally supplied clock (CK0, CK2). Internal oper- ating modes are defined by combinations of RAS, CAS, WE, S0/S2, DQMB, and CKE0 signals. A command decoder initiates the necessary timings for each operation. A 14-bit address bus accepts address information in a row/column multiplexing arrangement. Prior to any Access operation, the CAS latency, burst type, burst length, and Burst operation type must be programmed into the DIMM by address inputs A0-A9 during the Mode Register Set cycle. The DIMM uses serial presence detects implemented via a serial EEPROM using the two-pin IIC protocol. The first 128 bytes of serial PD data are used by the DIMM manufacturer. The last 128 bytes are available to the customer. All IBM 168-pin DIMMs provide a high-performance, flexible 8-byte interface in a 5.25" long space-saving footprint. Related products include both EDO DRAM and SDRAM unbuffered DIMMs in both non-parity x64 and ECC-Optimized x72 configurations. Card Outline (Front) 1 (Back) 85 19L7294.E93875A 8/99 10 11 94 95 40 41 124 125 84 168 ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 1 of 18 Discontinued (4/1/00 - last order; 7/31/00 - last ship) IBM13N4644MCB IBM13N4734MCB 4M x 64/72 One-Bank Unbuffered SDRAM Module Pin Description CK0, CK2 Clock Inputs CK1, CK3 Unused (terminated) Clock Inputs CKE0 DQ0 - DQ63 CB0 - CB7 DQMB0 - DQMB7 Clock Enable Data Input/Output Check Bit Data Input/Output Data Mask RAS Row Address Strobe VDD CAS Column Address Strobe VSS Ground WE Write Enable NC No Connect S0, S2 Chip Selects SCL Serial Presence Detect Clock Input Address Inputs SDA Serial Presence Detect Data Input/Output A0 - A9, A11 A10 /AP Address Input/Autoprecharge SA0-2 BA0, BA1 SDRAM Bank Address Inputs WP Power (3.3V) Serial Presence Detect Address Inputs Serial Presence Detect Write Protect Input Pinout Pin# Front Side Pin# Back Side Pin# Front Side Pin# Back Side Pin# Front Side Pin# Back Side Pin# Front Side Pin# Back Side 1 VSS 85 VSS 22 CB1 106 CB5 43 VSS 127 VSS 64 VSS 148 VSS 2 DQ0 86 DQ32 23 VSS 107 VSS 44 NC 128 CKE0 65 DQ21 149 DQ53 3 DQ1 87 DQ33 24 NC 108 NC 45 S2 129 NC 66 DQ22 150 DQ54 4 DQ2 88 DQ34 25 NC 109 NC 46 DQMB2 130 DQMB6 67 DQ23 151 DQ55 5 DQ3 89 DQ35 26 VDD 110 VDD 47 DQMB3 131 DQMB7 68 VSS 152 VSS 6 VDD 90 VDD 27 WE 111 CAS 48 NC 132 NC 69 DQ24 153 DQ56 7 DQ4 91 DQ36 28 DQMB0 112 DQMB4 49 VDD 133 VDD 70 DQ25 154 DQ57 8 DQ5 92 DQ37 29 DQMB1 113 DQMB5 50 NC 134 NC 71 DQ26 155 DQ58 DQ59 9 DQ6 93 DQ38 30 S0 114 NC 51 NC 135 NC 72 DQ27 156 10 DQ7 94 DQ39 31 NC 115 RAS 52 CB2 136 CB6 73 VDD 157 VDD 11 DQ8 95 DQ40 32 VSS 116 VSS 53 CB3 137 CB7 74 DQ28 158 DQ60 12 VSS 96 VSS 33 A0 117 A1 54 VSS 138 VSS 75 DQ29 159 DQ61 13 DQ9 97 DQ41 34 A2 118 A3 55 DQ16 139 DQ48 76 DQ30 160 DQ62 14 DQ10 98 DQ42 35 A4 119 A5 56 DQ17 140 DQ49 77 DQ31 161 DQ63 15 DQ11 99 DQ43 36 A6 120 A7 57 DQ18 141 DQ50 78 VSS 162 VSS 16 DQ12 100 DQ44 37 A8 121 A9 58 DQ19 142 DQ51 79 CK2 163 *CK3 17 DQ13 101 DQ45 38 A10/AP 122 BA0 59 VDD 143 VDD 80 NC 164 NC 18 VDD 102 VDD 39 BA1 123 A11 60 DQ20 144 DQ52 81 WP 165 SA0 19 DQ14 103 DQ46 40 VDD 124 VDD 61 NC 145 NC 82 SDA 166 SA1 20 DQ15 104 DQ47 41 VDD 125 *CK1 62 NC 146 NC 83 SCL 167 SA2 21 CB0 105 CB4 42 CK0 126 NC 63 NC 147 NC 84 VDD 168 VDD Note: All pin assignments are consistent for all 8-byte unbuffered versions. Check bits (CB0 - CB7) are applicable only to the x72 DIMM; for the x64 DIMM these pins are no connects (NC). *CK1 and CK3 are terminated. Ordering Information Part Number IBM13N4644MCB-260T IBM13N4644MCB-360T IBM13N4644MCB-10T IBM13N4734MCB-260T IBM13N4734MCB-360T IBM13N4734MCB-10T Organization Leads Dimension Power 10ns Gold 5.25" x 1.00" x 0.106" 3.3V 4Mx64 4Mx72 ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 2 of 18 Clock Cycle 19L7294.E93875A 8/99 Discontinued (4/1/00 - last order; 7/31/00 - last ship) IBM13N4644MCB IBM13N4734MCB 4M x 64/72 One-Bank Unbuffered SDRAM Module 4Mx64 SDRAM DIMM Block Diagram (1 Bank, 4Mx16 SDRAMs) S0 DQMB0 CS * DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQMB4 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 CS DQMB2 UDQM UDQM DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 D0 DQMB6 LDQM I/O 8 I/O 9 I/O 10 I/O 11 I/O 12 I/O 13 I/O 14 I/O 15 I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 D2 LDQM DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 I/O 8 I/O 9 I/O 10 I/O 11 I/O 12 I/O 13 I/O 14 I/O 15 S2 DQMB1 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQMB5 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 CS I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 CS DQMB3 UDQM UDQM DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 D1 DQMB7 LDQM I/O 8 I/O 9 I/O 10 I/O 11 I/O 12 I/O 13 I/O 14 I/O 15 I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 D3 LDQM DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 I/O 8 I/O 9 I/O 10 I/O 11 I/O 12 I/O 13 I/O 14 I/O 15 10Ω 10pF 10Ω 10pF CK 1 NOTE: Exact DQ wiring may differ from that shown above CK3 15pF A13/BS0: SDRAMs D0 - D3 A12/BS1: SDRAMs D0 - D3 A0-A11: SDRAMSs D0 - D3 BA0 BA1 A0-A11 VCC D0 - D3 0.1µF 0.33µF VSS RAS CLK: SDRAMs D0 - D1 CLK: SDRAMs D2 - D3 15pF SERIAL PD RAS: SDRAMs D0 - D3 CAS CAS: SDRAMs D0 - D3 CKE0 CKE: SDRAMs D0 - D3 WE D0 - D3 * All resistor values are 10 OHMS except as shown. 19L7294.E93875A 8/99 CK0 CK2 WE: SDRAMs D0 - D3 SCL WP 47K SDA A0 A1 A2 SA0 SA1 SA2 ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 3 of 18 Discontinued (4/1/00 - last order; 7/31/00 - last ship) IBM13N4644MCB IBM13N4734MCB 4M x 64/72 One-Bank Unbuffered SDRAM Module 4Mx72 SDRAM DIMM Block Diagram (1 Bank, 4Mx16 SDRAMs) S0 CS CS DQMB0 * DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 LDQM I/O 8 I/O 9 I/O 10 I/O 11 I/O 12 I/O 13 I/O 14 I/O 15 DQMB4 UDQM DQMB2 UDQM D0 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 LDQM I/O 8 I/O 9 I/O 10 I/O 11 I/O 12 I/O 13 I/O 14 I/O 15 DQMB6 D3 S2 CS CS DQMB1 DQMB3 UDQM DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 LDQM I/O 8 I/O 9 I/O 10 I/O 11 I/O 12 I/O 13 I/O 14 I/O 15 DQMB5 D1 BA0 BA1 A0 - A11 CK0 CK2 10pF I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 LDQM I/O 8 I/O 9 I/O 10 I/O 11 I/O 12 I/O 13 I/O 14 I/O 15 D2 A13/BS0: SDRAMs D0 - D4 A12/BS1: SDRAMs D0 - D4 A0-A11: SDRAMSs D0 - D4 CLK: SDRAMs D0 - D2 CLK: SDRAMs D3 - D4 D4 NOTE: Exact DQ wiring may differ from that shown above CS I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQMB7 UDQM CB0 CB1 CB2 CB3 CB4 CB5 CB6 CB7 UDQM RAS RAS: SDRAMs D0 - D4 CAS CAS: SDRAMs D0 - D4 CKE0 CKE: SDRAMs D0 - D4 WE WE: SDRAMs D0 - D4 SERIAL PD 10 pF 10Ω 10 pF CK3 VCC SCL WP 47 K 10Ω CK 1 SDA A0 A1 A2 SA0 SA1 SA2 D0 - D4 0.1 µF 0.33µF VSS D0 - D4 15pF * All Resistor Values are 10 OHMS except as shown. ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 4 of 18 19L7294.E93875A 8/99 Discontinued (4/1/00 - last order; 7/31/00 - last ship) IBM13N4644MCB IBM13N4734MCB 4M x 64/72 One-Bank Unbuffered SDRAM Module Input/Output Functional Description Symbol Type Signal Polarity Function CK0, CK2 Input Pulse Positive Edge The system clock inputs. All of the SDRAM inputs are sampled on the rising edge of their associated clock. CKE0 Input Level Active High Activates the CK0 and CK2 signals when high and deactivates them when low. By deactivating the clocks, CKE0 low initiates the Power Down mode, Suspend mode, or the Self Refresh mode. S0,S2 Input Pulse Enables the associated SDRAM command decoder when low and disables the command Active Low decoder when high. When the command decoder is disabled, new commands are ignored but previous operations continue. RAS, CAS WE Input Pulse Active Low BA0, BA1 Input Level — Selects which SDRAM bank is to be active. Level — During a Bank Activate command cycle, A0-A11 defines the row address (RA0-RA11) when sampled at the rising clock edge. During a Read or Write command cycle, A0-A7 defines the column address (CA0-CA7) when sampled at the rising clock edge. In addition to the column address, AP is used to invoke Autoprecharge operation at the end of the Burst Read or Write cycle. If AP is high, autoprecharge is selected and BA0/BA1 define the bank to be precharged. If AP is low, autoprecharge is disabled. During a Precharge command cycle, AP is used in conjunction with BA0/BA1 to control which bank(s) to precharge. If AP is high all 4 banks will be precharged regardless of the state of BA0/BA1. If AP is low, then BA0/BA1 are used to define which bank to precharge. Level — Data and Check Bit Input/Output pins operate in the same manner as on conventional DRAMs. The Data Input/Output mask places the DQ buffers in a high impedance state when sampled high. In Read mode, DQM has a latency of two clock cycles and controls the output buffers like an output enable. In Write mode, DQM has a latency of zero and operates as a byte mask by allowing input data to be written if it is low but blocks the Write operation if DQM is high. A0 - A9 A10/AP A11 Input DQ0 - DQ63, Input CB0 - CB7 Output When sampled at the positive rising edge of the clock, CAS, RAS, and WE define the operation to be executed by the SDRAM. DQMB0 DQMB7 Input Pulse Active High SA0 - SA2 Input Level — Address inputs. Connected to either VDD or VSS on the system board to configure the Serial Presence Detect EEPROM address. SDA Input Output Level — Serial Data. Bidirectional signal used to transfer data into and out of the Serial Presence Detect EEPROM. Since the SDA signal is Open Drain/Open Collector at the EEPROM, a pull-up resistor is required on the system board. SCL Input Pulse — Serial Clock. Used to clock all Serial Presence Detect data into and out of the EEPROM. Since the SCL signal is inactive in the “high” state, a pull-up resistor is recommended on the system board. WP Input Level Active High Hardware Write Protect. When WP is active, writing to the EEPROM array is inhibited. On the DIMM, this input is connected to the EEPROM Write Protect input and is also tied to ground through a 47K ohm pull-down resistor. VDD, VSS Supply 19L7294.E93875A 8/99 Power and ground for the module. ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 5 of 18 Discontinued (4/1/00 - last order; 7/31/00 - last ship) IBM13N4644MCB IBM13N4734MCB 4M x 64/72 One-Bank Unbuffered SDRAM Module Serial Presence Detect (Part 1 of 2) Byte # Description SPD Entry Value Serial PD Data Entry (Hexadecimal) 0 Number of Serial PD Bytes Written during Production 128 80 1 Total Number of Bytes in Serial PD device 256 08 2 Fundamental Memory Type SDRAM 04 3 Number of Row Addresses on Assembly 12 0C 4 Number of Column Addresses on Assembly 8 08 5 Number of DIMM Banks 1 01 x64 4000 x72 4800 6-7 Data Width of Assembly 4M x 64 4M x 72 8 Voltage Interface Level of this Assembly LVTTL 01 9 SDRAM Device Cycle Time at CL=3 10.0ns A0 10 SDRAM Device Access Time from Clock at CL=3 -260,-360 6.0ns 60 -10 8.0ns 80 11 DIMM Configuration Type 4M x 64 Non-Parity 00 4M x 72 ECC 02 12 Refresh Rate/Type 13 Primary SDRAM Device Width 14 Error Checking SDRAM Device Width 15 SDRAM Device Attr: Min Clk Delay, Random Col Access 16 17 SR/1x(15.625us) 80 x16 10 4M x 64 N/A 00 4M x 72 x16 10 1 Clock 01 SDRAM Device Attributes: Burst Lengths Supported 1,2,4,8, Full Page 8F SDRAM Device Attributes: Number of Device Banks 4 04 18 SDRAM Device Attributes: CAS Latencies Supported 2, 3 06 19 SDRAM Device Attributes: CS Latency 0 01 20 SDRAM Device Attributes: WE Latency 0 01 21 SDRAM Module Attributes Unbuffered 00 22 SDRAM Device Attributes: General Wr-1/Rd Burst, Precharge All, Auto-Precharge, VDD +/- 10% 0E -260 10.0ns A0 23 Minimum Clock Cycle at CL=2 -360 15.0ns F0 -10 15.0ns F0 -260, -360 6.0ns 60 -10 8.0ns 80 N/A 00 N/A 00 24 Maximum Data Access Time (tAC) from Clock at CL=2 25 Minimum Clock Cycle Time at CL=1 26 Maximum Data Access Time (tAC) from Clock at CL=1 27 Minimum Row Precharge Time (tRP) 28 Minimum Row Active to Row Active delay (tRRD) 29 Minimum RAS to CAS delay (tRCD) 1. 2. 3. 4. 5. 6. 7. -360 20ns 14 -10 30ns 1E -360 20ns 14 -10 20ns 14 -360 20ns 14 -10 30ns 1E Notes 1 1 See the AC output load circuit in the AC Characteristics section below cc = Checksum Data byte, 00-FF (Hex) “R” = Alphanumeric revision code, A-Z, 0-9 rr = ASCII coded revision code byte “R” yy = Binary coded decimal year code, 00-99 (Decimal) 00-63 (Hex) ww = Binary coded decimal week code, 01-52 (Decimal) 01-34 (Hex) ss = Serial number data byte, 00-FF (Hex) ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 6 of 18 19L7294.E93875A 8/99 Discontinued (4/1/00 - last order; 7/31/00 - last ship) IBM13N4644MCB IBM13N4734MCB 4M x 64/72 One-Bank Unbuffered SDRAM Module Serial Presence Detect (Part 2 of 2) Byte # Description 30 Minimum RAS Pulse width (tRAS) 31 Module Bank Density 32 Address and Command Setup Time Before Clock 33 Address and Command Hold Time After Clock 34 Data Input Setup Time Before Clock 35 Data Input Hold Time After Clock -360 -10 SPD Revision 63 Checksum for bytes 0 - 62 -360 1.0ns 10 -10 1.0ns 10 -360 2.0ns 20 -10 3.0ns 30 -360 1.0ns 10 -10 1.0ns 10 -360 -10 128 255 1. 2. 3. 4. 5. 6. 7. Undefined 00 1.2A 12 2 02 Checksum Data cc IBM A400000000000000 Toronto, Canada 91 Notes 2 Vimercate, Italy 53 4M x 64, -260 ASCII ‘13N4644MC”R”-260T’ 31334E343634344D43rr 2D32363054202020 4M x 64, -360 ASCII ‘13N4644MC”R”-360T’ 31334E343634344D43rr 2D33363054202020 4M x 64, -10 ASCII ‘13N4644MC”R”-10T’ 31334E343634344D43rr 2D31305420202020 4M x 72, -260 ASCII ‘13N4734MC”R”-260T’ 31334E343733344D43rr 2D32363054202020 4M x 72, -360 ASCII ‘13N4734MC”R”-360T’ 31334E343733344D43rr 2D33363054202020 4M x 72, -10 ASCII ‘13N4734MC”R”-10T’ 31334E343733344D43rr 2D31305420202020 3, 4 “R” plus ASCII blank rr20 Year/Week Code yyww 5, 6 Serial Number ssssssss 7 Undefined 00 -360 100 MHz 64 -10 66 MHz 66 -360 CK0, CK2, CL3,concurrent AP A5 -10 CL3, CL2 06 Undefined 00 99 - 125 Reserved Attributes for Clock Frequency defined in byte 126 08 20 95 - 98 Module Serial Number 127 3C 30 93 - 94 Module Manufacturing Date Module Supports this Clock Frequency 60ns 32MB 3.0ns 91 - 92 Module Revision Code 126 32 -10 Module Manufacturing Location 73 - 90 Module Part Number 50ns 2.0ns 64 - 71 Manufacturers’ JEDEC ID Code 72 Serial PD Data Entry (Hexadecimal) -360 36 - 61 Reserved 62 SPD Entry Value Open for Customer Use See the AC output load circuit in the AC Characteristics section below cc = Checksum Data byte, 00-FF (Hex) “R” = Alphanumeric revision code, A-Z, 0-9 rr = ASCII coded revision code byte “R” yy = Binary coded decimal year code, 00-99 (Decimal) 00-63 (Hex) ww = Binary coded decimal week code, 01-52 (Decimal) 01-34 (Hex) ss = Serial number data byte, 00-FF (Hex) 19L7294.E93875A 8/99 ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 7 of 18 Discontinued (4/1/00 - last order; 7/31/00 - last ship) IBM13N4644MCB IBM13N4734MCB 4M x 64/72 One-Bank Unbuffered SDRAM Module Absolute Maximum Ratings Symbol Parameter VDD Power Supply Voltage VIN Input Voltage VOUT TA TSTG PD IOUT Rating Units Notes -0.3 to +4.6 Output Voltage SDRAM Devices -0.3 to VDD+0.3 Serial PD Device -0.3 to +6.5 SDRAM Devices -0.3 to VDD+3.3 Serial PD Device -0.3 to +6.5 Operating Temperature (ambient) Storage Temperature Power Dissipation V 1 0 to +70 °C 1 -55 to +125 °C 1 W 1 mA 1 x64 2.02 x72 2.52 50 Short Circuit Output Current 1. Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Recommended DC Operating Conditions (TA= 0 to 70°C) Rating Symbol Parameter Min. Typ. Max. Units Notes VDD Supply Voltage 3.0 3.3 3.6 V 1 VIH Input High Voltage 2.0 — VDD + 0.3 V 1, 2 VIL Input Low Voltage -0.3 — 0.8 V 1, 3 1. All voltages referenced to VSS. 2. VIH(max) = VDD + 1.2V for pulse width ≤ 5ns. 3. VIL(min) = VDD - 1.2V for pulse width ≤ 5ns. Capacitance (TA= 25°C, f=1MHz, VDD= 3.3V ± 0.3V) Organization Symbol Parameter Units x64 Max. x72 Max. CI1 Input Capacitance (A0 - A9, A10/AP, A11, BA0, BA1, RAS, CAS, WE) 35 39 pF CI2 Input Capacitance (CKE0) 35 39 pF CI3 Input Capacitance (S0, S2) 26 30 pF CI4 Input Capacitance (CK0 - CK3) 52 51 pF CI5 Input Capacitance (DQMB0 - DQMB7) 14 18 pF CI6 Input Capacitance (SA0 - SA2, SCL, WP) 11 11 pF CIO1 Input/Output Capacitance (DQ0 - DQ63, CB0 - CB7) 12 12 pF CIO2 Input/Output Capacitance (SDA) 12 12 pF ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 8 of 18 19L7294.E93875A 8/99 Discontinued (4/1/00 - last order; 7/31/00 - last ship) IBM13N4644MCB IBM13N4734MCB 4M x 64/72 One-Bank Unbuffered SDRAM Module DC Output Load Circuit 3.3 V 1200Ω VOH (DC) = 2.4V, IOH = -2mA Output VOL (DC) = 0.4V, IOL = 2mA 50pF 870Ω Output Characteristics (TA= 0 to +70°C, VDD= 3.3V ± 0.3V) x64 Symbol II(L) x72 Parameter Input Leakage Current, any input (0.0V ≤ VIN ≤ VDD), All Other Pins Not Under Test = 0V IO(L) Output Leakage Current (DOUT is disabled, 0.0V ≤ VOUT ≤ VDD) VOH Output Level (LVTTL) Output “H” Level Voltage (IOUT = -2.0mA) VOL Output Level (LVTTL) Output “L” Level Voltage (IOUT = +2.0mA) Units Notes Min. Max. Min. Max. RAS, CAS, WE, CKE0, A0-A9, A10/AP, A11, BA0, BA1 -20 +20 -25 +25 CK0 -10 +10 -15 +15 CK2 -10 +10 -10 +10 S0 -10 +10 -15 +15 S2 -10 +10 -10 +10 DQMB1 -5 +5 -10 +10 DQMB0, 2, 3, 4, 5, 6, 7 -5 +5 -5 +5 DQ0 - 63 -5 +5 -5 +5 CB0 - 7 0 0 -5 +5 SA0, SA1, SA2, SCL, SDA -10 +10 -10 +10 WP -10 +50 -10 +50 DQ0 - 63 -5 +5 -5 +5 CB0 - 7 0 0 -5 +5 SDA -10 +10 -10 +10 2.4 - 2.4 - - 0.4 - 0.4 µA µA V 1 1. See DC output load circuit. 19L7294.E93875A 8/99 ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 9 of 18 Discontinued (4/1/00 - last order; 7/31/00 - last ship) IBM13N4644MCB IBM13N4734MCB 4M x 64/72 One-Bank Unbuffered SDRAM Module Operating, Standby, and Refresh Currents (TA= 0 to +70°C, VDD= 3.3V ± 0.3V) Speed/Organization Parameter Operating Current tRC = tRC(min), tCK = min Active-Precharge command cycling without Burst operation Precharge Standby Current in Power Down Mode Precharge Standby Current in Non-Power Down Mode No Operating Current (Active state: 4 bank) Symbol Test Condition Units Notes 275 mA 1, 2 5 5 mA 4 5 5 mA 100 100 125 125 mA 3 CKE0 ≥ VIH(min), ICC2NS tCK = Infinity, S0, S2 =VIH (min) 24 24 30 30 mA 4 CKE0 ≥ VIH(min), ICC3N tCK = min, S0, S2 =VIH (min) 120 120 150 150 mA 3 CKE0 ≤ VIL(max), tCK = min, ICC3P S0, S2 =VIH (min) (Power Down Mode) 12 12 15 15 mA 5 360 360 450 450 mA 2, 6 560 440 700 550 mA -260,-360/ x64 -10/x64 -260,-360/ x72 -10/x72 280 220 350 CKE0 ≤ VIL(max), ICC2P tCK = min, S0, S2 =VIH(min) 4 4 CKE0 ≤ VIL(max), ICC2PS tCK = Infinity, S0, S2 =VIH(min) 4 CKE0 ≥ VIH(min), ICC2N tCK = min, S0, S2 =VIH (min) ICC1 1 Bank operation Burst Operating Current ICC4 tCK = min, Read/write command cycling, multiple banks active, gapless data, BL = 4 Auto (CBR) Refresh Current ICC5 tCK = min, tRC = tRC(min), CBR command cycling Self Refresh Current ICC6 CKE0 ≤ 0.2V 4 4 5 5 mA Serial PD Device Standby Current ISB VIN = GND or VDD 30 30 30 30 µA 7 Serial PD Device Active Power Supply Current ICCA SCL Clock Frequency = 100KHz 1 1 1 1 mA 8 1. These parameters depend on the cycle rate and are measured with the cycle determined by the minimum value of tCK and tRC. Input signals are changed up to three times during tRC(min). 2. The specified values are obtained with the output open. 3. Input signals are changed once during three clock cycles. 4. Input signals are stable. 5. Active standby current will be higher if Clock Suspend is entered during a Burst Read cycle (add 1mA per DQ). 6. Input signals are changed once during tck(min). 7. VDD = 3.3V 8. Input pulse levels VDD x 0.1 to VDD x 0.9, input rise and fall times 10ns, input and output timing levels VDD x 0.5, output load 1 TTL gate and CL=100pf. ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 10 of 18 19L7294.E93875A 8/99 Discontinued (4/1/00 - last order; 7/31/00 - last ship) IBM13N4644MCB IBM13N4734MCB 4M x 64/72 One-Bank Unbuffered SDRAM Module AC Characteristics (TA= 0 to +70°C, VDD= 3.3V ± 0.3V) 1. An initial pause of 200µs, with DQMB0-7 and CKE0 held high, is required after power-up. A Precharge All Banks command must be given followed by a minimum of eight Auto (CBR) Refresh cycles before or after the Mode Register Set operation. 2. The Transition time is measured between VIH and VIL (or between VIL and VIH). 3. In addition to meeting the transition rate specification, the CK0, CK2, and CKE0 signals must transit between VIH and VIL (or between VIL and VIH) in a monotonic manner. 4. Load Circuit A: AC timing tests have VIL = 0.4 V and VIH = 2.4 V with the timing referenced to the 1.40V crossover point. 5. Load Circuit A: AC measurements assume tT=1.0 ns. 6. Load Circuit B: AC timing tests have VIL = 0.8 V and VIH = 2.0 V with the timing referenced to the 1.40V crossover point. 7. Load Circuit B: AC measurements assume tT=1.2 ns. AC Characteristics Diagrams tCKH Clock Vtt=1.4V VIH 1.4V VIL tCKL tSETUP tT 50Ω Output Zo = 50Ω 50pF AC Output Load Circuit (A) tHOLD Input 1.4V Output tAC tOH tLZ Output 19L7294.E93875A 8/99 1.4V Zo = 50Ω 50pF AC Output Load Circuit (B) ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 11 of 18 Discontinued (4/1/00 - last order; 7/31/00 - last ship) IBM13N4644MCB IBM13N4734MCB 4M x 64/72 One-Bank Unbuffered SDRAM Module Clock and Clock Enable Parameters -260 Symbol -360 -10 Parameter Units Notes Min. Max. Min. Max. Min. Max. tCK3 Clock Cycle Time, CAS Latency = 3 10 1000 10 1000 10 1000 ns tCK2 Clock Cycle Time, CAS Latency = 2 10 1000 15 1000 15 1000 ns 1 tAC3 (A) Clock Access Time, CAS Latency = 3 — — — — — 7 ns 2 tAC2 (A) Clock Access Time, CAS Latency = 2 — — — — — 8 ns 2 tAC3 (B) Clock Access Time, CAS Latency = 3 — 6 — 6 — 9 ns 3 tAC2 (B) Clock Access Time, CAS Latency = 2 — 6 — 9 — 9 ns 3 tCKH Clock High Pulse Width 3 — 3 — 3 — ns 4 tCKL Clock Low Pulse Width 3 — 3 — 3 — ns 4 tCES Clock Enable Set-up Time 2 — 2 — 3 — ns tCEH Clock Enable Hold Time 1 — 1 — 1 — ns tSB Power down mode Entry Time 0 10 0 10 0 10 ns tT Transition Time (Rise and Fall) 0.5 10 0.5 10 0.5 10 ns 1. 2. 3. 4. For -360 sort, 66MHz clock: CAS Latency = 2. Access time is measured at 1.4V. In AC Characteristics section, see notes 1, 2, 3, 4, and 5, and load circuit A. Access time is measured at 1.4V. In AC Characteristics section, see notes 1, 2, 3, 6, and 7, and load circuit B. tCKH is the pulse width of CLK measured from the positive edge to the negative edge referenced to VIH (min). tCKL is the pulse width of CLK measured from the negative edge to the positive edge referenced to VIL (max). ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 12 of 18 19L7294.E93875A 8/99 Discontinued (4/1/00 - last order; 7/31/00 - last ship) IBM13N4644MCB IBM13N4734MCB 4M x 64/72 One-Bank Unbuffered SDRAM Module Common Parameters -260 Symbol -360 -10 Parameter Units Notes Min. Max. Min. Max. Min. Max. tCS Command Setup Time 2 — 2 — 3 — ns tCH Command Hold Time 1 — 1 — 1 — ns tAS Address and Bank Select Set-up Time 2 — 2 — 3 — ns tAH Address and Bank Select Hold Time 1 — 1 — 1 — ns tRCD RAS to CAS Delay 20 — 20 — 28 — ns 1 tRC Bank Cycle Time 70 — 70 — 84 — ns 1 tRAS Active Command Period 50 100000 50 100000 60 100000 ns 1 tRP Precharge Time 20 — 20 — 30 — ns 1 tRRD Bank to Bank Delay Time 20 — 20 — 20 — ns 1 tCCD CAS to CAS Delay Time 1 — 1 — 1 — CLK 1. These parameters account for the number of clock cycle and depend on the operating frequency of the clock, as follows: the number of clock cycles = specified value of timing / clock period (count fractions as a whole number). Mode Register Set Cycle -260 Symbol tRSC -360 -10 Parameter Min. Max. Min. Max. Min. Max. 2 — 2 — 2 — Mode Register Set Cycle Time Units Notes clk 1 1. These parameters account for the number of clock cycle and depend on the operating frequency of the clock, as follows: the number of clock cycles = specified value of timing / clock period (count fractions as a whole number). Read Cycle -260 Symbol -360 -10 Parameter Units Min. Max. Min. Max. Min. Max. Notes tOH Data Out Hold Time 3 — 3 — 3 — ns tLZ Data Out to Low Impedance Time 0 — 0 — 0 — ns tHZ3 Data Out to High Impedance Time 3 6 3 6 3 7 ns 1 tHZ2 Data Out to High Impedance Time 3 6 3 8 3 8 ns 1 tDQZ DQM Data Out Disable Latency 2 — 2 — 2 — CLK 1 1. Referenced to the time at which the output achieves the open circuit condition, not to output voltage levels. 19L7294.E93875A 8/99 ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 13 of 18 Discontinued (4/1/00 - last order; 7/31/00 - last ship) IBM13N4644MCB IBM13N4734MCB 4M x 64/72 One-Bank Unbuffered SDRAM Module Refresh Cycle Symbol tREF tSREX Parameter -260 -360 Min. Max. Refresh Period — 64 Self Refresh Exit Time 10 -10 Min. Max. — 64 Min. Max. — 64 10 Units Notes ms 1 10 ns 1. 4096 auto refresh cycles. Write Cycle Symbol -260 Parameter -360 -10 Min. Max. Min. Max. Min. Max. Units tDS Data In Set-up Time 2 — 2 — 3 — ns tDH Data In Hold Time 1 — 1 — 1 — ns tDPL Data input to Precharge 15 — 15 — 15 — ns tDAL2 Data In to Active Delay CAS Latency = 2 4 — 4 — 4 — CLK tDAL3 Data In to Active Delay CAS Latency = 3 5 — 5 — 5 — CLK tDQW DQM Write Mask Latency 0 — 0 — 0 — CLK Presence Detect Read and Write Cycle Symbol Max. Units SCL Clock Frequency 100 kHZ TI Noise Suppression Time Constant at SCL, SDA Inputs 100 ns tAA SCL Low to SDA Data Out Valid 0.3 3.5 µs tBUF Time the Bus Must Be Free before a New Transmission Can Start 4.7 µs Start Condition Hold Time 4.0 µs tLOW Clock Low Period 4.7 µs tHIGH fSCL tHD:STA Parameter Min. Clock High Period 4.0 µs tSU:STA Start Condition Setup Time (for a Repeated Start Condition) 4.7 µs tHD:DAT Data in Hold Time 0 µs tSU:DAT Data in Setup Time 250 ns tr SDA and SCL Rise Time 1 tf SDA and SCL Fall Time 300 µs ns Stop Condition Setup Time 4.7 µs tDH Data Out Hold Time 300 ns tWR Write Cycle Time tSU:STO 15 Notes ms 1 1. The Write cycle time (tWR) is the time from a valid stop condition of a write sequence to the end of the internal Erase/Program cycle. During the Write cycle, the bus interface circuits are disabled, SDA is allowed to remain high per the bus-level pull-up resistor, and the device does not respond to its slave address. ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 14 of 18 19L7294.E93875A 8/99 Discontinued (4/1/00 - last order; 7/31/00 - last ship) IBM13N4644MCB IBM13N4734MCB 4M x 64/72 One-Bank Unbuffered SDRAM Module Functional Description and Timing Diagrams Refer to the IBM 64Mb Synchronous DRAM Die Revision C data sheet, document 19L3265.E35856, for the functional description and timing diagrams for SDRAM operation. Refer to the IBM Application Notes Serial Presence Detect on Memory DIMMs and SDRAM Presence Detect Definitions for the Serial Presence Detect functional description and timings. All AC timing information refers to the timings at the SDRAM devices. 19L7294.E93875A 8/99 ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 15 of 18 Discontinued (4/1/00 - last order; 7/31/00 - last ship) IBM13N4644MCB IBM13N4734MCB 4M x 64/72 One-Bank Unbuffered SDRAM Module Layout Drawing 133.35 5.25 131.35 5.171 (2x) 4.00 .157 127.35 5.014 Front 6.35 .250 3.0 .118 1780 .700 25.4 1.00 * (2) 0 3.18 .1255 1.27 Pitch .050 42.18 1.661 1.00 Width .039 66.68 2.63 See Detail A * Note: on x72 Module Only Detail A Side Scale 4/1 1.27 ± 0.10 0.050 ± .004 2.59 0.106 .311 min. 2.0 .078 3.0 .118 R 1.00 .0393 Note: All dimensions are typical unless otherwise stated. ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 16 of 18 Millimeters Inches 19L7294.E93875A 8/99 Discontinued (4/1/00 - last order; 7/31/00 - last ship) IBM13N4644MCB IBM13N4734MCB 4M x 64/72 One-Bank Unbuffered SDRAM Module Revision Log Rev Contents of Modification 3/99 Initial release. Reflects PC100 rev 1.2; new card outline and 64Mb Synchronous DRAM Die Rev C application specification 5/99 Updated ICC2NS in Operating, Standby, and Refresh Currents table 8/99 Removed Preliminary 19L7294.E93875A 8/99 ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 17 of 18 Discontinued (4/1/00 - last order; 7/31/00 - last ship) International Business Machines Corp.1999 Copyright Printed in the United States of America All rights reserved IBM and the IBM logo are registered trademarks of the IBM Corporation. This document may contain preliminary information and is subject to change by IBM without notice. IBM assumes no responsibility or liability for any use of the information contained herein. Nothing in this document shall operate as an express or implied license or indemnity under the intellectual property rights of IBM or third parties. The products described in this document are not intended for use in implantation or other direct life support applications where malfunction may result in direct physical harm or injury to persons. NO WARRANTIES OF ANY KIND, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, ARE OFFERED IN THIS DOCUMENT. For more information contact your IBM Microelectronics sales representative or visit us on World Wide Web at http://www.chips.ibm.com IBM Microelectronics manufacturing is ISO 9000 compliant.