128K x 32 FLASH Memory PUMA 2F4006-70/90/12 Elm Road, West Chirton, NORTH SHIELDS, Tyne & Wear NE29 8SE, England Tel. +44 (0)191 2930500 Fax. +44 (0) 191 2590997 Issue 4.1 April 1999 General Description The PUMA 2F4006 is a 4,194,304 bit CMOS 5.0V only FLASH memory in a 66 pin ceramic PGA package, which is configurable as 8, 16, 32 bit wide output using four chip selects.Flash memory combines the functionality of EEPROM with on chip electrical Write/Erase logic, thus simplifying the external control circuitry. The PUMA 2F4006 incorporates Automatic Programming and Erase functions, which allow up to 10,000 Write/Erase cycles (min). In addition, a Sector Erase function is available which can erase one 16K block of data randomly and more than one block simultaneously. The PUMA 2F4006 also features hardware sector protection, which enables both program and erase operations in any of the 32 sectors on the module. Features • Very Fast Access Times of 70ns/90ns/120ns. • Operating Power (Read) 660 mW (Max) (Program/Erase) 1100 mW (Max) Standby Power 2.2 mW (Max) Output Configurable as 32 / 16 / 8 bit wide. • Automatic Write/Erase by Embedded Algorithm end of Write/Erase indicated by DATA Polling and Toggle Bit. • Flexible Sector Erase Architecture - 16K byte sector size, with hardware protection of any number of sectors. • Single Byte Program of 14µs (typical), Sector Pro gram time of 0.3 sec. (typical). • Module FLASH Erase of 3 seconds (typical). • Erase/Write Cycle Endurance 10,000 (minimum) • Can be screened in accordance with MIL-STD-883. Block Diagram Pin Definition 1 A0~A16 D8 OE WE4 WE3 WE2 WE1 128K x 8 FLASH 128K x 8 FLASH 128K x 8 FLASH 128K x 8 FLASH 23 34 45 56 D15 D24 VCC D31 2 13 24 35 46 57 D9 CS2 D14 D25 CS4 D30 3 14 25 36 47 58 D10 GND D13 D26 WE4 D29 37 4 15 26 A14 D11 D12 5 16 27 A16 A10 OE 6 17 28 A11 CS1 CS2 CS3 CS4 D0~7 D8~15 D16~23 D24~31 12 WE2 A9 NC 7 18 29 A0 A15 WE1 VIEW FROM ABOVE Address Inputs Chip Select Write Enable Ground 59 D28 38 49 60 A12 A4 A1 39 50 61 NC A5 A2 40 51 62 A13 A6 A3 8 19 30 41 52 63 NC VCC D7 A8 WE3 D23 9 20 31 42 53 64 D0 CS1 D6 D16 CS3 D22 10 21 32 43 54 65 D1 NC D5 D17 GND D21 11 22 33 44 55 66 D2 D3 D4 D18 D19 D20 Pin Functions A0~A16 CS1~4 WE1~4 GND 48 D27 A7 D0~D31 OE VCC Data Input/Output Output Enable Power (+5V) PUMA 2F4006 - 70/90/12 Issue 4.1 April 1999 DC OPERATING CONDITIONS Absolute Maximum Ratings (1) Voltage on any pin w.r.t. Gnd(2) (except A9) Supply Voltage(2) Voltage on A9 w.r.t. Gnd Storage Temperature Notes : (1) (2) -2.0 to +7 -2.0 to +7 -2.0 to +14 -65 to +150 unit V V V °C Stresses above those listed may cause permanent damage to the device. This is a stress rating only and functional operationof the device at those or any other conditions above those indicated in the operational sections of this specification is not implied. Minimum DC voltage on any input or I/O pin is -0.5V. Maximum DC voltage on output and I/O pins is Vcc+0.5V. During transitions voltage may overshoot by +/-2V for up to 20ns Recommended Operating Conditions Parameter Symbol DC Logic Supply Voltage Input High Voltage TTL CMOS Input Low Voltage TTL CMOS Operating Temperature VCC VIH VIHC VIL VILC TA TAI TAM min typ max unit 4.5 2.0 0.7VCC -0.5 -0.5 0 -40 -55 5.0 - 5.5 VCC+0.5 VCC+0.5 0.8 0.8 70 85 125 V V V V V °C °C °C (-I suffix) (-M, MB suffix) DC Electrical Characteristics (TA= -55°C to +125°C,VCC=5V±10%) Parameter Input Leakage Current Output Leakage Current Standby Supply Current Symbol Test Condition ILI ILO ISB1 VIN=0 to VCC , VCC = VCC max. VOUT=0 to VCC ,VCC = VCC max. TTL CS1~4=VIH ,VCC = VCC max. CMOSISB2 CS1~4=VCC+0.5 , VCC = VCC max. Operating Current Read Program/Erase Output LowVoltage Output HighVoltage ICC1 ICC2 VOL VOH Low Vcc lock out voltage VLKO A9 voltage for autoselect VID CS1~4 = VIL, OE = VIH CS1~4 = VIL, OE = VIH IOL=12mA , VCC = VCC min. IOH=-2.5mA , VCC = VCC min. VCC =5.0V min typ - - - max - ±4 ±4 4 400 µA µA mA µA 2.4 - 120 200 0.45 - mA mA V V 3.2 - - V 11.5 - 12.5 V Capacitance (TA=25oC,f=1MHz) Parameter Input Capacitance: Output Capacitance: Symbol CIN COUT Test Condition VIN=0V VOUT=0V Note: Capacitance calculated not measured. 2 Unit typ 34 44 max 40 58 Unit pF pF PUMA 2F4006 - 70/90/12 Issue 4.1 April 1999 AC Test Conditions * Input pulse levels : 0.0V to 3.0V * Input rise and fall times : 5 ns * Input and output timing reference levels : 1.5V * VCC = 5V +/- 10% * Module tested in 32 bit mode 166 Ω I/O Pin 1.76V 30pF Operating Modes The following modes are used to control the PUMA 2F4006 OPERATION CS1~4 OE WE1~4 AO A1 A9 I /O Auto-Select Manufacturer Code L L H L L VID Code Auto Select Device Code L L H H L VID Code Read L L H A0 A1 A9 Dout Standby H X X X X X High Z Output Disable L H H X X X High Z Write L H L A0 A1 A9 Din Enable Sector Protect L VID L X X VID X Verify Sector Protect L L H L H VID Code CS1~4 and WE1~4 should be controlled by the user to configure the device for 8,16,or 32 bit operation. 3 PUMA 2F4006 - 70/90/12 Issue 4.1 April 1999 AC OPERATING CONDITIONS Read Parameter Symbol Read Cycle Time Address to output delay Chip Select to output Output Enable to output Chip Select to O/P High Z Output Enable to output High Z Output hold time (From address, -70 min max tRC tAC 70 - tCE tOE - tDF - tDF tOH 0 - -90 -12 min max min max unit 70 70 30 20 20 - 90 0 90 90 35 20 20 - 120 0 120 120 50 30 30 - ns ns ns ns ns ns ns max min max min max unit - 90 0 45 40 0 0 0 0 0 0 40 20 14 3 50 4 10 4 4 - 120 0 50 50 0 0 0 0 0 0 50 20 14 3 50 4 10 4 4 - ns ns ns ns ns ns ns ns ns ns ns ns µs s µs ns ns ns ns CS1~4 or OE whichever occurs first) Write/ Erase/ Program -70 Parameter Symbol min Write Cycle time Address Setup time Address Hold time Data Setup Time Data hold Time Output Enable Setup Time Output Enable Hold Time Read Recover before Write CS1~4 setup time CS1~4 hold time Write Pulse Width Write Pulse Width High Programming operation Erase operation(1) Vcc setup time(4) Voltage Transition Time(2,4) Write Pulse Width(2) OE Setup time to WE1~4 active(2,4) CS1~4 Setup time to WE1~4 active(3,4) Notes: (1) (2) (3) (4) tWC tAS tAH tDS tDH tOES tOEH tGHWL tCS tCH tWP tWPH tWHWH1 tWHWH2 tVCS tVLHT tWPP tOESP tCSP 70 0 45 30 0 0 0 0 0 0 35 20 14 3 50 4 10 4 4 -90 -12 This also includes the preprogramming time. These timings are for Sector Protect/Unprotect operations. This timing is only for Sector Unprotect. Not 100% tested. 4 PUMA 2F4006 - 70/90/12 Issue 4.1 April 1999 Write/Erase/Program (Alternate CS1~4 controlled Writes) -70 Parameter Write Cycle time Address Setup time Address Hold time Programming operation Data hold Time Output Enable Setup Time Output Enable Hold Time Read Recover before Write WE1~4 setup time WE1~4 hold time CS1~4 Pulse Width CS1~4 Pulse Width High Programming operation Erase operation(1) Vcc setup time(2) Notes: -90 -12 Symbol min max min max min max unit tWC tAS tAH tDS tDH tOES tOEH tGHEL tWS tWH tCP tCPH tWHWH1 tWHWH2 tVCS 70 0 45 30 0 0 0 0 0 0 35 20 14 3 2 - 90 0 45 40 0 0 0 0 0 0 40 20 14 3 2 - 120 0 50 50 0 0 0 0 0 0 50 20 14 3 2 - ns ns ns ns ns ns ns ns ns ns ns ns µs s µs (1) This also includes the preprogramming time. (2) Not 100% tested. 5 PUMA 2F4006 - 70/90/12 Issue 4.1 April 1999 AC Waveforms for Read Operation Address Valid Address tRC CS1~4 tCE tOE tDF OE WE1~4 tOH tACC Output Valid HIGH Z Data Out HIGH Z AC Programming Waveforms Data Polling 5555H Address PA t AS t WC PA t RC t AH CS1~4 t GHWL OE t WHWH1 t WP WE1~4 t OE t WPH t CS t DH A0H DATA t DF t DS D7 PD D OUT t CE t OH 5.0 V Notes: 1. PA is address of the memory location to be programmed. 2. PD is data to be programmed at byte/word address. 3. D7 is the output of the complement of the data written to the device. D7 and D15 are used for 16 bit mode, whilst D7,D15,D23,D31 are used for 32 bit mode. 4. DOUT is the output of the data written to the device. 5. Figure indicates last two bus cycles of four bus cycle sequence. 6 PUMA 2F4006 - 70/90/12 Issue 4.1 April 1999 AC Chip / Sector Erase Waveforms t AS 5555H Address t AH 2AAAH 5555H 5555H 2AAAH 55H 80H AAH 5HH SA CS1~4 t GHWL OE t WP WE1~4 t CS t WPH t DH Data t DS Vcc AAH 10H/30H t VCS NOTES 1. SA is the address for Sector Erase. Addresses = don't care for Chip Erase. 2. The data must be repeated on both bytes of the data bus for 16 bit mode and on all four bytes for 32 bit mode. AC Waveforms for Data Polling During Embedded Algorithm Operations t CH CS1~4 t DF t OE OE t OEH WE1~4 t OH t CE * D7 D7 t WHWH 1 OR 2 D0~6 D0~6=Invalid HIGH Z D7 = Valid Data D0~7 Valid Data HIGH Z t OE * D7 = Valid data(The device has completed the Embeded Operation).For 16 and 32 bit modes D7,D15 and D7,D15,D23,D31 are used respectively. 8 bit mode is shown above. 7 PUMA 2F4006 - 70/90/12 Issue 4.1 April 1999 AC Waveforms for Toggle Bit During Embedded Algorithm Operations WE1~4 tOEH CS1~4 OE * Data (D0~7) D6=Toggle D6 = Stop Toggling D0~7 Valid tOE tOH * D6=Toggle D6 stops toggling(The device has completed the Embedded operation). D6,D14 and D6,D14,D22,D30 are used for 16 bit and 32 bit modes respectively. 8 bit mode shown above. AC Waveforms For Sector Protection A16 A15 A14 SA X SA Y A0 A1 12V 5V A9 t VLHT t VLHT 12V 5V OE t WPP t VLHT WE1~4 t OESP CS1~4 Data t OE SAX = sector Addr for intial sector SAY = sector Addr for next sector 8 01H PUMA 2F4006 - 70/90/12 Issue 4.1 April 1999 AC Waveforms for Sector Unprotect ≈ A16 A15 A14 ≈ ≈ SA0 ≈ ≈ A0 ≈ ≈ A1 12V 5V A9 ≈ t VLHT ≈ ≈ A6 ≈ A7 A12 OE t VLHT ≈ ≈ 12V 5V t CSP t WPP WE1~4 CS1~4 t VLHT t VLHT ≈ Data ≈ 12V 5V Execute Auto Select Command Sequence 9 00H SA1 PUMA 2F4006 - 70/90/12 Issue 4.1 April 1999 A.C Waveforms - Alternate CS1~4 controlled Program operation timings Data Polling Address 5555H PA t WC t AS PA t AH WE1~4 t GHEL OE t CP t CPH CS1~4 DATA t WS t DH A0H PD D7 D OUT t DS VCC Notes: 1. PA is address of the memory location to be programmed. 2. PD is data to be programmed at byte/word address. 3. D7 is the output of the complement of the data written to the device. D7 and D15 are used for 16 bit mode, whilst D7,D15,D23,D31 are used for 32 bit mode. 4. DOUT is the output of the data written to the device. 5. Figure indicates last two bus cycles of four bus cycle sequence. 10 PUMA 2F4006 - 70/90/12 Issue 4.1 April 1999 Command Definitions Device operations are selected by writing specific address and data sequences into the command register. The following table defines these register command sequences for 8 bit mode. For 16 and 32 bit mode, the data values in the table should be repeated on each byte of the data bus, when entering a command sequence. Data to be stored should be entered normally as 16 or 32 bit. COMMAND Bus First Bus Second Bus Third bus Write Write Cycle Write Cycle Write Cycle Cycles SEQUENCE Req'd Addr Data Addr Data Addr Data Forth bus Read/Write Cycle Fifth Bus Write Cycle Addr Addr Data Sixth Bus Write Cycle Data Addr Data Read/Reset 4 5555H AAH 2AAAH 55H 5555H F0H RA RD Autoselect 4 5555H AAH 2AAAH 55H 5555H 90H 00H/01H 01H/20H Byte Program 4 5555H AAH 2AAAH 55H 5555H A0H PA PD Chip erase 6 5555H AAH 2AAAH 55H 5555H 80H 5555H AAH 2AAAH 55H 5555H 10H Sector erase 6 5555H AAH 2AAAH 55H 5555H 80H 5555H AAH 2AAAH 55H SA 30H NOTES: 1. Address bit A15=X=Don't care. Write Sequences may be initiated with A15 in either state. 2. Address bit A16=X=Don't care for all address commands except for Program Address (PA) and Sector Address (SA). 3. RA=Address of the memory location to be read. PA=Address of memory location to be programmed. Addresses are latched on the falling edge of the WE1~4 pulse. SA=Address of the sector to be erased. The combination of A16, A15 and A14 will uniquely select any sector in 32 bit mode. 4. RD=Data read from location RA during read operation. PD=Data to be programmed at location PA. Data is latched on the falling edge of WE1~4 Read/Reset Command The read or reset operation is initiated by writing the read/reset command sequence into the command register. Microprocessor read cycles retrieve array data from the memory. The device remains enabled for reads until the command register contents are altered. The device will automatically power-up in the read/reset state. In this case, a command sequence is not required to read data. Standard microprocessor read cycles will retrieve array data. This default value ensures that no spurious alteration of memory content occurs during the power transition. Refer to the AC Read Characteristics and Waveforms for specific timing parameters. 11 PUMA 2F4006 - 70/90/12 Issue 4.1 April 1999 Read Mode The PUMA 2F4006 has two control functions which must be satisfied in order to obtain data at the outputs. CS1~4 is the power control and should be used for device selection OE is the output control and should be used to gate data to the output pins if the device is selected. Standby Mode Two standby modes are available : CMOS standby : CS1~4 held at Vcc +/- 0.5V TTL standby : CS1~4 held at VIH In the standby mode the outputs are in a high impedance state independent of the OE input. If the device is deselected during erasure or programming the device will draw active current until the operation is completed. Output Disable With the OE input at a logic high level (VIH), output from the device is disabled. This will cause the output pins to be in a high impedance state. Autoselect The autoselect mode allows the reading out of a binary code from the device and will identify the DIE manufacturer and type. This mode is intended for use by programming equipment. This mode is functional over the full military temperature range. The autoselect codes are as follows : A16 A15 A14 DIE Manufacturer code X X DIE device code X X Sector protection A1 A0 CODE (HEX) D7 D6 D5 D4 D3 D2 D1 D0 X VIL VIL 01H 0 0 0 0 0 0 0 1 X VIL VIH 20H 0 0 1 0 0 0 0 0 Sector Address VIH VIL 01H* 0 0 0 0 0 0 0 1 * Outputs 01H at protected sector address. Outputs 00H at unprotected sector address.For 16 & 32 bit D0-D7 is repeated on each byte of the data bus. To activate this mode the programming equipment must force VID (11.5 to 12.5V) on address A9. Two identifier bytes may then be sequenced from each DIE device outputs by toggling A0 from VIL to VIH. All addresses are dont care apart from A1 & A0. All identifiers for manufacturer and device will exhibit odd parity with D7 defined as the parity bit. The manufacturer and device codes may also be read via the command register, for instances when the PUMA 2F4006 is erased or programmed in a system without access to high voltage on A9. All identifiers for manufacturers and device will exhibit odd parity with the MSB(D7/D15/D23/D31) defined as the parity bit. In order to read the proper device codes when executing the Autoselect, A1 must be VIL. Write Device erasure and programming are accomplished via the command register. The contents of the register serve as inputs to the internal state machine. The state machine outputs dictate the function of the device. The register is a latch used to store the commands along with the address and data information required to execute the command. The command register is written by bringing WE1~4 to VIL while CS1~4 is at VIL and OE is at VIH.Addresses are latched on the falling edge of WE1~4 while data is latched on the rising edge. 12 PUMA 2F4006 - 70/90/12 Issue 4.1 April 1999 Sector Protection The PUMA 2F4006 features hardware sector protection. This feature will disable both program and erase operations in any number of sectors (0 through 7). The sector protect feature is enabled using programming equipment at the users site. The device is shipped with all sectors unprotected. To activate this mode, the programming equipment must force VID on address pin A9 and control pin OE. The sector adresses (A16, A15 and A14) should be set to the sector to be protected. Programming of the protection circuitry begins on the falling edge of the WE1~4 pulse and is terminated with the rising edge of the same. Sector addresses must be held constant during the WE1~4 pulse. (See Sector Address Table) To verify programming of the protection equipment circuitry, the programming equipment must force VID on address pin A9 with CS1~4 and OE at VIL and WE1~4 at VIH. Reading the device at a particular sector address (A16, A15 and A14) will produce 01H at data outputs (D0-D7/D0-D15/D0-D31) for a protected sector. Otherwise the device will read 00H for unprotected sector. In this mode, the lower order addresses, except for A0 and A1, are don't care. Address location 02H is reserved to verify sector protection of the device. Address pin A1 must be held at VIH and A0 at VIL. Address location 00H and 01H are reserved for autoselect codes. If a verify of the sector protection circuitry were done at these addresses, the device would output the manufacturer and device codes respectively It is also possible to determine if a sector is protected in the system by writing the autoselect command. Performing a read operation at particular sector addresses (A16, A15 and A14) and with A1=VIH and A0=VIL (other addresses are a don't care) will produce 01H data if those sectors are protected. Otherwise the device will read 00H for an unprotected sector. (See Sector Protect/Unprotect Algorithms for more details.) Sector Address Table A16 A15 A14 Address Range SA0 0 0 0 00000H-03FFFH SA1 0 0 1 04000H-07FFFH SA2 0 1 0 08000H-0BFFFH SA3 0 1 1 0C000H-0FFFFH SA4 1 0 0 10000H-13FFFH SA5 1 0 1 14000H-17FFFH SA6 1 1 0 18000H-1BFFFH SA7 1 1 1 1C000H-1FFFFH 13 PUMA 2F4006 - 70/90/12 Issue 4.1 April 1999 Autoselect Command Flash memories are intended for use in applications where the local CPU alters memory contents. As such, manufacture and device codes must be accessible while the device resides in the target systems. PROM programmers typically access the signature codes by raising A9 to a high voltage. However, multiplexing high voltage onto the address lines is not generally a desired system design practice. The device contains an Autoselect operation to supplement traditional PROM programming methodology. The operation is initiated by writing the Autoselect command sequence into the command register. Following the command Write, a Read cycle from address XXX0H retrieves the manufacture code of 01H. A Read cycle from address XXX1H returns the device code 20H. A Read cycle from address XXX2H returns information as to which sectors are protected. All manufacturer and device codes will exhibit odd paritywith the MSB (D7) defined as the parity bit for 8 bit. D7 and D15 for 16 bit. D7, D15, D23 and D31 are used for 32 bit. To terminate the operation, it is necessary to write the read/reset command sequence into the register. Byte Programming The device is programmed on a byte/word-by-byte/word basis. Programming is a four bus cycle operation. There are two "unlock" write cycle. These are followed by the program set-up command and data write cycles. The addresses are latched on the falling edge of CS1~4 or WE1~4 (whichever first), the data is latched on the rising edge of CS1~4 or WE1~4 (whichever first), and then programming begins. Upon executing the Embedded Program Algorithm Command sequence the system is not required to provide further controls or timings. The device will automatically provide adequate internally generated program pulses and verify the programmed cell margin. The automatic programming operation is completed when the data on D7 is equivalent to data written to this bit (see write Operations Status) at which time the device returns to read mode and addresses are no longer latched. Data Polling must be performed at the memory location which is being programmed. Programming is allowed in any address sequence and across sector boundaries. Beware that data "0" cannot be programmed back to a "1". Attempting to do so will hang up the device, or result in an apparent success according to the data polling algorithm. However, a read from Read/Reset Mode will show data is still "0". Only an erase operation can convert "0"s to "1"s. Chip Erase Chip erase is a six bus cycle operation. There are two "unlock" write cycles. These are followed by writing the "set-up" command. Two more "unlock" write cycles are then followed by the chip erase command. Chip erase doesn't require the user to program the device prior to erase. Upon executing the Embedded Erase Algorithm command sequence the device automatically will program and verify the entire memory for an all zero data pattern prior to electrical erase. The systems is not required to provide any controls or timings during these operations. The automatic erase begins on the rising edge of the last WE1~4 pulse in the command sequence and terminates when the data on D7,D15,D23,D31 are "1" (See Written Operation Section) at which time the device returns to read the mode. 14 PUMA 2F4006 - 70/90/12 Issue 4.1 April 1999 Sector Erase For 16 and 32 bit modes, the data values for the sector erase command sequence should be repeated on each byte of the data bus. Sector erase is a six bus cycle operation. There are two "unlock"write cycles. These are followed by writing the "Set-up" command. Two more "unlock" write cycles are then followed by the sector erase command. The sector address (any address location within the desired sector) is latched on the falling edge of WE1~4, while the command (data) is latched on the rising edge of WE1~4. A time-out of 80µs from the rising edge of the last sector erase command will initiate the sector erase command(s). Multiple sectors may be erased concurrently by writing the six bus cycle operations as desribed above. This sequence is followed with writes of the sector erase command (30H) to addresses in other sectors required to be concurrently erased. The time between writes must be less than 80µs, otherwise that command will not be accepted. It is recommended that processor interrupts be disabled during this time to guarantee this condition. The interrupts can be re-enabled after the last Sector Erase command(s). If another falling edge of WE1~4 occurs within the 80µs time-out window , the timer is reset.(D3,D11,D19,D27, indicate if the timer window is still open on each 128K device on the module). Loading the sector erase buffer may be done in any sequence and with any number of sectors (0 to 7). Any command other than Sector Erase during this period will reset the device to read mode, ignoring the previous. Sector erase doesn't require the user to program the device prior to erase. The device automatically programs all memory locations in the sector(s) to be erased prior to electrical erase. When erasing a sector or sectors the remaining unselected sectors are not affected. The system is not required to provide any controls or timings during these operations. The automatic sector erase begins after the 100µs time-out from the rising edge of the WE1~4 pulse for the last sector erase command pulse and terminates when the data on D7,D15,D23 and D31 are "1" ( see Write Operation Status Section) at which time the device returns to read mode. Data polling must be preformed at an address within any of the sectors being erased. Write Operation Status Hardware Sequence Flags :STATUS D7 D6 D5 D3 D2-D0 Auto-Programming In Progress Programming in auto erase D7 0 Toggle Toggle 0 0 0 1 Reserved for Erasing in Auto Erase Auto-Programming Exceeded Programming in auto erase Time limits Erasing in Auto-Erase 0 D7 0 0 Toggle Toggle Toggle Toggle 0 1 1 1 1 0 1 1 future use Reserved for future use Data Polling - D7,D15,D23,D31 The PUMA 2F4006 features Data Polling as a method to indicate to the host system that the Embedded Algorithms are in progress or completed. During the Embedded Programming Algorithm, an attempt to read the device will produce complement data of the data last written to D7. Upon completion of the Embedded Programming Algorithm an attempt to read the device will produce the true data last written to D7. Data Polling is valid after the rising edge of the forth WE1~4 pulse in the four write pulse sequence. 15 PUMA 2F4006 - 70/90/12 Issue 4.1 April 1999 During the Embedded Erase Algorithm, D7 will be "0" until the erase operation is completed. Upon completion data at D7 is "1". For chip erase, the Data Polling is valid after the rising edge of the sixth WE1~4 pulse in the six write pulse sequence. For sector erase, Data Polling is valid after the last rising edge of the sector erase WE1~4 pulse. The Data Polling feature is only active during the Embedded Programming Algorithm, Embedded Erase Algorithm, or sector erase time-out. For 16 and 32 bit modes D15,D23 and D31 behave like D7. TOGGLE Bit - D6,D14,D22,D30 The PUMA 2F4006 also features the "toggle bit" as a method to indicate to the host system that the Embedded Algorithms are in progress or completed. During an Embedded Program or Erase Algorithm cycle, successive attempts to read(OE Toggling) data from the device will result in D6 toggling between one and zero. Once the Embedded Program or Erase Algorithm cycle is completed, D6 will stop toggling and valid data will be read on successive attempts. During programming, the Toggle bit is valid after the rising edge of the forth WE1~4 pulse in the four write pulse sequence. For chip erase, the Toggle bit is valid after the sixth WE1~4 pulse in the six write pulse sequence. For sector erase, the Toggle bit is valid after the last rising edge of the sector erase WE1~4 pulse. The Toggle Bit is active during the sector time-out. Note: CS1~4 or OE toggling will toggle D6. For 16 and 32 bit modes D14,D22 and D30 behave like D6. Exceeding Time Limits - D5,D13,D21,D29 D5 will indicate if the program or erase time has exceeded the specified limits. Under these conditions D5 will produce "1", indicating the program or erase cycle was not successfully completed . Data Polling is the only operating function of the device under this condition. The CS1~4 circuit will partially power down the device under these conditions (to approximately 2mA). The OE and WE1~4 pins will control the output disable functions . To reset the device, write reset command sequence to the device. This allows the system to continue to use the other active sectors in the device. If this failiure condition occurs during the sector erase operation, it specifies that a particular sector is bad and it may not be reused. However, other sectors are still functional and may be used for additional program or erase operations. The device must be reset to use other sectors. Write the Reset command sequence to the device, and then execute the program or erase command sequence. If this failure condition occurs during the chip erase operation, it specifies that the entire chip is bad or combination of sectors are bad. If this failure condition occurs during the byte programming operation, it specifies that the entire sector containing that byte is bad and this sector may not be reused(other sectors are still functional and can be reused). The device must be reset to use other sectors. The D5 failure condition may also appear if a user tries to program a non blank location without erasing. In this case the system never reads valid data on the D7 bit and D6 never stops toggling. Once the device has exceeded timing limits, the D5 bit will indicate a "1". Please note that this is not a device failure condition since the device was incorrectly used. The device must be reset to continue using the device.For 16 and 32 bit modes D13,D21 and D29 behave like D5. Hardware Sequence Flag - D4 ,D12,D20,D28 If the device has exceeded the specified erase or program time and D5 is "1", then D4 will indicate at which step in the algorithm the device exceeded the limits. A "0" in D4 indicates in programming, a "1" indicates an erase. 16 PUMA 2F4006 - 70/90/12 Issue 4.1 April 1999 If Data Polling or the Toggle Bit indicates the device has been written with a valid erase command, D3 may be used to determine if the sector erase timer window is still open. If D3 is high the internally controlled erase cycle has begun; attempts to write subsequent commands to the device will be ignored until the erase operation is completed as indicated by Data Polling or Toggle Bit. If D3 is low , the device will accept additional sector erase commands. To insure the command has been accepted, the software should check the status of D3 prior to and following each subsequent sector erase command. If D3 were high on the second status check, the command may not have been accepted. For 16 and 32 bit configurations D3,D11 and D3,D11,D19,D27 are used respectively. Sector Erase Timer - D3, D11, D19, D27 After the completion of the initial sector erase command sequence the sector erase time-out will begin. D3 will remain low until the time-out is complete. Data Polling and Toggle Bit are valid after the initial sector erase command sequence. For 16 and 32 bit configurations D11,D19 and D27 behave like D3. Data Protection The PUMA 2F4006 is designed to offer protection against accidental erasure or programming caused by spurious system level signals that may exist during power transition. During power up the device automatically resets the internal state machine in the Read mode. Also, with its controls register architecture , alteration of the memory contents only occurs after successful completion of specific multi-bus cycle command sequences. The device also incorporates several features to prevent inadvertent write cycles resulting from Vcc power up and power down transitions or system noise. Low VCC Write Inhibit To avoid initiation of a write cycle during VCC power up and power down, a write cycle is locked out for VCC less than 3.2V (typically 3.7V). If VCC<VLKO, the command register is disabled and all internal program/erase circuits are disabled. Under this condition the device will reset to read mode. Subsequent writes will be ignored until the VCC level is greater than VKLO. It is usually correct to prevent unintentional writes when VCC is above 3.2V. Write Pulse "Glitch" Protection Noise pulses of less than 5ns (typical) on OE, CS1~4, WE1~4 will not initiate a write cycle. Logical Inhibit Writing is inhibited by holding any one of OE=VIL, CS1~4=VIH or WE1~4=VIH. To initiate a write cycle CS1~4 and WE1~4 must be logical zero while OE is a logical one. Power-Up Write Inhibit Power-up of the device with WE1~4=CS1~4=VIL and OE=VIH will not accept commands on the rising edge of WE1~4. The internal state machine is automatically reset to the read mode on power-up. Sector Protect Sectors of the PUMA 2F4006 may be hardware protected at the users factory. The protection circuitry will disable both program and erase functions for the protected sector(s). Requests to program or erase a protected sector will be ignored by the device. 17 PUMA 2F4006 - 70/90/12 Issue 4.1 April 1999 Embedded Programming Algorithm Start Write Program Command Sequence (see below) Data Poll Device Yes No Last Address ? Increment Address Yes Programming Completed Program Command Sequence (Address /Command) 5555H/AAH 2AAAH/55H 5555H/A0H Program Address/Program data NOTE:AAH,55H, and A0H above should be repeated on each byte of the data bus for 16 and 32 bit configurations, program data should be entered normally in 8,16 or 32 bit form. 18 PUMA 2F4006 - 70/90/12 Issue 4.1 April 1999 Embedded Erase Algorithm START Write Erase Command Sequence (See below) Data Poll or Toggle Bit successfully complete Yes Erasure Completed Chip Erase Command Sequence Individual Sector/Mulitiple Sector (Address/Command): Erase Command Sequence (Address/Command): 5555H/AAH 5555H/AAH 2AAAH/55H 2AAAH/55H 5555H/80H 5555H/80H 5555H/AAH 5555H/AAH 2AAAH/55H 5555H/10H 2AAAH/55H Sector Address/30H Sector Address/30H Sector Address/30H } Additional sector erase commands are optional NOTE: All data above should be repeated on each byte of the data bus for 16 and 32 bit configurations. 19 PUMA 2F4006 - 70/90/12 Issue 4.1 April 1999 Data Polling Algorithm VA = Byte/Word Address for programming. = Any of the sector address within the sector erase during sector erase operation. = XXXXH during Chip Erase START Read Byte/ Word Addr=VA D7 = Data ? YES NO NO D5 = 1 ? YES Read Byte/ Word Addr=VA D7 = Data ? YES PASS (Note 1) NO FAIL NOTE: 1. D7 is rechecked even if D5 = 1 because D7 may change simultaneously with D5. 2. For 16 and 32 bit D5,D7,D13,D15 and D5,D7,D13,D15,D21,D23,D29,D31 are used respectively. Bold=data polling bits. TOGGLE Bit Algorithm START Read Byte/ Word Addr = VA NO D6=Toggle ? YES NO D5 = 1 ? YES Read Byte/ Word Addr = VA D6=Toggle ? NO PASS (Note 1) YES FAIL NOTE: 1. D6 is rechecked even if D5 = 1 because D6 may stop toggling at the same time as D5 changing to "1". 2. For 16 and 32 bit D5,D6,D13,D14 and D5,D6,D13,D14,D21,D22,D29,D30 are used respectively. Bold=Toggle bits. 20 PUMA 2F4006 - 70/90/12 Issue 4.1 April 1999 Sector Unprotect Algorithm START Set Vcc=5.0V Protect All Sectors PLSCNT = 1 Set Up Sector Unprotect Mode A12 = A7 = VIH , A6 = VIL Set Vcc=5.0V Set OE = CS1~4 = A9 = VID Activate WE1~4 Pulse Time Out 10ms Set OE = CS1~4= VIL Remove VID from A9 Increment PLSCNT Set Vcc=4.25V Write Autoselect Command Sequence Set Up Sector Addr SA0 Set A1=1, A0=0 Read Data from Device No Increment Sector Addr Data =00H ? No Write Reset Command PLSCNT =1000 ? Yes No Sector Device Failed Addr = SA7 ? Yes Set Vcc=5.0V Write Reset Command Sector Unprotect Completed NOTES: SA0 = Sector Addr for intial sector SA7 = Sector Addr to last sector 21 PUMA 2F4006 - 70/90/12 Issue 4.1 April 1999 Sector Protection Algorithm START Set Up Sector Addr (A16, A15, A14) PLSCNT = 1 OE = VID A9=VID,CS1~4=VIL Activate WE1~4 Pulse Time Out 100us Power Down OE Increment PLSCNT WE1~4 = V IH CS1~4 = OE =V IL A9 should remain VID Read from Sector Addr=SA, A0=0, A1=1 No PLSCNT No Data = 25 =01H ? ? Yes Device Failed Yes Protect Another Sector No Remove VID From A9 Write Reset Command Sector Protection Complete 22 Yes PUMA 2F4006 - 70/90/12 Issue 4.1 April 1999 Package Details Dimensions in mm(inches). PUMA 2 - 66 Pin Ceramic PGA 27.55 (1.085) square 4.83 (0.190) 27.05 (1.065) square 4.32 (0.170) 2.54 (0.100) typ. 15.24 (0.60) typ 0.53 (0.021) 0.38 (0.015) 1.40 (0.055) 2.54 (0.100) typ. 1.14 (0.045) 1.27 (0.050) 0.64 (0.025) 1.52 (0.060) 1.02 (0.040) 8.13 (0.320) max Military Screening Procedure Module Screening Flow for high reliability product is in accordance with MIL-STD-883 method 5004 Level B and is detailed below: MODULE SCREENING FLOW SCREEN TEST METHOD LEVEL Visual and Mechanical External visual Temperature cycle 2017 Condition B or manufacturers equivalent 1010 Condition C (10 Cycles,-65oC to +150oC) 100% 100% Per applicable device specifications at TA=+25oC TA=+125oC,160hrs minimum. 100% 100% Burn-In Pre-Burn-in electrical Burn-in Final Electrical Tests Per applicable Device Specification Static (DC) a) @ TA=+25oC and power supply extremes b) @ temperature and power supply extremes 100% 100% Functional a) @ TA=+25oC and power supply extremes b) @ temperature and power supply extremes 100% 100% Switching (AC) a) @ TA=+25oC and power supply extremes b) @ temperature and power supply extremes 100% 100% Percent Defective allowable (PDA) Calculated at post-burn-in at TA=+25oC Quality Conformance Per applicable Device Specification External Visual 2009 Per vendor or customer specification 23 5% Sample 100% PUMA 2F4006 - 70/90/12 Issue 4.1 April 1999 Ordering Information PUMA 2F4006MB-70E E = 100,000 W/E Cycles 70 90 12 = = = 70 ns 90 ns 120 ns Temp. range/screening Blank I M MB = = = = Commercial Temp. Industrial Temp (-40°C to +85°C) Military Temp (-55°C to 125°C) Screened in accordance with MIL-STD-883. Organisation 4006 = User configurable as 128K x 32, 256K x 16, or 512K x 8. Technology F = FLASH Memory Package PUMA 2 = Speed 66 pin ceramic PGA. Note : Although this data is believed to be accurate the information contained herein is not intended to and does not create any warranty of merchantibility or fitness for aparticular purpose. Our products are subject to a constant process of development. Data may be changed without notice. Products are not authorised for use as critical components in life support devices without the express written approval of a company director. 24