Ordering number : ENN*6710 LC868901/51 CMOS IC LC868901/51 Row Driver IC for Dot Matrix Graphic LCD Preliminary Overview The LC868901 sereis is a common driver for the liquid crystal dot-matrix graphic display. It generates 65 commons maximum. The LC868901series has the RC-oscillator circuit attached resistor and the capacitor outside, and generates the timing signals and LCD powers for the LC868900 segmentdrivers. As the LC868901 series is fabricated using CMOS process technology, combining it with a CMOS microcontroller produces an LCD device of low power demand. Features • Classification Interfacing allowed for 80-family and our LC868000 microcontroller :LC868901 Interfacing allowed for Motorola family :LC868951 • 65 common outputs • Automatic LCD display controller Duty 1 / 1 to 1 / 65 (programmable) Bias 1 / 5, 1 / 7 and 1 / 9 (programmable) Contrasts 32-step programmable Instructions Display on / off Horizontal display bit control [Horizontal display number] ✕ [Display pitch (bit length)] Busy flag readable • Built-in power booster • Stand-by function Two kinds of stand-by setting 1. Applying low level to STB 2. Programming Stand-by releasing Read after applying low level to CS and RD • Oscillator RC oscillator must be attached resistor and the capacitor outside. • Power supply Logic circuit 3V to 5V (VDD) • CMOS process • Factory shipment Chip delivery form QFP100E package Any and all SANYO products described or contained herein do not have specifications that can handle applications that require extremely high levels of reliability, such as life-support systems, aircraft's control systems, or other applications whose failure can be reasonably expected to result in serious physical and/or material damage. Consult with your SANYO representative nearest you before using any SANYO products described or contained herein in such applications. SANYO assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all SANYO products described or contained herein. SANYO Electric Co.,Ltd. Semiconductor Company TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN Ver. 1.01 61295 D2800 RM (IM) FS No.6710-1/20 LC868901/51 80 V3 (NC) VEE1 VEE2 VOT1 VOT2 CAP1 CAP2 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 C20 C21 C22 Pin Assignment 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 C23 C24 C25 C26 C27 C28 C29 C30 C31 C32 C33 C34 C35 C36 C37 C38 C39 C40 C41 C42 CS RD WR RS CL2 M STB C65 C64 C63 C62 C61 C60 C59 C58 C57 C56 C55 C54 C53 C52 C51 C50 C49 C48 C47 C46 C45 C44 C43 30 100 50 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 XV5 XV4 XV3 XV2 XV1 RES VDD OSC1 OSC2 VSS DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 (NC) (NC) SANYO : QIP-100E ILC00202 Package Dimension (unit : mm) 3151 0.65 0.575 20.0 0.3 1.6 0.575 0.15 80 81 51 50 15.6 14.0 0.825 1 30 21.6 0.8 31 100 3.0max 1.6 17.2 0.65 0.825 23.2 0.1 2.7 0.8 SANYO : QIP-100E (FLP100) No.6710-2/20 LC868901/51 Pads Pin No. Pad No. name 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 CS RD WR RS CL2 M STB C65 C64 C63 C62 C61 C60 C59 C58 C57 C56 C55 C54 C53 C52 C51 C50 C49 C48 C47 C46 C45 C44 C43 C42 C41 C40 C39 C38 C37 C36 C35 C34 C33 C32 C31 C30 C29 C28 C27 C26 C25 C24 C23 Pad axis X µm Yµm -- 2113 -- 1645 -- 1950 -- 1645 -- 1788 -- 1645 -- 1625 -- 1645 -- 1463 -- 1645 -- 1300 -- 1645 -- 1138 -- 1645 -- 914 -- 1794 -- 752 -- 1794 -- 589 -- 1794 -- 427 -1794 -- 264 -- 1794 -- 102 -- 1794 61 -- 1794 223 -- 1794 386 -- 1794 548 -- 1794 711 -- 1794 873 -1794 1036 -- 1794 1198 -- 1794 1361 -- 1794 1523 -- 1794 1686 -- 1794 1848 -- 1794 2011 -- 1794 2173 -- 1794 2336 -- 1794 2498 -- 1794 2661 -- 1794 2690 -- 1482 2690 -- 1320 2690 -- 1157 2690 -- 995 2690 -- 832 2690 -- 670 2690 -- 507 2690 -- 345 2690 -- 182 2690 -- 20 2690 143 2690 305 2690 468 2690 630 2690 793 2690 955 2690 1118 2690 1280 2690 1443 2690 1605 Pin No. Pad No. name 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 -79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 --- C22 C21 C20 C19 C18 C17 C16 C15 C14 C13 C12 C11 C10 C9 C8 C7 C6 C5 C4 C3 C2 C1 CAP2 CAP1 VOT2 VOT1 VEE2 VEE1 NC V3 XV5 XV4 XV3 XV2 XV1 RES VDD OSC1 OSC2 VSS DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 NC NC Pad axis X µm Yµm 2478 1764 2315 1764 2153 1764 1990 1764 1828 1764 1665 1764 1503 1764 1340 1764 1178 1764 1015 1764 853 1764 690 1764 528 1764 365 1764 203 1764 40 1764 -- 122 1764 -- 285 1764 -- 447 1764 -- 610 1764 -- 772 1764 -- 935 1764 -- 1569 1617 -- 1732 1617 -- 1894 1617 -- 2057 1617 -- 2278 1617 -- 2441 1617 -- 2603 -- 2526 -- 2526 -- 2526 -- 2526 -- 2526 -- 2556 -- 2556 -- 2556 -- 2556 -- 2556 -- 2556 -- 2556 -- 2556 -- 2556 -- 2556 -- 2556 -- 2556 -- 2556 1617 1156 993 831 668 506 316 153 -- 9 -- 172 -- 334 -- 497 -- 659 -- 822 -- 984 -- 1147 -- 1309 -- 1472 -- 1634 Notes 1. Using for chip, the substrate must be shortened to VDD, or left open. 2. Ask the solder-soaking condition for QFP100E package. No.6710-3/20 LC868901/51 Pin function Pin name VSS VDD VEE1, 2 VOT1, 2 CAP1, 2 DB0 to DB7 RES CS RD WR RS Pin No. 90 87 78, 77 76, 75 74, 73 91 I/O -----I/O Description Negative power pin (-- ) Positive power pin (+) LCD power pins Power booster pins Capacitor connecting pins for power booster Data bus 98 86 1 2 3 4 Input Input Input Input Input CL2 M STB V3 XV1 to XV5 C1 to C65 5 6 7 80 85 to 81 72 to 8 Output Output Input Output Output Output Reset (active low) Chip select (active low) Read (active low) Write (active low) Register select RS=1 : instruction register RS=0 : data register LCD clock for data shifting LCD clock for synchronizing Stand-by (active low) Monitor pin for LCD power LCD power suppliers Common outputs for LCD display Pin form type DB0-4, 7 : C DB5, 6 : D B A A A A E E B F C1 C65 Block Diagram VOT1 LCD DRIVERS POWER BOOSTER OSC1 VOT2 CAP1 CAP2 OSCILLATOR OSC2 STB V3 RS CS RD WR LCD POWER CIRCUIT TIMING GENERATOR SYSTEM CLOCK 1 RES CL2 XV3 XV4 SYSTEM CLOCK 2 XV5 M VDD CONTRAST CONTROL CIRCUIT VSS XV1 XV2 VEE1 VEE2 MODE REGISTER CONTRAST CONTROL REGISTER DB0 DB1 DATA REGISTER TIME DIVISION REGISTER DB2 DB3 INSTRUCTION REGISTER DB4 DB5 DB6 DISPLAY NUMBER REGISTER DISPLAY PITCH REGISTER BUSY FLAG DB7 MODE REGISTER ILC00203 No.6710-4/20 LC868901/51 Pin forms A type B type C type VDD VDD VDD DATA IN IN IN / OUT VSS OUTPUT CONTROL VSS ILC00205 ILC00204 CS, RD, WR, RS pins ILC00206 RES, STB pins D type DB0 to DB4, DB7 E type F type VDD VDD DATA VDD OUT V1 OUT OUT OUTPUT CONTROL V4 VSS VSS V5 ILC00207 DB5, DB6 ILC00208 CL2, M ILC00209 C1 to C65 No.6710-5/20 LC868901/51 1. Absolute Maximum Ratings at Ta=25°C, VSS=0V Parameter Supply voltage Input voltage Output voltage High-level output current Low-level output current Maximum power dissipation Operating temperature limits Storage temperature limits Symbol Pins Conditions VDD MAX VDD VI(1) CS, RD, WR, RS, RES VI(2) DB0 to DB7 VDD[v] min. -- 0.3 -- 0.3 Ratings typ. max. +7.0 VDD+0.3 At input mode -- 0.3 VDD+0.3 At output mode VDD-- 21 VEE2-- 0.3 -- 0.3 VDD+0.3 VDD+0.3 VDD+0.3 -- 0.3 VDD-- 21 VDD+0.3 VDD+0.3 unit V VI(3) VO(1) VO(2) VEE1, VEE2 C1 to C65 DB0 to DB7 VO(3) VO(4) ∑IOAH M, CL2 VOT1, VOT2, CAP1, CAP2 C1 to C65 The total all pins ∑IOAL C1 to C65 The total all pins 30 mA Pdmax QFP100E Ta= -- 30 to + 70°C 200 mW °C -- 25 mA Topg -- 30 70 Tstg -- 55 150 2. Recommended Operating Limits at Ta= -- 30°C to +70°C, VSS=0V Parameter Symbol Operating supply VDD voltage limits LCD power supply VEE voltage limits Input high voltage VIH(1) Pins Conditions VDD VEE1, VEE2 DB0 to DB7 VIH(2) CS, RD, WR, RS VIH(3) RES (schmitt), STB (schmitt) DB0 to DB7 Input low voltage VIL(1) VIL(2) CS, RD, WR, RS VIL(3) RES (schmitt), STB (schmitt) OSC1, OSC2 Oscillation FRC frequency limits VDD [V] 4.5 to 6.0 2.5 to 4.5 At input mode 4.5 to 6.0 2.5 to 4.5 4.5 to 6.0 2.5 to 4.5 4.5 to 6.0 2.5 to 4.5 At input mode 4.5 to 6.0 2.5 to 4.5 4.5 to 6.0 2.5 to 4.5 4.5 to 6.0 2.5 to 4.5 •RC oscillation 2.5 to 6.0 •Fig. 1 OSC1 min. 2.5 -- 2VDD -- VDD 2.2 0.75VDD 2.2 0.75VDD 0.75VDD 0.75VDD 0 0 0 0 0 0 20 Ratings typ. max. 6.0 unit V VDD VDD VDD VDD VDD VDD VDD VDD 0.8 0.25VDD 0.8 0.25VDD 0.25VDD 0.25VDD 500 kHz OSC2 Rext Cext Fig.1 RC-oscillator circuit ILC00210 No.6710-6/20 LC868901/51 3. Electrical Characteristics at Ta= -- 30°C to +70°C Parameter Output high voltage Output low voltage Pull-up resistance Symbol Pins VOH(1) DB80 to DB7 VOH(2) M, CL2 VOL(1) DB0 to DB7 VOL(2) M, CL2 RPU(1) DB0 to DB7 RPU(2) CS, RD, WR, RS, RES, STB C1 to C65 Drop voltage between VDD and Ci (i : 1 to 65) VD(1) Drop voltage between VX and Ci (X : 1, 4) (i : 1 to 65) VD(2) Drop voltage between VX and Ci (X : 1, 4) (i : 1 to 65) VD(3) C1 to C65 Boosted voltage VOT1 •VOT1 •Fig. 2 VOT2 C1 to C65 •VOT2 •Fig. 3 Conditions VDD [V] min. 4.5 to 6.0 VDD-- 1.0 •output mode •IOH= -- 1mA •output mode 2.5 to 6.0 VDD-- 0.5 •IOH= -- 0.1mA IOH= -- 0.4mA 4.5 to 6.0 VDD-- 0.4 IOH= -- 0.1mA 2.5 to 6.0 VDD-- 0.5 •output mode 4.5 to 6.0 •IOL=+0.6mA •output mode 2.5 to 6.0 •IOH=+0.1mA IOL=+0.4mA 4.5 to 6.0 IOL=+0.1mA 2.5 to 6.0 •input mode 4.5 to 6.0 150 •VIN=0V •input mode 2.5 to 4.5 300 •VIN=0V VIN=0V 4.5 to 6.0 150 VIN=0V 2.5 to 4.5 300 •-- 100µA at each 4.5 to 6.0 Ci pin •VDD--VEE2=11V •-- 15µA at each 2.5 to 6.0 Ci pin •VDD--VEE2=11V •-- 100µA at each 4.5 to 6.0 Ci pin •VDD--VEE2=11V •-- 15µA at each 2.5 to 6.0 Ci pin •VDD--VEE2=11V •+100µA at each 4.5 to 6.0 -- 150 Ci pin •VDD--VEE2=11V •+15µA at each 2.5 to 6.0 -- 120 Ci pin •VDD--VEE2=11V Load current 5.0 =500µA Load current =800µA Load current 2.9 =100µA Load current =200µA Load current 5.0 =500µA Load current =800µA Ratings typ. max. unit V 0.4 0.4 500 0.4 0.5 900 750 1500 500 750 900 1500 150 kΩ mV 120 150 mV 120 mV -- 4.5 V -- 4.0 -- 2.6 V -- 2.3 -- 8.0 V -- 6.0 No.6710-7/20 LC868901/51 Parameter Symbol Pins Hysterisis voltage VHIS XV1 output voltage VV1 RES, STB XV1 XV2 output voltage VV2 XV2 XV3 output voltage VV3 XV3 XV4 output voltage VV4 XV4 LCD power current •VEE1, VEE2 •1 / 5 bias •VEE1, VEE2 •1 / 7 bias •VEE1, VEE2 •1 / 9 bias •VEE1, VEE2 •CCR=01H •VEE1, VEE2 •CCR=02H •VEE1, VEE2 •CCR=04H •VEE1, VEE2 •CCR=08H •VEE1, VEE2 •CCR=10H ILCD1 ILCD2 ILCD3 Contrast current ILC1 ILC2 ILC3 ILC4 ILC5 Operation current IDD(1) dissipation Stand-by current dissipation IDD(2) Conditions Ratings unit VDD [V] min. typ. max. 2.5 to 6.0 0.1VDD V 2.5 to 6.0 0.75VDD 0.80VDD 0.85VDD V •LCD ON •1 / 5 bias •XV5=0V 2.5 to 6.0 0.55VDD 0.60VDD 0.65VDD •LCD clock frequency=0Hz 2.5 to 6.0 0.35VDD 0.40VDD 0.45VDD •Fig. 4 2.5 to 6.0 0.15VDD 0.20VDD 0.25VDD •LCD ON •VEE1=OPEN •VEE2=0V •XV1-XV5=OPEN •Fig. 5 •CCR0-4=0 •LCD ON •VEE1=OPEN •VEE2=-- 3V •XV5=0V •Fig. 6 •FRC=500kHz •LCD OFF •Fig. 7 •FRC=0Hz •LCD OFF •Fig. 7 5.0 2.9 5.0 2.9 5.0 2.9 5.0 2.9 5.0 2.9 5.0 2.9 5.0 2.9 5.0 2.9 4.5 to 6.0 2.5 to 4.5 4.5 to 6.0 2.5 to 4.5 25 15 18 10 14 8 750 750 370 370 200 200 100 100 50 50 50 29 35.7 20.7 27.8 16 1000 1000 500 500 250 250 125 125 62 62 200 100 100 60 70 40 56 32 1500 1500 750 750 400 400 200 200 100 100 400 300 µA 0.05 0.02 30 20 µA µA µA [Notes] The specifications above are for a die mounted in a QFP100E type package. However, we ship this product as a die only, not a package chip. Therefore, the operational characteristics may vary depending on the user's packaging techniques. No.6710-8/20 LC868901/51 VDD VDD OPEN OPEN VDD XV1 VDD XV5 V3 CAP1 V3 CAP2 OPEN VOT1 VSS XV5 CAP1 CAP2 V XV1 OSC1 OSC2 OPEN VOT1 VEE1 VEE2 VOT2 VSS V Fig.2 Measurement circuit for boosted voltage (1) OSC1 OSC2 VEE1 VEE2 Fig.3 Measurement circuit for boosted voltage (2) ILC00211 ILC00212 VDD VDD OPEN VDD OPEN XV1 CAP1 CAP2 VOT1 VOT2 VEE1 VEE2 VSS VDD XV4 OPEN V3 OPEN XV1 XV5 OPEN VOT1 VOT2 XV5 OSC1 VSS OSC2 V3 CAP1 CAP2 OSC1 OSC2 VEE1 VEE2 A V Fig.4 Measurement circuit for XV1 to XV4 Fig.5 Measurement circuit for LCD power current ILC00213 ILC00214 VDD VDD OPEN VDD OPEN XV1 A XV4 OPEN CAP1 CAP2 VOT1 VOT2 VSS VDD V3 OSC1 OSC2 XV5 VEE2 XV1 XV5 V3 CAP1 OPEN VEE1 OPEN CAP2 VOT1 VOT2 VSS OPEN VEE1 VEE2 OSC1 OSC2 A -- 3V Fig.6 Measurement circuit for contrast current Fig.7 Measurement circuit for current dissiation ILC00215 ILC00216 No.6710-9/20 LC868901/51 AC Characteristics at Ta= -- 30°C to +70°C • Reading cycle tCYC1 tPW1 RD tAS1 tR1 tAH1 CS, RS tDDR1 tF1 tDHR1 DB0 to 7 ILC00217 • Writing cycle tCYC2 tPW1 WR tR1 tAH2 tAS2 CS, RS tDSW1 tF1 tDHW1 DB0 to 7 ILC00218 No. 1 2 Item RD, WR cycle time 3 RD pulse width WR pulse width Rise / fall time 4 Address set-up time 5 Address hold time Symbol Pins and Conditions tCYC1 RD tCYC2 WR tPW1 RD WR RD tR1, tF1 tAS1 CS, RS, RD tAS2 CS, RS, WR tAH1 CS, RS, RD tAH2 CS, RS, WR 6 Data delay time tDDR1 RD, DB0 to DB7, CL=50pF 7 Data hold time tDHR1 RD, DB0 to DB7, CL=50pF 8 Data set-up time tDSW1 WR, DB0 to DB7, CL=50pF 9 Data hold time tDHW1 WR, DB0 to DB7, CL=50pF VDD [V] 4.5 to 6.0 2.5 to 4.5 4.5 to 6.0 2.5 to 4.5 4.5 to 6.0 2.5 to 4.5 4.5 to 6.0 2.5 to 4.5 4.5 to 6.0 2.5 to 4.5 4.5 to 6.0 2.5 to 4.5 4.5 to 6.0 2.5 to 4.5 4.5 to 6.0 2.5 to 4.5 4.5 to 6.0 2.5 to 4.5 4.5 to 6.0 2.5 to 4.5 4.5 to 6.0 2.5 to 4.5 4.5 to 6.0 2.5 to 4.5 Value min. max. (500) unit ns (500) ns (220) ns (20) ns (40) ns (40) ns (10) ns (10) ns (120) ns (20) ns (60) ns (10) ns No.6710-10/20 LC868901/51 Applications 1. 64✕160-dot display LCD powers CL2 WR RD RS CS DB LCD powers M CL2 WR RD RS CS LC868900 DB LC868900 LCD powers LC868901 M SEG CL2 SEG WR COM RD 81-160 RS CS DB 1-80 M LCD panel 64x160 dots 1-64 P0 P46 P47 LC868901 ILC00219 2. 65✕160-dot display LCD panel 65x160 dots 1-65 LCD powers CL2 WR RD RS CS DB LCD powers M CL2 WR RD RS CS DB LCD powers LC868910 M LC868910 CL2 LC868901 WR SEG RD SEG M 81-160 COM RS CS DB 1-80 P0 P46 P47 LC868901 ILC00220 No.6710-11/20 LC868901/51 Block Descriptions 1. Interfacing block The interfacing block is composed by an instruction register and five data registers. The instruction register selects the data register to transfer the following data. a. Instruction register The instruction register specifies five kinds of the data registers and holds the data until other instruction data is set to the instruction register. Also, this instruction register can be read a busy flag. • instruction setting conditions 1. Set CS to ‘0’ (low level). for chip selecting 2. Set WR to ‘0’. for write operating 3. Set RS to ‘1’. for instruction specifying 4. Set DB to the instruction data b. Data registers The five data-registers specify the parameters for displaying LCD, which are five of mode, display pitches, display number, time division, and contrast. • data setting conditions 1. Set CS to ‘0’ (low level). for chip selecting 2. Set WR to ‘0’. for write operating 3. Set RS to ‘0’. for parameter specifying 4. Set DB to the parameter data Note that the instruction and data can be written while the RC oscillation runs. Busy flag should be set during writing to the data register. The instruction data, code, is shown below. Specified register Mode register Display Pitch register Display Number register Time Division register Contrast Control register Read busy flag R/W 0 0 0 0 0 0 0 0 0 0 1 RS 1 0 1 0 1 0 1 0 1 0 1 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Notes 0 0 0 0 0 0 0 0 addressing mode data data setting 0 0 0 0 0 0 0 1 addressing VOPON VRSEL Dp - 1 data setting 0 0 0 0 0 0 1 0 addressing Dn - 1 data setting 0 0 0 0 0 0 1 1 addressing 0 0 Nx - 1 data setting 0 0 0 0 0 1 0 0 addressing BIAS1 BIAS0 BOOST contrast data data setting Busy no meaning data reading oscillation circuit 2. Timing control block The timing control block is composed by the oscillator circuit and the timing generator circuit. a. Oscillator Resistor and capacitor must be mounted externally. The oscillator should be stop in stand-by state. See later chapter for more details. b. Timing generator OSC1 The timing generator generates two system system clock1 S1 generator clocks and the several signals for LCD displaying. S1, system clock 1, runs for reading, writing and OSC2 system clock2 transferring data when the LC868901 is not in S2 generator RESET stand-by state and S2, system clock 2, runs while oscillation control the LCD controller works. STB mode register 7 6 5 4 3 2 1 0 ILC00221 No.6710-12/20 LC868901/51 CL2, M for LCD displaying should be generated to the LC868900 segment driver. In stand-by state, all the generated signals freeze. 3. Busy flag Busy flag is outputted to DB7 when reading operation is established with RS = 1. The busy flag should be set to ‘1’ during writing to the data register, not the instruction register. When the writing operation is completed, the busy flag should be reset to ‘0’. When the busy flag is set to ‘1’, new parameter data cannot be written. Thus, write the data after reading the busy flag and making sure that it is ‘0’. • busy-flag reading condition 1. Set CS to ‘0’ (low level). for chip selecting 2. Set RD to ‘0’. for read operating 3. Set RS to ‘1’. for busy-flag reading Reading operation need not to set the instruction register. Register Busy R/W 1 RS 1 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Busy no meaning 4. Data registers a. Mode register Write code ‘00H’ into the instruction register and specify the mode register. Register Instruction Mode R/W 0 0 RS 1 0 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 0 0 0 0 -mode data Mode0 (bit0 of mode register) LCD controller operation Mode0=1 LCD controller starts to work. (S1 and S2 run) Mode0=0 LCD controller stops. (S1 runs) Mode0=0 when resetting or at stand-by state Mode1 (bit1 of mode register) LCD display Mode1=1 LCD display enable (ON) Mode1=0 LCD display disable (OFF) Mode1=0 when resetting or at stand-by state Mode2 (bit2 of mode register) Stand-by Mode2=1 Stand-by state Mode2=0 Operation state Mode3 (bit3 of mode register) Scanning direction Mode3=1 C1 to C65 in 1 / 65 duty Mode3=0 C65 to C1 in 1 / 65 duty Mode3=0 when resetting No.6710-13/20 LC868901/51 • Waveforms in case of C1 to C65 VDD V1 V1 C O M 1 V4 V4 V5 V5 VDD V1 V1 V1 C O M 2 V4 V4 V1 V4 V5 V5 VDD V1 V1 V1 C O M 3 V4 V4 V1 V4 V5 V5 VDD VDD V1 V1 COM65 V4 V5 ILC00222 • Waveforms in case of C65 to C1 VDD V1 V1 C O M 6 5 V4 V4 V5 V5 VDD V1 V1 V1 C O M 6 4 V4 V4 V1 V4 V5 V5 VDD V1 V1 V1 C O M 6 3 V4 V4 V1 V4 V5 V5 VDD VDD V1 V1 COM1 V4 V5 ILC00223 Mode4 to Mode6 (bit4 to bit6 of mode register) Time division The following table shows the time division value. Mode6 0 0 0 0 1 1 1 1 Mode5 0 0 1 1 0 0 1 1 Mode4 0 1 0 1 0 1 0 1 OSC1 OSC2 oscillation circuit Time Division 1/1 1/2 1/4 1/8 1 / 16 1 / 32 1 / 64 1 / 128 divider reset Multiplexer 1 / 1 to 1 / 128 clock for LCD display ILC00224 Note that Mode1 should be set to ‘1’ after setting the required LC868901-registers and the registers and RAM data of the equipped LC868900. Next shows the setting sequence for displaying ON. 1. Set Mode0 to ‘1’ for starting the controller operation. 2. Set the registers of the LC868901/LC868900 and RAM data of the LC868900. 3. Set Mode1 to ‘1’ for displaying ON. Next shows the sequence for displaying OFF. 1. Set Mode1 to ‘0’ for displaying OFF. 2. Set Mode0 to ‘0’ for stopping the controller operation. No.6710-14/20 LC868901/51 b. Horizontal pitch register Write code ‘01H’ into the instruction register and specify the horizontal pitch register. The horizontal pitch register specifies the horizontal pitch, the LCD power output and ladder resistor value. Register Instruction Pitch R/W 0 0 RS DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 1 0 0 0 0 0 0 0 1 0 VOPON VRSEL ---Dp-1 • VOPON specifies the LCD power source. When VOPON=1, the LCD powers, XV1 to XV5, are provided through the OP-amps. When VOPON=0, the LCD powers are provided by the ladder resistors directly. • VRSEL specifies resistance of the ladder resistors. See the following table. When VRSEL=1, all resistance of the ladder resistors is specified to 4kohms. When VRSEL=0, all resistance is specified to 20kohms. • Dp indicates how many bits from the LC868900 RAM data appear in an 1-byte display. Dp must be set one of the following three values. Dp 6 7 8 DB2 1 1 1 DB1 0 1 1 DB0 1 0 1 Display pitch 6 7 8 RVD1 VRSEL 0 1 4kΩ 20kΩ V2 RV12 20kΩ 4kΩ V3 RV23 20kΩ 4kΩ V4 RV34 20kΩ 4kΩ RV45 20kΩ 4kΩ RVD1 V1 RV12 RV23 RV34 RV45 V5 ILC00225 Note that RV23 varies according to the specified bias. (c.f. RV23=60k ohms at VRSEL = 0 in 1 / 7-bias specification) c. Horizontal number register Write code ‘02H’ into the instruction register and specify the horizontal number register. The horizontal number register specifies the horizontal display number. Register Instruction Number R/W 0 0 RS 1 0 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 0 0 1 0 Dn - 1 • Dn indicates the number of bytes in the horizontal direction. • N, the total number of dots positioned horizontally on the screen, is given by the following formula. N=Dp * Dn (N≤80) • Numbers in range 2 to 10 in decimal can be set as Dn. d. Time division register Write code ‘03H’ into the instruction register and specify the time division register. The time division register specifies the display duty. Register Instruction Division R/W 0 0 RS 1 0 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 0 0 1 1 0 Nx - 1 No.6710-15/20 LC868901/51 • Nx represents the number of the time divisions. • Consequently, 1 / Nx value means the display duty. • Numbers in range 2 to 65 in decimal can be set as Nx. e. Contrast control register Write code ‘04H’ into the instruction register and specify the contrast control register. The contrast control register specifies the contrast resistor value, the display bias and the power booster. Register Instruction Contrast R/W 0 0 RS 1 0 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 1 0 0 0 BIAS1 BIAS0 BOOST CONTRAST • CONTRAST(CCR4-0) specifies in 32-step contrast resistor value. See the following table. CCR4 0 0 0 CCR3 0 0 0 CCR2 0 0 0 CCR1 0 0 1 CCR0 0 1 0 Value 0 1R 2R •• • •• • •• • •• • •• • •• • 1 1 1 1 1 1 1 1 0 1 30R 31R V5 • External contrast control available 1. CONTRAST=0for setting the contrast control resistance to 0 ohm. 2. Variable Resistor must be connected between VEE2 and the negative LCD power to adjust the LCD contrast. • BOOST specifies the LCD power booster function. When BOOST = 1, the double power booster (doubler) functions. When BOOST = 0, the triple power booster (tripler) functions. (a) Tripler BOOST=0 CCR0 1R CCR1 2R CCR2 4R CCR3 8R CCR4 16R VEE1 MODE1 VEE2 (b) Doubler BOOST=1 CAP1 CAP1 CAP2 CAP2 VDD VDD VOT1 VOT1 VOT2 VOT2 VEE2 VEE2 ILC00227 ILC00226 ILC00228 See 6. LCD power unit • BIASes specify the displayed LCD bias. BIAS1 0 0 1 1 BIAS0 0 1 0 1 bias 1/5 1/5 1/7 1/9 No.6710-16/20 LC868901/51 C1 C2 C3 C4 C5 C6 C7 C8 C9 C56 C57 C58 C59 C60 C61 C62 C63 C64 C65 5. LCD driver unit Next shows the common driver block diagram. VDD V1 common V4 dr ivers V5 Alternating signal to LCD common driver shift clock shift r egister frame signal MODE3=1 MODE3=0 ILC00229 Common waves (MODE3=1, 1 / 65 duty) 1 2 3 4 64 65 1 2 3 4 64 65 1 2 3 4 C L 2 M VDD V1 V1 C O M 1 V4 V4 V5 V5 VDD V1 V1 V1 C O M 2 V4 V4 V1 V4 V5 V5 VDD V1 V1 V1 C O M 3 V4 V4 V1 V4 V5 V5 VDD VDD V1 V1 COM65 V4 V5 ILC00230 Scanning direction can be set by MODE3, bit 3 of mode register. MODE3=1 from C1 to C65 MODE3=0 from C65 to C1 Ex.1. MODE3=1 and 1 / 64 duty Scanning direction C1 to C64 Available commons C1 to C64 Nonuse commons C65 Ex.2. MODE3=0 and 1 / 32 duty Scanning direction C65 to C34 Available commons C34 to C65 Nonuse commons C1 to C33 Ex.3. MODE3=0 and 1 / 64 duty Scanning direction C65 to C2 Available commons C2 to C65 Nonuse commons C1 No.6710-17/20 LC868901/51 6. LCD power unit The LCD power unit provides the LCD powers to the attached drivers according to the specified bias. XV1 to XV5 pins are used. • Bias BIASes specify the displayed LCD bias. BIAS1 0 0 1 1 BIAS0 0 1 0 1 bias 1/5 1/5 1/7 1/9 • LCD powers The voltage of VEE2 must be set according to the specified duty or the specification of an LCD panel. The following four connections can be allowed. 1. VEE2=VSS LC868901 1 / 16 duty or less (according to the LCD-panel characteristics) VDD CAP1 VDD -- VSS ≥ 5V CAP2 OPEN OPEN VSS VOT1 OPEN VEE1 VOT2 VEE2 ILC00231 2. VEE2=VOT1 The power booster provides two times of (VDD - VSS) voltage to VOT1. The power booster must be attached two a capacitors. The boosted powers are supplied to the following blocks. •LCD drivers •Ladder resistors •LCD contrast controller The LCD-drive current is specified by the capacitance of the attached capacitor. OPEN [Notes] Select doubler on program (BOOST = 1) when using VOT1.Never use VOT2 when selecting doubler. LC868901 VDD CAP1 CAP2 VSS VOT1 VEE1 VOT2 OPEN VEE2 ILC00232 No.6710-18/20 LC868901/51 3. VEE2=VOT2 Set BOOST to ‘0’ to use the tripler function. The power booster provides three times of (VDD-- VSS) voltage to VOT2. The power booster must be attached three capacitors. The boosted powers are supplied to the following blocks. •LCD drivers •Ladder resistors •LCD contrast controller The LCD-drive current is specified by the capacitance OPEN of the attached capacitors. LC868901 VDD CAP1 CAP2 VSS VOT1 VEE1 VOT2 VEE2 ILC00233 4. VEE2 supplied by the external power unit The external power unit must be attached between VSS and VEE2 if the LCD display voltage must be provided to the VDD-- VSS voltage or more without using builtin power booster. See the following figure. Set the external voltage as below. 0 v > [ external power supply ] > -- 3 x (VDD-- VSS) external power LC868901 VDD CAP1 OPEN CAP2 OPEN VOT1 OPEN VOT2 OPEN VSS VEE1 OPEN VEE2 ILC00234 • Contrast control The LCD contrast can be specified by CCR, which is allowed to 32-step contrast. If more than 32-step contrast must be needed, attach and adjust a variable resistor between VEE2 and the specified power supply. See Contrast control register. VDD V1 V2 V3 V4 V5 CCR0 1R CCR1 2R CCR2 4R CCR3 8R CCR4 16R VEE1 MODE1 VEE2 ILC00235 No.6710-19/20 LC868901/51 7. Stand-by function Stand-by function is prepared to reduce the dissipation current while LCD off. ‘Stand-by’ means all the LC868901 function freeze. Thus, in stand-by state, the LCD controller and drivers stop operation. Two ways to make the LC868901 stand-by is prepared. 1) Set MODE2 (bit2 of mode register) to ‘1’. 2) Supply STB to low. Also, two ways to release stand-by is prepared. 1) Reset Supply RES to low. It makes the LC868901 reset. Supply RES to high to make the LC868901 run. 2) Reading Read the target LC868901. (i.e., CS = 0 and RD = 0) [Notes] DB7 should be set output state at reading. So, ports connected to DB7 of the LC868901 must be set to the input state. 8. Reset function Reset to initialize when the power is turned on. Initialized value and state 1. busy flag reset 2. oscillator operate 3. stand-by release 4. LCD controller stop 5. LCD display off 6. LCD power XV1 to XV5=VDD, VEE1=VDD 7. scanning direction C65 to C1 8. power booster stop 9. LCD power source ladder resisters directly Note that resetting may make all bits of each register except MODE3 to MODE0 change during the operation. Re-set all of registers to re-display or re-operate. Specifications of any and all SANYO products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer's products or equipment. To verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer's products or equipment. SANYO Electric Co., Ltd. strives to supply high-quality high-reliability products. However, any and all semiconductor products fail with some probability. It is possible that these probabilistic failures could give rise to accidents or events that could endanger human lives, that could give rise to smoke or fire, or that could cause damage to other property. When designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. Such measures include but are not limited to protective circuits and error prevention circuits for safe design, redundant design, and structural design. In the event that any or all SANYO products(including technical data,services) described or contained herein are controlled under any of applicable local export control laws and regulations, such products must not be expor ted without obtaining the expor t license from the authorities concerned in accordance with the above law. No part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise, without the prior written permission of SANYO Electric Co., Ltd. Any and all information described or contained herein are subject to change without notice due to product/technology improvement, etc. When designing equipment, refer to the "Delivery Specification" for the SANYO product that you intend to use. Information (including circuit diagrams and circuit parameters) herein is for example only ; it is not guaranteed for volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties. This catalog provides information as of December, 2000. Specifications and information herein are subject to change without notice. PS No.6710-20/20