1M x 32 FLASH MODULE PUMA 68F32006/A-90/12/15 Issue 4.2 : December 1999 Elm Road, West Chirton, NORTH SHIELDS, Tyne & Wear NE29 8SE, England Tel. +44 (0191) 2930500 Fax. +44 (0191) 2590997 Description The PUMA 68F32006 is a high density 32Mbit CMOS 5V Only FLASH memory organised as 1M x 32 in a JEDEC 68 pin surface mount PLCC, with read access times of 90, 120, and 150ns. The output width is user configurable as 8 , 16 or 32 bits using four Chip Selects (CE1~4) for optimum application flexibility. The module incorporates Embedded Algorithms for Program and Erase with Sector architecture (64K sector) and supports full chip erase. The device also features hardware sector protection, which disables both program and erase operations in any of the 64 sectors on the module. A version 'A' with four independant write enables (WE1-4) is available. Block Diagram (see page 24 for 'A' version) Pin Definition (see page 24 for 'A' version) A0~A19 OE WE D0 D1 D2 D3 D4 D5 D6 D7 GND D8 D9 D10 D11 D12 D13 D14 D15 NC A0 A1 A2 A3 A4 A5 CS3 GND CS4 WE A6 A7 A8 A9 A10 Vcc Features • Fast Access Times of 90/120/150 ns. • Output Configurable as 32 / 16 / 8 bit wide. • Commercial, Industrial, or Military (Restricted) grade. • Automatic Write/Erase by Embedded Algorithm - end of Write/Erase indicated by DATA Polling and Toggle Bit. • Flexible Sector Erase Architecture - 64K byte sector size, with hardware protection of sector groups. • Single Byte Program of 7µs (Typ.) • Erase/Write Cycle Endurance 100,000 (Min.) - E variant. 1M x 8 1M x 8 1M x 8 1M x 8 FLASH FLASH FLASH FLASH PUMA 68F32006 D16 D17 D18 D19 D20 D21 D22 D23 GND D24 D25 D26 D27 D28 D29 D30 D31 Vcc A11 A12 A13 A14 A15 A16 CS1 OE CS2 A17 NC NC NC A18 GND A19 CS1 CS2 CS3 CS4 D0~7 D8~15 D16~23 D24~31 9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61 10 60 11 59 12 58 13 57 14 56 15 55 16 54 VIEW 17 53 FROM 18 52 19 51 ABOVE 20 50 21 49 22 48 23 47 24 46 25 45 26 44 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 A0-A19 CE1-4 OE GND Address Input Chip Enables Output Enable Ground Pin Functions D0-D31 WE Vcc Data Inputs/Outputs Write Enable (WE1-4 for 'A' version) Power (+5V) PUMA 68F32006/A-90/12/15 Issue 4.2 : December 1999 Absolute Maximum Ratings (1) max -2.0 to +7 -2.0 to +7 -2.0 to +13.5 -65 to +125 Voltage on any pin w.r.t. Gnd Supply Voltage (2) Voltage on A9 w.r.t. Gnd (3) Storage Temperature Notes : (1) (2) (3) unit V V V °C Stresses above those listed may cause permanent damage to the device. This is a stress rating only and functional operationof the device at those or any other conditions above those indicated in the operational sections of this specification is not implied. Minimum DC voltage on any input or I/O pin is -0.5V. Maximum DC voltage on output and I/O pins is Vcc+0.5V During transitions voltage may overshoot by +/-2V for upto 20ns Minimum DC input voltage on A9 is -0.5V during voltage transitions, A9 may overshoot Vss to -2V for periods of up to 20ns, maximum DC input voltage in A9 is 12.5V which may overshoot to 14.0V for periods up to 20ns Recommended Operating Conditions Parameter Supply Voltage Input High Voltage Input Low Voltage Operating Temperature VCC VIH VIL TA TAI TAM min 4.5 2.0 -0.5 0 -40 -55 typ 5.0 - max 5.5 VCC+0.5 VCC+0.8 70 85 115 unit V V V °C O C (-I suffix) O C (-M suffix) DC Electrical Characteristic (TA=-55°C to +125°C,VCC=5V ± 10%) Parameter Symbol Test Condition I/P Leakage CurrentAddress, OE, WE ILI1 A9 Input Leakage Current ILI2 Other Pins ILI3 Output Leakage Current ILO 32 bit ICCO32 VCC Operating Current 16 bit ICCO16 8 bit ICCO8 VCC=VCC max, VIN=0V or VCC VCC Program/Erase Current VCC=VCC max, A9=12V VCC=VCC max, VIN=0V or VCC VCC=VCC max, VOUT=0V or VCC CE=VIL(1), OE=VIH, IOUT=0mA, f=6MHz As above As above 32 bit 16 bit 8 bit ICCP32 ICCP16 ICCP8 Programming in Progress Standby Supply Current Autoselect / Sector Protect Voltage Output Low Voltage Output High Voltage Low VCC Lock-Out Voltage ISB1 VID VOL VOH1 VLKO VCC=VCC max, CE=VIH(1) OE = VIH As above As above VCC = 5.0V IOL=12mA. VCC = VCC min. IOH=-2.5mA. VCC = VCC min. min typ max Unit - - ±4 200 ±1 ±4 120 62 33 µA µA µA µA mA mA mA - - 240 122 63 mA mA mA 11.5 2.4 3.2 - 4 12.5 0.45 4.2 mA V V V V Notes (1) CE above are accessed through CE1-4. These inputs must be operated simultaneoulsy for 32 bit operation, in pairs in 16 bit mode and singly for 8 bit mode. 2 PUMA 68F32006/A-90/12/15 Issue 4.2 : December 1999 Capacitance (TA=25°C,f=1MHz) Parameter Symbol Test Condition Input CapacitanceAddress, OE, WE Other pins CIN1 CIN2 VIN=0V VIN=0V Output Capacitance COUT32 VOUT=0V 32 bit typ max Unit - 35 14 pF pF - 54 pF Note: These parameters are calculated, not measured. AC Test Conditions * Input pulse levels : 0.0V to 3.0V * Input rise and fall times : 5 ns * Input and output timing reference levels : 1.5V * VCC = 5V +/- 10% * Module tested in 32 bit mode I/O Pin 166 Ω 1.76V 30pF 3 PUMA 68F32006/A-90/12/15 Issue 4.2 : December 1999 AC OPERATING CONDITIONS Read Cycle Parameter Symbol min 90 90 typ max - Unit ns Read Cycle Time t RC Address to output delay tACC - - 90 ns Chip enable to output tCE - - 90 ns Output enable to output tOE - - 40 ns Output enable to output High Z tDF - - 20 ns Output hold time from address tOH 0 - - ns CE or OE whichever occurs first Parameter Symbol 120 typ max - Read Cycle Time t RC Address to output delay tACC - - 120 - - 150 ns Chip enable to output tCE - - 120 - - 150 ns Output enable to output tOE - - 50 - - 55 ns Output enable to output High Z tDF - - 30 - - 35 ns Output hold time from address tOH 0 - - 0 - - ns CE or OE whichever occurs first 4 min 150 150 typ max - min 120 Unit ns PUMA 68F32006/A-90/12/15 Issue 4.2 : December 1999 Write/Erase/Program Parameter Symbol min 90 typ max unit Write Cycle time (2) tWC 90 - - ns Address Setup time tAS 0 - - ns Address Hold time tAH 45 - - ns Data Setup Time tDS 45 - - ns Data hold Time tDH 0 - - ns Output Enable Setup Time tOES 0 - - ns Read Recover before Write tGHWL 0 - - ns CE setup time tCE 0 - - ns CE hold time tCH 0 - - ns WE Pulse Width tWP 45 - - ns WE Pulse Width High tWPH 20 - - ns Byte Programming operation tWHWH1 - 8 - µs Sector Erase operation (1) tWHWH2 - 1 15 sec tVCS 50 - - µs min 120 typ max min 150 typ max unit Vcc setup time (2) Parameter Symbol Write Cycle time (2) tWC 120 - - 150 - - ns Address Setup time tAS 0 - - 0 - - ns Address Hold time tAH 50 - - 50 - - ns Data Setup Time tDS 50 - - 50 - - ns Data hold Time tDH 0 - - 0 - - ns Output Enable Setup Time tOES 0 - - 0 - - ns Read Recover before Write tGHWL 0 - - 0 - - ns CE setup time tCE 0 - - 0 - - ns CE hold time tCH 0 - - 0 - - ns WE Pulse Width tWP 50 - - 50 - - ns WE Pulse Width High tWPH 20 - - 20 - - ns tWHWH1 - 8 - - 8 - µs tWHWH2 - 1 15 - 1 15 sec tVCS 50 - - 50 - - µs Byte Programming operation Sector Erase operation Vcc setup time (2) (1) Notes: (1) This does not include the preprogramming time. (2) Not 100% tested. 5 PUMA 68F32006/A-90/12/15 Issue 4.2 : December 1999 Write/Erase/Program Alternate CE controlled Writes Parameter Symbol min 90 typ max unit Write Cycle time (2) Address Setup time tWC tAS 90 0 - - ns ns Address Hold time tAH 45 - - ns Data Setup Time tDS 45 - - ns Data hold Time tDH 0 - - ns Output Enable Setup Time tOES 0 - - ns Read Recover before Write tGHEL 0 - - ns WE setup time tWS 0 - - ns WE hold time tWH 0 - - ns CE Pulse Width tCP 45 - - ns CE Pulse Width High tCPH 20 - - ns tWHWH1 - 8 - us tWHWH2 - 1 15 sec tVCS - 50 - us min 120 typ max min 150 typ max unit Programming operation Sector Erase operation (1) Vcc setup time (2) Parameter Symbol Write Cycle time (2) Address Setup time tWC tAS 120 0 - - 150 0 - - ns ns Address Hold time tAH 50 - - 50 - - ns Data Setup Time tDS 50 - - 50 - - ns Data hold Time tDH 0 - - 0 - - ns Output Enable Setup Time tOES 0 - - 0 - - ns Read Recover before Write tGHEL 0 - - 0 - - ns WE setup time tWS 0 - - 0 - - ns WE hold time tWH 0 - - 0 - - ns CE Pulse Width tCP 50 - - 50 - - ns CE Pulse Width High tCPH 20 - - 20 - - ns tWHWH1 - 8 - - 8 - us tWHWH2 - 1 15 - 1 15 sec tVCS - 50 - - 50 - us Programming operation Sector Erase operation Vcc setup time (2) (1) Note: (1) Does not include pre-programming time. (2) Not 100% tested. 6 PUMA 68F32006/A-90/12/15 Issue 4.2 : December 1999 AC Waveforms for Read Operation t RC Addresses Stable Addresses t ACC CE t DF t OE OE t OH t CE WE High Z Outputs High Z Output Valid AC Waveforms Program Data Polling Address 5555H PA tWC t AS PA tAH tRC CE t GHWL OE tWP tWHP tWHWH1 WE tOE tCS tDF t DH DATA A0H PD DQ7 DDOUT OUT tDS tCE VCC Notes: 1. PA is address of the memory location to be programmed. 2. PD is data to be programmed at byte address. 3. DQ7 is the out put of the complement of the data written to the device. 4. DOUT is the output of the data written to the device. 5. Figure indicates last two bus cycles of four bus cycle sequence. 7 t OH PUMA 68F32006/A-90/12/15 Issue 4.2 : December 1999 A.C Waveforms - Alternate CE controlled Program operation timings Data Polling Address 5555H PA t WC tAS PA t AH tR C WE tGHE L OE tC P t C HP t WHWH 1 CE t OE t WS tD F t DH DATA A0H PD DQ7 DDOUT OUT tD S tC E V t OH CC NOTES: 1. PA is address of memory location to be programmed. 2. PD is data to be programmed at byte address. 3. DQ7 is the output of the complement of the data written to the device. 4. DOUT is the output of the data written to the device. 5. Figure indicates last two bus cycles of four bus cycle sequence. AC Waveforms for Data Polling During Embedded Algorithm Operations t CH CE t DF t OE OE tOEH t CE WE t OH * DQ7 DQ7= Valid Data DQ7 HIGH Z t WHWH 1 or 2 DQ0-DQ6 = Invalid DQ0-DQ6 DQ0-DQ7= Vaild Data tOE 8 HIGH Z PUMA 68F32006/A-90/12/15 Issue 4.2 : December 1999 AC Waveforms for Toggle Bit During Embedded Algorithm Operations CE WE tOEH OE * DATA (DQ0-DQ7) DQ6=Toggle DQ0-DQ7 Valid DQ6= Stop Toggling DQ6=Toggle t OE * DQ6 stops toggling ( the device has completed the embedded operations) AC Waveforms Chip / Sector Erase tAS Address 5555H tAH 2AAAH 5555H 5555H 2AAAH SA CE tGHWL OE tWP WE tWPH tCS tDH Data Vcc tDS AAH 55H 80H AAH tVCS NOTES: 1. SA is the address for sector erase. Addresses = don't care for Chip Erase. 9 55H 10H/30H PUMA 68F32006/A-90/12/15 Issue 4.2 : December 1999 EMBEDDED PROGRAMMING ALGORITHM Start Write Program Command Sequence (see below) Data Poll Device Increment Address Last Address ? No Yes Programming Completed Program Command Sequence (Address /Command) 5555H/AAH 2AAAH/55H 5555H/A0H Program Address/Program data 10 PUMA 68F32006/A-90/12/15 Issue 4.2 : December 1999 EMBEDDED ERASE ALGORITHM START Write Erase Command Sequence (See below) Data Poll or Toggle Bit Successfully Completed Erasure Completed Chip Erase Command Sequence Individual Sector/Mulitiple Sector (Address/Command): Erase Command Sequence (Address/Command): 5555H/AAH 5555H/AAH 2AAAH/55H 2AAAH/55H 5555H/80H 5555H/80H 5555H/AAH 5555H/AAH 2AAAH/55H 5555H/10H 2AAAH/55H Sector Address/30H Sector Address/30H Sector Address/30H 11 } Additional sector erase commands are optional PUMA 68F32006/A-90/12/15 Issue 4.2 : December 1999 DATA POLLING ALGORITHM START Read Byte (DQ0-DQ7) Addr =VA YES DQ7 = Data ? NO NO DQ5 = 1 ? YES Read Byte (DQ0-DQ7) Addr =VA DQ7 = Data ? YES PASS NO FAIL NOTE: 1. DQ7 is rechecked even if DQ5 = 1 because DQ7 may change simultaneously with DQ5. 2. VA = Byte address for programming. = Any of the sector addresses within the sector being erased during sector erase operation = Valid address equals any Non-protected sector group address during chip erase. TOGGLE BIT ALGORITHM START Read Byte (DQ0-DQ7) Addr=Don't Care NO DQ6=Toggle ? YES NO DQ5 = 1 ? YES Read Byte (DQ0-DQ7) Addr=Don't Care DQ6=Toggle ? NO PASS YES FAIL NOTES: 1. DQ6 is rechecked even if DQ5 = 1 because DQ6 may stop toggling at the same time as DQ5 changing to "1". 12 PUMA 68F32006/A-90/12/15 Issue 4.2 : December 1999 DEVICE OPERATION The following description deals with the device operating in 8 bit mode accessed through CE1, however status flag definitions shown apply equally to the corresponding flag for each device in the module. Read Mode The device has two control functions which must be satisfied in order to obtain data at the outputs CE1-4 is the power control and should be used for device selection OE is the output control and should be used to gate data to the output pins if the device is selected. Standby Mode Two standby modes are available : CMOS standby : CE1-4 held at Vcc +/- 0.3V TTL standby : CE1-4 held at VIH In the standby mode the outputs are in a high impedance state independent of the OE input. If the device is deselected during erasure or programming the device will draw active current until the operation is completed. Output Disable With the OE input at a logic high level (VIH), output from the device is disabled. This will cause the output pins to be in a high impedance state. Autoselect The autoselect mode allows the reading out of a binary code from the device and will identify the die manufacturer and type. This mode is intended for use by programming equipment. This mode is functional over the full military temperature range. The autoselect codes for the first device are as follows : Type Manufacture Code A17-A19 A6 A1 A0 DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0 VIL Code (HEX) 01H X VIL VIL 0 0 0 0 0 0 0 1 X VIL VIL VIH A4H 1 1 0 1 0 1 0 1 VIL VIH VIL 01H* 0 0 0 0 0 0 0 1 Device Code Sector Group Sector Group Protection Address * Outputs 01H at protected sector address To activate this mode the programming equipment must force VID on address A9 . Two identifier bytes may then be sequenced from each die device outputs by toggling A0 from VIL to VIH. All addresses are dont care apart from A0, A1, A6. All identifiers for manufacturer and device will exhibit odd parity with D7 defined as the parity bit. In order to read the proper device codes when executing the autoselect A1 must be VIL. Write Device erasure and programming are accomplished via the command register. The contents of the register serve as inputs to the internal state machine. The state machine outputs dictate the function of the device. The register is a latch used to store the commands along with the address and data information required to execute the command. The command register is written by bringing WE/WE1-4 to VIL while CE1-4 is at VIL and OE is at VIH.Addresses are latched on the falling edge of WE/WE1-4 while data is latched on the rising edge. 13 PUMA 68F32006/A-90/12/15 Issue 4.2 : December 1999 COMMAND DEFINITIONS Device operations are selected by writing specific address and data sequences into the command register. The following table defines these register command sequences. Command Sequence Read/Reset Bus Write Cycles Req'd First Bus Write Cycle Addr Data Second Bus Write Cycle Third Bus Write Cycle Addr Data Addr Data Fourth Bus Read/Write Cycle Addr Data RD Fifth Bus Write Cycle Sixth Bus Write Cycle Addr Data Addr Data F0H Read/Reset 1 XXXXH Read/Reset 3 5555H AAH 2AAAH 55H 5555H F0H RA Autoselect 3 5555H AAH 2AAAH 55H 5555H 90H 00H/ 01H Byte Program 4 5555H AAH 2AAAH 55H 5555H A0H PA Chip Erase 6 5555H AAH 2AAAH 55H 5555H 80H 5555H AAH 2AAAH 55H 5555H 10H Sector Erase 6 5555H AAH 2AAAH 55H 5555H 80H 5555H AAH 2AAAH 55H SA 30H Erase Suspend 1 XXXXH B0H Erase Resume 1 XXXXH 30H 01H/D5H PD NOTES: 1. Address bit A15,A14,A13, A12, A11=X=Don't care. 2. RA=Address of the memory location to be read. PA=Address of memory location to be programmed. Addresses are latched on the falling edge of the WE pulse . SA=Address of the sector to be erased. The combination of A19, A18, A17 and A16 will uniquely select any sector. 3. RD=Data read from location RA during read operation. PD=Data to be programmed at location PA. Data is latched on the falling edge of WE Read / Reset Command The read or reset operation is initiated by writing the read/reset command sequence into the command register. Microprocessor read cycles retrieve array data from the memory. The device remains enabled for reads until the command register contents are altered. The device will automatically power-up in the read/reset state. In this case, a command sequence is not required to read data. Standard microprocessor read cycles will retrieve array data. This default value ensures that no spurious alteration of memory content occurs during the power transition. Refer to the AC Read Characteristics and Waveforms for specific timing parameters. 14 PUMA 68F32006/A-90/12/15 Issue 4.2 : December 1999 Sector Group Protection The device features hardware sector group protection. This feature will disable both program and erase operations in any combination of sector groups of memory. The sector protect feature is enabled using programming equipment at the users site. The device is shipped with all sector groups unprotected. It is also possible to determine if a sector is protected in the system by writing the autoselect command. Performing a read operation at XX02H , where the higher order addresses (A17, A18, A19) is the desired sector group address, will produce 01H data at DQ0 for a protected sector group. Sector Address Table A19 0 A18 0 A17 0 A16 0 0 0 0 0 0 0 0 1 1 1 0 1 0 1 0 0 0 0 1 1 1 0 1 1 0 1 1 1 0 0 0 0 0 1 080 000h -0 8FF F Fh 090 000h -0 9FF F Fh 1 0 1 0 SA 12 SA 13 1 1 1 0 1 1 1 0 0 1 0 1 0A0 000h -0A FFFFh 0B0 000h -0B FFFFh SA 14 1 1 1 0 0C 0000 h-0 CF FF Fh 0D 0000 h-0 DF FF Fh 0E0 000h -0E FFFFh SA 15 1 1 1 1 0F 000 0h-0F FF FF h SA 0 SA 1 SA 2 SA 3 SA 4 SA 5 SA 6 SA 7 SA 8 SA 9 SA 10 SA 11 Address R an ge 000 000h -0 0FF F Fh 010 000h -0 1FF F Fh 020 000h -0 2FF F Fh 030 000h -0 3FF F Fh 040 000h -0 4FF F Fh 050 000h -0 5FF F Fh 060 000h -0 6FF F Fh 0 1 070 000h -0 7FF F Fh Sector Group Address Table SGA0 SGA1 SGA2 SGA3 SGA4 SGA5 SGA6 SGA7 A19 0 A18 0 0 0 0 0 1 1 0 0 1 1 1 1 1 1 15 A17 0 1 0 1 S e c to rs SA0-SA1 SA2-SA3 SA4-SA5 SA6-SA7 1 0 SA8-SA9 S A 1 0 -S A 1 1 S A 1 2 -S A 1 3 1 S A 1 4 -S A 1 5 0 PUMA 68F32006/A-90/12/15 Issue 4.2 : December 1999 Autoselect Command Flash memories are intended for use in applications where the local CPU alters memory contents. As such, manufacture and device codes must be accessible while the device resides in the target systems. PROM programmers typically access the signature codes by raising A9 to a high voltage. However, multiplexing high voltage onto the address lines is not generally a desired system design practice. The device contains an autoselect operation to supplement traditional PROM programming methodology. The operation is initiated by writing the autoselect command sequence into the command register. Following the command write, a read cycle from address XX00H retrieves the manufacture code of 01H. A read cycle from address XX01H returns the device code D5H. Further, the write protect status of sectors can be read in this mode. Scanning the sector group addresses (A17, A18, A19) while (A6,A1,A0)=(0, 1, 0) will produce a logical '1' at device output DQ0 for a protected sector group. To terminate the operation, it is necessary to write the read/reset command sequence into the register. Byte Programming The device is programmed on a byte-by-byte basis. Programming is a four bus cycle operation. There are two "unlock" write cycle. These are followed by the program set-up command and data write cycles. Addresses are latched on the falling edge of WE/WE1-4 or CE1-4, whichever happens later, while the data are latched on the rising edge of WE/WE1-4 or CE1-4 whichever happens first. The rising edge of WE/WE1-4 or CE1-4 begins programming. Upon executing the Embedded Program Algorithm Command sequence the system is not required to provide further controls or timings. The device will automatically provide adequate internally generated program pulses and verify the programmed cell margin. The automatic programming operation is completed when the data on D7 is equivalent to data written to this bit (see written Operations Status) at which time the device returns to read mode. Data Polling must be performed at the memory location which is being programmed. Programming is allowed in any address sequence and across sector boundaries. Chip Erase Chip erase is a six bus cycle operation. There are two "unlock" write cycles. These are followed by writing the "set-up" command. Two more "unlock" write cycles are then followed by the chip erase command. Chip erase doesn't require the user to program the device prior to erase. Upon executing the Embedded Erase Algorithm command sequence the device will automatically program and verify the entire memory for an all zero data pattern prior to electrical erase. The systems is not required to provide any controls or timings during these operations. The automatic erase begins on the rising edge of the last WE pulse in the command sequence and terminates when the data on D7 is "1" (See Written Operation Section) at which time the device returns to read the mode. 16 PUMA 68F32006/A-90/12/15 Issue 4.2 : December 1999 Sector Erase Sector erase is a six bus cycle operation. There are two "unlock"write cycles. These are followed by writing the "Set-up" command. Two more "unlock" write cycles are then followed by the sector erase command. The sector address (any address location within the desired sector) is latched on the falling edge of WE, while the command (30H) is latched on the rising edge of WE. A time-out of 50us from the rising edge of the last sector erase command will initiate the sector erase command(s). Multiple sectors may be erased sequentially by writing the six bus cycle operations as desribed above. This sequence is followed with writes of the sector erase command to addresses in other sectors desired to be sequentially erased. A time-out of 50us from the rising edge of the WE pulse for the last sector erase command will initiate the sector erase. If another sector erase command is wriiten within the 50us time-out window the timer is reset. Any command other than sector erase within the time-out window will reset the device to the read mode, ignoring the previous command string (refer to Write Operation Status section for Sector Erase Timer operation). Loading the sector erase buffer may be done in any sequence and with any number of sectors (0 to 7). Sector erase doesn't require the user to program the device prior to erase. The device automatically programs all memory locations in the sector(s) to be erased prior to electrical erase. When erasing a sector or sectors the remaining unselected sectors are not affected. The system is not required to provide any controls or timings during these operations. The automatic sector erase begins after the 50us time-out from the rising edge of the WE pulse for the last sector erase command pulse and terminates when the data on D7 is "1" ( see Written Operation Status Section) at which time the device returns to read mode. Data polling must be preformed at an address within any of the sectors being erased. Erase Suspend Erase suspend allows the user to interrupt a sector erase operation and then perform data reads or programs to a sector not being erased. This command is only applicable during the sector erase operation which includes the time-out period for sector erase. Writing the erase suspend command during the sector erase time-out results in immediate termination of the time-out period & suspension of the erase operation. Writing the erase resume command resumes the erase operation. When the erase operation has been suspended, the device defaults to the erase-suspend-read mode. After entering the erase-suspend-read mode, the user can program the device by writing the appropriate command sequence for Byte program. The end of the erase-suspend program operation is detected by data polling, or by the toggle bit. Note that DQ7 must be read from the byte program address. To resume the sector erase operation, the resume command (30H) should be written. Any further writes of the resume command at this point will be ignored. 17 PUMA 68F32006/A-90/12/15 Issue 4.2 : December 1999 Operating Modes The following modes are used to control the device. OPERATION CE OE WE A0 A1 A6 A9 I /O Auto-Select Manufacturer Code L L H L L L V ID Code Auto Select Device Code L L H H L L V ID Code Read(1) L L X A0 A1 A6 Standby H X X X X Output Disable L H H X Write L H L A0 A1 L H L H Verify Sector Group Protect L X A9 D OUT X X High Z X X High Z A6 L A9 Din V ID Code 1) L=VIL, H=VIH, X=Don't Care NOTE: 1) WE can be VIL if OE is VIL , OE at VIH initiates write cycle. WRITE OPERATIONS STATUS Status DQ7 DQ6 DQ5 DQ3 DQ2 Byte Program in Embedded Program Algorithm DQ 7 Tog gle 0 0 1 0 Tog gle 0 1 Tog gle 1 1 0 0 Emb edded Erase Algorithm Erase Suspend Read (Eras e Sus pend Sector) I n P rogr ess Erase Suspended Mode Erase Suspend Read (Non-Erase Suspend Sector) Da ta Erase Suspend Program (Non-Erase Suspend Sector) Byte Program in Embedded Program Algorithm Exceeded Time Limits Erase Suspend Program (Non-Erase Suspend Sector) Da ta Tog gle Da ta Da ta Da ta 1 0 0 DQ 7 Tog gle 1 0 1 0 Tog gle 1 1 N/A DQ 7 Tog gle 1 1 N/A DQ 7 Program/Erase in Embedded Erase Algorit hm Erase Suspended Mode Tog gle (No te 1) (No te 2) (No te 3) Notes: 1. Perf orming successive read operations from th e erase-suspended s ector will c ause DQ2 to toggle. 2. Perf orming successive read operations from any address will cause DQ6 to toggle. 3. Reading the byte addres s being programmed while in the erase-suspend program mode will indicat e logic '1' at the DQ2 bit. However, successive reads from the erase-suspended sector will cause DQ2 to toggle. 18 PUMA 68F32006/A-90/12/15 Issue 4.2 : December 1999 D7 Data Polling The device features Data Polling as a method to indicate to the host system that the Embedded Algorithms are in progress or completed. During the Embedded Programming Algorithm, an attempt to read the device will produce the complement of the data last written to D7. Upon completion of the Embedded Programming Algorithm an attempt to read the device will produce the true data last written to D7. During the Embedded Erase Algorithm, D7 will be "0" until the erase operation is completed. Upon completion data at D7 is "1". For chip erase, the Data Polling is valid after the rising edge of the sixth WE pulse in the six write pulse sequence. For sector erase, Data Polling is valid after the last rising edge of the sector erase WE pulse. The Data Polling feature is only active during the Embedded Programming Algorithm, Embedded Erase Algorithm, Erase Suspend, Erase-Suspend-Program, or sector erase time-out. D6 Toggle Bit The device also features the "toggle bit" as a method to indicate to the host system that the Embedded Algorithms are in progress or completed. During an Embedded Program or Erase Algorithm cycle, successive attempts to read data from the device will result in D6 toggling between one and zero. Once the Embedded Program or Erase Algorithm cycle is completed, D6 will stop toggling and valid data will be read on successive attempts. During programming, the Toggle bit is valid after the rising edge of the forth WE pulse in the four write pulse sequence. For chip erase, the Toggle bit is valid after the rising edge of the sixth WE pulse in the six write pulse sequence. For Sector Erase, the toggle bit is valid after the last rising edge of the sector erase WE pulse. The Toggle Bit is active during the sector time-out. D5 Exceeding Time Limits D5 will indicate if the program or erase time has exceeded the specified limits. Under these conditions D5 will produce "1", indicating the program or erase cycle was not successfully completed . Data Polling is the only operating function of the device under this condition. The CE circuit will partially power down the device under these conditions (to approximately 2mA). The OE and WE pins will control the output disable functions . The D5 failure condition may also appear if the user tries to program a non blank location without erasing. In this case the device locks out and never completes the embedded algorithm operation. Hence the system never reads a valid data on D7 and D6 never stops toggling. Once the device has exceeded timing limits, the D5 bit will indicate '1' D3 Sector Erase Timer After the completion of the initial sector erase command sequence the sector erase time-out will begin. D3 will remain low until the time-out is complete. Data Polling and Toggle Bit are valid after the initial sector erase command sequence. If Data Polling or the Toggle Bit indicates the device has been written with a valid erase command, D3 may be used to determine if the sector erase timer window is still open. If D3 is high the internally controlled erase cycle has begun; attempts to write subsequent commands to the device will be ignored until the erase operation is completed as indicated by Data Polling or Toggle Bit. If D3 is low , the device will accept additional sector erase commands. To insure the command has been accepted, the software should check the status of D3 prior to and following each subsequent sector erase command. If D3 were high on the second status check, the command may not have been accepted. 19 PUMA 68F32006/A-90/12/15 Issue 4.2 : December 1999 DATA PROTECTION The device is designed to offer protection against accidental erasure or programming caused by spurious system level signals that may exist during power transition. During power up the device automatically resets the internal state machine in the Read mode. Also, with its controls register architecture , alteration of the memory contents only occurs after successful completion of specific multi-bus cycle command sequences. The device also incorporates several features to prevent inadvertent write cycles resulting from Vcc power up and power down transitions or system noise. Low Vcc Write Inhibit To avoid initiation of a write cycle during VCC power up and power down, a write cycle is locked out for VCC<VLKO . If VCC<VLKO, the command register is disabled and all internal program/erase circuits are disabled. Under this condition the device will reset to read mode. Subsequent writes will be ignored until the VCC level is greater than VLKO. It is usually correct to prevent unintentional writes when VCC>VLKO. Write Pulse "Glitch" Protection Noise pulses of less than 5ns (typical) on OE, CE, WE will not initiate a write cycle Logical Inhibit Writing is inhibited by holding any one of OE=VIL, CE=VIH or WE=VIH. To initiate a write cycle CE and WE must be logical zero while OE is a logical one. Power Up Write Inhibit Power-up of the device with WE=CE=VIL and OE=VIH will not accept commands on the rising edge of WE. The internal state machine is automatically reset to the read mode on power-up. Sector Protect Sectors of the device may be hardware protected at the users factory. The protection circuitry will disable both program and erase functions for the protected sector(s). Requests to program or erase a protected sector will be ignored by the device. ERASE AND PROGRAMMING PERFORMANCE Parameter Min Sector Erase Time - Byte Programming Time - Chip Programming Time - Chip Erase Time - Limits Typ Max 1 15 (Note 1) 7 1000 (Note 1) 7.2 50 (Note 1) 16 (Note 1) Notes: (1) 25OC, 5V VCC, 100,000 cycles. 20 240 Unit sec Comments us Excludes 00H programming prior to erasure. Excludes System-level overhead. sec Excludes system-level overhead. sec Exclude 00H programming prior to erase PUMA 68F32006/A-90/12/15 Issue 4.2 : December 1999 Version 'A' Block Diagram NC A0 A1 A2 A3 A4 A5 CS3 GND CS4 WE1 A6 A7 A8 A9 A10 Vcc Version 'A' Pin Definition 9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61 10 60 11 59 12 58 13 57 14 56 15 55 16 54 VIEW 17 53 FROM 18 52 19 51 ABOVE 20 50 21 49 22 48 23 47 24 46 25 45 26 44 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 PUMA 68F32006A D16 D17 D18 D19 D20 D21 D22 D23 GND D24 D25 D26 D27 D28 D29 D30 D31 Vcc A11 A12 A13 A14 A15 A16 CS1 OE CS2 A17 WE2 WE3 WE4 A18 GND A19 D0 D1 D2 D3 D4 D5 D6 D7 GND D8 D9 D10 D11 D12 D13 D14 D15 21 A0~A19 OE WE4 WE3 WE2 WE1 CS1 CS2 CS3 CS4 D0~7 D8~15 D16~23 D24~31 1M x 8 1M x 8 1M x 8 1M x 8 FLASH FLASH FLASH FLASH PUMA 68F32006/A-90/12/15 Issue 4.2 : December 1999 Package Information Dimensions in mm(inches) Plastic 68 Pin JEDEC Surface mount PLCC 25.27 (0.995) sq. 5.08 (0.200) max 25.02 (0.985) sq. 0.10 (0.004) 23.11 (0.910) 0.46 (0.018) typ. 24.13 (0.950) 1.27 (0.050) typ. 0.90 (0.035) typ. Ordering Information PUMA 68F32006AM-90E Speed 90 = 90 ns 12 = 120 ns 15 = 150 ns Temperature range Blank = Commercial Temperature I = Industrial Temperature M = Military Temperature (Restricted) Special Features Blank = Single WE A = WE1-4 Organisation 32006 = 1M x 32, user configurable as 2M x 16 and 4M x 8 Memory Type Package F = FLASH PUMA 68 = 68 pin "J" Leaded PLCC NOTE: The E variant is designated to parts with extended Erase/Write Cycle Endurance (100,000 Min.). If not specified when ordered only a Erase/Write Cycle Endurance of 10,000 Minimum can be guaranteed. Note : Although this data is believed to be accurate the information contained herein is not intended to and does not create any warranty of merchantibility or fitness for aparticular purpose. Our products are subject to a constant process of development. Data may be changed without notice. Products are not authorised for use as critical components in life support devices without the express written approval of a company director. 22 PUMA 68F32006/A-90/12/15 Issue 4.2 : December 1999 ISSUE HISTORY PUMA 68F32006-90/12/15 Issue 4.1 DCN3964 First issue based on AMD29F080. Issue 4.2 Restricted military Operating temperature from 125OC to 115OC 23