FSEZ1216 — Primary-Side-Regulation PWM Integrated Power MOSFET Features Description Constant-Voltage (CV) and Constant-Current (CC) Control without Secondary-Feedback Circuitry Green Mode: Frequency Reduction at Light-Load Cable Voltage Drop Compensation in CV Mode The primary-side PWM integrated Power MOSFET, FSEZ1216, significantly simplifies power supply design that requires CV and CC regulation capabilities. FSEZ1216 controls the output voltage and current precisely only with the information in the primary side of the power supply, not only removing the output current sensing loss, but also eliminating all secondary feedback circuitry. Fixed Over-Temperature Protection with Latch DIP-8 Package Available Fixed PWM Frequency at 42kHz with Frequency Hopping to Reduce EMI Low Startup Current: 10μA The green-mode function with a low startup current (10µA) maximizes the light load efficiency so the power supply can meet stringent standby power regulations. Low Operating Current: 3.5mA Peak-Current-Mode Control in CV Mode Cycle-by-Cycle Current Limiting VDD Over-Voltage Protection with Auto-Restart VDD Under-Voltage Lockout (UVLO) Gate Output Maximum Voltage Clamped at 18V Compared with conventional secondary side regulation approach, the FSEZ1216 can reduce total cost, component count, size, and weight, while simultaneously increasing efficiency, productivity, and system reliability. A typical output CV/CC characteristic envelope is shown in Figure 1. Applications Battery Chargers for Cellular Phones, Cordless Phones, PDA, Digital Cameras, Power Tools Replaces Linear Transformer and RCC SMPS Offline High Brightness (HB) LED Drivers Figure 1. Typical Output V-I Characteristic Ordering Information Part Number Operating Temperature Range FSEZ1216NY -40°C to +105°C MOSFET BVDSS MOSFET RDS.ON Eco Status Package Packing Method 600V 9.3Ω (Typical) Green 8-Lead, Dual Inline Package (DIP-8) Tube For Fairchild’s definition of Eco Status, please visit: http://www.fairchildsemi.com/company/green/rohs_green.html. © 2009 Fairchild Semiconductor Corporation FSEZ1216 • Rev. 1.0.1 www.fairchildsemi.com FSEZ1216 — Primary-Side-Regulation PWM Integrated Power MOSFET April 2009 CSN 2 RSN 2 VO Bridge Rectifier Diode RSN1 VDL + CDL CSN1 NP NS DR CO RSTAR T - IO DSN DDD AC Line CDD NA FSEZ1216 RCS CS DRAIN 1 CCOMR RCOMR 8 2 COMR GND 7 3 COMI VDD 6 4 COMV VS 5 RS1 RS2 CC OM I RC OM I CS CCOMV RCOMV Figure 2. Typical Application Internal Block Diagram + VDD 6 OVP Auto Restart Protection 28V + Internal Bias Brownout 8 DRAIN Latch Protection OTP - FSEZ1216 — Primary-Side-Regulation PWM Integrated Power MOSFET Application Diagram 16V/5V OSC with Frequency Hopping S Q Soft-Driver R Q PWM Comparator PWM Comparator + + 1.3V Leading-Edge Blanking Slope Compensation IO Estimator + Green Mode Controller + EA_I 2.5V Cable Drop Compensation - GND Brownout Protection t DIS Detector 5 VS Temperature Compensation EA_V 7 VO Estimator 3 4 COMI 2 COMV Figure 3. © 2009 Fairchild Semiconductor Corporation FSEZ1216 • Rev. 1.0.1 1 CS + PWM Comparator COMR Functional Block Diagram www.fairchildsemi.com 2 F- Fairchild Logo Z- Plant Code X- 1-Digit Year Code Y- 1-Digit Week Code TT- 2-Digits Die Run Code T- Package Type (N=DIP) P- Z: Pb Free, Y: Green Package M- Manufacture Flow Code Figure 4. Top Mark Pin Configuration DRAIN CS COMR GND COMI VDD COMV VS Figure 5. Pin Configuration Pin Definitions Pin # Name 1 CS 2 COMR Cable Compensation. This pin connects a capacitor between COMR and GND for compensation voltage drop due to output cable loss in CV mode. 3 COMI Constant Current Loop Compensation. This pin connects a capacitor and a resistor between COMI and GND for compensation current loop gain. 4 COMV Constant Voltage Loop Compensation. This pin connects a capacitor and a resistor between COMV and GND for compensation voltage loop gain. 5 VS 6 VDD Power Supply. The power supply pin for the IC operating current and MOSFET driving current. This pin is connects to an external VDD capacitor (typically 10μF). The threshold voltages for startup and turn-off are 16V and 5V, respectively. 7 GND Ground. 8 DRAIN FSEZ1216 — Primary-Side-Regulation PWM Integrated Power MOSFET Marking Information Description Current Sense. This pin connects a current-sense resistor to sense the MOSFET current for peak-current-mode control in CV mode and provides for output-current regulation in CC mode. Voltage Sense. This pin detects the output voltage information and discharge time based on voltage of auxiliary winding. This pin connects two divider resistors and one capacitor. Drain. This pin is the high-voltage power MOSFET drain. © 2009 Fairchild Semiconductor Corporation FSEZ1216 • Rev. 1.0.1 www.fairchildsemi.com 3 Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. Symbol Parameter Min. (1) VVDD DC Supply Voltage Max. Unit 30 V VVS VS Pin Input Voltage -0.3 7.0 V VCS CS Pin Input Voltage -0.3 7.0 V VCOMV Voltage Error Amplifier Output Voltage -0.3 7.0 V VCOMI Voltage Error Amplifier Output Voltage -0.3 7.0 V 600 V VDS Drain-Source Voltage ID Continuous Drain Current TC=25°C 1.0 TC=100°C 0.6 A IDM Pulsed Drain Current 4 A EAS Single Pulse Avalanche Energy 33 mJ IAR Avalanche Current 1 A PD Power Dissipation (TA＜50°C) 800 mW ΘJA Thermal Resistance Junction-to-Air 113 °C/W ΘJC Thermal Resistance Junction-to-Case 67 °C/W +150 °C TJ TSTG TL ESD Operating Junction Temperature Storage Temperature Range +150 °C Lead Temperature (Wave Soldering or IR, 10 Seconds) -55 +260 °C Electrostatic Discharge Capability, Human Body Model, JEDEC: JESD22-A114 2.5 KV 1250 V Electrostatic Discharge Capability, Charged Device Model, JEDEC: JESD22-C101 FSEZ1216 — Primary-Side-Regulation PWM Integrated Power MOSFET Absolute Maximum Ratings Note: 1. All voltage values, except differential voltages, are given with respect to GND pin. Recommended Operating Conditions The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend exceeding them or designing to Absolute Maximum Ratings. Symbol TA Parameter Conditions Operating Ambient Temperature © 2009 Fairchild Semiconductor Corporation FSEZ1216 • Rev. 1.0.1 Min. -40 Typ. Max. Unit +105 °C www.fairchildsemi.com 4 VDD=15V and TA=25°C unless otherwise specified. Symbol Parameter Conditions Min. Typ. Max. Units VDD Section 25 V VDD-ON VOP Turn-On Threshold Voltage 15 16 17 V VDD-OFF Turn-Off Threshold Voltage 4.5 5.0 5.5 V 0 1.6 10.0 μA 3.5 5.0 mA 1 2 mA IDD-ST IDD-OP Continuously Operating Voltage Startup Current Operating Current 0< VDD < VDD-ON-0.16V VDD=20V, fS=fOSC, VVS=2V, VCS=3V, CL=1nF VDD=20V, VVS=2.7V, fS=fOSC-N-MIN, VCS=0V, CL=1nF, VCOMV=0V IDD-GREEN Green Mode Operating Supply Current VDD-OVP VDD Over-Voltage Protection Level VCS=3V, VVS=2.3V, 27 28 29 V tD-VDDOVP VDD Over-Voltage Protection Debounce Time fs= fOSC, VVS=2.3V 100 250 400 μs Center Frequency TA=25°C 39 42 45 Frequency Hopping Range TA=25°C ±1.8 ±2.6 ±3.6 Oscillator Section fOSC Frequency tFHR Frequency Hopping Period TA=25°C 3 KHz ms fOSC-N-MIN Minimum Frequency at No Load VVS=2.7V, VCOMV=0V 550 Hz fOSC-CM-MIN Minimum Frequency at CCM VVS=2.3V, VCS=0.5V 20 KHz fDV Frequency Variation vs. VDD Deviation VDD=10V to 25V 5 % fDT Frequency Variation vs. Temperature Deviation TA=-40°C to +85°C 15 % FSEZ1216 — Primary-Side-Regulation PWM Integrated Power MOSFET Electrical Characteristics Voltage-Sense Section IVS-UVP Itc VBIAS-COMV Sink Current for Brownout Protection RVS=20KΩ IC Compensation Bias Current Adaptive Bias Voltage Dominated by VCOMV VCOMV=0V, TA=25°C, RVS=20KΩ 180 μA 9.5 μA 1.4 V Current-Sense Section tPD Propagation Delay to GATE Output 100 200 ns tMIN-N Minimum On Time at No Load VVS=-0.8V, RS=2KΩ, VCOMV=1V 1100 ns tMINCC Minimum On Time in CC Mode VVS=0V, VCOMV=2V 400 ns Duty Cycle of SAW Limiter 40 % Threshold Voltage for Current Limit 1.3 V DSAW VTH Continued on following page… © 2009 Fairchild Semiconductor Corporation FSEZ1216 • Rev. 1.0.1 www.fairchildsemi.com 5 VDD=15V and TA=25°C unless otherwise specified. Symbol Parameter Conditions Min. Typ. Max. Units 2.475 2.500 2.525 V Voltage-Error-Amplifier Section VVR Reference Voltage VN Green Mode Starting Voltage on fS=fOSC-2KHz, VVS=2.3V COMV Pin 2.8 V VG Green Mode Ending Voltage on COMV Pin fS=1KHz 0.8 V Output Sink Current VVS=3V, VCOMV=2.5V 90 μA Output Source Current VVS=2V, VCOMV=2.5V 90 μA Output High Voltage VVS=2.3V IV-SINK IV-SOURCE VV-HGH 4.5 V Current-Error-Amplifier Section VIR Reference Voltage II-SINK Output Sink Current VCS=3V, VCOMI=2.5V 55 μA Output Source Current VCS=0V, VCOMI=2.5V 55 μA Output High Voltage VCS=0V II-SOURCE VI-HGH 2.475 2.500 2.525 V 4.5 V Cable Compensation Section VCOMR Variation Test Voltage on COMR RCOMR=100k Pin for Cable Compensation 0.735 V 75 % Internal MOSFET Section DCYMAX Maximum Duty Cycle BVDSS Drain-Source Breakdown Voltage ID=250μA, VGS=0V ∆BVDSS /∆TJ Breakdown Voltage Temperature Coefficient ID=250μA, Referenced to 25°C 600 V 0.6 V/°C IS Maximum Continuous DrainSource Diode Forward Current 1 A ISM Maximum Pulsed Drain-Source Diode Forward Current 4 A 11.5 Ω RDS(ON) Static Drain-Source OnResistance IDSS Drain-Source Leakage Current tD-ON Turn-On Delay Time tr tD-OFF tf (2,3) ID=0.5A, VGS=10V 9.3 VDS=600V, VGS=0V, TC=25°C 1 VDS=480V, VGS=0V, TC=100°C 10 VDS=300V, ID=1.1A, RG=25Ω μA 7 24 ns Rise Time 21 52 ns Turn-Off Delay Time 13 36 ns Fall Time CISS Input Capacitance COSS Output Capacitance VGS=0V, VDS=25V, fS=1MHz FSEZ1216 — Primary-Side-Regulation PWM Integrated Power MOSFET Electrical Characteristics 27 64 ns 130 170 pF 19 25 pF Over-Temperature-Protection Section TOTP Threshold Temperature for (4) OTP +140 °C Notes: 2. Pulse test: pulse width ≦ 300µs, duty cycle ≦ 2%. 3. Essentially independent of operating temperature. 4. When over-temperature protection is activated, the power system enters latch mode and output is disabled. © 2009 Fairchild Semiconductor Corporation FSEZ1216 • Rev. 1.0.1 www.fairchildsemi.com 6 5.5 16.6 5.3 VDD-OFF (V) VDD-ON (V) 17 16.2 15.8 15.4 5.1 4.9 4.7 15 4.5 -40 -30 -15 0 25 50 75 85 100 125 -40 -30 -15 0 Temperature (ºC) Figure 6. Turn-On Threshold Voltage (VDD-ON) vs. Temperature Figure 7. 4.5 75 85 100 125 Turn-Off Threshold Voltage (VDD-OFF) vs. Temperature 44 fOSC (KHz) IDD-OP (mA) 50 45 4.1 3.7 3.3 2.9 43 42 41 40 2.5 39 -40 -30 -15 0 25 50 75 85 100 125 -40 -30 -15 Temperature (ºC) Figure 8. 0 25 50 75 85 100 125 Temperature (ºC) Operating Current (IDD-OP) vs. Temperature Figure 9. 2.525 2.525 2.515 2.515 2.505 2.505 VIR (V) VVR (V) 25 Temperature (ºC) 2.495 2.485 FSEZ1216 — Primary-Side-Regulation PWM Integrated Power MOSFET Typical Performance Characteristics Center Frequency (fOSC) vs. Temperature 2.495 2.485 2.475 2.475 -40 -30 -15 0 25 50 75 85 100 125 -40 Temperature (ºC) -15 0 25 50 75 85 100 125 Temperature (ºC) Figure 10. Reference Voltage (VVR) vs. Temperature © 2009 Fairchild Semiconductor Corporation FSEZ1216 • Rev. 1.0.1 -30 Figure 11. Reference Voltage (VIR) vs. Temperature www.fairchildsemi.com 7 25 560 23 fOSC-CM-MIN (KHz) fOSC-N-MIN (Hz) 600 520 480 440 21 19 17 400 15 -40 -30 -15 0 25 50 75 85 100 125 -40 -30 -15 Temperature (ºC) 25 75 85 100 125 Figure 13. Minimum Frequency at CCM (fOSC-CM-MIN) vs. Temperature 1000 25 950 20 900 tMIN-N (ns) 30 15 10 5 850 800 750 0 700 -40 -30 -15 0 25 50 75 85 100 125 -40 -30 -15 0 Temperature (ºC) 25 50 75 85 100 125 Temperature (ºC) Figure 14. Green Mode Frequency Decreasing Rate (SG) vs. Temperature Figure 15. Minimum On Time at No Load (tMIN-N) vs. Temperature 5 1 4 0.8 3 0.6 VG (V) VN (V) 50 Temperature (ºC) Figure 12. Minimum Frequency at No Load (fOSC-N-MIN) vs. Temperature SG (KHz/V) 0 FSEZ1216 — Primary-Side-Regulation PWM Integrated Power MOSFET Typical Performance Characteristics (Continued) 2 0.4 0.2 1 0 0 -40 -30 -15 0 25 50 75 85 100 -40 125 Figure 16. Green Mode Starting Voltage on COMV Pin (VN) vs. Temperature © 2009 Fairchild Semiconductor Corporation FSEZ1216 • Rev. 1.0.1 -30 -15 0 25 50 75 85 100 125 Temperature (ºC) Temperature (ºC) Figure 17. Green Mode Ending Voltage on COMV Pin (VG) vs. Temperature www.fairchildsemi.com 8 95 92 91 IV-SOURCE (µA) IV-SINK (µA) 95 89 86 83 87 83 79 80 75 -40 -30 -15 0 25 50 75 85 100 125 -40 -30 -15 0 25 Temperature (ºC) 75 85 100 125 Figure 19. Output Source Current (IV-SOURCE) vs. Temperature 65 65 62 62 II-SOURCE (µA) II-SINK (µA) Figure 18. Output Sink Current (IV-SINK) vs. Temperature 59 56 53 59 56 53 50 50 -40 -30 -15 0 25 50 75 85 100 125 -40 -30 -15 Temperature (ºC) 0 25 50 75 85 100 125 Temperature (ºC) Figure 20. Output Sink Current (II-SINK) vs. Temperature Figure 21. Output Source Current (II-SOURCE) vs. Temperature 2 80 1.6 76 DCYMAX (%) VCOMR (V) 50 Temperature (ºC) FSEZ1216 — Primary-Side-Regulation PWM Integrated Power MOSFET Typical Performance Characteristics (Continued) 1.2 0.8 0.4 72 68 64 0 60 -40 -30 -15 0 25 50 75 85 100 125 -40 Temperature (ºC) -15 0 25 50 75 85 100 125 Temperature (ºC) Figure 22. Variation Test Voltage on COMR Pin for Cable Compensation (VCOMR) vs. Temperature © 2009 Fairchild Semiconductor Corporation FSEZ1216 • Rev. 1.0.1 -30 Figure 23. Maximum Duty Cycle (DCYMAX) vs. Temperature www.fairchildsemi.com 9 Figure 24 shows the basic circuit diagram of primaryside regulated flyback converter, with typical waveforms shown in Figure 25. Generally, discontinuous conduction mode (DCM) operation is preferred for primary-side regulation since it allows better output regulation. The operation principles of DCM flyback converter are as follows: IO D + V DL VAC Lm + + VF - VO - During the MOSFET ON time (tON), input voltage (VDL) is applied across the primary-side inductor (Lm). Then MOSFET current (Ids) increases linearly from zero to the peak value (Ipk). During this time, the energy is drawn from the input and stored in the inductor. L O A D - Ids EA_I V COMI IO Estimator CS RCS Ref t DIS Detector PWM Control When the MOSFET is turned off, the energy stored in the inductor forces the rectifier diode (D) to turn on. While the diode is conducting, the output voltage (VO), together with diode forward voltage drop (VF), are 2 applied across the secondary-side inductor (Lm×Ns / 2 Np ) and the diode current (ID) decreases linearly from the peak value (Ipk× Np/Ns) to zero. At the end of inductor current discharge time (tDIS), all the energy stored in the inductor has been delivered to the output. V COMV VS NA VDD VO Estimator EA_V RS1 Ref RS2 Primary-Side Regulation Controller + Vw - Figure 24. Simplified PSR Flyback Converter Circuit When the diode current reaches zero, the transformer auxiliary winding voltage (VW) begins to oscillate by the resonance between the primary-side inductor (Lm) and the effective capacitor loaded across MOSFET. Id s (MOSFET Drain-to-Source Current) I pk During the inductor current discharge time, the sum of output voltage and diode forward voltage drop is reflected to the auxiliary winding side as (VO+VF)× NA/NS. Since the diode forward voltage drop decreases as current decreases, the auxiliary winding voltage reflects the output voltage best at the end of diode conduction time where the diode current diminishes to zero. By sampling the winding voltage at the end of the diode conduction time, the output voltage information can be obtained. The internal error amplifier for output voltage regulation (EA_V) compares the sampled voltage with internal precise reference to generate error voltage (VCOMV), which determines the duty cycle of the MOSFET in CV mode. ID (Diode Current) I pk • NP NS I D .avg = I o VW (Auxiliary Winding Voltage) VF • Meanwhile, the output current can be estimated using the peak drain current and inductor current discharge time since output current is same as the average of the diode current in steady state. The output current estimator picks up the peak value of the drain current with a peak detection circuit and calculates the output current using the inductor discharge time (tDIS) and switching period (tS). These output information is compared with internal precise reference to generate error voltage (VCOMI), which determines the duty cycle of the MOSFET in CC mode. NA NS VO • t ON t t NA NS DI S S Figure 25. Key Waveforms of DCM Flyback Converter Among the two error voltages, VCOMV and VCOMI, the smaller actually determines the duty cycle. During constant voltage regulation mode, VCOMV determines the duty cycle while VCOMI is saturated to HIGH. During constant current regulation mode, VCOMI determines the duty cycle while VCOMV is saturated to HIGH. © 2009 Fairchild Semiconductor Corporation FSEZ1216 • Rev. 1.0.1 ID Np:Ns FSEZ1216 — Primary-Side-Regulation PWM Integrated Power MOSFET Functional Description www.fairchildsemi.com 10 Switching Frequen cy When it comes to cellular phone charger applications, the actual battery is located at the end of cable, which causes, typically, several percent of voltage drop on the actual battery voltage. FSEZ1216 has a programmable cable voltage drop compensation, which provides a constant output voltage at the end of the cable over the entire load range in CV mode. As load increases, the voltage drop across the cable is compensated by increasing the reference voltage of voltage regulation error amplifier. The amount of compensation is programmed by the resistor on the COMR pin. The relationship between the amount of compensation and the COMR resistor is shown in Figure 26. 42kHz Dee p Green Mode 15 Green Mode Normal Mode 550H z 14 0.8V 13 V COMV 2.8V Figure 27. Switching Frequency in Green Mode 12 Compensation Percentage (%) 11 10 9 Frequency Hopping 8 EMI reduction is accomplished by frequency hopping, which spreads the energy over a wider frequency range than the bandwidth measured by the EMI test equipment. FSEZ1216 has an internal frequency hopping circuit that changes the switching frequency between 39.4kHz and 44.6kHz with a period of 3ms, as shown in Figure 28. 7 6 5 4 3 2 Gate Drive Signal 1 10 20 30 40 50 60 RCOMR (k ) 70 80 90 100 t s t s t s Figure 26. Cable Voltage Drop Compensation Temperature Compensation Built-in temperature compensation provides constant voltage regulation over wide a range of temperature variation. This internal compensation current compensates the forward-voltage drop variation of the secondary-side rectifier diode. fs Green-Mode Operation 44.6kHz 42.0kHz 39.4kHz The FSEZ1216 uses voltage regulation error amplifier output (VCOMV) as an indicator of the output load and modulates the PWM frequency, as shown in Figure 27, such that the switching frequency decreases as load decreases. In heavy load conditions, the switching frequency is fixed at 42KHz. Once VCOMV decreases below 2.8V, the PWM frequency starts to linearly decrease from 42KHz to 550Hz to reduce the switching losses. As VCOMV decreases below 0.8V, the switching frequency is fixed at 550Hz and FSEZ1216 enters deep green mode, where the operating current reduces to 1mA, further reducing the standby power consumption. © 2009 Fairchild Semiconductor Corporation FSEZ1216 • Rev. 1.0.1 FSEZ1216 — Primary-Side-Regulation PWM Integrated Power MOSFET Cable Voltage Drop Compensation 3ms Figure 28. Frequency Hopping t www.fairchildsemi.com 11 enables and disables the switching of the MOSFET until the fault condition is eliminated (see Figure 30). Meanwhile, OTP is latch mode protection, which is reset when VDD is fully discharged by un-plugging the AC power line. At the instant the MOSFET is turned on, there is a highcurrent spike through the MOSFET, caused by primaryside capacitance and secondary-side rectifier reverse recovery. Excessive voltage across the RCS resistor can lead to premature turn-off of MOSFET. FSEZ1216 employs an internal leading-edge blanking (LEB) circuit. To inhibit the PWM comparator for a short time after the MOSFET is turned on. External RC filtering is not required. VDS Fault Occurs Power On Fault Removed Startup Figure 29 shows the typical startup circuit and transformer auxiliary winding for a FSEZ1216 application. Before FSEZ1216 begins switching, it consumes only startup current (typically 10μA) and the current supplied through the startup resistor charges the VDD capacitor (CDD). When VDD reaches turn-on voltage of 16V (VDD-ON), FSEZ1216 begins switching, and the current consumed by FSEZ1216 increases to 3.5mA. Then, the power required for FSEZ1216 is supplied from the transformer auxiliary winding. The large hysteresis of VDD provides more holdup time, which allows using a small capacitor for VDD. VDD 16V 5V Operating Current VD L + CD L - 3.5mA Np 10µA RSTAR T Normal Operation DD D Fault Situation Normal Operation Figure 30. Auto-Restart Operation CD D AC Line NA VDD Over-Voltage Protection (OVP) VDD over-voltage protection prevents damage from overvoltage conditions. If the VDD voltage exceeds 28V by open feedback condition, OVP is triggered. The OVP has a de-bounce time (typcal 250µs) to prevent false trigger by switching noise. It also protects other switching devices from over voltage. FSEZ1216 1 2 3 4 CS DRAIN 8 COMR SGND COMI VDD COMV VS 7 RS1 6 5 RS2 FSEZ1216 — Primary-Side-Regulation PWM Integrated Power MOSFET Leading-Edge Blanking (LEB) Over-Temperature Protection (OTP) A built-in temperature-sensing circuit shuts down PWM output if the junction temperature exceeds 140°C. Figure 29. Startup Circuit Brownout Protection FSEZ1216 detects the line voltage using auxiliary winding voltage since the auxiliary winding voltage reflects the input voltage when the MOSFET is turned on. The VS pin is clamped at 1.15V while the MOSFET is turned on and brownout protection is triggered if the current out of the VS pin is less than IVS-UVP (typical 180μA) during the MOSFET conduction. Protections The FSEZ1216 has several self-protective functions, such as Over-Voltage Protection (OVP), OverTemperature Protection (OTP), and brownout protection. All the protections except OTP are implemented as auto-restart mode. Once the fault condition occurs, switching is terminated and the MOSFET remains off. This causes VDD to fall. When VDD reaches the VDD turn-off voltage of 5V, the current consumed by FSEZ1216 reduces to the startup current (typically 10µA) and the current supplied startup resistor charges the VDD capacitor. When VDD reaches the turnon voltage of 16V, FSEZ1216 resumes its normal operation. In this manner, the auto-restart alternately © 2009 Fairchild Semiconductor Corporation FSEZ1216 • Rev. 1.0.1 Pulse-by-Pulse Current Limit When the sensing voltage across the current sense resistor exceeds the internal threshold of 1.4V, the MOSFET is turned off for the remainder of switching cycle. In normal operation, the pulse-by-pulse current limit is not triggered since the peak current is limited by the control loop. www.fairchildsemi.com 12 Application Fairchild Devices Input Voltage Range Output Cell Phone Charger FSEZ1216 90~265VAC 5V/0.78A (3.9W) Features High efficiency (>66% at full load) meeting Energy StarSM V2.0 and CEC regulation Low standby power consumption (Pin=0.095W for 115VAC and Pin=0.138W for 230VAC) Tight output regulation (CV:±5%, CC:±7%) 74 6 72 5 Efficiency (%) Output Voltage (V) 115V60Hz (68.7% avg) 70 230V50Hz (66.9% avg) 68 66 66.3% : Energy Star V2.0 (Nov. 2008) 4 3 AC90V AC120V AC230V AC264V 2 64 1 62 62.2% : CEC (2008) 25 50 75 0 100 0 100 200 300 Load (%) 400 500 600 700 800 Output Current (mA) Figure 31. Measured Efficiency and Output Regulation 1nF 30Ω CSN2 RSN2 1mH + 1N4007 1N4007 1N4007 1N4007 1kΩ CDL2 CDL1 4.7µF 4.7µF LP 15µH SB260 VDL RSTART 2MΩ 4.7µH RSN1 CSN1 100kΩ 1nF RDAMP IO VO DR N1 N3 CO 470µF 270Ω DSN 1N4007 1N4007 DDD CDD AC Line 900 FSEZ1216 — Primary-Side-Regulation PWM Integrated Power MOSFET Typical Application Circuit (Primary-Side Regulated Flyback Charger) CP 220µF RPL 1kΩ N2 10µF FSEZ1216 1 2 100kΩ RCS 1.4Ω RCOMR 3 4 CS DRAIN COMR SGND COMI COMV VDD VS 8 RS1 7 115kΩ 6 5 RS2 1µF 24.9kΩ CCOMR 10nF 68nF CCOMI 200kΩRCOMI CCOMV CS RCOMV 43kΩ 47pF Figure 32. Schematic of Typical Application Circuit © 2009 Fairchild Semiconductor Corporation FSEZ1216 • Rev. 1.0.1 www.fairchildsemi.com 13 FSEZ1216 — Primary-Side-Regulation PWM Integrated Power MOSFET Typical Application Circuit (Continued) Transformer specification Core: EE16 Bobbin: EE16 Pin Specifications Primary-Side Inductance 1－3 2.3mH ± 5% 100kHz, 1V Primary-Side Effective Leakage 1－8 65μH ± 5%. Short one of the secondary windings © 2009 Fairchild Semiconductor Corporation FSEZ1216 • Rev. 1.0.1 Remark www.fairchildsemi.com 14 9.83 9.00 6.67 6.096 8.255 7.61 3.683 3.20 5.08 MAX 7.62 0.33 MIN 3.60 3.00 (0.56) 2.54 0.56 0.355 0.356 0.20 1.65 1.27 9.957 7.87 7.62 FSEZ1216 — Primary-Side-Regulation PWM Integrated Power MOSFET Physical Dimensions NOTES: UNLESS OTHERWISE SPECIFIED A) THIS PACKAGE CONFORMS TO JEDEC MS-001 VARIATION BA B) ALL DIMENSIONS ARE IN MILLIMETERS. C) DIMENSIONS ARE EXCLUSIVE OF BURRS, MOLD FLASH, AND TIE BAR EXTRUSIONS. D) DIMENSIONS AND TOLERANCES PER ASME Y14.5M-1994 E) DRAWING FILENAME AND REVSION: MKT-N08FREV2. Figure 33. 8-Lead, Dual Inline Package (DIP-8) Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/. © 2009 Fairchild Semiconductor Corporation FSEZ1216 • Rev. 1.0.1 www.fairchildsemi.com 15 FSEZ1216 — Primary-Side-Regulation PWM Integrated Power MOSFET © 2009 Fairchild Semiconductor Corporation FSEZ1216 • Rev. 1.0.1 www.fairchildsemi.com 16 www.fairchildsemi.com AN-6067 Design and Application of Primary-Side Regulation (PSR) PWM Controller FAN100 / FAN102 / FSEZ1016A / FSEZ1216 Abstract Features This application note describes a typical charger using the PSR controller. Both the features of this controller, as well as the operation of the power supply adaptor, are presented in detail. Based on the proposed design guideline, a design example with detailed parameters is given to demonstrate the superior performance of the controller. Applications Battery chargers for cellular phones, cordless phones, PDAs, digital cameras, power tools Optimal choice for the replacement of linear transformers and RCC SMPS Constant-Voltage (CV) and Constant-Current (CC) Control without Secondary-Feedback Circuitry Accurate Constant Current Achieved by Fairchild’s Proprietary TRUECURRENT™ Technique Green-Mode Function: PWM Frequency Decreasing Linearly Fixed PWM Frequency at 42kHz with Frequency Hopping to Solve EMI Problems Low Startup Current: 10μA (Typical) Low Operating Current: 3.5mA (Typical) Peak-Current-Mode Control Cycle-by-Cycle Current Limiting VDD Over-Voltage Protection (OVP) VDD Under-Voltage lockout (UVLO) Gate Output Maximum Voltage Clamped at 18V Fixed Over-Temperature Protection (OTP) Cable Compensation for Tight CV Regulation (FAN102 / FSEZ1216) PSR PWM Controller FAN100 FAN102 FSEZ1016A FSEZ1216 PSR PWM Controller FAN100 + Cable Compensation FAN100 + MOSFET (1A/600V) FAN102 + MOSFET (1A/600V) Pin Configurations Figure 1. FAN100 © 2008 Fairchild Semiconductor Corporation Rev. 1.0.1 • 1/26/10 Figure 2. FAN102 Figure 3. FSEZ1016A Figure 4. FSEZ1216 www.fairchildsemi.com AN-6067 APPLICATION NOTE Typical Applications Vbus 3 COMI 8 3 COMI CS 1 4 COMV PGND 2 6 GND GATE 4 COMV 6 7 VDD VS 5 7 VDD SGND VS 5 GATE 8 CS 1 COMR 2 FAN100 Figure 5. FAN100 Figure 6. FAN102 (FAN100 + Cable Compensation) Vbus Vbus 6 VDD 3 COMI 4 COMV 2 GND 6 VDD VS 5 DRAIN CS 8 3 COMI 1 4 COMV N.C. 7 7 DRAIN CS 8 1 COMR 2 FSEZ1216 FSEZ1016A Figure 7. FSEZ1016A (FAN100 + MOSFET) © 2008 Fairchild Semiconductor Corporation Rev. 1.0.1 • 1/26/10 GND VS 5 Figure 8. FSEZ1216 (FAN102 + MOSEFET) www.fairchildsemi.com 2 AN-6067 APPLICATION NOTE Block Diagrams Figure 9. FSEZ1016A (FAN100 + MOSFET) © 2008 Fairchild Semiconductor Corporation Rev. 1.0.1 • 1/26/10 www.fairchildsemi.com 3 AN-6067 APPLICATION NOTE Block Diagrams (Continued) Figure 10. FSEZ1216 (FAN102 + MOSFET) © 2008 Fairchild Semiconductor Corporation Rev. 1.0.1 • 1/26/10 www.fairchildsemi.com 4 AN-6067 APPLICATION NOTE Introduction protection function shuts down the controller with auto recovery when over heating occurs. This highly integrated PSR PWM controller contains several features to enhance the performance of low-power flyback converters. The patented topology of the PSR controller allows for simplified of circuit designs, particularly battery charger applications. CV and CC control can be accurately achieved without secondary feedback circuitry. With the addition of frequency-hopping in PWM operation, EMI problems can be solved using minimized filter components. As a result, a low-cost, smaller, and lighter charger is produced when compared to a conventional design or a linear transformer. By using the PSR controller, a charger can be implemented with few external components and at a minimized cost. Internal Block Operation Constant Voltage Output Regulation PSR controller’s innovative method can achieve accurate output CV/CC characteristic without voltage and current sensing circuitry on the secondary side. The application circuit and a conceptualized internal block diagram relating to the constant voltage regulation are shown in Figure 11, and the key waveform is shown in Figure 12. The secondary output status is taken from the primary auxiliary winding when the MOSFET is off. A unique sampling method is used to acquire a duplication of the output voltage (Vsah) and the output diode discharge time (tdis). The sampled voltage (Vsah) is then compared with the precise internal reference voltage (Vref) to determine the on-time of the MOSFET by modulating error amplifier’s output. This inexpensive method achieves accurate output voltage regulation. To minimize standby power consumption, the proprietary green-mode function provides off-time modulation to linearly decrease the PWM frequency under light-load conditions. This green-mode function is designed to help the power supply meet power conservation requirements. The startup current is only 10µA, which allows for the use of large startup resistance for further power savings. The PSR controller also provides numerous protection functions. The VDD pin is equipped with over-voltage protection and under-voltage lockout. Pulse-by-pulse current limiting and CC control ensure over-current protection during heavy loads. The GATE output is clamped at 15V to protect the external/internal MOSFET from over-voltage damage. Additionally, the internal over-temperature- Vin Naux iS IO Nsec Npri CO R1 S/H − n :1 Vref VS RO + VO iP PWM Vsah R2 CS COMV RS Figure 11. Internal Block of Constant Voltage Output Operation © 2008 Fairchild Semiconductor Corporation Rev. 1.0.1 • 1/26/10 www.fairchildsemi.com 5 AN-6067 APPLICATION NOTE Constant Current Output Regulation Green-Mode Operation As shown in Figure 12, the output current IO can be expressed by Equation 1 when the flyback converter is operated in DCM. As a result, the output current IO can be calculated by the signal ipk, tdis. The PSR controller then determines the on-time of the MOSFET to modulate input power and provide constant output current. The proprietary green-mode function of the PSR controller provides off-time modulation to linearly decrease the PWM frequency at light-load conditions, as low as 500Hz. With the green-mode function, the power supply can easily meet the most stringent of power conservation requirements. Figure 13 shows the characteristics of the PWM frequency vs. the output voltage of the error amplifier (VCOMV). The PSR controller uses the positive, proportional, output load parameter (VCOMV) as an indication of the output load for modulating the PWM frequency. In heavy load conditions, the PWM frequency is fixed at 42KHz. Once VCOMV is lower than VN, the PWM frequency starts to linearly decrease from 42KHz to 500Hz. Figure 14 is a measured waveform at burst-mode operation. Gate Vin Lp iP Ts i pk tdis ton Frequency n ⋅ Vo Lp 2 iS - IO 42KHz 40KHz sampling voltage 1KHz 500Hz VS VG Figure 12. Principal Operation Waveform of the Flyback Converter (DCM) [ 1 ⋅ t dis ⋅ is , pk 2Ts [ Vo(AC) 100mV/Div Gate 10V/Div ] ] 1 ⋅ n p ⋅ i pk ⋅ t dis 2Ts ⎤ V 1 ⎡ = ⋅ ⎢n p ⋅ CS ⋅ t dis ⎥ 2Ts ⎣ RCS ⎦ = VCOMV Figure 13. PWM Frequency vs. VCOMV The current-sense resistor can adjust the value of the constant current. Through better design of the transformer operations under discontinuous current mode, the PSR controller’s proprietary control structure is able to achieve accurate and constant current characteristics. Detailed design guideline for the transformer is introduced in the following section. Io = VN VCOMV 500mV/Div (1) Figure 14. Measured Waveform at Burst-Mode Operation where: is,pk is the peak inductor current of the secondary side, ipk is the peak inductor of primary side. tdis is discharge-time of transformer inductor current. np is the turn ratio between primary and secondary winding. RCS is the current-sense resistor. VCS is the voltage on current-sense resistor. © 2008 Fairchild Semiconductor Corporation Rev. 1.0.1 • 1/26/10 www.fairchildsemi.com 6 AN-6067 APPLICATION NOTE 42kHz frequency, the MOSFET’s on-time is determined by VCOMI to modulate the output current. Frequency Hopping Operation A frequency hopping function is built in to further improve EMI system performance. The frequency hopping period is no longer than 3ms and the PWM switching frequency range is 42kHz +/- 2.6kHz. CC Regulation CV Regulation decreasing output impedance VCOMV VCOMI 4.5V Deep Green Mode Charging Sequence 44.6KHz Figure 17. CV/CC Regulation Charging Sequence +/- 2.6KHz 39.4KHz Temperature Compensation Frequency Hopping Period → 3mS The PSR controller has built-in temperature compensation circuitry to provide constant reliable voltage regulation even at a different ambient temperature. This internal positive temperature coefficient (PTC) compensation current is used to compensate for the temperature due to the forwardvoltage drop of the diode output. Without temperature compensation, the output voltage is distinctly higher in high temperatures than in lower temperature condition, as shown in Figure 18. Figure 15. Gate Signal with Frequency Hopping CV / CC Regulation Battery chargers are typically designed for two modes of operation, constant-voltage charging and constant-current charging. The basic charging characteristic is shown in Figure 16. When the battery voltage is low, the charger operates on a constant current charging. This is the main method for charging batteries and most of the charging energy is transferred into the batteries. When the battery voltage reaches its end-of-charge voltage, the current begins to taper-off. The charger then enters the constant voltage method of charging. Finally, the charging current continues to taper-off until reaching zero. Vo high temp. after compensation at high temp. room temp. Vo(V) CV Regulation Sequence Io CC Regulation Charging Figure 18. Output V-I Curve with Temperature Compensation As shown in Figure 19, the accuracy value of R1 and R2 determines the voltage regulation amount. The suggested deviation for R1 and R2 is a +/-1% tolerance. Temperature Compensation Io(mA) Figure 16. Basic Charging V-I Characteristic As mentioned in the CV regulation region section, the VCOMV modulates MOSFET’s on-time and PWM frequency to provide enough power to the output load. As shown in Figure 17, as the output load increases, VCOMV gradually rises until the system shifts into the CC regulation region. At the same time, VCOMV increases to 4.5V and the MOSEFT’s on time is controlled by VCOMI. However, when power system operates in the CC regulation region at a fixed © 2008 Fairchild Semiconductor Corporation Rev. 1.0.1 • 1/26/10 PTC Vs S/H Auxiliary Winding Vref PSR Controller Figure 19. Temperature Compensation www.fairchildsemi.com 7 AN-6067 APPLICATION NOTE The maximum power dissipation of RIN is: Startup Circuitry When the power is activated, the input voltage charges the hold-up capacitor (C1) via the startup resistors, as shown in Figure 20. As the voltage (VDD) reaches the startup voltage threshold (VDD-ON), the PSR controller activates and drives the entire power supply. PRIN ,MAX − VDD ) 2 dc , max RIN V ≅ dc ,max RIN 2 (3) where Vdc,max is the maximum rectified input voltage. Vdc Take a wide-ranging input (90VAC~264VAC) as an example, Vdc =100V~380V: R IN PRIN ,MAX TD_ON VDD 380 2 = ≅ 96mW 1.5 ×10 6 (4) D1 PSR Controller Built-in Slope Compensation C1 The sensed voltage across the current sense resistor is used for peak-current-mode control and cycle-by-cycle current limiting. Within every switching cycle, the PSR controller produces a positively sloped, synchronized ramp signal. The built-in slope compensation function improves power supply stability and prevents peak-current-mode control from causing sub-harmonic oscillations. GND Figure 20. Single-Step Circuit Connected to the PSR Controller The power-on delay is determined as follows: TD _ ON (V = ⎛ VDD −ON = − RIN ⋅ C1 ⋅ ln⎜⎜1 − ⎝ Vac ⋅ 2 − I DD − ST ⋅ RIN ⎞ ⎟ ⎟ ⎠ Leading Edge Blanking (LEB) Each time the MOSFET is powered on, a spike, induced by the diode reverse recovery and by the output capacitances of the MOSFET and diode, appears on the sensed signal. To avoid premature termination of the MOSEFT, a leadingedge blanking time is introduced in the PSR controller. During the blanking period, the current-limit comparator is disabled and unable to switch off the gate driver. (2) where IDD-ST is the startup current of the PSR controller. Due to the low startup current, a large RIN value, such as 1.5MΩ can be used. With a hold-up capacitor of 4.7µF, the power-on delay TD_ON is less than 3s for a 90VAC input. If a shorter startup time is required, a two-step startup circuit, as shown in Figure 21, is recommended. In this circuit, a smaller C1 capacitor can be used to decrease startup time without a need for a smaller startup resistor (RIN) and increase the power dissipation on the RIN resistor. The energy supporting the PSR controller after startup is mainly from a larger capacitor C2. Under-Voltage Lockout (UVLO) The power-on and off thresholds of the PSR controller are fixed at 16V/5V. During startup, the hold-up capacitor must be charged to 16V through the startup resistor to enable PSR controller. The hold-up capacitor continues to supply VDD until power can be delivered from the auxiliary winding of the main transformer (VDD must not drop below 5V during this startup process). This UVLO hysteresis window ensures that the hold-up capacitor can adequately supply VDD during startup. Vdc R IN VDD Over-Voltage Protection (OVP) TD_ON VDD over-voltage protection prevents damage due to overvoltage conditions. When VDD exceeds 28V due to abnormal conditions, PWM output is turned off. Over-voltage conditions are usually caused by open feedback loops. VDD PSR Controller C1 C2 GND Over-Temperature Protection (OTP) The PSR controller has a built-in temperature sensing circuit to shut down the PWM output if the junction temperature exceeds 145°C. When the PWM output shuts down, the VDD voltage gradually drops to the UVLO voltage. Some of the internal circuits shut down and VDD gradually starts Figure 21. Two Steps of Providing Power to the PSR Controller © 2008 Fairchild Semiconductor Corporation Rev. 1.0.1 • 1/26/10 www.fairchildsemi.com 8 AN-6067 APPLICATION NOTE increasing again. When VDD reaches 16V, all the internal circuits, including the temperature sensing circuit, start operating normally. If the junction temperature is still higher than 145°C, the PWM controller shuts down immediately. This continues until the temperature drops below 120°C. For example, a power board for a charger application is 5V/1A. Short the COMR pin to GND first and measure the output voltage from light load to maximum load. If the output voltage with cable is 4.7V at 1A, the percentage to 5V is 6%. Calculate the RCOMR as: RCOMR = GATE Output The PSR controller BiCMOS output stage is a fast totem pole gate driver. Cross conduction design elimination was used to minimize heat dissipation, increase efficiency, and enhance reliability. The output driver is clamped by an internal 15V Zener diode for the protection of power MOSFET against over-voltage gate signals. 6 ≅ 59.5KΩ 100.8 × 10 −6 (6) Choose the approximate value of RCOMR and let the output voltage compensate gradually. Figure 23 is RCOMR compared to percentage curve for reference. 12 10 Percentage (%) Brownout Protection The PSR controller has a built-in brownout protection circuit to shut down the PWM output. As the input voltage decreases, the flowing current from VS pin is less than IVSUVP, the PWM output shuts down immediately and enters an auto restart mode. The VDD voltage gradually drops to the UVLO voltage. 8 6 4 2 0 10 20 30 39 51 60 R COMR (K ohm) 68 81 91 100 Figure 23. RCOMR vs. Percentage R VS Vs Lab Note Auxiliary Before reworking or soldering / desoldering on the power supply, discharge the primary capacitors by way of the external bleeding resistor. If not, the PWM IC may be destroyed by external high-voltage discharge during the soldering / desoldering. Winding I VS-UVP PSR Controller MOS turns on Figure 22. Brownout Protection Cable Compensation The FAN102/FSEZ1216 PWM controller has a cable compensation function used to compensate the output voltage drop due to output cable loss. Use an external resistor connected from COMR pin to GND adjusts the amount of cable compensation. In CV regulation control, the on-time of MOSFET only regulates on-board voltage, not including output cable. Different cable wire gauge or length results in different output voltage. As previous mentioned in the CC regulation control section that can calculate the output current. This calculated signal can provide the controller the output load condition and determine the amount of cable compensation, then rescue output voltage drop. To calculate compensation percentage, use the equation below: RCOMR = Percentage 100.8 × 10 −6 © 2008 Fairchild Semiconductor Corporation Rev. 1.0.1 • 1/26/10 (5) www.fairchildsemi.com 9 AN-6067 APPLICATION NOTE Determine Maximum and Minimum Input Voltage Figure 26 shows the corrected input voltage waveform. The red line shows ripple voltage on the bulk capacitor and the minimum and maximum voltage on the bulk capacitor is expressed in equations 7 and 8, respectively. The CBULK is the input capacitor and a typical value is 2-3µF per watt of output power for wide range input voltage (90-264V). Application Information Transformer Design The transformer inductor current must operate in DCM under any conditions. A typical output V-I curve is shown in Figure 24. For discontinuous current mode operation, the transformer inductor should be small enough to meet this condition. Point “B” is the lowest output voltage within the CC regulation and the widest discharge time of the transformer inductor due to the reflected voltage on the primary inductor. It is the easiest into CCM condition for transformer inductor. Vin.min Assume 2.5mS Point “A” is the maximum output power of the power system. Ensure that the magnetic flux density falls within 0.25~0.3 Tesla, considered a safe range. The number of turns for primary transformer inductor can be determined on point “A.” Figure 25 shows the characteristic curve of turn ratio and transformer inductance. Vo Figure 26. Bridge Rectifier and Bulk Capacitor Voltage Waveform Vin. min = 2 ⋅ Vac ,min 2 - maximum output power (determine turn number ) 2 ⋅Vo ⋅ I o ⋅ (1- 0.3) η ⋅ Cbulk ⋅ 120 (7) Vin.max = 2 ⋅Vac.max (8) A Determine the Turn Ratio The transformer turn ratio (np=Npri/Nsec) is an important parameter of the flyback converter; it affects the maximum duty ratio when the input voltage is at a minimum value. It also influences the voltage stresses on the MOSFET and the secondary rectifier. The permissible voltage stresses and the maximum voltage stresses on the MOSFET, as well as the secondary rectifier, can be expressed as: determine primary inductor B Io Figure 24. Critical Operating Points to Determine the Transformer VDS .max = Vin.max + n p ⋅ (Vo + V f ) B=0.5V B=1V B=1.5V B=2V VF .max = 3.5 inductance(mH) 3 Vin.max + Vo np (9) (10) The leakage spike due to leakage inductance on the MOSFET and rectifier must also be taken into account. 2.5 2 1.5 Determine Transformer Inductance Determine the VDD voltage level and if the output voltage is defined. The turn ratio between auxiliary winding and secondary winding can be calculated as: 1 0.5 Io = 1A, Vf = 0.45V 0 5 6 7 8 9 10 11 12 13 14 15 na = n(turn ratio) Figure 25. Characteristic Curve of Turn Ratio and Inductance VDD + V fa VO + V f (11) where VDD is voltage on VDD cap, usually ranging from about 15V~20V. In the CC regulation region, on point “B,” the power system shuts down if the output voltage is too low and the VDD © 2008 Fairchild Semiconductor Corporation Rev. 1.0.1 • 1/26/10 www.fairchildsemi.com 10 AN-6067 APPLICATION NOTE voltage reaches the turn-off threshold voltage of the PSR controller. Therefore, if na was calculated, the Vo,“B” can be obtained as: ⎛ V fa + 6.75 - V f ⋅ na ⎞ VO ," B " = ⎜ ⎟ na ⎝ ⎠ Determine Primary Inductance Turn Number Based on Faraday’s law and the peak inductor current, the minimum turns for the primary inductance is calculated as: N pri = (12) Lp ⋅ i pk ," A" Bmax ⋅ Ae ⋅ 106 (17) where: where: Vfa is forward-voltage of rectifier diode of auxiliary winding. Bmax is the saturation magnetic flux density, Vf is forward-voltage of output diode. Ae is the effective area of the core-section. 6.75V is typically the turn-off threshold voltage of the PSR controller. The number of turns for the secondary winding is defined as: N sec = The maximum duty ratio can be calculated by using a point “B” output condition: d on.max," B " = n p ⋅ (Vo ," B " + V f ) Vin.min," B " + n p ⋅ (Vo ," B " + V f ) Lp = 2 ⋅Vo," B " ⋅ I o ⋅ f s N aux = na ⋅ Nsec (14) ⎡n ⎤ R1 = R2 ⋅ ⎢ a ⋅ (VO + V f ) − 1⎥ ⎥⎦ ⎣⎢ Vref η,”B” is the estimated system efficiency of point “B.” If no values are available, use 0.45~0.5 as an initial value. fs is the PWM frequency. As discussed in the Constant Current Output Regulation section, the region of constant current output operation can be adjusted by the current-sense resistor. After the turn ratio (np) has been determined, the relationship between the output current IO and current sense resistor Rs is expressed as: (15) where Ts is the switching period. The primary peak inductor current (IPK) of point “A” at full load and low line input voltage condition is: i pk ," A" = Vin.min," A" Lp ⋅ don.max," A" ⋅ TS © 2008 Fairchild Semiconductor Corporation Rev. 1.0.1 • 1/26/10 (20) where Vref=2.5V, R2 is typically set to 15~20KΩ. After the primary inductance is calculated, the maximum duty ratio of point “A” can be expressed as: d on . max," A" (19) Determine the Divider Resistor (R1) and CurrentSense Resistor (RS) Once the output voltage VO and auxiliary winding have been defined, the feedback signal divider resistor, R1, can be calculated as: where: 2 ⋅ VO ," A" ⋅ I O ⋅ LP = η," A" ⋅ Vin . min," A" 2 ⋅ Ts (18) np Once the secondary winding has been calculated, the number of turns for the auxiliary winding is defined as: (13) The transformer inductance (Lp) is designed specifically for DCM operation and a CC tolerance of +/-10% should be considered. The transformer inductance can be obtained as: η," B " ⋅ Vin. min," B "2 ⋅ d max," B " 2 N pri RS = 0.111875 ⋅ n p IO (21) As Figure 27 shows, a design spreadsheet can be used to calculate the transformer design and select the power system components for a first prototype. A 5V/1A design example is shown in Figure 27. (16) www.fairchildsemi.com 11 AN-6067 APPLICATION NOTE Figure 27. Calculated System Parameter by Design Spreadsheet The parameters in Figure 27 can be found in the corresponding components in Figure 28. Vdc Rin Vdc - VFa + Naux + VF - + VO Nsec Npri R1 VDD VDD Cap. − + n : n p :1 Vds a VS Vs Cap. R2 RS - Figure 28. Application Circuit Primary Winding Transformer Structure N1 Drain N2 Secondary Winding 2 MOS ' s As mentioned in the Constant Voltage Output Regulation section, the PSR controller incorporates a proprietary control design to achieve CV/CC regulations. A correct sampling voltage of the auxiliary winding is critical to the CV/CC performance. Therefore, the coupling of the auxiliary winding and the secondary winding should be precise. The suggested transformer structure is shown in Figure 29 and Figure 30. The coupling coefficient between the secondary winding and the auxiliary winding can be effectively improved by sloughing off the EMI shielding between auxiliary winding and secondary winding. Further effectiveness is achieved by increasing the coupling area through a well-paved the auxiliary winding on the top layer. 6 1 Vin 8 3 Auxiliary Winding 4 N3 EMI Shielding Figure 29. Transformer Winding 3 6 EMI Shielding 4 8 Auxiliary Winding ( N 3) Secondary Winding ( N 2) ( Insulated ) 1 Primary Winding ( N1) 2 EMI Shielding Figure 30. Recommended Transformer Structure © 2008 Fairchild Semiconductor Corporation Rev. 1.0.1 • 1/26/10 www.fairchildsemi.com 12 AN-6067 APPLICATION NOTE Effect of the Vs Pin Capacitor A VS capacitor with 22~68pF placed closely between Vs pin and the GND pin is recommended. The capacitor is used to bypass switching induced noise and keep the accuracy of the sampled voltage. The value of the capacitor affects the load regulation and constant current performance. Figure 31 illustrates the measured waveform on the Vs pin with a different VS capacitor. If a higher value VS capacitor is used, the charging time becomes longer and the sampled voltage is higher than the actual value. Figure 32 shows the effect on the sampled voltage with a different VS capacitor. No-Load Figure 33 shows a measured Vs pin waveform at a no-load condition. As illustrated, the feedback voltage is too narrow. Additionally, a large VS capacitor causes the inaccurate sampling of the voltage; resulting in the rising of the output voltage. Figure 24 shows the influence of the VS capacitor on the V-I curve. VS Gate COMV Vf Figure 33. Measured Vs Pin Waveform at No Load Vo Lower Vs Cap. Higher Vs Cap. Io Figure 34. Comparison of V-I Curve with Different Vs Capacitor Effect of VDD and Snubber Capacitors VDD voltage and snubber capacitors are related to the feedback signal inaccuracy and cause output voltage to rise at no-load condition. If the VDD capacitor is not big enough, the decreasing PWM frequency at no-load condition causes VDD voltage to drop quickly. In such a condition, the feedback signal is dominated by the VDD voltage, but not the secondary output voltage. To avoid this, it is recommended the VDD capacitor value be larger than 4.7µF(6.8~10µF). Figure 31. Measured Waveform with Different VS Capacitor higher Vs Cap lower Vs Cap Vs pin waveform sampling voltage On the other hand, the value of the snubber capacitor also affects the output voltage performance. When the MOSEFT is turned off, the polarity of the transformer primary side inductor is reversed and the energy stored in the transformer inductor is delivered to the secondary to supply load current. In the meantime, if the output voltage is higher than the voltage on the secondary winding (Vsec), the output diode is still reversed. The resulting voltage Vpri is then applied to the primary inductor, Lp, which charges the snubber capacitor. The charge time influences the feedback voltage signal on the auxiliary winding. It is recommended that the snubber capacitor remain under 472pF(332~102pF). sampling voltage No - Load Figure 32. Effect on Sampling Voltage with Different VS Capacitor © 2008 Fairchild Semiconductor Corporation Rev. 1.0.1 • 1/26/10 www.fairchildsemi.com 13 AN-6067 APPLICATION NOTE - V fa + Vin Ra + R1 VDD SGP100 VDD Cap. + Vaux Vpri - - VS Vs Cap. + Vf - + Vsec + VO - − na : n p : 1 VO > Vsec R2 Figure 35. VDD and Snubber Capacitors Effect on Output Voltage Reducing No-Load Output Voltage with a “Dummy” Load At no-load and very light load conditions, due to the very low PWM frequency caused by feedback signal deviations and output voltage rises, especially at low-line input voltage condition. Increasing the addition of a dummy load can fix this problem. Figure 36 shows the effect of a higher and lower dummy load on the V-I curve. The level of the dummy load is suggested at about 25~100mW. Vo lower snubber cap, higher VDD cap , dummy load higher snubber cap, lower VDD cap , dummy load Io Figure 36. Dummy Load Effect on Output Characteristic © 2008 Fairchild Semiconductor Corporation Rev. 1.0.1 • 1/26/10 www.fairchildsemi.com 14 AN-6067 APPLICATION NOTE PCB Layout Considerations High-frequency switching current / voltage make PCB layout a very important design issue. Good PCB layout minimizes excessive EMI and helps the power supply survive during surge/ESD tests. Suggestion for the Ground Connections GND 3→2→4→1: May make it possible to avoid common impedance interference for the sense signal. Regarding the ESD discharge path, the charges go from secondary through the transformer stray capacitance to GND2 first. Then the charges go from GND2 to GND1 and back to the mains. It should be noted that control circuits should not be placed on the discharge path. General Guidelines The numbers in the following guidelines refer to Figure 37. To improve EMI performance and reduce line frequency ripples, the output of the bridge rectifier should be connected to capacitors C1 and C2 first, then to the switching circuits. 5 Should a point-discharge route to bypass the static electricity energy. As shown in Figure 38, it is suggested to map out this discharge route. The high-frequency current loop is in C2 – Transformer – MOSFET – R7 – C2. The area enclosed by this current loop should be as small as possible. Start in secondary GND to the positive terminal of C2, then to front terminal of bridge rectifier. If this discharge route is connected to the primary GND, it should be connected to the negative terminal of C2 (GND1) directly. Keep the traces (especially 4→1) short, direct, and wide. High voltage traces related to the drain of MOSFET and RCD snubber should be kept far way from control circuits to prevent unnecessary interference. If a heatsink is used for the MOSFET, connect this heatsink to a ground. However, the creepage distance between these two pointed ends should be long enough to satisfy the requirements of applicable standards. As indicated by 3, the ground of the control circuits should be connected first, then to other circuitry. As indicated by 2, the area enclosed by the transformer aux winding, D1 and C3, should also be kept small. Place C3 close to the PSR controller for good decoupling. 5 R13 5 T1 BD1 R8 C1 C6 C2 D4 L1 R1 1 D1 R2 C3 R3 U1 7 3 COMI C8 R10 C7 R9 VS 5 VDD 4 COMV 6 SGND GATE CS PGND PSR Controller 8 1 2 D3 C5 R4 R5 R6 2 R7 4 3 Figure 37. Layout Consideration © 2008 Fairchild Semiconductor Corporation Rev. 1.0.1 • 1/26/10 www.fairchildsemi.com 15 AN-6067 APPLICATION NOTE PCB Layout Considerations (Continued) Figure 38. PCB Layout Example (5V/1A, 5W Power Board) © 2008 Fairchild Semiconductor Corporation Rev. 1.0.1 • 1/26/10 www.fairchildsemi.com 16 AN-6067 APPLICATION NOTE Reference Circuits R13 R11 L1 C8 D4 L2 T1 BD1 R8 C1 C5 C2 C9 C10 R12 D3 R1 D1 R2 C3 R3 U1 7 VDD 3 COMI R4 VS 5 C4 C7 R10 C6 R9 4 COMV 6 SGND GATE 8 CS 1 PGND 2 R5 R6 R7 Figure 39. Application Circuit FAN100 (5V/1A) BOM List Symbol Component Symbol Component R1 Resistor 1.5MΩ 1/2W D4 Diode 5A/60V SB560 R2 Resistor 4.7Ω C1 Electrolytic Capacitor 1µF/400V R3 Resistor 115KΩ 1% C2 Electrolytic Capacitor 10µF/400V R4 Resistor 18KΩ 1% C3 Electrolytic Capacitor 10µF/50V R5 Resistor 47Ω C4 MLCC X7R 22pF R6 Resistor 100Ω C5 Snubber Capacitor 472pF/1KV R7 Resistor 1.4Ω 1/2W 1% C6 MLCC X7R 683pF R8 Resistor 100KΩ 1/2W C7 MLCC X7R 103pF R9 Resistor 200KΩ C8 MLCC 102pF/100V R10 Resistor 30KΩ C9 Electrolytic Capacitor 560uF/10V L-ESR R11 Resistor 47Ω C10 Electrolytic Capacitor 330µF/10V L-ESR R12 Resistor 510Ω L1 Inductor 1mH R13 WireWound Resistor 18Ω L2 Inductor 5µH BD1 Rectifier Diode 1N4007 *4 Q1 Fairchild 2A/600V 2N60 TO-251 D1 Diode 1A/200V FR103 U1 FAN100 D3 Diode 1A/1000V 1N4007 © 2008 Fairchild Semiconductor Corporation Rev. 1.0.1 • 1/26/10 TR1 EE-16 Lm=1.5mH Pri:Sec:Aux=135:10:33 www.fairchildsemi.com 17 AN-6067 APPLICATION NOTE Reference Circuits (Continued) R10 R8 L1 C8 D4 L2 T1 BD1 R5 C1 C5 C2 C9 C10 D3 R9 R1 D1 C3 R2 U1 6 VDD VS R3 5 C4 C7 R7 3 COMI 4 COMV DRAIN CS 8 1 R4 C6 R6 2 GND N.C. 7 Figure 40. Application Circuit FSEZ1016A (FAN100 + MOSFET) (5V/1A) BOM List Symbol Symbol Component Component R1 Resistor 1.5MΩ C1 Electrolytic Capacitor 1µF/400V R2 Resistor 127KΩ 1% C2 Electrolytic Capacitor 10µF/400V R3 Resistor 20KΩ 1% C3 Electrolytic Capacitor 10µF/50V R4 Resistor 1.36Ω 1/2W 1% C4 MLCC X7R 47pF R5 Resistor 100KΩ 1/2W C5 Snubber Capacitor 472pF/1KV R6 Resistor 200KΩ C6 MLCC X7R 683pF R7 Resistor 39KΩ C7 MLCC X7R 103pF R8 Resistor 47Ω C8 MLCC 102pF/100V R9 Resistor 510Ω C9 Electrolytic Capacitor 560µF/10V R10 WireWound Resistor 18Ω C10 Electrolytic Capacitor 330µF/10V BD1 Rectifier Diode 1N4007 *4 L1 Inductor 1mH D1 Diode 1A/200V FR103 L2 Inductor 5µH D3 Diode 1A/1000V 1N4007 U1 FSEZ1016A D4 Diode 5A/60V SB560 © 2008 Fairchild Semiconductor Corporation Rev. 1.0.1 • 1/26/10 TR1 EE-16 Lm=1.5mH Pri:Sec:Aux=135:10:33 www.fairchildsemi.com 18 AN-6067 APPLICATION NOTE Reference Circuits (Continued) R13 R11 L1 D4 C9 L2 T1 BD1 C6 R8 C1 C2 C10 C11 R12 D3 R1 D1 C3 R3 U1 7 VDD VS R4 5 C5 3 COMI C8 R10 C7 R9 4 COMV 6 GND GATE CS COMR 8 R5 1 2 Q1 R6 R7 R2 C4 Figure 41. Application Circuit FAN102 (5V/1A) BOM List Symbol Component Symbol Component Symbol Component R1 Resistor 1.5MΩ 1/2 W D3 Diode 1A/1000V 1N4007 Q1 1A/600V 1N60 TO-251 R2 Resistor 82KΩ 1% D4 Diode 5A/60V SB560 TR1 EE-16 Lm=1.5mH Pri:Sec:Aux=135:10:33 R3 Resistor 110KΩ 1% C1 Electrolytic Capacitor 1µF/400V R4 Resistor 18KΩ 1% C2 Electrolytic Capacitor 10µF/400V R5 Resistor 47Ω C3 Electrolytic Capacitor 10µF/50V R6 Resistor 100Ω C4 MLCC 104pF R7 Resistor 1.4Ω 1/4W 1% C5 MLCC X7R 22pF R8 Resistor 100KΩ 1/2W C6 Snubber Capacitor 472pF/1KV R9 Resistor 200KΩ C7 MLCC X7R 683pF R10 Resistor 47KΩ C8 MLCC X7R 103pF R11 Resistor 20Ω C9 MLCC 102pF/100V R12 Resistor 510Ω C10 R13 WireWound Resistor 18Ω C11 BD1 Rectifier Diode 1N4007 *4 L1 Inductor 1mH 1/2W Diode 1A/200V FR103 L2 Inductor 5µH D1 © 2008 Fairchild Semiconductor Corporation Rev. 1.0.1 • 1/26/10 U1 FAN102 Electrolytic Capacitor 560µF/10V L-ESR Electrolytic Capacitor 330µF/10V L-ESR www.fairchildsemi.com 19 AN-6067 APPLICATION NOTE Reference Circuits (Continued) R10 R8 L1 C8 D4 L2 T1 BD1 R5 C1 C5 C2 C9 C10 D3 R9 R1 D1 C3 R2 U1 6 VDD VS R3 5 C4 C7 R7 C6 R6 3 COMI DRAIN 8 4 COMV CS 1 7 GND COMR 2 R4 R11 C11 Figure 42. Application Circuit FSEZ1216 (5V/1A) BOM List Symbol Component Symbol Component Symbol Component R1 Resistor 1.5M Ω D4 Diode 5A/60V SB560 R2 Resistor 110KΩ 1% C1 Electrolytic Capacitor 1µF/400V R3 Resistor 18KΩ 1% C2 Electrolytic Capacitor 10µF/400V R4 Resistor 1.4Ω 1/2W 1% C3 Electrolytic Capacitor 10µF/50V R5 Resistor 100KΩ 1/2W C4 MLCC X7R 47pF R6 Resistor 200KΩ C5 Snubber Capacitor 472pF/1KV R7 Resistor 47KΩ C6 MLCC X7R 683pF R8 Resistor 47Ω C7 MLCC X7R 103pF R9 Resistor 510Ω C8 MLCC 102pF/100V R10 WireWound Resistor 18Ω C9 Electrolytic Capacitor 560µF/10V R11 Resistor 82KΩ 1% C10 Electrolytic Capacitor 330µF/10V BD1 Rectifier Diode 1N4007 *4 C11 MLCC X7R 104pF D1 Diode 1A/200V FR103 L1 Inductor 1mH D3 Diode 1A/1000V 1N4007 L2 Inductor 5µH © 2008 Fairchild Semiconductor Corporation Rev. 1.0.1 • 1/26/10 U1 TR1 FSEZ1216 EE-16 Lm=1.5mH Pri:Sec:Aux=135:10:33 www.fairchildsemi.com 20 AN-6067 APPLICATION NOTE Related Datasheets FAN100 — Primary-Side Regulation PWM Controller FAN102 — Primary-Side Regulation PWM Controller FSEZ1016A — Primary-Side Regulation PWM with Integrated Power MOSFET FSEZ1216 — Primary-Side Regulation PWM with Integrated Power MOSFET DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION, OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, or (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in significant injury to the user. © 2008 Fairchild Semiconductor Corporation Rev. 1.0.1 • 1/26/10 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com 21