ITE IT6605

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IT6605
ITE TECH. INC.
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Dual-Port HDMI 1.4 Receiver with 3D Support
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Feb-2012 Rev:0.92
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IT6605
General Description
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The IT6605 is a dual-port HDMI receiver, fully compatible with HDMI 1.3, compatible with HDMI 1.4a
3D and HDCP 1.4 and also backward compatible to DVI 1.0 specifications. The IT6605 with its Deep
Color capability (up to 36-bit) ensures robust reception of high-quality uncompressed video content,
along with state-of-the-art uncompressed and compressed digital audio content such as DTS-HD and
Dolby TrueHD in digital televisions and projectors. The IT6605 also supports all the primary 3D
formats which are compliant with the HDMI 1.4a 3D specification.
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Aside from the various video output formats supported, the IT6605 also receives and provides up to 8
channels of I2S digital audio outputs, with sampling rate up to 192kHz and sample size up to 24 bits,
facilitating direct connection to industry-standard low-cost audio DACs. Also, an S/PDIF output is
provided to support up to compressed audio of 192kHz frame rate. Super Audio Compact Disc (SACD)
is supported at up to 8 channels and 88.2kHz through DSD (Direct Stream Digital ports) ports.
The High-Bit Rate (HBR) audio is also provided by the IT6605 in two interfaces: with the four I2S input
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ports or the S/PDIF input port. With both interfaces the highest possible HBR frame rate is supported
at up to 768kHz.
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Each IT6605 comes preprogrammed with an unique HDCP key, in compliance with the HDCP 1.4
standard so as to provide secure transmission of high-definition content. Users of the IT6605 need not
purchase any HDCP keys or ROMs.
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The IT6605 is pin compatible with the CAT6023, the previous HDMI 1.3 receiver.
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Dual-port HDMI 1.4 receiver
Pin compatible with CAT6023
Compliant with HDMI 1.3, HDMI 1.4a 3D, HDCP 1.4 and DVI 1.0 specifications
Supporting link speeds of up to 2.25Gbps (link clock rate of 225MHz).
Supporting all the primary 3D formats which are compliant with the HDMI 1.4a 3D specification.
Š Supporting 3D video up to [email protected]/59.95/60Hz, [email protected]/24/29.97/30Hz,
[email protected]/59.94/60/Hz, [email protected]/24/29.97/30Hz, [email protected]/59.94/60Hz
Š Supporting formats: Framing Packing, Side-by-Side ( half ), Top-and-Bottom.
ƒ Video output interface supporting digital video standards such as:
Š 24/30/36-bit RGB/YCbCr 4:4:4
Š 16/20/24-bit YCbCr 4:2:2
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IT6605
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Š 8/10/12-bit YCbCr 4:2:2 (ITU BT-656)
Š 12/15/18-bit double data rate interface (data bus width halved, clocked with both rising and
falling edges) for RGB/YCbCr 4:4:4
Š 24/30/36-bit double data rate interface (full bus width, pixel clock rate halved, clocked with both
rising and falling edges)
Š Input channel swap
Š MSB/LSB swap
Bi-direction Color Space Conversion (CSC) between RGB and YCbCr color spaces with
programmable coefficients.
Up/down sampling between YCbCr 4:4:4 and YCbCr 4:2:2
Dithering for conversion from 12-bit component to 10-bit/8-bit
Digital audio output interface supporting
Š up to four I2S interface supporting 8-channel audio, with sample rates of 32~192 kHz and
smaple sizes of 16~24 bits
Š S/PDIF interface supporting PCM, Dolby Digital, DTS digital audio at up to 192kHz frame rate
Š Optional support for 8-channel DSD audio up to 8 channels at 88.2kHz sample rate
Š Support for high-bit-rate (HBR) audio such as DTS-HD and Dolby TrueHD through the four I2S
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interface or the S/PDIF interface, with frame rates as high as 768kHz
Š automatic audio error detection for programmable soft mute, preventing annoying harsh output
sound due to audio error or hot-unplug
Auto-calibrated input termination impedance provides process-, voltage- and temperature-invariant
matching to the input transmission lines.
Integrated pre-programmed HDCP keys
Intelligent, programmable power management
144-pin LQFP (20mm x 20mm) package
RoHS Compliant ( 100% Green available )
Model
Temperature Range
Package Type
Green/Pb free Option
IT6605E
0~70
144-pin LQFP
Green
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Ordering Information
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Feb-2012 Rev:0.92
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IT6605
AVCC18
AVSS
R1X2P
R1X2M
AVCC33
AVSS
R1X1P
R1X1M
AVCC33
AVSS
R1X0P
R1X0M
AVCC33
AVSS
R1XCP
R1XCM
AVCC33
REXT
PVCC18
PVSS
R0X2P
R0X2M
AVCC33
AVSS
R0X1P
R0X1M
AVCC33
AVSS
R0X0P
R0X0M
AVCC33
AVSS
R0XCP
R0XCM
AVCC33
AVCC18
Pin Diagram
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67
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65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
73
36
AVSS
74
35
R0PWR5V
MUTE_DR3
75
34
DDCSCL0
NC
76
33
DDCSDA0
DSD_DL3
77
32
OVDD
SPDIF_DL2
78
31
OVSS
IVSS
79
30
R1PWR5V
IVDD
80
29
DDCSCL1
I2S0_DL0
81
28
DDCSDA1
I2S1_DR1
82
27
PCSCL
I2S2_DL1
83
26
PCSDA
I2S3_DR2
84
25
IVDD
WS_DR0
85
24
IVDD
SCK_DCLK
86
23
IVSS
OVSS
87
22
EVENODD
OVDD
88
21
VSYNC
MCLK
89
20
HSYNC
IVSS
90
19
DE
IVDD
91
18
OVDD
APVDD18
92
17
OVSS
APVSS
93
16
QE0
XTALOUT
94
15
QE1
XTALIN
95
14
QE2
XTALVDD33
96
13
QE3
REGVCC
97
12
IVDD
RSVDL
98
11
IVSS
RSVDL
99
10
QE4
SYSRSTN
100
9
QE5
SCDT
101
8
QE6
INT#
102
7
QE7
OVSS
103
6
OVDD
OVDD
104
5
PCLK
PCADR
105
4
OVSS
IVSS
106
3
QE8
IVDD
107
2
QE9
QE35
108
1
QE10
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
QE33
QE32
OVSS
OVDD
QE31
QE30
QE29
QE28
IVSS
IVDD
QE27
QE26
QE25
QE24
OVSS
OVDD
QE23
QE22
QE21
QE20
IVSS
IVDD
QE19
QE18
QE17
QE16
OVSS
OVDD
QE15
QE14
140
141
142
143
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QE11
113
IVDD
112
IVSS
111
QE12
110
QE13
109
QE34
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OVSS
OVDD
Figure 1. IT6605 pin diagram
Note:
1. Pin55 must be connected with an external 500Ω SMD resistor to ground. This resistor serves to calibrate the
on-chip termination impedances of all four pairs of high-speed serial links.
2. Pins marked with NC should be left unconnected.
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IT6605
Pin Description
Digital Video Onput Pins
Pin Name
Direction
Description
QE[35:0]
Output
Digital Video Output Pins. Channel swap and
Type
Pin No.
LVTTL
1-3, 7-10, 13-16,
108-111, 114-117,
setting.
120-123, 126-129,
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MSB-LSB reversal are supported through register
Output data clock. The backend controller should
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Output
use the rising edge of PCLK to strobe QE[35:0]
Output
Data enable
HSYNC
Output
Horizontal sync. signal
VSYNC
Output
Vertical sync. signal
EVENODD
Output
Indicates whether the current field is Even or Odd
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for interlaced format
19
LVTTL
20
LVTTL
21
LVTTL
22
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Digital Audio Onput Pins
5
LVTTL
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PCLK
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132-135, 138-141,
Direction
Description
XTALIN
Input
Crystal clock input (for Audio PLL)
XTALOUT
Output
Crystal clock output (for Audio PLL)
MCLK
Output
Audio master clock
SCK_DCLK
Output
I2S serial clock output, doubles as DSD clock
WS_DR0
Output
I2S word select output, doubles as DSD Serial Right CH0 data
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Pin Name
Type
Pin No.
LVTTL
95
LVTTL
94
LVTTL
89
LVTTL
86
LVTTL
85
LVTTL
81
LVTTL
82
LVTTL
83
LVTTL
84
LVTTL
78
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I2S2_DL1
Output
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I2S1_DR1
Output
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I2S3_DR2
Output
I2S serial data output, doubles as DSD Serial Left CH0 data
output
I2S serial data output, doubles as DSD Serial Right CH1 data
output
I2S serial data output, doubles as DSD Serial Left CH1 data
output
Output
I2S serial data output, doubles as DSD Serial Right CH2 data
output
SPDIF_DL2
Output
S/PDIF audio output, doubles as DSD Serial Left CH2 data
output
MUTE_DR3
Output
Mute output, doubles as DSD Serial Right CH3 data output
LVTTL
75
DSD_DL3
Output
DSD Serial Left CH3 data output
LVTTL
77
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IT6605
Programming Pins
Pin No.
Interrupt output. Default active-low (5V-tolerant)
LVTTL
102
SYSRSTN
Input
Hardware reset pin. Active LOW (5V-tolerant)
Schmitt
100
DDCSCL0
I/O
DDC I2C Clock for HDMI Port 0 (5V-tolerant)
Schmitt
34
DDCSDA0
I/O
DDC I2C Data for HDMI Port 0 (5V-tolerant)
Schmitt
33
R0PWR5V
Input
TMDS transmitter detection for Port 0(5V-tolerant)
LVTTL
35
DDCSCL1
I/O
DDC I2C Clock for HDMI Port 1 (5V-tolerant)
Schmitt
29
DDCSDA1
I/O
DDC I2C Data for HDMI Port 1 (5V-tolerant)
Schmitt
28
R1PWR5V
Input
TMDS transmitter detection for Port 1(5V-tolerant)
LVTTL
30
PCSCL
Input
Serial Programming Clock for chip programming (5V-tolerant)
Schmitt
27
PCSDA
I/O
Serial Programming Data for chip programming (5V-tolerant)
Schmitt
26
PCADR
Input
Serial Programming device address select. Device address is
LVTTL
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Output
51
INT#
9
Type
44
Description
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0x90 when PCADR is pulled low, 0x92 otherwise
Output
Indication for active HDMI signal at input port
LVTTL
101
RSVDL
Input
Must be tied low via a resistor.
LVTTL
99
Must be left unconnected
NC
Must be left unconnected
98
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RSVDL
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SCDT
Direction
Description
Type
Pin No.
R0X2P
Analog
HDMI Channel 2 positive input for HDMI Port 0
TMDS
52
R0X2M
Analog
HDMI Channel 2 negative input for HDMI Port 0
TMDS
51
R0X1P
Analog
HDMI Channel 1 positive input for HDMI Port 0
TMDS
48
R0X1M
Analog
HDMI Channel 1 negative input for HDMI Port 0
TMDS
47
R0X0P
Analog
HDMI Channel 0 positive input for HDMI Port 0
TMDS
44
R0X0M
Analog
HDMI Channel 0 negative input for HDMI Port 0
TMDS
43
Analog
HDMI Clock Channel positive input for HDMI Port 0
TMDS
40
Analog
HDMI Clock Channel negative input for HDMI Port 0
TMDS
39
Analog
External resistor for setting termination impedance value. Should
Analog
55
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R0XCP
R0XCM
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HDMI analog front-end interface pins
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REXT
be tied to GND via a 500Ω SMD resistor.
R1X2P
Analog
HDMI Channel 2 positive input for HDMI Port 1
TMDS
70
R1X2M
Analog
HDMI Channel 2 negative input for HDMI Port 1
TMDS
69
R1X1P
Analog
HDMI Channel 1 positive input for HDMI Port 1
TMDS
66
R1X1M
Analog
HDMI Channel 1 negative input for HDMI Port 1
TMDS
65
R1X0P
Analog
HDMI Channel 0 positive input for HDMI Port 1
TMDS
62
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IT6605
R1X0M
Analog
HDMI Channel 0 negative input for HDMI Port 1
TMDS
61
R1XCP
Analog
HDMI Clock Channel positive input for HDMI Port 1
TMDS
58
R1XCM
Analog
HDMI Clock Channel negative input for HDMI Port 1
TMDS
57
Power/Ground Pins
IVDD
Digital logic power (1.8V)
Type
Pin No.
Power
12, 24, 25, 80, 91,
9
Description
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Pin Name
I/O Pin ground
HDMI analog frontend power (3.3V)
HDMI analog frontend power (1.8V)
AVSS
HDMI analog frontend ground
11, 23, 79, 90,
HDMI receiver PLL ground
APVDD18
HDMI audio PLL power (1.8V)
APVSS
XTALVDD33
REGVCC
,
PVSS
6, 18, 32, 74, 88,
104, 113, 125, 137
4, 17, 31, 73, 87,
103, 112, 124, 136
Power
38, 42, 46, 50,
56, 60, 64, 68
Power
37, 72
Ground
36, 41, 45, 49,
59, 63, 67, 71
Power
54
Ground
53
Power
92
HDMI audio PLL ground
Ground
93
Power for crystal oscillator (3.3V)
Power
96
Regulator power (3.3V) for audio PLL
Power
97
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HDMI receiver PLL power (1.8V)
Ground
106, 118, 130, 142
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PVCC18
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AVCC18
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AVCC33
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Power
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I/O Pin power (3.3V)
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Ground
44
Digital logic ground
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IVSS
51
107, 119, 131, 143
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IT6605
Functional Description
Figure 2. Functional block diagram of the IT6605
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The IT6605 is the 3nd generation HDMI receiver and provides complete solutions for HDMI v1.4 Sink
systems, supporting reception and processing of Deep Color video and state-of-the-art digital audio
such as DTS-HD and Dolby TrueHD. The IT6605 with its two HDMI input ports supports color depths
of 10 bits and 12 bits up to 1080p. Advanced processing algorithms are employed to optimize the
performance of video processing such as color space conversion and up/down sampling. The
following picture is the functional block digram of the IT6605, which describes clearly the data flow.
Note that only one the two inputs can be activated at a time.
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Receiver Analog Frontend (Rcvr. AFE)
The two integrated TMDS receiver analog frontend macros are capable of receiving and decoding
HDMI data at up to 2.25Gbps (with a TMDS clock of 225MHz). Adaptive equalization is employed to
support long cables. Only one port can be actived at a time and the system firmware has total control
over this through register settings.
While not indicated in Figure 2, the two HDMI PWR5V signals of the two respective inputs are also
monitored by the IT6605. The system controller could poll registers to confirm the existence of actually
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IT6605
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connected port.
Figure 3. Video data processing flow of the IT6605
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Video Data Processing Flow
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Figure 3 depicts the video data processing flow. For the purpose of retaining maximum flexibility, most
of the block enablings and path bypassings are controlled through register programming. Please refer
to IT6605 Programming Guide for detailed and precise descriptions.
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As can be seen from Figure 3, the received and recovered HDMI raw data is first HDCP-decrypted.
The extracted video data then go through various processing blocks, as described in the following
paragraphs, before outputting the proper video format to the backend video controller.
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The video processing including YCbCr up/down-sampling, color-space conversion and dithering.
Depending on the selected input and output video formats, different processing blocks are either
enabled or bypassed via register control. For the sake of flexibility, this is all done in software register
programming. Therefore, extra care should be taken in keeping the selected output format and the
corresponding video processing block selection. Please refer to the IT6605 Programming Guide for
suggested register setting.
Designated as QE[35:0], the output video data could take on bus width of 8 bits to 36 bits, depending
on the formats and color depths. The output interface could be configured through register setting to
provide various data formats as listed in Table 1 in order to cater to different preferences of different
backend controllers.
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IT6605
Major video processings in the IT6605 are carried out in 14 bits per channel in order to minimize
rounding errors and other computational residuals that occur during processing. General description
of video processing blocks is as follows:
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HDCP engine (HDCP)
The HDCP engine decrypts in incoming data. Preprogrammed HDCP keys are embedded in the
IT6605. Users need not worry about the purchasing and management of the HDCP keys as Chip
Advanced Technology will take care of them.
:
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Upsampling (YCbCr422 to YCbCr444)
In cases where input HDMI video data are in YCbCr 4:2:2 format and output is selected as 4:4:4, this
block is enabled to do the upsampling. Well-designed signal filtering is employed to avoid visible
artifacts generated during upsampling.
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Bi-directional Color Space Conversion (YCbCr ↔ RGB)
Many video decoders only offer YCbCr outputs, while DVI 1.0 supports only RGB color space. In order
to offer full compatibility between various Source and Sink combination, this block offers bi-directional
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RGB ↔ YCbCr color space conversion (CSC). To provide maximum flexibility, the matrix coefficients
of the CSC engine in the IT6605 are fully programmable. Users could elect to employ their preferred
conversion formula.
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Downsampling (YCbCr444 to YCbCr422)
In cases where input HDMI video data are in YCbCr 4:4:4 format and output is selected as YCbCr
4:2:2, this block is enabled to do the downsampling. Well-designed signal filtering is employed to avoid
visible artifacts generated during downsampling.
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Dithering (Dithering 12-to-10 or 12-to-8)
For outputing to the 10-bits / 8-bits-per-channel formats, decimation might be required depending on
the exact input formats. This block performs the necessary dithering for decimation to prevent visible
artifacts from appearing.
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Supported output Video Formats
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Table 1 lists the output video formats supported by the IT6605. The listed Output Pixel Clock
Frequency in MHz is the actual clock frequency at the output pin PCLK, regardless of the color depth.
According to the HDMI Specification v1.3, the input TMDS clock frequency could be 1.25 times or 1.5
times that of the output PCLK frequency, depending on the color depth:
For 24-bit inputs, TMDS Clock frequency = 1 x PCLK frequency
For 30-bit inputs, TMDS Clock frequency = 1.25 x PCLK frequency
For 36-bit inputs, TMDS Clock frequency = 1.5 x PCLK frequency
The IT6605 also provides automatic video mode detection. The system controller can elect to check
out respective status registers to get the informations.
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IT6605
Output Pixel Clock Frequency (MHz)
Color
Video
Bus
Hsync/
Space
Format
Width
Vsync
480p
XGA
720p
1080i
SXGA
1080p
UXGA
13.5
27
65
74.25
74.25
108
148.5
162
13.5
27
65
74.25
74.25
108
148.5
13.5
27
65
74.25
74.25
13.5
27
65
74.25
74.25
108
148.5
13.5
27
65
74.25
74.25
108
Separate
13.5
27
65
74.25
74.25
Separate
13.5
27
74.25
74.25
Embedded
13.5
27
74.25
74.25
Separate
27
54
148.5
148.5
Embedded
27
54
148.5
148.5
4:4:4
Separate
30/36
12/15/18
YCbCr
16/20/24
4:2:2
8/10/12
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24
162
148.5
51
Separate
44
12/15/18
71
30/36
:
4:4:4
148.5
148.5
QQ
RGB
Separate
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480i
Table 1. Output video formats supported by the IT6605
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Notes:
1. Table cells that are left blanks are those format combinations that are not supported by the IT6605.
2. Output channel number is defined by the way the three color components (either R, G & B or Y, Cb & Cr) are
arranged. Refer to Video Data Bus Mappings for better understanding.
3. Embedded sync signals are defined by CCIR-656 standard, using SAV/EAV sequences of FF, 00, 00, XY.
4. The lowest TMDS clock frequency specified by the HDMI standard is 25MHz for [email protected]
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Supported 3D Formats
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[email protected] -- Top-and-Bottom
[email protected]/60Hz -- Top-and-Bottom
[email protected]/30Hz -- Framing Packing, Top-and-Bottom
[email protected]/24Hz -- Framing Packing, Side-by-Side ( Half ), Top-and-Bottom
[email protected] – Frame Packing, Side-by-Side ( Half )
[email protected]/60Hz – Frame Packing, Side-by-Side ( Half )
1280x [email protected] -- Framing Packing, Side-by-Side ( Half ), Top-and-Bottom
1280x [email protected]/60Hz -- Framing Packing, Side-by-Side ( Half ), Top-and-Bottom
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The IT6605 supports all the HDMI 1.4a 3D mandatory formats including
Audio Clock Recovery and Data Processing
The audio processing block in the HDMI Sink is crucial to the system performance since human
hearing is susceptive to audio imperfection. The IT6605 prides itself in outstanding audio recovery
performances. In addition, the audio clock recovery PLL uses an external crystal reference so as to
provide stable and reliable audio clocks for all audio output formats.
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IT6605
The IT6605 supports all audio formats and interfaces specified by the HDMI Specification v1.3 through
I2S, S/PDIF and optional one-bit audio outputs. The one-bit audio outputs take on the pins used by I2S
outputs, so only one between the two could be activated at a time.
Audio sample frequency
44.1kHz
48kHz
88.2kHz
96kHz
QQ
176.4kHz
192kHz
128
4.096
5.645
6.144
11.290
12.288
22.579
24.576
256
8.192
11.290
12.288
22.579
24.576
45.158
49.152
384
12.288
16.934
18.432
33.869
36.864
67.738
73.728
512
16.384
22.579
24.576
45.158
49.152
90.317
98.304
640
20.480
28.224
30.720
56.448
61.440
(112.896)
(122.880)
768
24.576
33.868
36.864
67.738
73.728
(135.475)
(147.456)
896
28.672
39.514
43.008
79.027
86.016
(158.054)
(172.032)
1024
32.768
45.158
49.152
90.316
98.304
(180.634)
(196.608)
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41
5
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限
85
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32kHz
,
sample frequency
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Multiple of audio
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I 2S
Four I2S outputs are provided to support 8-channel uncompressed audio data at up to 192kHz sample
rate. A coherent multiple (master) clock MCLK is generated at pin 89 to facilitate proper functions of
mainstream backend audio DAC ICs. The supported multiplied factor and sample frequency as well as
the resultant MCLK frequencies are summarized in Table 2.
Table 2. Output MCLK frequencies (MHz) supported by the IT6605
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Notes:
1. The MCLK frequencies in parenthesis are MCLK frequencies over 100MHz. These frequencies are implemented
in the IT6605 and could be output through register setting as well. However, the I/O circuit of the MCLK pin does
not guarantee to be operating at such a high frequency under normal operation conditions. In addition, few audio
backend ICs such as DACs support such high MCLK frequencies. Therefore, using the MCLKs in parenthesis is
strongly discouraged.
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S/PDIF
The S/PDIF output provides 2-channel uncompressed PCM data (IEC 60958) or compressed
multi-channel data (IEC 61937) at up to 192kHz. By default the clock of S/PDIF is carried within the
datastream itself via coding. The IT6605 also supplies coherent MCLK in cases of S/PDIF output to
help ease the implementation with certain audio processing ICs.
One-Bit Audio (DSD/SACD)
Direct stream digital (DSD) audio is an one-bit audio format which is prescribed by Super Audio CD
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Feb-2012 Rev:0.92
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IT6605
(SACD) to provide superiore audio hearing experiences. Based on the register setting of the system
controller, the IT6605 outputs DSD audio optionally through existing I2S output pins. A total of 8 data
outputs are provided for right channels and left channels. Refer to Pin Description on page 5 for
detailed port-to-pin mapping.
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High-Bit-Rate Audio (HBR)
High-Bit-Rate Audio is also new to the HDMI standard. It is called upon by high-end audio system
such as DTS-HD and Dolby TrueHD. No specific interface is defined by the HBR standard. The
IT6605 supports HBR audio in two ways. One is to employ the four I2S outputs simultaneously, where
the original streaming DSD audio is broken into four parallel data streams. The other is to use the
S/PDIF output port. The data rate in the later case is as high as 98.304Mbps. A coherent MCLK is
generated by the IT6605 for the backend audio processors.
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Smart Audio Error Detection
Some previous HDMI Sink products were reported to generate unbearably harsh sounds during
hot-plug/unplug as well as unspecified audio error. Like its predecessor CAT6011, the IT6605 prides
itself for detecting all kinds of audio error and soft-mutes the audio accordingly, therefore preventing
unpleasant noise from outputting.
Interrupt Generation
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To provide automatic format setting, hot plug/unplug handling and error handling, the system
micro-controller should monitor the interrupt signal output at Pin 102 (INT#). The IT6605 generates an
interrupt signal whenever events involving the following signals or situations occur:
1. A status change of incoming 5V power signals at pin 30 or pin 35 (corresponding to plug/unplug)
2. Stable video is acquired (SCDT at pin 101 is asserted)
3. Events of audio errors and/or audio mute
4. Events of ECC errors
5. Video mode change
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Without software intervention the hardware of the IT6605 should be able to output some sort of
displayable video data. However, this video could be in the wrong format or color space. Also,
hardware alone is not sufficient in handling the exception events listed above. The micro-controller
must monitor the INT# signal carefully and poll the corresponding registers for optimum operation.
Configuration and Function Control
The IT6605 comes with three serial programming ports: one for interfacing with micro-controller, the
other two allowing access by HDMI Sources through the two DDC channels of the HDMI links.
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IT6605
The serial programming interface for interfacing the micro-controller is a slave interface, comprising
PCSCL (Pin 27) and PCSDA (Pin 26). The micro-controller uses this interface to monitor all the
statuses and control all the functions. Two device addresses are available, depending on the input
logic level of PCADR (Pin 105). If PCADR is pulled high by the user, the device address is 0x92. If
pulled low, 0x90.
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Since the IT6605 provides two HDMI input ports, two DDC I2C interface are present at DDCSCL0 (Pin
34) & DDCSDA0 (Pin 33) and DDCSCL1 (Pin 29) & DDCSDA1 (Pin 28). With the interfaces, the
IT6605 responds to the access of HDMI Sources via the DDC channels. HDMI Sources use the
interfaces to perform HDCP authentication with the IT6605.
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All serial programming interfaces conform to standard I2C transactions and operate at up to 100kHz.
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Feb-2012 Rev:0.92
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IT6605
Electrical Specifications
Absolute Maximum Ratings
Unit
-0.3
2.5
V
I/O pins supply voltage
-0.3
4.0
V
AVCC33
HDMI analog frontend power
-0.3
4.0
V
AVCC18
HDMI analog frontend power
-0.3
2.5
V
PVCC18
HDMI receiver PLL power
-0.3
2.5
V
APVDD18
HDMI audio PLL power
-0.3
2.5
V
XTALVDD33
Power for crystal oscillator
-0.3
4.0
V
REGVCC
Power for regulator
-0.3
4.0
V
VI
Input voltage
-0.3
OVDD+0.3
V
VO
Output voltage
-0.3
OVDD+0.3
V
TJ
Junction Temperature
125
°C
TSTG
Storage Temperature
150
°C
ESD_HB
Human body mode ESD sensitivity
81
OVDD
51
Core logic supply voltage
9
Max
44
IVDD
Typ
71
Min.
:
Parameter
-65
2000
V
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Symbol
Parameter
IVDD
Core logic supply voltage
OVDD
I/O pins supply voltage
技
有
限
Symbol
公
Functional Operation Conditions
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ESD_MM
Machine mode ESD sensitivity
200
V
Notes:
1. Stresses above those listed under Absolute Maximum Ratings might result in permanent damage to the device.
2
Min.
Typ
Max
Unit
1.6
1.8
2.0
V
2.97
3.3
3.63
V
HDMI analog frontend power
3.135
3.3
3.465
V
AVCC18
HDMI analog frontend power
1.6
1.8
2.0
V
PVCC18
HDMI receiver PLL power
1.6
1.8
2.0
V
HDMI audio PLL power
1.6
1.8
2.0
V
Power for crystal oscillator
3.0
3.3
3.6
V
REGVCC
Power for regulator
3.0
3.3
3.6
V
VCCNOISE
Supply noise
100
mVpp
TA
Ambient temperature
70
°C
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APVDD18
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AVCC33
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XTALVDD33
0
25
Junction to ambient thermal resistance
Θja
Notes:
1. AVCC33, AVCC18, PVCC18 and APVDD18 should be regulated.
2. AVCC33 supplies the termination voltage. Therefore the range is specified by the HDMI Standard.
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Feb-2012 Rev:0.92
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IT6605
Symbol
Parameter
PCLK
Typ
Unit
IIVDD_OP
IVDD current under normal operation
27MHz
64
mA
74.25MHz
146
mA
148.5MHz
250
mA
222.75MHz
325
mA
27MHz
14
9
Operation Supply Current Specification
74.25MHz
41
148.5MHz
60
222.75MHz
mA
74.25MHz
65
mA
148.5MHz
82
mA
222.75MHz
106
mA
27MHz
57
mA
74.25MHz
57
mA
148.5MHz
57
mA
222.75MHz
58
mA
27MHz
5
mA
74.25MHz
13
mA
148.5MHz
23
mA
222.75MHz
35
mA
27MHz
6
mA
74.25MHz
6
mA
148.5MHz
6
mA
222.75MHz
6
mA
QQ
18
66
(with input Vdiff= 750 mV)
85
,
AVCC33 current under normal operation
PVCC18 current under normal operation
限
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IPVCC18_OP
APVDD18 current under normal operation
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IAPVDD18_OP
81
50
27MHz
43
41
5
IAVCC33_OP
mA
mA
AVCC18 current under normal operation
(with input Vdiff= 750 mV)
mA
72
:
IAVCC18_OP
51
(with 20pF capacitive output loading)
mA
44
OVDD current under normal operation
71
IOVDD_OP
XTALVDD33 current under normal operation
(all speeds)
1
mA
IREGVCC
REGVCC current under normal operation
(all speeds)
0
mA
27MHz
463
mW
74.25MHz
741
mW
148.5MHz
1039
mW
222.75MHz
1282
mW
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PWTOTAL_OP
合
IXTALVDD33
Total power consumption under normal operation3
Notes:
1. Typ: OVDD=AVCC33=XTALVDD33=REGVCC=3.3V, IVDD=AVCC18=PVCC18=APVDD18=1.8V
PCLK=27MHz: 480p with 48kHz/8-channel audio,
PCLK=74.25MHz: 1080i with 192kHz/8-channel audio,
PCLK=148.5MHz: 1080p with 192kHz/8-channel audio,
PCLK=222.75MHz: [email protected] Deep Color with 192kHz/8-channel audio
2. PWTOTAL_OP are calculated by multiplying the supply currents with their corresponding supply voltage and summing up all the items.
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Feb-2012 Rev:0.92
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IT6605
DC Electrical Specification
Under functional operation conditions
Symbol
Parameter
VIH
Input high voltage1
Pin Type
LVTTL
Input low voltage1
Min.
2.0
LVTTL
Switching threshold
LVTTL
VT-
Schmitt trigger negative going threshold
Schmitt
0.8
1.6
1
IOZ
Tri-state output leakage current
IOL
Serial programming output sink current2
3
V
0.4
IOH=-2~-16mA
all
VIN=5.5V or 0
±5
μA
all
VIN=5.5V or 0
±10
μA
Schmitt
VOUT=0.2V
:
LVTTL
2.4
QQ
Input leakage current
2.0
V
IOL=2~16mA
85
,
IIN
1
V
LVTTL
4
43
41
5
Output high voltage1
71
voltage
VOH
1.1
44
Schmitt
1
Output low voltage1
0.8
V
51
voltage
VOL
Unit
V
1.5
1
Schmitt trigger positive going threshold
Max
9
VT
1
VT+
Typ
81
VIL
Conditions
16
mA
技
有
限
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司
,
18
66
Vdiff
TMDS input differential swing
TMDS
150
1200
mV
REXT=500Ω
Notes:
1. Guaranteed by I/O design.
2. The serial programming output ports are not real open-drain drivers. Sink current is guaranteed by I/O design
under the condition of driving the output pin with 0.2V. In a real I2C environment, multiple devices and pull-up
resistors could be present on the same bus, rendering the effective pull-up resistance much lower than that
specified by the I2C Standard. When set at maximum current, the serial programming output ports of the IT6605
are capable of pulling down an effective pull-up resistance as low as 500Ω connected to 5V termination voltage
to the standard I2C VIL. When experiencing insufficient low level problem, try setting the current level to higher
than default. Refer to IT6605 Programming Guide for proper register setting.
3. Limits defined by HDMI 1.3a standard
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Audio AC Timing Specification
Conditions
Up to 8 channels
FS_SPDIF
S/PDIF sample rate
2 channels
FS_DSD
DSD sample rate
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Under functional operation conditions
Symbol
Parameter
FS_I2S
I2S sample rate
Up to 8 channels
Min.
32
32
Typ
Max
192
Unit
kHz
192
kHz
96
kHz
1
深
FXTAL
External audio crystal frequency
±300ppm accuracy
24
27
28.5
MHz
Notes:
1. The IT6605 is designed to work in default with a 27MHz crystal for audio functions. Crystals of other frequencies
within the designated functional range mandate certain register programming for proper functioning.
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IT6605
Video AC Timing Specification
Fpixel
PCLK pixel clock frequency
TCDE
PCLK dual-edged clock period2
PCLK dual-edged clock frequency
TPDUTY
PCLK clock duty cycle
TPH
PCLK rising edge to Transition time4
clocking
25
225
MHz
8.88
40
ns
25
112.5
MHz
40%
60%
Single-pixel mode
0
Max
40
Unit
ns
0.4
ns
44
FCDE
Single-edged
Dual-edged clocking
2
Typ
9
1
Min.
4.44
81
Conditions
51
Under functional operation conditions
Symbol
Parameter
Tpixel
PCLK pixel clock period1
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71
Notes:
1. Fpixel is the inverse of Tpixel. Operating frequency range is given here while the actual video clock frequency
should comply with all video timing standards. Refer to Table 1 for supported video timings and corresponding
pixel frequencies.
2. 12-bit dual-edged clocking is supported up to 74.5MHz of PCLK frequency, which covers 720p/1080i.
3. All setup time and hold time specifications are with respect to the latching edge of PCLK selected by the user
through register programming.
4. The PCLK rising edge to transition time could be got when Vclk_inv (reg[0x1D]bit[4]=‘0’) is disabled. If user
intends to delay 0.5Tpixel for TTL data output, please enable Vclk_inv bit (reg[0x1D]bit[4]=‘1’). And then TPH will
increase 0.5Tpixel.
PCLK rising edge to transition time under single-pixel mode
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IT6605
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Reset Timing
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Note: No special request for time interval between 3.3V and 1.8V
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IT6605
Video Data Bus Mappings
The IT6605 supports various output data mappings and formats, including those with embedded
control signals only. Corresponding register setting is to be taken care of for any chosen input data
mappings. Refer to IT6605 Programming Guide for detailed instruction.
4:4:4
YCbCr
24/30/36
Seperate
1X
12/15/18
Seperate
Dual-edged
9
24/30/36
Seperate
0.5X, Dual-edged
4
24/30/36
Seperate
1X
4
12/15/18
Seperate
Dual-edged
9
24/30/36
Seperate
0.5X, Dual-edged
4
Seperate
1X
5
Embedded
1X
6
Seperate
2X
8
Embedded
2X
7
16/20/24
43
41
5
4:2:2
81
51
44
4
18
66
8/10/12
Table
9
Clocking
71
4:4:4
H/Vsync
:
RGB
Bus Width
QQ
Video Format
85
,
Color Space
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Table 3. Output video format supported by the IT6605
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IT6605
RGB 4:4:4 and YCbCr 4:4:4 with Separate Syncs
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24-bit
NC
NC
NC
NC
Cb0
Cb1
Cb2
Cb3
Cb4
Cb5
Cb6
Cb7
NC
NC
NC
NC
Y0
Y1
Y2
Y3
Y4
Y5
Y6
Y7
NC
NC
NC
NC
Cr0
Cr1
Cr2
Cr3
Cr4
Cr5
Cr6
Cr7
HSYNC
VSYNC
DE
:
71
44
YCbCr
30-bit
NC
NC
Cb0
Cb1
Cb2
Cb3
Cb4
Cb5
Cb6
Cb7
Cb8
Cb9
NC
NC
Y0
Y1
Y2
Y3
Y4
Y5
Y6
Y7
Y8
Y9
NC
NC
Cr0
Cr1
Cr2
Cr3
Cr4
Cr5
Cr6
Cr7
Cr8
Cr9
HSYNC
VSYNC
DE
QQ
85
,
36-bit
Cb0
Cb1
Cb2
Cb3
Cb4
Cb5
Cb6
Cb7
Cb8
Cb9
Cb10
Cb11
Y0
Y1
Y2
Y3
Y4
Y5
Y6
Y7
Y8
Y9
Y10
Y11
Cr0
Cr1
Cr2
Cr3
Cr4
Cr5
Cr6
Cr7
Cr8
Cr9
Cr10
Cr11
HSYNC
VSYNC
DE
43
41
5
24-bit
NC
NC
NC
NC
B0
B1
B2
B3
B4
B5
B6
B7
NC
NC
NC
NC
G0
G1
G2
G3
G4
G5
G6
G7
NC
NC
NC
NC
R0
R1
R2
R3
R4
R5
R6
R7
HSYNC
VSYNC
DE
,
司
公
限
技
有
36-bit
B0
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
G0
G1
G2
G3
G4
G5
G6
G7
G8
G9
G10
G11
R0
R1
R2
R3
R4
R5
R6
R7
R8
R9
R10
R11
HSYNC
VSYNC
DE
合
Pin Name
QE0
QE1
QE2
QE3
QE4
QE5
QE6
QE7
QE8
QE9
QE10
QE11
QE12
QE13
QE14
QE15
QE16
QE17
QE18
QE19
QE20
QE21
QE22
QE23
QE24
QE25
QE26
QE27
QE28
QE29
QE30
QE31
QE32
QE33
QE34
QE35
HSYNC
VSYNC
DE
RGB
30-bit
NC
NC
B0
B1
B2
B3
B4
B5
B6
B7
B8
B9
NC
NC
G0
G1
G2
G3
G4
G5
G6
G7
G8
G9
NC
NC
R0
R1
R2
R3
R4
R5
R6
R7
R8
R9
HSYNC
VSYNC
DE
Table 4. RGB & YCbCr 4:4:4 Mappings
These are the simpliest formats, with a complete definition of every pixel in each clock period. Timing
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IT6605
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examples of 36-bit and 30-bit RGB 4:4:4 is depicted in Figure 4 and Figure 5 respectively.
Pixel0
Pixel1
Pixel2
Pixel3
Pixel4
Pixel5
Pixel6
...
val
Rpix0
Rpix1
Rpix2
Rpix3
Rpix4
Rpix5
Rpix6
....
val
val
val
val
Gpix0
Gpix1
Gpix2
Gpix3
Gpix4
Gpix5
Gpix6
....
val
val
val
val
Bpix0
Bpix3
Bpix4
Bpix5
Bpix6
....
val
val
val
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Bpix2
合
PCLK
Bpix1
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QE[1:0]
技
有
限
QE[13:12]
QE[11:2]
blank
公
QE[23:14]
司
QE[25:24]
18
66
blank
,
QE[35:26]
43
41
5
Figure 4. 36-bit RGB 4:4:4 Timing Diagram
深
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H/VSYNC
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Figure 5, 30-bit RGB 4:4:4 Timing Diagram
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IT6605
YCbCr 4:2:2 with Separate Syncs
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16-bit
Pixel#2N
Pixel#2N+1
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
Y0
Y0
Y1
Y1
Y2
Y2
Y3
Y3
Y4
Y4
Y5
Y5
Y6
Y6
Y7
Y7
NC
NC
NC
NC
NC
NC
NC
NC
Cb0
Cr0
Cb1
Cr1
Cb2
Cr2
Cb3
Cr3
Cb4
Cr4
Cb5
Cr5
Cb6
Cr6
Cb7
Cr7
HSYNC
HSYNC
VSYNC
VSYNC
DE
DE
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66
43
41
5
85
,
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20-bit
Pixel#2N
Pixel#2N+1
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
Y0
Y0
Y1
Y1
Y2
Y2
Y3
Y3
Y4
Y4
Y5
Y5
Y6
Y6
Y7
Y7
Y8
Y8
Y9
Y9
NC
NC
NC
NC
Cb0
Cr0
Cb1
Cr1
Cb2
Cr2
Cb3
Cr3
Cb4
Cr4
Cb5
Cr5
Cb6
Cr6
Cb7
Cr7
Cb8
Cr8
Cb9
Cr9
HSYNC
HSYNC
VSYNC
VSYNC
DE
DE
,
司
公
限
技
有
讯
科
合
Pin Name
QE0
QE1
QE2
QE3
QE4
QE5
QE6
QE7
QE8
QE9
QE10
QE11
QE12
QE13
QE14
QE15
QE16
QE17
QE18
QE19
QE20
QE21
QE22
QE23
QE24
QE25
QE26
QE27
QE28
QE29
QE30
QE31
QE32
QE33
QE34
QE35
HSYNC
VSYNC
DE
24-bit
Pixel#2N
Pixel#2N+1
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
Y0
Y0
Y1
Y1
Y2
Y2
Y3
Y3
Y4
Y4
Y5
Y5
Y6
Y6
Y7
Y7
Y8
Y8
Y9
Y9
Y10
Y10
Y11
Y11
Cb0
Cr0
Cb1
Cr1
Cb2
Cr2
Cb3
Cr3
Cb4
Cr4
Cb5
Cr5
Cb6
Cr6
Cb7
Cr7
Cb8
Cr8
Cb9
Cr9
Cb10
Cr10
Cb11
Cr11
HSYNC
HSYNC
VSYNC
VSYNC
DE
DE
Table 5. Mappings of YCbCr 4:2:2 with separate syncs
YCbCr 4:2:2 format does not have one complete pixel for every clock period. Luminace channel (Y) is
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Feb-2012 Rev:0.92
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IT6605
43
41
5
85
,
QQ
:
71
44
51
81
9
given for every pixel, while the two chroma channels are given alternatively on every other clock
period. The average bit amount of Y is twice that of Cb or Cr. Depending on the bus width, each
component could take on different lengths. The DE period should contain an even number of clock
periods. Figure 6 gives a timing example of 24-bit YCbCr 4:2:2.
val
Cbpix0
[7:0]
Crpix0
[7:0]
Cbpix2
[7:0]
val
Ypix0
[7:0]
Ypix1
[7:0]
Pixel5
Pixel6
...
blank
Crpix2
[7:0]
Cbpix4
[7:0]
Crpix4
[7:0]
Cbpix6
[7:0]
....
val
val
val
Ypix2
[7:0]
Ypix3
[7:0]
Ypix4
[7:0]
Ypix5
[7:0]
Ypix6
[7:0]
....
val
val
val
市
金
合
PCLK
DE
Pixel4
讯
科
QE[15:0]
技
有
QE[27:24]
QE[23:16]
Pixel3
,
Pixel2
司
Pixel1
限
QE[35:28]
Pixel0
公
blank
18
66
Figure 6. 24-bit YCbCr 4:2:2 with separate syncs
深
圳
H/VSYNC
www.ite.com.tw
Figure 7. 16-bit YCbCr 4:2:2 with separate syncs
Feb-2012 Rev:0.92
24/38
IT6605
YCbCr 4:2:2 with Embedded Syncs
深
圳
市
金
:
71
44
51
81
9
16-bit
Pixel#2N
Pixel#2N+1
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
Y0
Y0
Y1
Y1
Y2
Y2
Y3
Y3
Y4
Y4
Y5
Y5
Y6
Y6
Y7
Y7
NC
NC
NC
NC
NC
NC
NC
NC
Cb0
Cr0
Cb1
Cr1
Cb2
Cr2
Cb3
Cr3
Cb4
Cr4
Cb5
Cr5
Cb6
Cr6
Cb7
Cr7
embedded
embedded
embedded
embedded
embedded
embedded
18
66
43
41
5
85
,
QQ
20-bit
Pixel#2N
Pixel#2N+1
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
Y0
Y0
Y1
Y1
Y2
Y2
Y3
Y3
Y4
Y4
Y5
Y5
Y6
Y6
Y7
Y7
Y8
Y8
Y9
Y9
NC
NC
NC
NC
Cb0
Cr0
Cb1
Cr1
Cb2
Cr2
Cb3
Cr3
Cb4
Cr4
Cb5
Cr5
Cb6
Cr6
Cb7
Cr7
Cb8
Cr8
Cb9
Cr9
embedded
embedded
embedded
embedded
embedded
embedded
,
司
公
限
技
有
讯
科
合
Pin Name
QE0
QE1
QE2
QE3
QE4
QE5
QE6
QE7
QE8
QE9
QE10
QE11
QE12
QE13
QE14
QE15
QE16
QE17
QE18
QE19
QE20
QE21
QE22
QE23
QE24
QE25
QE26
QE27
QE28
QE29
QE30
QE31
QE32
QE33
QE34
QE35
HSYNC
VSYNC
DE
24-bit
Pixel#2N
Pixel#2N+1
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
Y0
Y0
Y1
Y1
Y2
Y2
Y3
Y3
Y4
Y4
Y5
Y5
Y6
Y6
Y7
Y7
Y8
Y8
Y9
Y9
Y10
Y10
Y11
Y11
Cb0
Cr0
Cb1
Cr1
Cb2
Cr2
Cb3
Cr3
Cb4
Cr4
Cb5
Cr5
Cb6
Cr6
Cb7
Cr7
Cb8
Cr8
Cb9
Cr9
Cb10
Cr10
Cb11
Cr11
embedded
embedded
embedded
embedded
embedded
embedded
Table 6. Mappings of YCbCr 4:2:2 with embedded syncs
Similar to YCbCr 4:2:2 with Separate Sync. The only difference is that the syncs are now non-explicit,
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Feb-2012 Rev:0.92
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IT6605
i.e. embedded. Bus width could be 16-bit, 20-bit or 24-bit. Figure 8 gives a timing example of 24-bit
YCbCr 4:2:2 and Figure 9 that of 16-bit. Note that while "embedded syncs" implies that neither DE nor
H/VSYNC are required, the IT6605 optionally output these signals via proper register setting to ease
the design for some backend processors.
Pixel0
Pixel1
Pixel2
Pixel3
Pixel4
Pixel5
...
....
blank
val
val
val
Cbpix0
[11:0]
Crpix0
[11:0]
Cbpix2
[11:0]
Crpix2
[11:0]
Cbpix4
[11:0]
Crpix4
[11:0]
QE[23:12]
FF
00
00
XY
Ypix0
[11:0]
Ypix1
[11:0]
Ypix2
[11:0]
Ypix3
[11:0]
Ypix4
[11:0]
Ypix5
[11:0]
51
val
....
val
FF
71
44
QE[35:24]
81
9
SAV
:
QE[11:0]
85
,
QQ
PCLK
技
有
限
公
司
,
18
66
43
41
5
Figure 8. 24-bit YCbCr 4:2:2 with embedded syncs
深
圳
市
金
合
讯
科
Figure 9. 16-bit YCbCr 4:2:2 with embedded syncs
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Feb-2012 Rev:0.92
26/38
IT6605
CCIR-656 Format
深
圳
85
,
43
41
5
18
66
81
9
8-bit
PCLK#2N+1
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
Y0
Y1
Y2
Y3
Y4
Y5
Y6
Y7
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
embedded
embedded
embedded
:
71
44
51
PCLK#2N
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
C0
C1
C2
C3
C4
C5
C6
C7
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
embedded
embedded
embedded
QQ
10-bit
PCLK#2N
PCLK#2N+1
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
C0
Y0
C1
Y1
C2
Y2
C3
Y3
C4
Y4
C5
Y5
C6
Y6
C7
Y7
C8
Y8
C9
Y9
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
embedded
embedded
embedded
embedded
embedded
embedded
,
司
公
限
技
有
讯
科
合
市
金
Pin Name
QE0
QE1
QE2
QE3
QE4
QE5
QE6
QE7
QE8
QE9
QE10
QE11
QE12
QE13
QE14
QE15
QE16
QE17
QE18
QE19
QE20
QE21
QE22
QE23
QE24
QE25
QE26
QE27
QE28
QE29
QE30
QE31
QE32
QE33
QE34
QE35
HSYNC
VSYNC
DE
12-bit
PCLK#2N
PCLK#2N+1
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
C0
Y0
C1
Y1
C2
Y2
C3
Y3
C4
Y4
C5
Y5
C6
Y6
C7
Y7
C8
Y8
C9
Y9
C10
Y10
C11
Y11
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
embedded
embedded
embedded
embedded
embedded
embedded
Table 7. Mappings of CCIR-656
The CCIR-656 format is yet another variation of the YCbCr formats. The bus width is further reduced
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Feb-2012 Rev:0.92
27/38
IT6605
18
66
43
41
5
85
,
QQ
:
71
44
51
81
9
by half compared from the previous YCbCr 4:2:2 formats, to either 8-bit, 10-bit or 12-bit. To
compensate for the halving of data bus, PCLK frequency is doubled. With the double-rate output clock,
luminance channel (Y) and chroma channels (Cb or Cr) are alternated. The syncs signals are
embedded in the Y-channel. Normally this format is used only for 480i, 480p, 576i and 576p. The
IT6605 supports CCIR-656 format of up to 720p or 1080i, with the doubled-rate clock running at
148.5MHz. CCIR-656 format supports embedded syncs only. Figure 10 and Figure 11 give examples
of 12-bit and 8-bit CCIR-656 respectively. Note that while "embedded syncs" implies that neither DE
nor H/VSYNC are required, the IT6605 optionally output these signals via proper register setting to
ease the design for some backend processors.
,
Figure 10. 12-bit CCIR-656
司
SAV
00
00
限
FF
XY
技
有
QE[23:16]
Pixel2 ~ Pixel3
...
blank
公
QE[35:24]
Pixel0 ~ Pixel1
讯
科
QE[15:0]
Ypix0
[7:0]
Crpix0
[7:0]
Ypix1
[7:0]
Cbpix2
[7:0]
Ypix2
[7:0]
Crpix2
[7:0]
Ypix3
[7:0]
....
FF
Figure 11. 8-bit CCIR-656
深
圳
市
金
合
PCLK
Cbpix0
[7:0]
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Feb-2012 Rev:0.92
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IT6605
CCIR-656 + separate syncs
深
圳
:
71
44
51
81
9
8-bit
PCLK#2N
PCLK#2N+1
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
C0
Y0
C1
Y1
C2
Y2
C3
Y3
C4
Y4
C5
Y5
C6
Y6
C7
Y7
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
HSYNC
HSYNC
VSYNC
VSYNC
DE
DE
18
66
43
41
5
85
,
QQ
10-bit
PCLK#2N
PCLK#2N+1
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
C0
Y0
C1
Y1
C2
Y2
C3
Y3
C4
Y4
C5
Y5
C6
Y6
C7
Y7
C8
Y8
C9
Y9
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
HSYNC
HSYNC
VSYNC
VSYNC
DE
DE
,
司
公
限
技
有
讯
科
合
市
金
Pin Name
QE0
QE1
QE2
QE3
QE4
QE5
QE6
QE7
QE8
QE9
QE10
QE11
QE12
QE13
QE14
QE15
QE16
QE17
QE18
QE19
QE20
QE21
QE22
QE23
QE24
QE25
QE26
QE27
QE28
QE29
QE30
QE31
QE32
QE33
QE34
QE35
HSYNC
VSYNC
DE
12-bit
PCLK#2N
PCLK#2N+1
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
C0
Y0
C1
Y1
C2
Y2
C3
Y3
C4
Y4
C5
Y5
C6
Y6
C7
Y7
C8
Y8
C9
Y9
C10
Y10
C11
Y11
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
HSYNC
HSYNC
VSYNC
VSYNC
DE
DE
Table 8. Mappings of CCIR-656 + separate syncs
This format is not specified by CCIR-656. It's simply the previously mentioned CCIR-656 format plus
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Feb-2012 Rev:0.92
29/38
IT6605
QQ
:
71
44
51
81
9
separate syncs. Examples of this mode are given in Figure 12 and Figure 13.
Pixel0 ~ Pixel1
QE[35:24]
FF
00
00
XY
Cbpix0
[7:0]
Crpix0
[7:0]
Ypix1
[7:0]
Cbpix2
[7:0]
Pixel2 ~ Pixel3
Ypix2
[7:0]
...
Crpix2
[7:0]
Ypix3
[7:0]
....
blank
FF
,
QE[15:0]
Ypix0
[7:0]
18
66
QE[23:16]
43
41
5
SAV
85
,
Figure 12. 12-bit CCIR-656 + separate syncs
司
PCLK
限
公
DE
技
有
H/VSYNC
深
圳
市
金
合
讯
科
Figure 13. 8-bit CCIR-656 + separate syncs
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Feb-2012 Rev:0.92
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IT6605
12/15/18-bit RGB 4:4:4 and YCbCr 4:4:4 Using Dual-Edge Triggering
RGB
15-bit
18-bit
12-bit
YCbCr
15-bit
18-bit
12-bit
2nd
edge
1st
edge
2nd
edge
1st
edge
2nd
edge
1st
edge
2nd
edge
1st
edge
2nd
edge
1st
edge
2nd
edge
QE0
QE1
QE2
QE3
QE4
QE5
QE6
QE7
QE8
QE9
QE10
QE11
QE12
QE13
QE14
QE15
QE16
QE17
QE18
QE19
QE20
QE21
QE22
QE23
QE24
QE25
QE26
QE27
QE28
QE29
QE30
QE31
QE32
QE33
QE34
QE35
HSYNC
VSYNC
DE
B0
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
G0
G1
G2
G3
G4
G5
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
G6
G7
G8
G9
G10
G11
R0
R1
R2
R3
R4
R5
R6
R7
R8
R9
R10
R11
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
B0
B1
B2
B3
B4
B5
B6
B7
B8
B9
G0
G1
G2
G3
G4
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
G5
G6
G7
G8
G9
R0
R1
R2
R3
R4
R5
R6
R7
R8
R9
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
B0
B1
B2
B3
B4
B5
B6
B7
G0
G1
G2
G3
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
G4
G5
G6
G7
R0
R1
R2
R3
R4
R5
R6
R7
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
Cb0
Cb1
Cb2
Cb3
Cb4
Cb5
Cb6
Cb7
Cb8
Cb9
Cb10
Cb11
Y0
Y1
Y2
Y3
Y4
Y5
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
Y6
Y7
Y8
Y9
Y10
Y11
Cr0
Cr1
Cr2
Cr3
Cr4
Cr5
Cr6
Cr7
Cr8
Cr9
Cr10
Cr11
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
Cb0
Cb1
Cb2
Cb3
Cb4
Cb5
Cb6
Cb7
Cb8
Cb9
Y0
Y1
Y2
Y3
Y4
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
Y5
Y6
Y7
Y8
Y9
Cr0
Cr1
Cr2
Cr3
Cr4
Cr5
Cr6
Cr7
Cr8
Cr9
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
Cb0
Cb1
Cb2
Cb3
Cb4
Cb5
Cb6
Cb7
Y0
Y1
Y2
Y3
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
Y4
Y5
Y6
Y7
Cr0
Cr1
Cr2
Cr3
Cr4
Cr5
Cr6
Cr7
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
81
51
44
71
:
QQ
85
,
43
41
5
18
66
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Pin Name
1st
edge
HSYNC
HSYNC
HSYNC
HSYNC
HSYNC
HSYNC
HSYNC
HSYNC
HSYNC
HSYNC
HSYNC
HSYNC
VSYNC
VSYNC
VSYNC
VSYNC
VSYNC
VSYNC
VSYNC
VSYNC
VSYNC
VSYNC
VSYNC
VSYNC
DE
DE
DE
DE
DE
DE
DE
DE
DE
DE
DE
DE
Table 9. Mappings of 12/15/18-bit 4:4:4 dual-edge triggered
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Feb-2012 Rev:0.92
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IT6605
Pixel0
Pixel1
Pixel2
...
blank
81
blank
9
In this double-edge triggering mode, PCLK frequency remains at the nominal pixel clock rate. The
halved data pins, however, run at a data rate double that of the nominal pixel clock rate. Each set of
data are clocked out by the rising edge and the falling edge alternatively. Overall one complete pixel is
output within one PCLK period. Figure 14 and Figure 15 give examples of 18-bit and 12-bit RGB 4:4:4
Dual-Edge Triggered output respectively.
Gpix0
[5:0]
Rpix0
[11:6]
Gpix1
[5:0]
Rpix1
[11:6]
Gpix2
[5:0]
Rpix2
[11:6]
....
val
QE[11:6]
val
Bpix0
[11:6]
Rpix0
[5:0]
Bpix1
[11:6]
Rpix1
[5:0]
Bpix2
[11:6]
Rpix2
[5:0]
....
QE[5:0]
val
Bpix0
[5:0]
Gpix0
[11:6]
Bpix1
[5:0]
Gpix1
[11:6]
Bpix2
[5:0]
Gpix2
[11:6]
....
val
val
val
val
val
val
val
val
val
43
41
5
PCLK
71
val
85
,
val
:
val
QQ
QE[17:12]
44
51
QE[35:18]
DE
18
66
H/VSYNC
QE[13:10]
val
Gpix0
[3:0]
Pixel2
...
blank
Gpix1
[3:0]
Rpix1
[7:4]
Gpix2
[3:0]
Rpix2
[7:4]
....
val
val
val
val
Bpix0
[7:4]
Rpix0
[3:0]
Bpix1
[7:4]
Rpix1
[3:0]
Bpix2
[7:4]
Rpix2
[3:0]
....
val
val
val
val
Bpix0
[3:0]
Gpix0
[7:4]
Bpix1
[3:0]
Gpix1
[7:4]
Bpix2
[3:0]
Gpix2
[7:4]
....
val
val
val
val
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val
Rpix0
[7:4]
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val
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QE[17:14]
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QE[35:18]
QE[9:6]
Pixel1
公
Pixel0
限
blank
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Figure 14. 18-bit RGB 4:4:4 dual-edge triggered
圳
QE[5:0]
深
PCLK
DE
H/VSYNC
Figure 15. 12-bit RGB 4:4:4 dual-edge triggered
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Feb-2012 Rev:0.92
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IT6605
RGB 4:4:4 and YCbCr 4:4:4 Triggered with 0.5X PCLK at Dual Edges
Pixel2
Pixel3
Pixel4
Pixel5
Pixel6
Rpix6
val
val
val
val
Rpix0
Rpix1
Rpix2
Rpix3
Rpix4
Rpix5
QE[23:12]
val
val
val
val
Gpix0
Gpix1
Gpix2
Gpix3
Gpix4
Gpix5
QE[11:0]
val
val
val
val
Bpix0
Bpix1
Bpix2
Bpix3
Bpix4
Bpix5
Gpix6
Bpix6
blank
....
val
....
val
....
val
QQ
:
71
QE[35:24]
...
81
Pixel1
51
Pixel0
44
blank
9
The bus mapping in this format is the same as that of RGB 4:4:4 and YCbCr 4:4:4 with Separate
Syncs. The only difference is that the output video clock (PCLK) is now halved in frequency. The data
are in turn to be latched in with both the rising and falling edges of the 0.5X PCLK.
85
,
PCLK
DE
43
41
5
H/VSYNC
18
66
Figure 16. 36-bit RGB 4:4:4 dual-edges triggered with 0.5X PCLK
val
val
val
val
Pixel4
Pixel5
Pixel6
...
val
blank
Rpix0
Rpix1
Rpix2
Rpix3
Rpix4
Rpix5
Rpix6
....
val
限
技
有
val
val
val
Gpix0
Gpix1
Gpix2
Gpix3
Gpix4
Gpix5
Gpix6
....
val
val
val
Bpix0
Bpix1
Bpix2
Bpix3
Bpix4
Bpix5
Bpix6
....
val
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QE[1:0]
Pixel3
合
QE[13:12]
QE[11:2]
Pixel2
司
val
QE[25:24]
QE[23:14]
Pixel1
公
val
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QE[35:26]
Pixel0
,
blank
圳
PCLK
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H/VSYNC
Figure 17. 30-bit RGB 4:4:4 dual-edges triggered with 0.5X PCLK
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Feb-2012 Rev:0.92
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IT6605
System Design Consideration
51
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The IT6605 is a very high-speed interface chip. It receives TMDS differential signals at as high as
2.25Gbps and output TTL signals at up to 148.5MHz with 36-bit data bus. At such high speeds any
PCB design imperfection could lead to compromised signal integrity and hence degraded
performance. To get the optimum performance the system designers sould follow the guideline below
when designing the application circuits and PCB layout.
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1. Pin 54 (PVCC18) and Pin 53 (PVSS) should be supplied with clean power: ferrite-decoupled and
capacitively-bypassed, since they supply the power for the receiver PLL, which is a crucial block in
terms of receiving quality. Excess power noise might degrade the system performance.
Figure 18. Layout example for decoupling capacitors.
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2. It is highly recommended that all power pins are decoupled to ground pins via capacitors of 0.01uF
and 0.1uF. Low-ESL capacitors are prefered. Generally these capacitors should be placed on the
same side of the PCB with the IT6605 and as close to the pins as possible, preferably within 0.5cm
from the pins. It is also recommended that the power and ground traces run relatively short distances
and are connected directly to respecitve power and ground planes through via holes.
3. The IT6605 supports 36-bit output bus running at as high as 148.5MHz. To maintain signal integrity
and lower EMI, the following guidelines should be followed:
A. Employ 4-layer PCB design, where a ground or power plane is directly placed under the
signal buses at middle layes. The ground and power planes underneath these buses should
be continuous in order to provide a solid return path for EM-wave introduced currents.
B. Whenever possible, keep all TTL signal traces on the same layer with the IT6605 and the
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Feb-2012 Rev:0.92
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IT6605
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backend scalers.
C. TTL output traces to the scaler should be kept as short as possible
D. 33Ω resistors could be placed in series to the output pins. This slow down the signal rising
edges, reduces current spikes and lower the reflections.
E. The PCLK signal should be kept away from other signal traces to avoid crosstalk interference.
A general guideline is 2X the dielectric thickness. For example, if the dielectric layer between
the signal layer and the immediate power/ground layer is 7 mil, then the PCLK trace should
be kept at least 14 mil away from all other signal traces.
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43
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4. The characteristic impedance of all differential PCB traces should be kept at 100Ω all the way from
the HDMI connector to the IT6605. This is crucial to the system performance at high speeds. When
layouting these differential transmission lines, the following guidelines should be followed:
A. The signals traces should be on the outside layers (TOP layer or BOTTOM layer) while
beneath it there should be a continuous ground plane in order to maintain the so-called
micro-strip transmission line structure, giving stable and well-defined characteristic
impedances.
B. Carefully choose the width and spacing of the differential transmission lines as their
characteristic impedance depends on various parameters of the PCB: trace width, trace
spacing, copper thickness, dielectric constant, dielectric thickness, etc. Careful 3D EM
simulation is the best way to derive a correct dimension that enables a nominal 100Ω
differential impedance.
C. Cornering, through holes, crossing and any irregular signal routing should be minimized so as
to prevent from disrupting the EM field and creating discontinuity in characteristic impedance.
D. The IT6605 should be placed as close to the HDMI connector as possible. If the distance
between the chip and the connector is under 2 cm, the reflections could be kept small even if
the PCB traces do not have an 100Ω characteristic impedance. The extra signal attenuation
contributed by the PCB traces could be minimized, too.
深
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5. Special care should be taken when adding discrete ESD devices to all differential PCB traces
(RX2P/M, RX1P/M, RX0P/M, RXCP/M). The IT6605 is designed to provide ESD protection for up to
2kV at these pins, which is good enough to prevent damages during assembly. To meet the system
EMC specification, external discrete ESD diodes might be added. But note that adding discrete ESD
diodes inevitably add capacitive loads, therefore degrade the electrical performance at high speeds. If
not chosen carefully, these diodes coupled with less-than-optimal layout would prevent the system
from passing the SINK TMDS-Differential Impedance test in the HDMI Compliance Test (Test ID 8-8).
One should only use low-capacitance ESD diode to protect these high-speed pins. Commercially
available devices such as Semtech's RClamp0524p that take into consideration of all aspects of
designing and protecting high-speed transmission lines are recommended. (http://www.semtech.com/
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Feb-2012 Rev:0.92
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IT6605
18
66
43
41
5
85
,
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9
products/product-detail.jsp?navId=H0,C2,C222,P3028).
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Figure 19. Layout example for high-speed TMDS differential signals
限
6. By default Pin 55 (REXT) should be connected to ground via a 500Ω/1% precision SMD resistor to
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provide for receiver termination calibration. If this pin is to be left open, be sure to set the bit 6 of
register 0x6A to '1' in order to disable the termination calibration. Disabling the termination calibration
would leave the value of termination impedance subject to process, supply voltage and temperature
variation, sometimes rendering it out of specification and degrading the performance. Therefore it is
highly recommended that this calibration function is left turned-on and a 500Ω/1% resistor is
connected between Pin 55 and ground. The resistor should be placed as close to the IT6605 as
possible.
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Feb-2012 Rev:0.92
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IT6605
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43
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5
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Package Dimensions
Figure 20. 144-pin LQFP Package Dimensions
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Feb-2012 Rev:0.92
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IT6605
Classification Reflow Profiles
3℃/second max.
Preheat
-Temperature Min(Tsmin)
-Temperature Max(Tsmax)
-Time(tsmin to ts tsmax)
150℃
200℃
60-180 seconds
44
51
Average Ramp-Up Rate (Tsmax to Tp)
9
Pb-Free Assembly
81
Reflow Profile
Time maintained above:
-Temperature(TL)
-Time(tL)
QQ
:
71
217℃
60-150 seconds
Peak Temperature(Tp)
85
,
260 +0 /-5℃
Time within 5 ℃ of actual Peak
Temperature(tp)
43
41
5
20-40 seconds
Ramp-Down Rate
8 minutes max.
18
66
Time 25℃ to Peak Temperature
6℃/second max.
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Note: All Temperature refer to topside of the package, measured on the package body surface.
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Feb-2012 Rev:0.92
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