MDTIC MK6A20P

MK6A20P
8Bit Microcontroller
General Description
The MK6A20P is an 8 bit RISC high performance microcontroller. It is equipped with 2Kx14bits OTP(One
Time Programmable) ROM, 72 Bytes RAM, Timer/Counter, Interrupt, LVR(Low Voltage Reset) and I/O
ports in a single chip.
1. Feature
z
ROM size: 2K x 14 bits
z
RAM: 72 x 8 bits
z
STACK: 6 Levels
z
One instruction is built by 4 system clock.
z
Reset mode:
- Power-On reset
- Low voltage reset
- RESETB/PA5 (if set as reset pin) input a negative pulse.
- Watchdog timer count overflow reset
z
5 oscillation mode can be selected
- External RC, LS (Low Speed) Crystal, NS (Normal Speed) Crystal and HS (High Speed) Crystal
- Internal 4MHz RC oscillator
z
z
Timer/counter: 2 sets.
-
TMR0: 8 bit count up timer/counter with auto reload function
-
TMR1: 8 bit count up timer/counter with auto reload function
Watchdog Timer: On chip WDT is based on an internal RC oscillator (for WDT used only). Have 8
period can be selected. User can extend the WDT overflow period by using prescaler.
z
Interrupt events:
- TMR0 Internal timer/event counter interrupt
- TMR1 Internal timer/event counter interrupt
- External INT pin
z
I/O port: 25 pins
- PA0~7: 7 pull high I/O pins, 1 input only pin (PA5)
- PB0~7: 8 pull high I/O pins with pin wake up function
- PC0~7: 8 pull high I/O pins
- PD0~1: 2 pull high I/O pins
z
Wake-up mode:
A.
Watch Dog timer wakeup
B.
Port B (PB0~7) pin change wakeup
C. i_WDT wakeup
MK6A20P
z
Different Package Type:
MK6A20PD28C: 28 pin DIP
MK6A20PS28C: 28 pin SOP
MK6A20PD20C: 20 pin DIP
MK6A20PS20C: 20 pin SOP
2. Block Diagram
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MK6A20P
3. Pin Definition & Pad Assignment
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MK6A20P
4. Pin Description
Name
PA0 ~ PA3
I/O
I/O
Description
1. General purpose I/O port
2. With pull high resistor
PA4/RTCC0
I/O
1. General purpose I/O port
2. With pull high resistor .
3. External clk input (for TMR0).
PA5/RESETB
I
1. Input pin only
2. System reset signal (active low)
PA6/OSC1
I/O
1. General purpose I/O port
2. With pull high resistor .
3. Oscillator input pin (Crystal mode can not set pull high)
PA7/OSC2
I/O
1. General purpose I/O port
2. With pull high resistor .
3. Oscillator output pin (Crystal mode can not set pull high)
PB0 ~ PB7
I/O
1. General purpose I/O port
2. With pull high resistor .
3. Pin change wake up from sleep mode
PC0 ~ PC4
I/O
1. General purpose I/O port
2. With pull high resistor
PC5/CLKO
I/O
1. General purpose I/O port
2. With pull high resistor .
3. System clk output , sys_c($13) b2=1.
PC6
I/O
1. General purpose I/O port
2. With pull high resistor
PC7/RTCC1
I/O
1. General purpose I/O port
2. With pull high resistor .
3. External clk input (for TMR1).
PD0
I/O
1. General purpose I/O port
2. With pull high resistor .
PD1/INT
I/O
1. General purpose I/O port
2. With pull high resistor .
3. External interrupt active by rising edge trigger(option)
VDD
P
System Power Input
VSS
P
System Ground Input
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1. Memory Map
The MK6A20P have two kinds of memory which are ROM (program memory) and RAM (data memory). The
ROM is used to store the program, table and interrupt vectors. It is continuous 2048x14bits and don’t need to
switch bank. The RAM is 92(20+72)x8bits that include special function register and general-purpose RAM.
5.1 Program Memory (ROM)
Instruction and table are stored at this area. There is only one interrupt vector existed which means all the
interrupt occurred would jump to the same vector. Programmer should use interrupt flag to judge what kind of
interrupt is occurred. The program counter (PC) is 10 bit which can directly address all the 2048x14bits
location. Look-up table can be put at anywhere of ROM.
The RESET vector is located at 7FFH and Interrupt vector is at 7FEH. The map is as below:
000H
PC (10bit)
STACK Level 1
STACK Level 2
STACK Level 3
STACK Level 4
STACK Level 5
STACK Level 6
INTERRUPT VECTOR
RESET VECTOR
7FEH
7FFH
<Note> LCALL and LGOTO allow directly operate 2K word addressing
5.2 Data Memory (RAM)
The total RAM volumes are 92x8bits which includes two kinds of register group. One is 72×8bits general
purpose RAM, the other is special purpose register that are 20×8bits. Every byte of special purpose register
stored control’s data or operation’s data.
The data memory map is as below:
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<Note> LCALL and LGOTO allow directly operate 2K word addressing
Special Purpose Register
Name
Bit8
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
CONFIGL
RTCE
RESETE
LV1
LV0
WDTE
CPT
INRC
FOSC1
FOSC0
Name
Bit8
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
CONFIGH
ADJ6
ADJ5
ADJ4
ADJ3
ADJ2
ADJ1
ADJ0
VER
TYPE
<Note> CONFIG is a 14 bit X 2 special register
Name
Addr
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
IAR
$00
A7
A6
A5
A4
A3
A2
A1
A0
TM0_LA
$01
D7
D6
D5
D4
D3
D2
D1
D0
PCL
$02
A7
A6
A5
A4
A3
A2
A1
A0
STATUS
$03
--
BS1
BS0
TO
PD
Z
DC
C
BSR
$04
1
RAM_BANK6
RAM_BANK5
D4
D3
D2
D1
D0
PA
$05
PA7
PA6
--
PA4
PA3
PA2
PA1
PA0
PB
$06
PB7
PB6
PB5
PB4
PB3
PB2
PB1
PB0
PC
$07
PC7
PC6
PC5
PC4
PC3
PC2
PC1
PC0
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MK6A20P
PD
$08
--
--
--
--
--
--
PD1
PD0
IRQM
$09
INTM
--
--
--
--
EXINTM
IRQF
$0A
--
--
--
--
--
EXINTF
TM1F
TM0F
* PA_PUP
$0B
UA7
UA6
--
UA4
UA3
UA2
UA1
UA0
* PB_PUP
$0C
UB7
UB6
UB5
UB4
UB3
UB2
UB1
UB0
* PC_PUP
$0D
UC7
UC6
UC5
UC4
UC3
UC2
UC1
UC0
* PD_PUP
$0E
--
--
--
--
--
--
UD1
UD0
WAKEUP
$0F
EN7
EN6
EN5
EN4
EN3
EN2
EN1
EN0
TM0_CTL
$10
TM0_EN
WR_CNT
SUR0
EDGE
PSA
PRE2
PRE1
PRE0
TM1_CTL
$12
TM1_EN
WR_CNT
SUR0
EDGE
--
PRE2
PRE1
PRE0
TM1_LA
$13
D7
D6
D5
D4
D3
D2
D1
D0
SYS_C
$14
i_WDT
i_STAB
EXINTE
--
TM1M TM0M
CLK_OE RTCE1
RTCE0
<Note> “—“ : mean no use.
“ * “ : mean write only .
Configure Register
Name
Bit8
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
CONFIGL
RTCE
RESETE
LV1
LV0
WDTE
CPT
INRC
FOSC1
FOSC0
Name
Bit8
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
CONFIGH
ADJ6
ADJ5
ADJ4
ADJ3
ADJ2
ADJ1
ADJ0
VER
TYPE
CONFIG_H :
z
Bit8~2 (ADJ6~0): Used to calibrated internal RC oscillator.
z
Bit1 (VER) : Version select .
0 : Old version .
1 : New version (init) for MK6A20P .
z
Bit0 (TYPE): for old version set (Don’t care)
CONFIG_L :
z
Bit8 (RTCE): for old version set (Don’t care)
z
Bit7 (RESETE): RESETB pin define
0: RESETB is normal input pin
1: RESETB is system reset pin
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MK6A20P
z
z
Bit6~5 (LV1, LV0): Set reset voltage level of Low Voltage Reset (LVR)
Bit6
Bit5
LV1
LV0
0
0
4V
0
1
Don’t use
1
0
2.2V
1
1
Don’t use
Detect voltage
Bit4 (WDTE): Watchdog timer enable/disable
0: WDT disable
1: WDT enable
z
Bit3 (CPT): ROM Code Protection bit
0: ON
1: OFF
z
Bit2~0 (INRC, FOSC1~0): OSC type and system clock select
Bit2
Bit1
Bit0
INRC
FOSC1
FOSC0
0
0
0
LS (low speed)
System clock=32~200KHz
0
0
1
NS (Normal speed)
System clock=200K~10MHz
0
1
0
HS (high speed)
System clock=10~20MHz
0
1
1
External RC
System clock=32K ~ 10MHz
1
0
0
Reserved
Reserved
1
0
1
Reserved
Reserved
1
1
0
Reserved
Reserved
1
1
1
Internal RC
System clock=4MHz
OSC Type
8
Resonance Frequency
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MK6A20P
6. Function Deceptions
This device provide many functions that are I/O ports, Timer, WDT, Interrupt, Table location, Reset, Program
Counter and STATUS register. We would like to describe in detail.
6.1 I/O Port
There are 4 I/O ports (A ,B,C&D) to input or output data, each port has different function. The port A,C,D are
general purpose I/O port with pull up resistor. The port B have multiple functions which can be used as general
purpose I/O port with pull up resistor and pin wake up function. And some of them have another function by
option.
6.1.1 Port A
A. PA ($05H):
Register
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PA
PA7
PA6
--
PA4
PA3
PA2
PA1
PA0
z
Bit3~0 (IOA3~0): Data of I/O ports A
B. PA_PUP ($0BH):
Register
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PA_PUP
UA7
UA6
--
UA4
UA3
UA2
UA1
UA0
z
Bit7~0 (UA7~0): Pull up resistor enables/disable
0: Pull up resistor disable.
1: Pull up resistor enable.
<Note> 1. PA5 is shared with RESETB and only can be used as input port. If used as PA5 then there is no pull
up resistor. If used as RESETB, then there is pull up resistor.
2. UA6 and UA7 is used in RC oscillation mode only. If user use Crystal mode, then these two bits are
useless and can not be set to pull up. Otherwise, it will cause malfunction.
6.1.2 Port B
A. PB ($06H):
Register
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PB
PB7
PB6
PB5
PB4
PB3
PB2
PB1
PB0
z
Bit7~0 (PB7~0): Data of I/O Ports B
B. PB_PUP ($0CH):
Register
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PB_PUP
UB7
UB6
UB5
UB4
UB3
UB2
UB1
UB0
z
Bit7~0 (UB7~0): Pull up resistor enable/disable.
0: Pull up resistor disable.
1: Pull up resistor enable.
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6.1.3 Port C
A. PC ($07H):
Register
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PC
PC7
PC6
PC5
PC4
PC3
PC2
PC1
PC0
z
Bit7~0 (PB7~0): Data of I/O Ports B
B. PC_PUP ($0DH):
Register
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PC_PUP
UC7
UC6
UC5
UC4
UC3
UC2
UC1
UC0
z
Bit7~0 (UC7~0): Pull up resistor enable/disable.
0: Pull up resistor disable.
1: Pull up resistor enable.
6.1.4 Port D
A. PD ($08H):
Register
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PD
--
--
--
--
--
--
PD1
PD0
z
Bit7~0 (PB7~0): Data of I/O Ports B
B. PD_PUP ($0EH):
Register
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PD_PUP
--
--
--
--
--
--
UD1
UD0
Bit 2
Bit 1
Bit 0
z
Bit7~0 (UD7~0): Pull up resistor enable/disable.
0: Pull up resistor disable.
1: Pull up resistor enable.
6.15 SYS_C ($14H):
Register
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
SYS_C
i_WDT
i_STAB
--
EXTINTE
--
z
CLK_OE RTCCE1 RTCCE0
Bit7 : i_WDT mode :
0 : i_WDT mode disable (init)
1 : i_WDT mode enable (WDTE must enable)
z
Bit5: i_STAB ( i_WDT mode) wakeup times set .
0: 1.25ms ( init) .
1: 625us ( Low power consumption)
z
Bit4 : EXTINTE external interrupt function
0 : PD1 pin is PD1 I/O pin
1 : PD1 pin is external interrupt pin (rising edge)
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MK6A20P
z
Bit2 : CLK_OE system clk output function
0 : PC5 pin is PC5 I/O pin
1 : PC5 pin is system_clk output
z
Bit1 : RTCCE1 TMR1 external clk function
0 : disable
1 : enable
<Note> The method to count RTCC1 input are:
1. Set TMR1_CTL($12) SUR0(bit5) to 1.
2. Set RTCCE1 bit to 1 to set PC7 pin as RTCC and enable the RTCC clock in.
z
Bit0 : RTCCE0 TMR0 external clk function
0 : disable
1 : enable
<Note> The method to count RTCC0 input are:
1. Set TMR0_CTL($10) SUR0(bit5) to 1.
2. Set RTCCE0 bit to 1 to set PA4 pin as RTCC and enable the RTCC clock in.
6.16. WAKEUP ($0FH):
Register
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
WAKEUP
EN7
EN6
EN5
EN4
EN3
EN2
EN1
EN0
z
Bit7~0 (EN7~0): Port B wakeup enable/disable
0: Port B wakeup disable
1: Port B wakeup enable
<Note> If i_WDT mode was enabled, bit 7(EN7) will be inhibited automatically.
6.2 Timer/Counter
The MK6A20P provide two up count timers/counters and 1 watchdog timer. Clock source of counters can be
system clock or external clock by setting each timer control register. The detailed registers setting and block
diagram are as below.
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MK6A20P
6.21. TM0_CTL ($10H):
Register
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
TM0_CTL
TM0_EN
WR_CNT
SUR0
EDGE
PSA
PRE2
PRE1
PRE0
z
Bit7 : (TM0_EN) Timer0 enable/disable
0 : disable
1 : enable
z
Bit6 : (WR_CNT) Auto pre_load TMR0 data
0 : disable
1 : enable
z
Bit5 : (SUR0) TMR0 clk source select
0 : (system clk)/4
1 : external clk input (PA4/RTCC0)
z
Bit4 : (EDGE) TMR0 external clk edge control bit
0 : increment when L→H transition on external clock
1 : increment when H→L transition on external clock
z
Bit3 : (PSA) Prescaler assignment bit
0 : Prescaler assigned to TMR0
1 : Prescaler assigned to WDT
z
Bit2~0 (PRE2~0): Set TM0(WDT) prescaler rate
Bit2
Bit1
Bit0
PRE2
PRE1
PRE0
0
0
0
TM0 Prescaler rate
WDT Prescaler rate
0
1:2
1:1
0
1
1:4
1:2
0
1
0
1:8
1:4
0
1
1
1:16
1:8
1
0
0
1:32
1:16
1
0
1
1:64
1:32
1
1
0
1:128
1:64
1
1
1
1:256
1:128
6.22. TM0_LA ($01H):
Register
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
TM0_LA
D7
D6
D5
D4
D3
D2
D1
D0
z
Bit7~0 : (TM0_LA) Timer0 Data
<Note> The timer is up counter timer. When it up counts to FF(FF->00) that will occur overflow and TM0F will
be set to “1”. At this moment, the zero flag will not be affected. So, please read TM0F to judge whether it
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overflow or not.
6.23. TM1_CTL ($12H):
Register
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
TM1_CTL
TM1_EN
WR_CNT
SUR0
EDGE
--
PRE2
PRE1
PRE0
z
Bit7 : (TM1_EN) Timer1 enable/disable
0 : disable
1 : enable
z
Bit6 : (WR_CNT) Auto pre_load TMR1 data
0 : disable
1 : enable
z
Bit5 : (SUR0) TMR1 clk source select
0 : (system clk)/4
1 : external clk input (PC7/RTCC1)
z
Bit4 : (EDGE) TMR1 external clk edge control bit
0 : increment when L→H transition on external clock
1 : increment when H→L transition on external clock
z
Bit2~0 (PRE2~0): Set TM1 prescaler rate
Bit2
Bit1
Bit0
PRE2
PRE1
PRE0
0
0
0
1:2
0
0
1
1:4
0
1
0
1:8
0
1
1
1:16
1
0
0
1:32
1
0
1
1:64
1
1
0
1:128
1
1
1
1:256
TM1 Prescaler rate
6.22. TM1_LA ($13H):
Register
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
TM1_LA
D7
D6
D5
D4
D3
D2
D1
D0
z
Bit7~0 : (TM1_LA) Timer1 Data
<Note> The timer is up counter timer. When it up counts to FF(FF->00) that will occur overflow and TM1F will
be set to “1”. At this moment, the zero flag will not be affected. So, please read TM1F to judge whether it
overflow or not.
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MOVLA
b’10000001’
MOVAM
IRQM ; set tm0 irq enable ;
CLR
IRQF ; clear tm0 flag ;
MOVLA
b’01000010’
MOVAM
TM0_CTL ; bit6=1; auto pre_load, bit5=0; clk=system clk/4,
Bit3=0; pre-scaler assign to tm0, pre-scaler=1:8
MOVLA
b‘10000000’
MOVAM
TM0_LA
BS
TM0_CTL,7 ; tm0 start = inrc(4mhz)/4 x 8 x 128=1024us ;
.
.
.
.
INT:
CLR
IRQF ; clear tm0 flag ;
.
.
.
.
RETI
6.3 Indirect Addressing
Register IAR($00) and BSR($04) will be used to address indirectly. BSR (Bank Select Register) allows 7-bit
wide operand to directly access the whole data (00~7F) memory. The method is as below map:
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MK6A20P
Direct Addressing mode :
Indirect Addressing mode :
(Opcode)
M7
M6
M5
M4
M3
(BSR)
M2
M1
M0
1
b6
b5
b4
b3
b2
b1
b0
00
7F
Data
memory
6.4 WDT (Watchdog Timer)
WDT is a timer to prevent software from malfunction or jumping to an unknown location with unpredictable
result. The source clock of WDT is an independent internal RC oscillator. This timer would be affected by
temperature, voltage and different production lot. The minimum time is around 20ms. Programmer can use
TM0_CTL(bit3) to set prescaler and get the different duration.
6.5 Reset
There are 4 events will cause reset which is listed as below. The power-down event will cause MK6A20P reset.
This condition is used to protect chip in deficient power environment. The last two cases are called warm reset.
Different reset events will affect registers and RAM. The
TO and PD bits can be used to determine the
type of reset.
(1) Power-on reset.
(2) Low voltage reset (LVR).
(3) RESETB pin reset (input a negative pulse).
(4) WDT timer overflow reset.
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System Clock
Power on reset
Synchronize with ripple counter
Low voltage reset
RESETB pin
RESET
Delay for setup time
Watchdog Timer
Internal specific RC
OSC
WDT
overflow
System Reset Block
<Note>: the watchdog setup time is approximately 20ms that will has some tolerance due to power voltage,
process and temperature variations.
Address
Name
Cold Reset
Warm Reset
N/A
Accumulator
xxxx xxxx
pppp pppp
PA
1111 1111
1111 1111
PB
1111 1111
1111 1111
PC
1111 1111
1111 1111
PD
xxxx xx11
xxxx xx11
N/A
IODIR
00h
IAR
---- ----
---- ----
01h
TM0_LA
0000 0000
0000 0000
02h
PCL
11 1111 1111
11 1111 1111
03h
STATUS
0001 1xxx
#00# #ppp
04h
BSR
1xxx xxxx
1ppp pppp
05h
PA
xxxx xxxx
ppxp pppp
06h
PB
xxxx xxxx
pppp pppp
07h
PC
xxxx xxxx
pppp pppp
08h
PD
xxxx xxxx
xxxx xxpp
09h
IRQM
0000 0000
0000 0000
0Ah
IRQF
0000 0000
0000 0000
0Bh
PA_PUP
00x0 0000
00x0 0000
0Ch
PB_PUP
0000 0000
0000 0000
0Dh
PC_PUP
0000 0000
0000 0000
0Eh
PD_PUP
0000 0000
0000 0000
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MK6A20P
0Fh
WAKEUP
0000 0000
0000 0000
10h
TM0_CTL
0110 0000
0110 0000
12h
TM1_CTL
0000 0000
0000 0000
13h
TM1_LA
0000 0000
0000 0000
14h
SYS_C
00x0 x000
00x0 x000
xxxx xxxx
pppp pppp
General Purpose
28h~6Fh
RAM
<Note> x: unknown; p: keep as previous data ; #: value depends on condition
-:unimplemented and read as”0”.
6.5.1 Reset condition of STATUS register
Status Register
Condition
TO
PD
1.Power-on reset
1
1
2.RESETB reset during normal operation<Note 3>
U
U
3.RESETB reset during sleep <Note 3>
1
0
4.WDT reset during sleep
0
0
5.WDT reset during normal operation
0
1
6.Wake up by pin changed
1
0
<Note> 1. If execute CLRWDT then the content of item 4,5 would not be as the above.
2. U: Unchanged
3. The data of
TO and PD is as the table only when reset and PSA bit (TM0_CTL register) was set
to “1”. If PSA doesn’t set to “1”, the data after reset is not as table.
6.6 Interrupt
The MK6A20P provides 3 interrupts which are TM0, TM1 and external INT. IRQM and IRQF registers are
used to control or declare request state of all interrupts. IRQM is used to enable/disable interrupt and IRQF is
used to indicate which interrupt is occurred. If the specific IRQM doesn’t enable then the hardware interrupt
would not occurred. But the IRQF will response the status no matter how IRQM enable or not. For example,
user enable TMR0 to start counting. If IRQM bit 0 is enabled, the hardware interrupt would generate when
timer overflow and IRQF bit 1 will be set. At the same time, program will jump to interrupt vector. User should
clear IRQF in interrupt service routine, otherwise the interrupt would not work properly. Another condition is if
IRQM bit 0 is disabled, the interrupt would not generate when timer overflow, but IRQF bit 1 still will be set.
Program would not jump to interrupt vector.
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A. IRQM ($09H)
Register
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
IRQM
INTM
--
--
--
--
EXINTM
Bit 1
Bit 0
TM1M
TM0M
z Bit7 (INTM): Global enable bit.
0: Disable. All interrupts are mask.
1: Enable. All interrupt are unmask
When interrupt is serving, the INTM will reset to “0” to prevent the other interrupt happen. After
served, the RETI instruction will set INTM as ‘1’.
z Bit2 (EXTINTM): external INT pin interrupt enable/disable
0: Disable Interrupt
1: Enable Interrupt
z Bit1 (TM1M): TM0 interrupt enable/disable
0: Disable Interrupt
1: Enable Interrupt
z Bit0 (TM0M): TM0 interrupt enable/disable
0: Disable Interrupt
1: Enable Interrupt
B. IRQF ($0AH)
Register
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
IRQF
--
--
--
--
--
EXINTF
TM1F
TM0F
z Bit2 (EXINTF): external INT pin interrupt flag
0: Interrupt signal doesn’t occurred
1: Interrupt signal occurred
z Bit1 (TM1F): TM1 interrupt flag
0: Interrupt signal doesn’t occurred
1: Interrupt signal occurred
z Bit0 (TM0F): TM0 interrupt flag
0: Interrupt signal doesn’t occurred
1: Interrupt signal occurred
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6.7 STATUS Register
The STATUS register is an 8-bit register that contains the zero flag (Z), carry flag (C), Nibble carry flag (DC),
power down flag ( PD ), and watchdog timer overflow flag ( TO ). It records the status information.
A. STATUS($03H)
Register
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
STATUS
--
BS1
BS0
TO
PD
Z
DC
C
z Bit6~5 (BS1,BS0) : Bank select
0 0 (init) : Bank0 ( 000H ~ 1FFH).
01:
Bank1 ( 200H ~ 3FFH ).
10
: Bank2 ( 400H ~ 5FFH).
11:
Bank3 ( 600H ~ 7FFH )
z Bit4 ( TO ): Timer overflow flag bit
z Bit3 ( PD ):Power down flag bit
Description
TO
PD
0
0
WDT timer overflow from sleep mode
0
1
WDT timer overflow from normal mode
1
0
Input a ‘low” at RESETB from sleep mode
1
1
Power on reset
Unchanged
Unchanged Input a “low” at RESETB from normal mode
z Bit2 (Z): zero flag bit
0: the result of a logic operation is not zero
1: the result of a logic operation is zero
z Bit1 (DC): Nibble Carry and Nibble
Borrow flag bit
ADD instruction:
0: no carry
1: a carry from the low nibble bits of the result occurred
SUB instruction
0: a borrow from the low nibble bits of the result occurred
1: no borrow
z Bit0 (C): Carry and
Borrow flag bit
ADD instruction:
0: no carry
1: a carry occurred from the MSB
SUB instruction
0: a borrow occurred from the MSB
1: no borrow
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6.8 Wake up function
a. pin change wake_up
The chip provide pin signal toggle wake up function. It will return from sleep mode when signal toggle in input
port. In order to safely wake up from sleep mode, we suggest to read the input pin to store data before entering
sleep mode. The sample program is as below:
MOVLA
FFh
IODIR
PB
………
………..
MOV
PB,a
BS
WAKEUP,0
SLEEP
;// set bit0~7 of port B as input. Only input pin can be wake up
;//Store the data of input pin before sleep
;//Set PB0 is wakeup pin
;// if doesn’t perform the read instruction, then can not enter
;// SLEEP mode
NOP
;//Add NOP instruction to delay a while when chi
b. i_WDT wake_up
The chip provide internal watch dog (i_WDT) wake up function. It will return from sleep mode when watch dog
timer overflow. In order to safely wake up from sleep mode, this wake up mode must set one config bit enable
WDTE(bit4), one register SYS_C ($14h) i_WDT(bit7)=1, At this stage, bit 7 (EN7) of register WAKEUP ($0FH)
will be inhibited. The setting flow of i_WDT is as below:
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i_WDT-Wakeup :
(Internal watch-dog timer
wake-up)
WDT-Wakeup :
(Watch-dog timer wake-up)
Set Config :
Set Config :
WDTE(bit4)=enable
WDTE(bit4)=enable
Set Register :
(prescaler)
Set Register :
(prescaler)
TM0_CTL($10h)
TM0_CTL($10h)
B＇0000 1xxx＇
(Max=2S)
B＇0000 1xxx＇(N)
(Max=2S)
.
.
.
SLEEP
NOP
Set Register :
SYS_C ($14h)
i_WDT=1 (bit7)
i_STAB=1 or 0 (bit6)
Wait
(20ms*N sleep
time+20ms clk
stable time)
(N=1~128)
.
.
.
SLEEP
NOP
System Reset
Wait
(20ms*N sleep
time+i_STAB
times( clk stable
time)
(N=1~128)
Next(sleep)
instruction
NOP
.
* CLRWDT
.
.
start
clrwdt
movla
0Fh
movam tm0_ctl ;set prescaler
for WDT
.
& prescaler=128
.
.
System reset
*When wakeup must
CLRWDT, otherwise watchdog timer will keep operation
start
Sleep
nop
clrwdt
movla
select
.
.
.
Sleep
nop
clrwdt
.
0fh
;set prescaler for WDT
& prescaler=128
.
.
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Instruction
<Note> Instruction cycle is system clock/4
Mnemonic
Instruction
Operands
Code (Advance)
ADD M, m
(M)+(acc) → (M)
1
C, DC, Z 01 0101 1MMM MMMM
ADD M, a
(M)+(acc) → (acc)
1
C, DC, Z 01 0101 0MMM MMMM
AND M, m
(M)．(acc) → (M)
1
Z
01 0100 1MMM MMMM
AND M, a
(M)．(acc) → (acc)
1
Z
01 0100 0MMM MMMM
ANDLA I
Literal ．(acc) → (acc)
1
Z
11 1001 iiii iiii
BC M, b0
Clear bit0 of (M)
1
None
00 1100 0MMM MMMM
BC M, b1
Clear bit1 of (M)
1
None
00 1100 1MMM MMMM
BC M, b2
Clear bit2 of (M)
1
None
00 1101 0MMM MMMM
BC M, b3
Clear bit3 of (M)
1
None
00 1101 1MMM MMMM
BC M, b4
Clear bit4 of (M)
1
None
00 1110 0MMM MMMM
BC M, b5
Clear bit5 of (M)
1
None
00 1110 1MMM MMMM
BC M, b6
Clear bit6 of (M)
1
None
00 1111 0MMM MMMM
BC M, b7
Clear bit7 of (M)
1
None
00 1111 1MMM MMMM
BS M, b0
Set bit0 of (M)
1
None
00 1000 0MMM MMMM
BS M, b1
Set bit1 of (M)
1
None
00 1000 1MMM MMMM
BS M, b2
Set bit2 of (M)
1
None
00 1001 0MMM MMMM
BS M, b3
Set bit3 of (M)
1
None
00 1001 1MMM MMMM
BS M, b4
Set bit4 of (M)
1
None
00 1010 0MMM MMMM
BS M, b5
Set bit5 of (M)
1
None
00 1010 1MMM MMMM
BS M, b6
Set bit6 of (M)
1
None
00 1011 0MMM MMMM
BS M, b7
Set bit7 of (M)
1
None
00 1011 1MMM MMMM
Cycles
Status
Affected
OP-code
BTSC M, b0
If bit0 of (M) = 0, skip next instruction 1 + (skip)
None
00 0100 0MMM MMMM
BTSC M, b1
If bit1 of (M) = 0, skip next instruction 1 + (skip)
None
00 0100 1MMM MMMM
BTSC M, b2
If bit2 of (M) = 0, skip next instruction 1 + (skip)
None
00 0101 0MMM MMMM
BTSC M, b3
If bit3 of (M) = 0, skip next instruction 1 + (skip)
None
00 0101 1MMM MMMM
BTSC M, b4
If bit4 of (M) = 0, skip next instruction 1 + (skip)
None
00 0110 0MMM MMMM
BTSC M, b5
If bit5 of (M) = 0, skip next instruction 1 + (skip)
None
00 0110 1MMM MMMM
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BTSC M, b6
If bit6 of (M) = 0, skip next instruction 1 + (skip)
None
00 0111 0MMM MMMM
BTSC M, b7
If bit7 of (M) = 0, skip next instruction 1 + (skip)
None
00 0111 1MMM MMMM
BTSS M, b0
If bit0 of (M) = 1, skip next instruction 1 + (skip)
None
00 0000 0MMM MMMM
BTSS M, b1
If bit1 of (M) = 1, skip next instruction 1 + (skip)
None
00 0000 1MMM MMMM
BTSS M, b2
If bit2 of (M) = 1, skip next instruction 1 + (skip)
None
00 0001 0MMM MMMM
BTSS M, b3
If bit3 of (M) = 1, skip next instruction 1 + (skip)
None
00 0001 1MMM MMMM
BTSS M, b4
If bit4 of (M) = 1, skip next instruction 1 + (skip)
None
00 0010 0MMM MMMM
BTSS M, b5
If bit5 of (M) = 1, skip next instruction 1 + (skip)
None
00 0010 1MMM MMMM
BTSS M, b6
If bit6 of (M) = 1, skip next instruction 1 + (skip)
None
00 0011 0MMM MMMM
BTSS M, b7
If bit7 of (M) = 1, skip next instruction 1 + (skip)
None
00 0011 1MMM MMMM
CLRA
Clear accumulator
1
Z
01 0001 0000 0000
CLR M
Clear memory M
1
Z
01 0001 1MMM MMMM
CLRWDT
Clear watch-dog register
1
TO, PO
01 0000 0000 0001
COM M, m
~(M) → (M)
1
Z
01 0010 1MMM MMMM
COM M, a
~(M) → (acc)
1
Z
01 0010 0MMM MMMM
DEC M, m
Decrement M to M
1
Z
01 0110 1MMM MMMM
DEC M, a
(M) - 1 → (acc)
1
Z
01 0110 0MMM MMMM
DECSZ M, m
(M) - 1 → (M), skip if (M) = 0
1 + (skip)
None
01 0111 1MMM MMMM
DECSZ M, a
(M) - 1 → (acc), skip if (M) = 0
1 + (skip)
None
01 0111 0MMM MMMM
INC M, m
(M) + 1 → (M)
1
Z
01 1000 1MMM MMMM
INC M, a
(M) + 1 → (acc)
1
Z
01 1000 0MMM MMMM
INCSZ M, m
(M) + 1 → (M), skip if (M) = 0
1 + (skip)
None
01 1001 1MMM MMMM
INCSZ M, a
(M) + 1 → (acc), skip if (M) = 0
1 + (skip)
None
01 1001 0MMM MMMM
IODIR M
Set i/o direction
1
None
01 0000 0000 MMMM
IOR M, m
(M) ior (acc) → (M)
1
Z
01 1111 1MMM MMMM
IOR M, a
(M) ior (acc) → (acc)
1
Z
01 1111 0MMM MMMM
IORLA l
Literal ior (acc) → (acc)
1
Z
11 0011 iiii iiii
2
None
2
None
LCALL I
LGOTO I
Call subroutine. However, LCALL can
addressing 1K address
Go branch to any address
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MOVAM m
Move data form acc to memory
1
None
01 0000 1MMM MMMM
MOVLA l
Move literal to accumulator
1
None
11 0001 iiii iiii
MOV M, m
(M) → (M)
1
Z
01 0011 1MMM MMMM
MOV M, a
(M) → (acc)
1
Z
01 0011 0MMM MMMM
NOP
No operation
1
None
01 0000 0000 0000
RET
Return
2
None
11 1111 0111 1111
RETI
Return and enable INTM
2
None
11 1111 1111 1111
RETLA l
Return and move literal to accumulator
2
None
11 1100 iiii iiii
RL M, m
Rotate left from m to itself
1
C
01 1100 1MMM MMMM
RL M, a
Rotate left from m to acc
1
C
01 1100 0MMM MMMM
RR M, m
Rotate right from m to itself
1
C
01 1110 1MMM MMMM
RR M, a
Rotate right from m to acc
1
C
01 1110 0MMM MMMM
SLEEP
Enter sleep (saving) mode
1
TO, PO
01 0000 0000 0011
SUB M, m
(M)–(acc) → (M)
1
C, DC, Z 01 1010 1MMM MMMM
SUB M, a
(M) –(acc) → (acc)
1
C, DC, Z 01 1010 0MMM MMMM
SWAP M, m
Swap data from m to itself
1
None
01 1101 1MMM MMMM
SWAP M, a
Swap data from m to acc
1
None
01 1101 0MMM MMMM
XOR M, m
(M) xor (acc) → (M)
1
Z
01 1011 1MMM MMMM
XOR M, a
(M) xor (acc) → (acc)
1
Z
01 1011 0MMM MMMM
XORLA l
Literal xor (acc) → (acc)
1
Z
11 1000 iiii iiii
<Note> After SLEEP instruction, please add a NOP instruction to perform transient.
7. Electrical Characteristics
7.1 Absolute Maximum Ratings
Supply Voltage …. Vss-0.3V to Vss+5.5V
Input Voltage …… Vss-0.3V to VDD+0.3V
Storage Temperature ……. –40℃ to 125℃
Operating Temperature ….
0℃ to 70℃
7.2 DC Characteristics
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Symbol
Test Conditions
Parameter
VDD
Min.
Typ.
Max.
Unit
2.2
5.5
V
2
Vdd
V
V
Conditions
VDD
Operating Voltage
---
VIH
Input HighVoltage
5V
I/O Port
VIL
Input Low Voltage
5V
I/O Port
0.8
WDT disable,(LV ON)
3
WDT disable,(LV OFF)
1
WDT enable,(LV ON)
11
WDT enable, (LV OFF)
9
WDT disable,(LV ON)
1
WDT disable,(LV OFF)
1
WDT enable,(LV ON)
2
WDT enable,(LV OFF)
2
5V
IDD1
Standby Current
3V
IDD1
IIL
operating current
Input Leakage
Current
5V
reset=hi, Fosc=4MHZ, No
5V
Vin=VDD, VSS
1
μA
Voh=4.5V
9
mA
Voh=4.0V
18
mA
Voh=3.5V
22
mA
PA0~3 output port ,
Voh=3.0V
26
mA
PB0~7 output port,
Voh=2.5V
29
mA
Driving
Voh=2.7V
4
mA
Current
Voh=2.4V
7
mA
Voh=2.1V
9
mA
Voh=2.1V
10
mA
Voh=1.8V
12
mA
Voh=0.5V
20
mA
Voh=1.0V
37
mA
Voh=1.5V
48
mA
PA0~3 output port ,
Voh=2.0V
55
mA
PB0~7 output port,
Voh=2.5V
59
mA
Sink
Voh=0.3V
8
mA
3V
5V
IOL
mA
Load
5V
IOH
2
μA
Current
26
3V
Voh=0.6V
Voh=0.9V
16
mA
2008/10/30 Rev.01
21
mA
Voh=1.2V
25
mA
Voh=1.5V
26
mA
MK6A20P
VLV
Low Voltage
1.9
2
reset(LVR)
RPH
Pull-high Resistance
RPL
Pull-low Resistance
2.1
V
3V
80
100
120
KΩ
5V
30
50
70
KΩ
3V
50
65
80
KΩ
5V
25
35
45
KΩ
7.3 AC Characteristics
Symbol
Parameter
Test Conditions
Conditions
fsys1
System Clock
fsys2
System Clock
fsys3
System Clock
fsys4
System Clock
Twdt
Watchdog Timer
Trht
Reset Hold Time
Min
Typ
Max
Unit
VDD
LP Crystal mode
NT Crystal mode
HS Crystal mode
RC mode
5V
32
200
3V
32
200
5V
0.2
10
3V
0.2
10
5V
10
20
5V
3.4
4
4.6
3V
3.4
4
4.6
5V
Khz
Mhz
Mhz
Mhz
20
mS
20
mS
3V
5V
3V
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7.4 EXT_RC Oscillator Frequencies
VCC
Rext
OSCI
Cext
MCU
7
The typical external RC oscillation frequency is as below table
When Cext = 0.01uf (103)
Rext
5V
3V
300K
500 KHZ
470 KHZ
120K
1.1 MHZ
1.1 MHZ
65K
2.1 MHZ
2 MHZ
32K
4.3 MHZ
4.1 MHZ
17K
8.3 MHZ
8 MHZ
14K
10.3 MHZ
10 MHZ
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