Audio Subsystem with Class-D Speaker and Capless Headphone Driver SSM2804 FEATURES 3 single-ended stereo audio inputs with optional differential mode Stereo, 1.4 W, filterless Class-D amplifiers with Σ-Δ modulation Integrated receiver path bypass switch Configurable, high performance capless headphone output with true ground Class-G technology Optional hardware-based headphone level limiter I2C control interface Volume control Flexible input/output mixing Output mode control EMI emissions control Automatic level control (ALC) Adjustable headphone level limiter Low shutdown current Short-circuit and thermal protection Pop-and-click suppression Available in a 30-ball, 2.5 mm × 3.0 mm WLCSP APPLICATIONS Mobile phones Portable multimedia devices GENERAL DESCRIPTION The SSM2804 is an audio subsystem designed specifically for mobile phones and portable multimedia devices. This highly flexible subsystem includes three input channels that can be configured as single-ended stereo or monaural differential for multimedia audio sources. Each set of inputs is independently adjustable with the 2-wire I2C interface and features an adjustable gain over a 30 dB range in steps of 1 dB. Each set of input channels also offers the choice of variable input impedance PGA mode or fixed input impedance boost mode. The input signals are then mixed and routed to the desired set of outputs. This configuration is set using the 2-wire I2C control interface. The SSM2804 includes three selectable output modes. The first output mode is a stereo Class-D speaker driver capable of delivering 2 × 1.4 W of continuous power to an 8 Ω bridge-tied load (BTL) with 1% THD + N when using a 5 V supply. This Class-D amplifier incorporates three-level Σ-Δ output modulation designed to increase battery life and improve EMI performance. The Class-D amplifier offers an I2C-adjustable volume control with a gain range from +12 dB to −63 dB in 31 steps. The second output mode is a pair of high performance headphone drivers capable of delivering 20 mW per channel into stereo 32 Ω single-ended loads with 1% THD + N. The stereo headphone drivers use a highly efficient, true ground centered Class-G architecture. The headphone outputs incorporate I2C-adjustable volume control with a gain range from 0 dB to −75 dB in 32 steps. The third output mode is an integrated receiver path bypass switch for passing voice signals from the audio baseband. The SSM2804 is specified over the industrial temperature range of −40°C to +85°C. It has built-in thermal shutdown and output short-circuit protection. The SSM2804 is available in a 30-ball, 2.5 mm × 3.0 mm wafer level chip scale package (WLCSP). Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2011 Analog Devices, Inc. All rights reserved. SSM2804 TABLE OF CONTENTS Features .............................................................................................. 1 Register Map Details ...................................................................... 21 Applications ....................................................................................... 1 Input Channel Mode Control, Address 0x00 ......................... 21 General Description ......................................................................... 1 Channel A Line Input Volume, Address 0x01 ........................ 22 Revision History ............................................................................... 2 Channel B Line Input Volume, Address 0x02 ........................ 23 Functional Block Diagram .............................................................. 3 Channel C Line Input Volume, Address 0x03 ........................ 24 Specifications..................................................................................... 4 Class-D Left Loudspeaker Output Volume, Address 0x04 ... 25 I C Timing Characteristics .......................................................... 6 Class-D Right Loudspeaker Output Volume, Address 0x05 ... 26 Absolute Maximum Ratings............................................................ 7 Left Headphone Output Volume, Address 0x06 .................... 27 Thermal Resistance ...................................................................... 7 Right Headphone Output Volume, Address 0x07 ................. 28 ESD Caution .................................................................................. 7 Headphone Input Mixer Control, Address 0x08.................... 29 Pin Configuration and Function Descriptions ............................. 8 Class-D Input Mixer Control, Address 0x09 .......................... 29 Typical Performance Characteristics ............................................. 9 ALC Control 1, Address 0x0A .................................................. 30 Theory of Operation ...................................................................... 13 ALC Control 2, Address 0x0B .................................................. 31 Pop-and-Click Suppression ....................................................... 13 ALC Control 3, Address 0x0C .................................................. 32 Output Modulation Description .............................................. 13 Power-Down Control, Address 0x0D ...................................... 32 Hardware-Based Headphone Limiter ...................................... 14 Additional Control, Address 0x0E ........................................... 34 Activating or Deactivating the Emission Limiting Circuitry...14 Chip Status Register, Address 0x0F.......................................... 35 Automatic Level Control (ALC) ............................................... 14 Software Reset Register, Address 0x10 .................................... 35 Typical Application Circuits.......................................................... 17 Outline Dimensions ....................................................................... 36 I C Software Control Interface...................................................... 19 Ordering Guide .......................................................................... 36 2 2 Register Map.................................................................................... 20 REVISION HISTORY 7/11—Revision 0: Initial Version Rev. 0 | Page 2 of 36 SSM2804 FUNCTIONAL BLOCK DIAGRAM AVDD PVDD RCV+ EP+ RCV– EP– SSM2804 INA2 BOOST = 0dB TO +20dB PGA = –12dB TO +18dB LSPK+ LSPK– INA1 RSPK+ RSPK– +12dB TO –63dB 31 STEPS INB2 BOOST = 0dB TO +20dB PGA = –12dB TO +18dB CLASS-D MIX/MUX INB1 HPL INC2 BOOST = 0dB TO +20dB PGA = –12dB TO +18dB HPR INC1 CLASS-G CLASS-G SUPPLY BIAS CF1 CF2 I2C CPVDD BIAS AGND PGND SCL Figure 1. Rev. 0 | Page 3 of 36 SDA CPVSS 09960-001 SD 0dB TO –75dB 32 STEPS SSM2804 SPECIFICATIONS TA = 25°C, AVDD = 3.3 V, PVDD = 3.6 V, gain = 0 dB, unless otherwise noted. Table 1. Parameter POWER SUPPLY Analog Voltage Supply (AVDD) Speaker Voltage Supply (PVDD) Total Quiescent Current (IDD) Min Typ Max Unit Test Conditions/Comments 2.5 2.7 3.3 3.6 3.5 6.0 9.8 400 1 3.6 5.5 V V mA mA mA μA μA HP mode only Stereo Class-D mode only HP and Class-D modes Receiver path mode SD pin low 10 ms SD rising edge from AGND to AVDD 54 6.5 +18 kΩ kΩ dB Minimum gain setting Maximum gain setting INAx, INBx, INCx inputs, 31 steps 20 kΩ dB INAx, INBx, INCx inputs, 3 steps Power-Down Current (ISD) INPUT CHARACTERISTICS Turn-On Time PGA Mode Operation Input Impedance Gain Range Boost Mode Operation Input Impedance Gain Range CLASS-D AMPLIFIER Output Offset Voltage (VOS) 38 4.5 −12 20 0 2.3 12 mV mV 310 700 1.0 1.4 700 1.5 2.0 2.9 400 860 1.2 1.7 900 1.8 2.5 3.6 0.01 mW mW W W mW W W W mW mW W W mW W W W % 40 94 80 80 55 89 μV dB dB dB dB % Ω kHz dB Output Power (POUT) Total Harmonic Distortion Plus Noise (THD + N) Output Noise (Vn) Signal-to-Noise Ratio (SNR) Power Supply Rejection Ratio (PSRR) Common-Mode Rejection Ratio (CMRR) Efficiency Minimum Load Resistance (RLOAD) Average Switching Frequency (fSW) Volume Control Gain Range 4 400 −63 +12 Rev. 0 | Page 4 of 36 Output muted Output unmuted f = 1 kHz, mono operation PVDD = 2.7 V, RL = 8 Ω + 33 μH, THD + N = 1% PVDD = 3.6 V, RL = 8 Ω + 33 μH, THD + N = 1% PVDD = 4.2 V, RL = 8 Ω + 33 μH, THD + N = 1% PVDD = 5.0 V, RL = 8 Ω + 33 μH, THD + N = 1% PVDD = 2.7 V, RL = 4 Ω + 15 μH, THD + N = 1% PVDD = 3.6 V, RL = 4 Ω + 15 μH, THD + N = 1% PVDD = 4.2 V, RL = 4 Ω + 15 μH, THD + N = 1% PVDD = 5.0 V, RL = 4 Ω + 15 μH, THD + N = 1% PVDD = 2.7 V, RL = 8 Ω + 33 μH, THD + N = 10% PVDD = 3.6 V, RL = 8 Ω + 33 μH, THD + N = 10% PVDD = 4.2 V, RL = 8 Ω + 33 μH, THD + N = 10% PVDD = 5.0 V, RL = 8 Ω + 33 μH, THD + N = 10% PVDD = 2.7 V, RL = 4 Ω + 15 μH, THD + N = 10% PVDD = 3.6 V, RL = 4 Ω + 15 μH, THD + N = 10% PVDD = 4.2 V, RL = 4 Ω + 15 μH, THD + N = 10% PVDD = 5.0 V, RL = 4 Ω + 15 μH, THD + N = 10% RL = 8 Ω + 33 μH, POUT = 250 mW 20 Hz to 20 kHz, A-weighted 2.0 V rms output, A-weighted, PVDD = 5 V 217 Hz, 200 mV p-p ripple 1 kHz, 200 mV p-p ripple Differential input mode, 1 kHz, 10 mV rms POUT = 700 mW SSM2804 Parameter HEADPHONE OUTPUT Output Offset Voltage (VOS) Min Output Power (POUT) Total Harmonic Distortion Plus Noise (THD + N) Output Noise (Vn) Signal-to-Noise Ratio (SNR) Power Supply Rejection Ratio (PSRR) Crosstalk Minimum Load Resistance (RLOAD) Maximum Capacitive Load (CLOAD) Gain Range ESD Protection RECEIVER PATH (BYPASS SWITCH) Path Impedance (RON), Receiver Inputs to Speaker Outputs Signal Path THD + N Typ Max Unit Test Conditions/Comments 2 8 20 40 mV mV mW mW 0.012 % Headphone only INAx, INBx, INCx inputs RL = 32 Ω, THD + N = 1% RL = 16 Ω, THD + N = 1%, 1 μF charge pump capacitor RL = 32 Ω, POUT = 15 mW 0.02 16 96 95 85 90 RL = 16 Ω, POUT = 10 mW 20 Hz to 20 kHz, A-weighted 800 mV rms output, A-weighted 217 Hz, 200 mV p-p ripple 1 kHz, 200 mV p-p ripple 1 kHz, POUT = 12 mW ±8 % μV dB dB dB dB Ω pF dB kV 1.5 Ω RCV+ to EP+ and RCV− to EP− 0.1 % 10 90 μV dB V POUT = 70 mW, RL = 32 Ω or POUT = 17.5 mW, RL = 8 Ω 20 Hz to 20 kHz, A-weighted 217 Hz, 200 mV p-p ripple 16 500 0 −75 Output Noise Off Channel Isolation Input Common Mode PVDD/2 Table 2. Digital Logic Levels (CMOS Levels) Parameter Input Low Level (VIL) Input High Level (VIH) Output Low Level (VOL) Output High Level (VOH) Min Typ Max 0.35 1.35 0.1 × AVDD 0.9 × AVDD Rev. 0 | Page 5 of 36 Unit V V V V SSM2804 I2C TIMING CHARACTERISTICS Table 3. Parameter tSCS tSCH tPH tPL fSCL tDS tDH tRT tFT tHCS tMIN 600 600 600 1.3 0 100 Limit tMAX Unit ns ns ns μs kHz ns ns ns ns ns 526 900 300 300 600 Description Start condition setup time Start condition hold time SCL pulse width high SCL pulse width low SCL frequency Data setup time Data hold time SDA and SCL rise time SDA and SCL fall time Stop condition setup time Timing Diagram tSCH tHCS SDA tDS tSCS tPH SCL tRT tDH Figure 2. I2C Timing Rev. 0 | Page 6 of 36 tFT 09960-002 tPL SSM2804 ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. THERMAL RESISTANCE Table 4. θJA is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages. Parameter Analog Supply Voltage (AVDD) Speaker Supply Voltage (PVDD) Input Voltage SD, SCL, SDA, RCV+, RCV− INA1, INA2, INB1, INB2, INC1, INC2 ESD (HBM) on Headphone Output Storage Temperature Range Operating Temperature Range Junction Temperature Range Lead Temperature (Soldering, 60 sec) Rating −0.3 V to +3.6 V −0.3 V to +3.6 V VDD −0.3 V to +6.0 V −0.3 V to AVDD + 0.3 V 8 kV −65°C to +150°C −40°C to +85°C −65°C to +165°C 300°C Table 5. Thermal Resistance Package Type 30-Ball, 2.5 mm × 3.0 mm WLCSP ESD CAUTION Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Rev. 0 | Page 7 of 36 PCB 1S0P 2S0P θJA 162 76 θJB 39 21 Unit °C/W °C/W SSM2804 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 1 2 3 4 5 6 A LSPK+ PVDD RSPK+ EP+ RCV+ INA1 B LSPK– PGND RSPK– EP– RCV– INA2 C CF2 CPVSS SCL SDA INB2 INB1 D AGND CPVDD HPR SD INC2 INC1 E CF1 AVDD HPL AGND AVDD BIAS TOP VIEW (BALL SIDE DOWN) Not to Scale 09960-003 BALL A1 CORNER Figure 3. Pin Configuration Table 6. Pin Function Descriptions Pin No. A1 B1 C1 D1 E1 A2 B2 C2 D2 E2 A3 B3 C3 D3 E3 A4 B4 C4 D4 E4 A5 B5 C5 D5 E5 A6 B6 C6 D6 E6 Mnemonic LSPK+ LSPK− CF2 AGND CF1 PVDD PGND CPVSS CPVDD AVDD RSPK+ RSPK− SCL HPR HPL EP+ EP− SDA SD AGND RCV+ RCV− INB2 INC2 AVDD INA1 INA2 INB1 INC1 BIAS Description Class-D Loudspeaker Output Left + Class-D Loudspeaker Output Left − Charge Pump Flyback Capacitor, Terminal 2 Analog Ground Charge Pump Flyback Capacitor, Terminal 1 Speaker Power Supply Speaker Ground Charge Pump Negative Supply for Class-G Charge Pump Positive Supply for Class-G Analog Power Supply Class-D Loudspeaker Output Right + Class-D Loudspeaker Output Right − 2-Wire I2C Control Interface Clock Input Class-G Headphone Output, Right Channel Class-G Headphone Output, Left Channel Integrated Switch Output + Integrated Switch Output − 2-Wire I2C Control Interface Data Input/Output Shutdown Control, Active Low (Optional Limiter Threshold Voltage) Analog Ground Baseband Receiver (Voice) Input + Baseband Receiver (Voice) Input − Configurable Input B2 (Single-Ended Input B− or Stereo Input B, Left Channel) Configurable Input C2 (Single-Ended Input C− or Stereo Input C, Left Channel) Analog Power Supply Configurable Input A1 (Single-Ended Input A+ or Stereo Input A, Right Channel) Configurable Input A2 (Single-Ended Input A− or Stereo Input A, Left Channel) Configurable Input B1 (Single-Ended Input B+ or Stereo Input B, Right Channel) Configurable Input C1 (Single-Ended Input C+ or Stereo Input C, Right Channel) Device Bias Pin Rev. 0 | Page 8 of 36 SSM2804 TYPICAL PERFORMANCE CHARACTERISTICS 100 100 RL = 8Ω + 33µH RL = 4Ω + 15µH 10 10 PVDD = 3.6V 1 0.1 THD + N (%) THD + N (%) PVDD = 3.6V PVDD = 2.7V 1 PVDD = 2.7V PVDD = 4.2V 0.1 PVDD = 4.2V 0.01 0.01 PVDD = 5V 0.01 0.1 1 10 OUTPUT POWER (W) 0.001 0.0001 PVDD = 5V 0.001 0.01 10 Figure 4. THD + N vs. Output Power into 8 Ω, Class-D Amplifier, Mono Operation Figure 7. THD + N vs. Output Power into 4 Ω, Class-D Amplifier, Mono Operation 100 100 RL = 4Ω + 15µH 10 10 PVDD = 2.7V 0.1 PVDD = 4.2V 0.01 1 PVDD = 2.7V 0.1 PVDD = 4.2V 0.01 PVDD = 5V PVDD = 5V 0.001 0.01 0.1 1 10 OUTPUT POWER (W) 0.001 0.0001 09960-006 0.001 0.01 0.1 1 10 OUTPUT POWER (W) Figure 5. THD + N vs. Output Power into 8 Ω, Class-D Amplifier, Stereo Operation Figure 8. THD + N vs. Output Power into 4 Ω, Class-D Amplifier, Stereo Operation 100 100 PVDD = 2.7V RL = 8Ω + 33µH 10 10 500mW 300mW THD + N (%) 1 PVDD = 2.7V RL = 4Ω + 15µH 125mW 0.1 0.01 1 0.1 250mW 62.5mW 0.01 125mW 0.001 10 100 1k 10k 100k FREQUENCY (Hz) 09960-008 62.5mW 0.001 10 100 1k FREQUENCY (Hz) 10k 100k 09960-009 0.001 0.0001 09960-007 1 PVDD = 3.6V THD + N (%) PVDD = 3.6V THD + N (%) 1 OUTPUT POWER (W) RL = 8Ω + 33µH THD + N (%) 0.1 09960-005 0.001 09960-004 0.001 0.0001 Figure 9. THD + N vs. Frequency, Class-D Amplifier, Mono Operation, RL = 4 Ω, PVDD = 2.7 V Figure 6. THD + N vs. Frequency, Class-D Amplifier, Mono Operation, RL = 8 Ω, PVDD = 2.7 V Rev. 0 | Page 9 of 36 SSM2804 100 100 PVDD = 3.6V RL = 4Ω + 15µH PVDD = 3.6V RL = 8Ω + 33µH 600mW 0.1 500mW 1.1W 1 0.1 250mW 125mW 125mW 0.01 0.01 1k 10k 100k FREQUENCY (Hz) 09960-010 100 0.001 10 Figure 10. THD + N vs. Frequency, Class-D Amplifier, Mono Operation, RL = 8 Ω, PVDD = 3.6 V PVDD = 4.2V RL = 4Ω + 15µH 10 10 1 1 0.1 900mW 1.5W 0.1 125mW 250mW 1W 250mW 0.01 0.01 10k 100k 0.001 10 09960-012 1k Figure 11. THD + N vs. Frequency, Class-D Amplifier, Mono Operation, RL = 8 Ω, PVDD = 4.2 V 100 1k 10k 100k FREQUENCY (Hz) 09960-013 500mW 500mW 100 FREQUENCY (Hz) Figure 14. THD + N vs. Frequency, Class-D Amplifier, Mono Operation, RL = 4 Ω, PVDD = 4.2 V 100 100 PVDD = 5V RL = 8Ω + 33µH 10 PVDD = 5V RL = 4Ω + 15µH 10 THD + N (%) 1.2W 1 0.1 1 2.2W 0.1 250mW 1W 250mW 0.01 1.5W 0.01 500mW 100 1k FREQUENCY (Hz) 500mW 10k 100k 0.001 10 09960-014 0.001 10 100k 100 THD + N (%) THD + N (%) 10k Figure 13. THD + N vs. Frequency, Class-D Amplifier, Mono Operation, RL = 4 Ω, PVDD = 3.6 V PVDD = 4.2V RL = 8Ω + 33µH THD + N (%) 1k FREQUENCY (Hz) 100 0.001 10 100 09960-011 500mW 250mW 0.001 10 Figure 12. THD + N vs. Frequency, Class-D Amplifier, Mono Operation, RL = 8 Ω, PVDD = 5.0 V 100 1k FREQUENCY (Hz) 10k 100k 09960-015 1 10 THD + N (%) THD + N (%) 10 Figure 15. THD + N vs. Frequency, Class-D Amplifier, Mono Operation, RL = 4 Ω, PVDD = 5.0 V Rev. 0 | Page 10 of 36 SSM2804 2.0 3.5 f = 1kHz RL = 8Ω + 33µH 1.8 f = 1kHz RL = 4Ω + 15µH 3.0 1.4 1.2 OUTPUT POWER (W) OUTPUT POWER (W) 1.6 THD + N = 1% 1.0 0.8 THD + N = 10% THD + N = 0.1% 0.6 2.5 THD + N = 1% 2.0 1.5 THD + N = 10% THD + N = 0.1% 1.0 0.4 3.0 3.5 4.0 4.5 5.0 SUPPLY VOLTAGE (V) 0 2.5 09960-016 0 2.5 Figure 16. Output Power vs. Supply Voltage, Class-D Amplifier, RL = 8 Ω 3.0 3.5 5.0 800 RL = 8Ω + 33µH RL = 4Ω + 15µH 350 700 PVDD = 5V PVDD = 4.2V 300 SUPPLY CURRENT (mA) PVDD = 3.6V 250 PVDD = 2.7V 200 150 100 50 PVDD = 4.2V 600 PVDD = 5V 500 PVDD = 3.6V 400 300 PVDD = 2.7V 200 100 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 OUTPUT POWER (W) 0 09960-018 0 Figure 17. Supply Current vs. Output Power into 8 Ω, Class-D Amplifier 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 OUTPUT POWER (W) 09960-019 SUPPLY CURRENT (mA) 4.5 Figure 19. Output Power vs. Supply Voltage, Class-D Amplifier, RL = 4 Ω 400 0 4.0 SUPPLY VOLTAGE (V) 09960-017 0.5 0.2 Figure 20. Supply Current vs. Output Power into 4 Ω, Class-D Amplifier 100 100 PVDD = 2.7V 90 90 80 80 PVDD = 5V 70 EFFICIENCY (%) PVDD = 4.2V 60 PVDD = 3.6V 50 40 30 20 50 40 20 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 RL = 4Ω + 15µH 10 1.8 OUTPUT POWER (W) Figure 18. Efficiency vs. Output Power into 8 Ω, Class-D Amplifier 0 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 OUTPUT POWER (W) Figure 21. Efficiency vs. Output Power into 4 Ω, Class-D Amplifier Rev. 0 | Page 11 of 36 09960-021 RL = 8Ω + 33µH 10 0 PVDD = 2.7V PVDD = 3.6V PVDD = 4.2V PVDD = 5V 60 30 09960-020 EFFICIENCY (%) 70 SSM2804 100 100 RL = 32Ω 10 10 1 1 THD + N (%) 0.1 0.1 0.001 0.01 0.1 1 10 OUTPUT POWER (W) 0.001 0.0001 09960-023 0.001 0.0001 Figure 22. THD + N vs. Output Power into 16 Ω, Headphone Amplifier, Stereo Operation 0.01 0.1 100 PVDD = 2.7V RL = 32Ω 10 1 1 THD + N (%) 10 10mW 0.1 0.01 5mW 0.1 0.01 1k 10k 100k FREQUENCY (Hz) 0.001 10 09960-025 100 –30 –40 –40 –50 –50 –60 –60 PSRR (dB) –30 –70 –80 –80 –90 –100 –100 –110 –110 100k FREQUENCY (Hz) 100k –70 –90 09960-022 PSRR (dB) –20 10k 10k Figure 26. THD + N vs. Frequency, Headphone Amplifier, RL = 32 Ω, PVDD = 2.7 V –20 1k 1k FREQUENCY (Hz) Figure 23. THD + N vs. Frequency, Headphone Amplifier, RL = 16 Ω, PVDD = 2.7 V 100 100 09960-026 10mW 20mW –120 10 10 Figure 25. THD + N vs. Output Power into 32 Ω, Headphone Amplifier, Stereo Operation PVDD = 2.7V RL = 16Ω 0.001 10 1 OUTPUT POWER (W) 100 THD + N (%) 0.001 09960-024 0.01 0.01 –120 10 100 1k 10k 100k FREQUENCY (Hz) Figure 27. Power Supply Rejection Ratio (PSRR) vs. Frequency, Headphone Amplifier Figure 24. Power Supply Rejection Ratio (PSRR) vs. Frequency, Class-D Amplifier Rev. 0 | Page 12 of 36 09960-027 THD + N (%) RL = 16Ω SSM2804 THEORY OF OPERATION The SSM2804 audio subsystem features a filterless modulation scheme that greatly reduces the external component count, conserving board space and, thus, reducing system cost. The SSM2804 does not require an output filter but, instead, relies on the inherent inductance of the speaker coil and the natural filtering of the speaker and human ear to fully recover the audio component of the square wave output. Most Class-D amplifiers use some variation of pulse-width modulation (PWM), but the SSM2804 uses Σ-Δ modulation to determine the switching pattern of the output devices, resulting in a number of important benefits. • • • Σ-Δ modulators do not produce a sharp peak with many harmonics in the AM frequency band, as pulse-width modulators often do. Σ-Δ modulation provides the benefits of reducing the amplitude of spectral components at high frequencies, that is, reducing EMI emissions that might otherwise be radiated by speakers and long cable traces. The SSM2804 does not require external EMI filtering for twisted speaker cable lengths shorter than 10 cm. If longer speaker cables are used, the SSM2804 has emission limiting circuitry that allows significantly longer speaker cable. Due to the inherent spread-spectrum nature of Σ-Δ modulation, the need for modulator synchronization is eliminated for designs that incorporate multiple SSM2804 amplifiers. 2 Using the I C control interface, the gain of the SSM2804 can be selected from a range of +12 dB to −63 dB in 32 steps. Other features accessed from the I2C interface include the following: • • • • OUTPUT MODULATION DESCRIPTION The SSM2804 uses three-level, Σ-Δ output modulation. Each output can swing from GND to VDD and vice versa. Ideally, when no input signal is present, the output differential voltage is 0 V because there is no need to generate a pulse. In a real-world situation, noise sources are always present. Due to the constant presence of noise, a differential pulse is generated, when required, in response to this stimulus. A small amount of current flows into the inductive load when the differential pulse is generated. Most of the time, however, the output differential voltage is 0 V, due to the Analog Devices, Inc., three-level, Σ-Δ output modulation. This feature ensures that the current flowing through the inductive load is small. When the user wants to send an input signal, an output pulse (OUT+ and OUT−) is generated to follow the input voltage. The differential pulse density (VOUT) is increased by raising the input signal level. Figure 28 depicts three-level, Σ-Δ output modulation with and without input stimulus. OUTPUT = 0V OUT+ +5V 0V +5V OUT– 0V +5V VOUT 0V –5V Independent left/right channel shutdown Variable ultralow EMI emission limiting circuitry Automatic level control (ALC) for high quality speaker protection Stereo-to-mono mixing operation OUTPUT > 0V OUT+ 0V +5V OUT– 0V +5V VOUT The SSM2804 also offers protection circuits for overcurrent and overtemperature protection. POP-AND-CLICK SUPPRESSION 0V OUTPUT < 0V OUT+ 0V 0V VOUT Rev. 0 | Page 13 of 36 +5V 0V +5V OUT– Voltage transients at the output of audio amplifiers can occur when shutdown is activated or deactivated. Voltage transients as low as 10 mV can be heard as an audio pop in the speaker. Clicks and pops can also be classified as undesirable audible transients generated by the amplifier system and, therefore, as not coming from the system input signal. Such transients may be generated when the amplifier system changes its operating mode. For example, the following may be sources of audible transients: system power-up and power-down, mute and unmute, input source change, and sample rate change. +5V –5V Figure 28. Three-Level, Σ-Δ Output Modulation With and Without Input Stimulus 09960-104 • The SSM2804 has a pop-and-click suppression architecture that reduces these output transients, resulting in noiseless activation and deactivation. SSM2804 HARDWARE-BASED HEADPHONE LIMITER To provide fail-safe headphone level limiting independent of the register values sent to the amplifier over the I2C bus, the SSM2804 incorporates an optional hardware-based headphone limiter feature. The user controls the limiter level by supplying a voltage at the SD pin (see Table 7). The hardware limiter is activated by setting the LIM_MODE bit to 0 in the additional control register (Bit D3 of Register 0x0E). After the desired limiter value is set, the user can lock the limiter setting by setting the LIMLOCK bit (Bit D7 of Register 0x0E). Table 7. Hardware Limiter Options Limiter Level Shutdown ±0.40 V Power into 32 Ω (mW) N/A 2.5 Power into 16 Ω (mW) N/A 5 <0.87 V 0.87 V < VSD < 1.08 V ±8 V 10 20 1.08 V < VSD < 1.29 V ±1.13 V 20 40 VSD > 1.29 V SD Pin Voltage Note that after the hardware limiter lock bit is set, the locked levels cannot be reset until the SSM2804 is powered down, the SD pin is strobed low, or all eight bits of the software reset register (Register 0x10) are set to 0. In addition to the hardware-based limiter, several other limiter levels can be selected using the I2C-based limiter function (set the HPLIM bits of Register 0x0E; see Table 44). The effect of the limiter function on the headphone output is shown in Figure 29. The trade-off is slightly lower efficiency and noise performance. The penalty for using the emission control circuitry is far less than the decreased performance observed when using a ferrite bead based EMI filter for emission limiting purposes. AUTOMATIC LEVEL CONTROL (ALC) Automatic level control (ALC) is a function that automatically adjusts amplifier gain to generate the desired output amplitude with reference to a particular input stimulus. The primary use for the ALC is to protect an audio power amplifier or speaker load from the damaging effects of clipping or current overloading. This is accomplished by limiting the output amplitude of the amplifier upon reaching a preset threshold voltage. Another benefit of the ALC is that it makes sound sources with a wide dynamic range more intelligible by boosting low level signals and limiting very high level signals. Before activating the ALC by setting the ALCEN bit (Bit D7 of Register 0x0B), the user has full control of the left and right channel PGA gain. After the ALC is activated (ALCEN = 1), the user has no control over the gain settings; the left channel PGA gain is locked into the device and controls the gain for both the left and right channels. To change the gain, the user must reset the ALCEN bit to 0 and then load the new gain settings. Figure 30 shows the response of the SSM2804 to a linearly increasing input signal. When the output reaches the current threshold value, the amplifier gain decreases by 0.5 dB so that the output voltage remains under the threshold. As more attenuation is added to the system, the threshold increases according to a profile determined by the compressor setting bits in the ALC Control 2 register (Bits[D6:D5] of Register 0x0B), causing a rounded “knee” as the output voltage approaches the output limiter level. The effect of this compression curve is shown in Figure 30. 5.6 5.2 CH1 500mV BW M20.0ms A CH1 110mV Figure 29. Limited Headphone Signal ACTIVATING OR DEACTIVATING THE EMISSION LIMITING CIRCUITRY 4.4 4.0 3.6 3.2 2.8 2.4 2.0 INPUT GAIN = 6dB GAIN = 12dB GAIN = 18dB GAIN = 24dB 1.6 1.2 0.8 0.4 To activate or deactivate the emission limiting circuitry, change the value of the EDGE bits in the additional control register (Bits[D1:D0] of Register 0x0E). Four levels of emission control are available, allowing the user to determine the best trade-off between efficiency and EMI reduction. In the default (fastest edge) mode, the user can pass FCC Class-B emission testing with 10 cm twisted pair speaker wire for loudspeaker connection. If longer speaker wire is desired, change the EDGE setting to a slower edge rate mode. 0 0 20 40 60 80 100 120 TIME (ms) 140 160 180 200 09960-034 09960-028 OUTPUT VOLTAGE LEVEL (V) 4.8 Figure 30. Output Response to Linearly Increasing Input Ramp Signal When the input level is small and the output voltage is smaller than the ALC threshold value, the gain of the amplifier stays at the preset gain setting. When the input exceeds the ALC threshold value, the ALC gradually reduces the gain from the preset gain setting down to 1 dB. Rev. 0 | Page 14 of 36 SSM2804 2.5 ALC Compression and Limiter Modes 00 (COMPRESSION MODE 1) 01 (COMPRESSION MODE 2) 10 (COMPRESSION MODE 3) 11 (LIMITER MODE) 2.7V × 0.78 = 2.106V 0 0 0.05 0.10 0.15 0.20 0.25 0.30 0.35 INPUT VOLTAGE (V) 0.40 0.45 0.50 Figure 31. Adjustable Compression Settings, PVDD = 2.7 V, ALC Threshold Level = 78% 3.5 3.0 2.5 2.0 1.5 1.0 00 (COMPRESSION MODE 1) 01 (COMPRESSION MODE 2) 10 (COMPRESSION MODE 3) 11 (LIMITER MODE) 3.6V × 0.78 = 2.808V 0.5 The attack time is the time taken to reduce the gain from maximum to minimum. The hold time is the time that the reduced gain is maintained. The release time is the time taken to increase the gain from minimum to maximum. These times are shown in Table 8. The attack time and the release time can be set using the ALC 1 control register (Address 0x0A). 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 INPUT VOLTAGE (V) 0.8 0.9 1.0 09960-118 When the amplifier input signal exceeds a preset threshold, the ALC reduces amplifier gain rapidly until the output voltage settles to a target level. This target level is maintained for a certain period. If the input voltage does not exceed the threshold again, the ALC increases the gain gradually. Figure 32. Adjustable Compression Settings, PVDD = 3.6 V, ALC Threshold Level = 78% 4.5 4.0 Table 8. ALC Attack, Hold, and Release Times 3.5 Duration 32 μs to 4 ms (per 0.5 dB step) 90 ms to 120 ms 4 ms to 512 ms (per 0.5 dB step) The attack time and release time can be adjusted using the I2C interface. The hold time cannot be adjusted. 3.0 2.5 2.0 1.5 00 (COMPRESSION MODE 1) 01 (COMPRESSION MODE 2) 10 (COMPRESSION MODE 3) 11 (LIMITER MODE) 5.0V × 0.78 = 3.9V 1.0 0.5 Soft-Knee Compression Often performed using sophisticated DSP algorithms, soft-knee compression provides maximum sound quality with effective speaker protection. Instead of using a fixed compression setting prior to limiting, the SSM2804 allows for a much more subtle transition into limiting mode, preserving the original sound quality of the source audio. Figure 31 to Figure 33 show the various soft-knee compression settings that can be selected using the COMP bit settings (Bits[D6:D5] of Register 0x0B). Rev. 0 | Page 15 of 36 0 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 INPUT VOLTAGE (V) 1.6 1.8 2.0 Figure 33. Adjustable Compression Settings, PVDD = 5.0 V, ALC Threshold Level = 78% 09960-119 OUTPUT VOLTAGE (V) 1 1.0 0.5 Attack Time, Hold Time, and Release Time Time1 Attack Time Hold Time Release Time 1.5 09960-107 OUTPUT VOLTAGE (V) As the input signal becomes very large, the ALC transitions to limiter mode. In this mode, the output stays at a given threshold level, VTH, even if the input signal grows larger. As an example of limiter mode operation, when a large input signal increases by 3 dB, the ALC reduces the amplifier gain by 3 dB and, thus, the output increases by 0 dB. When the amplifier gain is reduced to 1 dB, the ALC cannot reduce the gain further, and the output increases again. This is because the total range of the ALC operation has bottomed out due to extreme input voltage at high gain. To avoid potential speaker damage, the maximum input amplitude should not be large enough to exceed the maximum attenuation (to a level of 1 dB) of the limiter mode. 2.0 OUTPUT VOLTAGE (V) The ALC implemented on the SSM2804 has two operation modes: compression mode and limiter mode. When the ALC is triggered for medium-level input signals, the ALC is in compression mode. In this mode, an increase of the output signal is one-third the increase of the input signal. For example, if the input signal increases by 3 dB, the ALC reduces the amplifier gain by 2 dB and, thus, the output signal increases by only 1 dB. SSM2804 NORMAL TRANSITION The ALC operation of the SSM2804 incorporates techniques to reduce the audible artifacts associated with gain change transitions. First, the gain is changed in small increments of 0.5 dB. In addition to this small step size, the rate of gain change is reduced, proportional to the attack time setting. This feature drastically reduces and virtually eliminates the presence of zipper noise and other artifacts associated with gain transitions during ALC operation. Figure 34 shows the soft transition operation. 0.5dB SOFT TRANSITION (32µs TO 256µs) 0.5dB 09960-108 ALC Soft Transition Figure 34. Soft Transition Rev. 0 | Page 16 of 36 SSM2804 TYPICAL APPLICATION CIRCUITS 0.1µF 10µF 0.1µF AVDD 2.5V TO 3.6V 10µF VBATT 2.7V TO 5.5V AVDD PVDD EARPIECE EP+ RCV+ RCV IN+ RCV– RCV IN– EP– SSM2804 LSPK IN– (DIFF IN1–) 0.1µF INA2 CLASS-D OUTPUT LEFT LSPK+ BOOST = 0dB TO +20dB PGA = –12dB TO +18dB 0.1µF LSPK IN+ (DIFF IN1+) LSPK– INA1 RSPK+ RSPK– MP3 INL (DIFF IN2–) 0.1µF +12dB TO –63dB 31 STEPS INB2 MIX/MUX BOOST = 0dB TO +20dB PGA = –12dB TO +18dB MP3 INR (DIFF IN2+) 0.1µF CLASS-D OUTPUT RIGHT CLASS-D INB1 HEADPHONE OUTPUT LEFT HPL 0.1µF FM INL (DIFF IN3–) INC2 BOOST = 0dB TO +20dB PGA = –12dB TO +18dB SHUTDOWN HPR INC1 0dB TO –75dB 32 STEPS SD HEADPHONE OUTPUT RIGHT CLASS-G CF1 BIAS CLASS-G SUPPLY I2C 1µF CF2 CPVDD 1µF TO 2.2µF BIAS AGND PGND SCL SDA CPVSS I2C DATA I2C CLOCK CPVDD 1.2V TO 2.2V 1µF TO 2.2µF CPVSS –2.2V TO +1.2V Figure 35. Application Circuit with External Components Rev. 0 | Page 17 of 36 09960-031 0.1µF FM INR (DIFF IN3+) SSM2804 BYPASS CLASS-D MIX/MUX CLASS-G 09960-032 1.2V < CPVDD < +2.2V/–2.2V < CPVSS < –1.2V (INTERNALLY GENERATED) 2.7V < PVDD < 5V 2.5V < AVDD < 3.6V Figure 36. Power Supply Domains Rev. 0 | Page 18 of 36 SSM2804 I2C SOFTWARE CONTROL INTERFACE The I2C interface provides access to the user-selectable control registers and operates with a 2-wire interface. SDA generates the serial control data-word, and SCL clocks the serial data. The I2C bus address (Bits[A7:A1]) is 0x3B (01110110 for write and 01110111 for read). Bit A0 is the designated read/write bit. Each control register consists of 16 bits, MSB first. Bits[B15:B9] are the register map address, and Bits[B8:B0] are the register data for the associated register map. SCL S START 1 TO 7 8 9 ADDR R/W ACK 8 1 TO 7 SUBADDRESS 9 1 TO 7 ACK DATA 8 9 P ACK STOP 09960-029 SDA Figure 37. 2-Wire I2C Generalized Clocking Diagram WRITE SEQUENCE S A7 ... A1 A0 A(S) B15 ... B9 B8 A(S) B7 ... B0 A(S) P 0 DEVICE ADDRESS READ SEQUENCE S A7 ... A1 REGISTER ADDRESS A0 A(S) B15 ... REGISTER DATA B9 0 A(S) S A7 ... A1 0 DEVICE ADDRESS A0 A(S) B7 ... B0 A(M) 0 ... 0 B8 A(M) P 1 REGISTER ADDRESS DEVICE ADDRESS 09960-030 S/P = START/STOP BIT. A0 = I2C R/W BIT. A(S) = ACKNOWLEDGE BY SLAVE. A(M) = ACKNOWLEDGE BY MASTER. A(M) = ACKNOWLEDGE BY MASTER (INVERSION). REGISTER DATA (SLAVE DRIVE) Figure 38. I2C Write and Read Sequences Rev. 0 | Page 19 of 36 SSM2804 REGISTER MAP The 7-bit I2C address of the SSM2804 is 0x3B (0111011). Table 9. Register Map Address 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F 0x10 1 2 Name Input mode INA volume INB volume INC volume Class-D left volume Class-D right volume LHP volume RHP volume HP input mixer Class-D input mixer ALC Control 1 ALC Control 2 ALC Control 3 Power-down control Additional control Chip status1 Software reset2 D7 0 0 0 0 0 D6 ZCD 0 0 0 0 0 0 0 0 INAVOL[4:0] INBVOL[4:0] INCVOL[4:0] LCDVOL[4:0] Default 0x00 0x00 0x00 0x00 0x00 0 0 0 RCDVOL[4:0] 0x00 0 0 LHPVOL[4:0] RHPVOL[4:0] 0x00 0x00 0x00 0x00 0 0 0 0 POPTIME[1:0] CDSM[1:0] 0 ALCEN 0 PASSPDB D4 D3 GAINMOD[2:0] D2 RHPMOD[2:0] RCDMOD[2:0] D1 D0 INMOD[2:0] LHPMOD[2:0] LCDMOD[2:0] 0 RECTIME[2:0] ATTIME[2:0] COMP[1:0] ALCLV_FIX ALCLV[3:0] LCDBOOST RCDBOOST SOFTSTART SOFTCLIPEN NGEN NGATE[1:0] INCPDB INBPDB INAPDB RCDPDB LCDPDB HPPDB PWDB LIMLOCK 0 D5 HPLIM[2:0] 0 0 LIM_MOD 0 OCCD SOFTRESET This byte is read-only. This byte is write-only. Rev. 0 | Page 20 of 36 TO OCHP EDGE[1:0] OW OT 0x2B 0x4B 0x00 0x00 0x00 0x00 0x00 SSM2804 REGISTER MAP DETAILS INPUT CHANNEL MODE CONTROL, ADDRESS 0x00 Table 10. Input Channel Mode Control Register Bit Map D7 0 D6 ZCD D5 D4 GAINMOD[2:0] D3 D2 D1 INMOD[2:0] D0 Table 11. Input Channel Mode Control Register Bit Descriptions Bit Name ZCD Description Zero cross-detector enable GAINMOD[2:0] Input amplifier gain mode INMOD[2:0] Input mode control Settings 0 = disable (default) 1 = enable xx0 = Input A PGA mode xx1 = Input A boost mode x0x = Input B PGA mode x1x = Input B boost mode 0xx = Input C PGA mode 1xx = Input C boost mode xx0 = Input A stereo mode (INA1, INA2 > INAL, INAR) xx1 = Input A differential mode (INA1, INA2 > INA+, INA−) x0x = Input B stereo mode (INB1, INB2 > INBL, INBR) x1x = Input B differential mode (INB1, INB2 > INB+, INB−) 0xx = Input C stereo mode (INC1, INC2 > INCL, INCR) 1xx = Input C differential mode (INC1, INC2 > INC+, INC−) See Table 12 for complete information about the naming table Table 12. Input Mode Naming Table INMOD[2:0] 000 001 010 011 100 101 110 111 INA1 Pin INAL INAL INAL INAL INA+ INA+ INA+ INA+ INA2 Pin INAR INAR INAR INAR INA− INA− INA− INA− INB1 Pin INBL INBL INB+ INB+ INBL INBL INB+ INB+ Rev. 0 | Page 21 of 36 INB2 Pin INBR INBR INB− INB− INBR INBR INB− INB− INC1 Pin INCL INC+ INCL INC+ INCL INC+ INCL INC+ INC2 Pin INCR INC− INCR INC− INCR INC− INCR INC− SSM2804 CHANNEL A LINE INPUT VOLUME, ADDRESS 0x01 Table 13. Channel A Line Input Volume Register Bit Map D7 0 D6 0 D5 0 D4 D3 Table 14. Channel A Line Input Volume Register Bit Descriptions Bit Name INAVOL[4:0] Description Analog Channel A input volume control Settings See Table 15 Table 15. Descriptions of Channel A Volume Register Bits INAVOL[4:0] 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 10000 10001 10010 10011 10100 10101 10110 10111 11000 11001 11010 11011 11100 11101 11110 11111 PGA Mode (dB) Mute −12 −11 −10 −9 −8 −7 −6 −5 −4 −3 −2 −1 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 Boost Mode (dB) Mute 0 0 0 0 0 0 0 0 0 0 0 0 0 9 9 9 9 9 9 20 20 20 20 20 20 20 20 20 20 20 20 Rev. 0 | Page 22 of 36 D2 INAVOL[4:0] D1 D0 SSM2804 CHANNEL B LINE INPUT VOLUME, ADDRESS 0x02 Table 16. Channel B Line Input Volume Register Bit Map D7 0 D6 0 D5 0 D4 D3 Table 17. Channel B Line Input Volume Register Bit Descriptions Bit Name INBVOL[4:0] Description Analog Channel B input volume control Settings See Table 18 Table 18. Descriptions of Channel B Input Volume Register Bits INBVOL[4:0] 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 10000 10001 10010 10011 10100 10101 10110 10111 11000 11001 11010 11011 11100 11101 11110 11111 PGA Mode (dB) Mute −12 −11 −10 −9 −8 −7 −6 −5 −4 −3 −2 −1 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 Boost Mode (dB) Mute 0 0 0 0 0 0 0 0 0 0 0 0 0 9 9 9 9 9 9 20 20 20 20 20 20 20 20 20 20 20 20 Rev. 0 | Page 23 of 36 D2 INBVOL[4:0] D1 D0 SSM2804 CHANNEL C LINE INPUT VOLUME, ADDRESS 0x03 Table 19. Channel C Line Input Volume Register Bit Map D7 0 D6 0 D5 0 D4 D3 Table 20. Channel C Line Input Volume Register Bit Descriptions Bit Name INCVOL[4:0] Description Analog Channel C input volume control Settings See Table 21 Table 21. Descriptions of Channel C Input Volume Register Bits INCVOL[4:0] 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 10000 10001 10010 10011 10100 10101 10110 10111 11000 11001 11010 11011 11100 11101 11110 11111 PGA Mode (dB) Mute −12 −11 −10 −9 −8 −7 −6 −5 −4 −3 −2 −1 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 Boost Mode (dB) Mute 0 0 0 0 0 0 0 0 0 0 0 0 0 9 9 9 9 9 9 20 20 20 20 20 20 20 20 20 20 20 20 Rev. 0 | Page 24 of 36 D2 INCVOL[4:0] D1 D0 SSM2804 CLASS-D LEFT LOUDSPEAKER OUTPUT VOLUME, ADDRESS 0x04 Table 22. Class-D Left Loudspeaker Output Volume Register Bit Map D7 0 D6 0 D5 0 D4 D3 D2 LCDVOL[4:0] Table 23. Class-D Left Loudspeaker Output Volume Register Bit Descriptions Bit Name LCDVOL[4:0] Description Left channel Class-D volume control Settings 00000 = mute (default) 00001 = −75 dB 00010 = −71 dB 00011 = −67 dB 00100 = −63 dB 00101 = −59 dB 00110 = −55 dB 00111 = −51 dB 01000 = −47 dB 01001 = −44 dB 01010 = −41 dB 01011 = −38 dB 01100 = −35 dB 01101 = −32 dB 01110 = −29 dB 01111 = −26 dB 10000 = −23 dB 10001 = −21 dB 10010 = −19 dB 10011 = −17 dB 10100 = −15 dB 10101 = −13 dB 10110 = −11 dB 10111 = −9 dB 11000 = −7 dB 11001 = −6 dB 11010 = −5 dB 11011 = −4 dB 11100 = −3 dB 11101 = −2 dB 11110 = −1 dB 11111 = 0 dB Rev. 0 | Page 25 of 36 D1 D0 SSM2804 CLASS-D RIGHT LOUDSPEAKER OUTPUT VOLUME, ADDRESS 0x05 Table 24. Class-D Right Loudspeaker Output Volume Register Bit Map D7 0 D6 0 D5 0 D4 D3 D2 RCDVOL[4:0] Table 25. Class-D Right Loudspeaker Output Volume Register Bit Descriptions Bit Name RCDVOL[4:0] Description Right channel Class-D volume control Settings 00000 = mute (default) 00001 = −75 dB 00010 = −71 dB 00011 = −67 dB 00100 = −63 dB 00101 = −59 dB 00110 = −55 dB 00111 = −51 dB 01000 = −47 dB 01001 = −44 dB 01010 = −41 dB 01011 = −38 dB 01100 = −35 dB 01101 = −32 dB 01110 = −29 dB 01111 = −26 dB 10000 = −23 dB 10001 = −21 dB 10010 = −19 dB 10011 = −17 dB 10100 = −15 dB 10101 = −13 dB 10110 = −11 dB 10111 = −9 dB 11000 = −7 dB 11001 = −6 dB 11010 = −5 dB 11011 = −4 dB 11100 = −3 dB 11101 = −2 dB 11110 = −1 dB 11111 = 0 dB Rev. 0 | Page 26 of 36 D1 D0 SSM2804 LEFT HEADPHONE OUTPUT VOLUME, ADDRESS 0x06 Table 26. Left Headphone Output Volume Register Bit Map D7 0 D6 0 D5 0 D4 D3 D2 LHPVOL[4:0] Table 27. Left Headphone Output Volume Register Bit Descriptions Bit Name LHPVOL[4:0] Description Left headphone output volume control Settings 00000 = mute (default) 00001 = −75 dB 00010 = −71 dB 00011 = −67 dB 00100 = −63 dB 00101 = −59 dB 00110 = −55 dB 00111 = −51 dB 01000 = −47 dB 01001 = −44 dB 01010 = −41 dB 01011 = −38 dB 01100 = −35 dB 01101 = −32 dB 01110 = −29 dB 01111 = −26 dB 10000 = −23 dB 10001 = −21 dB 10010 = −19 dB 10011 = −17 dB 10100 = −15 dB 10101 = −13 dB 10110 = −11 dB 10111 = −9 dB 11000 = −7 dB 11001 = −6 dB 11010 = −5 dB 11011 = −4 dB 11100 = −3 dB 11101 = −2 dB 11110 = −1 dB 11111 = 0 dB Rev. 0 | Page 27 of 36 D1 D0 SSM2804 RIGHT HEADPHONE OUTPUT VOLUME, ADDRESS 0x07 Table 28. Right Headphone Output Volume Register Bit Map D7 0 D6 0 D5 0 D4 D3 D2 RHPVOL[4:0] Table 29. Right Headphone Output Volume Register Bit Descriptions Bit Name RHPVOL[4:0] Description Right headphone output volume control Settings 00000 = mute (default) 00001 = −75 dB 00010 = −71 dB 00011 = −67 dB 00100 = −63 dB 00101 = −59 dB 00110 = −55 dB 00111 = −51 dB 01000 = −47 dB 01001 = −44 dB 01010 = −41 dB 01011 = −38 dB 01100 = −35 dB 01101 = −32 dB 01110 = −29 dB 01111 = −26 dB 10000 = −23 dB 10001 = −21 dB 10010 = −19 dB 10011 = −17 dB 10100 = −15 dB 10101 = −13 dB 10110 = −11 dB 10111 = −9 dB 11000 = −7 dB 11001 = −6 dB 11010 = −5 dB 11011 = −4 dB 11100 = −3 dB 11101 = −2 dB 11110 = −1 dB 11111 = 0 dB Rev. 0 | Page 28 of 36 D1 D0 SSM2804 HEADPHONE INPUT MIXER CONTROL, ADDRESS 0x08 Table 30. Headphone Input Mixer Control Register Bit Map D7 D6 POPTIME[1:0] D5 D4 RHPMOD[2:0] D3 D2 D1 LHPMOD[2:0] D0 Table 31. Headphone Input Mixer Control Register Bit Descriptions Bit Name POPTIME[1:0] Description Headphone turn-on time constant setting RHPMOD[2:0] Right headphone input mixer LHPMOD[2:0] Left headphone input mixer Settings 00 = 10 ms (default) 01 = 20 ms 10 = 40 ms 11 = 80 ms (smallest pop-and-click) xx0 = Analog Input A disabled (default) xx1 = Analog Input A enabled x0x = Analog Input B disabled (default) x1x = Analog Input B enabled 0xx = Analog Input C disabled (default) 1xx = Analog Input C enabled xx0 = Analog Input A disabled (default) xx1 = Analog Input A enabled x0x = Analog Input B disabled (default) x1x = Analog Input B enabled 0xx = Analog Input C disabled (default) 1xx = Analog Input C enabled CLASS-D INPUT MIXER CONTROL, ADDRESS 0x09 Table 32. Class-D Input Mixer Control Register Bit Map D7 D6 CDSM[1:0] D5 D4 RCDMOD[2:0] D3 D2 D1 LCDMOD[2:0] Table 33. Class-D Input Mixer Control Register Bit Descriptions Bit Name CDSM[1:0] Description Class-D stereo/mono mode control RCDMOD[2:0] Right Class-D input mixer LCDMOD[2:0] Left Class-D input mixer Settings x0 = left channel disabled (default) x1 = left channel enabled (left and right) 0x = right channel disabled (default) 1x = right channel enabled (left and right) xx0 = Analog Input A disabled (default) xx1 = Analog Input A enabled x0x = Analog Input B disabled (default) x1x = Analog Input B enabled 0xx = Analog Input C disabled (default) 1xx = Analog Input C enabled xx0 = Analog Input A disabled (default) xx1 = Analog Input A enabled x0x = Analog Input B disabled (default) x1x = Analog Input B enabled 0xx = Analog Input C disabled (default) 1xx = Analog Input C enabled Rev. 0 | Page 29 of 36 D0 SSM2804 ALC CONTROL 1, ADDRESS 0x0A Table 34. ALC Control 1 Register Bit Map D7 0 D6 0 D5 D4 RECTIME[2:0] D3 D2 D1 ATTIME[2:0] Table 35. ALC Control 1 Register Bit Descriptions Bit Name RECTIME[2:0] Description ALC release rate ATTIME[2:0] ALC attack rate Settings 000 = 4 ms per 0.5 dB step (6 dB/48 ms) 001 = 8 ms 010 = 16 ms 011 = 32 ms 100 = 64 ms 101 = 128 ms (default) 110 = 256 ms 111 = 512 ms 000 = 32 μs per 0.5 dB step (6 dB/384 μs) 001 = 64 μs 010 = 128 μs 011 = 256 μs (default) 100 = 512 μs 101 = 1 ms 110 = 2 ms 111 = 4 ms Rev. 0 | Page 30 of 36 D0 SSM2804 ALC CONTROL 2, ADDRESS 0x0B Table 36. ALC Control 2 Register Bit Map D7 ALCEN D6 D5 COMP[1:0] D4 ALCLV_FIX D3 D2 D1 ALCLV[3:0] D0 Table 37. ALC Control 2 Register Bit Descriptions Bit Name ALCEN Description ALC enable COMP[1:0] Compressor setting (see the Soft-Knee Compression section for more information) ALCLV_FIX ALC threshold mode setting ALCLV[3:0] ALC threshold level setting Settings 0 = ALC disabled (default) 1 = ALC enabled 00 = Compression Mode 1 (1:4 to 1:∞) 01 = Compression Mode 2 (1:1.7 to 1:4 to 1:∞) 10 = Compression Mode 3 (1:1.3 to 1:2.5 to 1:∞) 11 = Limiter mode (1:∞) 0 = supply tracking (threshold is a constant fraction of supply voltage) 1 = fixed power (threshold is a fixed voltage) See Table 38 Table 38. ALC Threshold Levels ALCLV[3:0] Value 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Supply Tracking Threshold (% of PVDD) (ALCLV_FIX = 0) 65 67 69 72 75 78 81 85 88 93 97 102 108 114 122 130 Fixed Power Threshold (V) (ALCLV_FIX = 1) 2.74 2.89 3.04 3.19 3.34 3.50 3.65 3.80 3.95 4.10 4.25 4.40 4.56 4.71 4.86 5.01 Rev. 0 | Page 31 of 36 SSM2804 ALC CONTROL 3, ADDRESS 0x0C Table 39. ALC Control 3 Register Bit Map D7 0 D6 LCDBOOST D5 RCDBOOST D4 SOFTSTART D3 SOFTCLIPEN D2 NGEN D1 D0 NGATE[1:0] Table 40. ALC Control 3 Register Bit Descriptions Bit Name LCDBOOST Description Left channel Class-D gain boost RCDBOOST Right channel Class-D gain boost SOFTSTART Soft start enable SOFTCLIPEN Soft clip enable NGEN Noise gate enable NGATE[1:0] Noise gate level Settings 0 = 0 dB (default) 1 = +6 dB boost 0 = 0 dB (default) 1 = +6 dB boost 0 = soft start disabled (default) 1 = soft start enabled 0 = soft clip disabled (default) 1 = soft clip enabled 0 = noise gate disabled (default) 1 = noise gate enabled 00 = 2 mV (default) 01 = 4 mV 10 = 8 mV 11 = 16 mV POWER-DOWN CONTROL, ADDRESS 0x0D Table 41. Power-Down Control Register Bit Map D7 PASSPDB D6 INCPDB D5 INBPDB D4 INAPDB D3 RCDPDB D2 LCDPDB Table 42. Power-Down Control Register Bit Descriptions Bit Name PASSPDB Description Passive switch power-down INCPDB Input Channel C power-down INBPDB Input Channel B power-down INAPDB Input Channel A power-down RCDPDB Class-D right channel power-down LCDPDB Class-D left channel power-down HPPDB Headphone power-down PWDB System power-down Settings 0 = power down (default) 1 = power up 0 = power down (default) 1 = power up 0 = power down (default) 1 = power up 0 = power down (default) 1 = power up 0 = power down (default) 1 = power up 0 = power down (default) 1 = power up 0 = power down (default) 1 = power up 0 = power down (default) 1 = power up Rev. 0 | Page 32 of 36 D1 HPPDB D0 PWDB SSM2804 AVDD PVDD RCV+ EP+ RCV– EP– SSM2804 PASSPDB INA2 LCDPDB LSPK+ INAPDB LSPK– INA1 RSPK+ RSPK– INB2 RCDPDB MIX/MUX INBPDB INB1 HPL INC2 INCPDB HPR INC1 HPPDB BIAS CLASS-G SUPPLY PWDB I2C CF2 CF1 CF2 CPVDD AGND PGND SCL SDA Figure 39. Power Management Control Register Blocks Rev. 0 | Page 33 of 36 CPVSS 09960-035 CF1 SD SSM2804 ADDITIONAL CONTROL, ADDRESS 0x0E Table 43. Additional Control Register Bit Map D7 LIMLOCK D6 D5 HPLIM[2:0] D4 D3 LIM_MODE D2 TO D1 D0 EDGE[1:0] Table 44. Additional Control Register Bit Descriptions Bit Name LIMLOCK HPLIM[2:0] Description Headphone limiter lock bit. After the limiter is locked, the locked levels cannot be reset until the SSM2804 is powered down, the SD pin is strobed low, or all eight bits of the software reset register (Register 0x10) are set to 0. Headphone limiter level adjust. LIM_MODE Headphone limiter mode selection. TO Timeout control. EDGE[1:0] Class-D output stage edge control. Settings 0 = disable (default) 1 = enable 000 = off (default) 001 = ±1.13 V 010 = ±0.98 V 011 = ±0.80 V 100 = ±0.57 V 101 = ±0.40 V 110 = ±0.28 V 111 = ±0.22 V 0 = hardware mode (external resistor limiter via SD pin; default) 1 = software mode (I2C adjustable limiter) 0 = 30 ms (default) 1 = 60 ms 00 = normal mode (default) 01 = slow edge 10 = slower edge (PVDD > 3.0 V recommended) 11 = slowest edge (PVDD > 4.0 V recommended) Rev. 0 | Page 34 of 36 SSM2804 CHIP STATUS REGISTER, ADDRESS 0x0F This register is read-only. Table 45. Chip Status Register Bit Map D7 0 D6 0 D5 0 D4 0 D3 OCCD D2 OCHP D1 OW D0 OT D1 D0 Table 46. Chip Status Register Bit Descriptions Bit Name OCCD Description Overcurrent for Class-D OCHP Overcurrent for headphone OW Overtemperature warning OT Overtemperature error (thermal shutdown) Settings 0 = normal 1 = overcurrent 0 = normal 1 = overcurrent 0 = normal 1 = overtemperature warning 0 = normal 1 = overtemperature shutdown SOFTWARE RESET REGISTER, ADDRESS 0x10 This register is write-only. Table 47. Software Reset Register Bit Map D7 D6 D5 D4 D3 SOFTRESET D2 Table 48. Software Reset Register Bit Descriptions Bit Name SOFTRESET Description Software reset Settings 00000000 = software reset Rev. 0 | Page 35 of 36 SSM2804 OUTLINE DIMENSIONS 3.000 2.960 2.920 6 5 4 3 2 1 A BALL A1 IDENTIFIER 2.500 2.460 2.420 B 2.00 REF C D 0.50 BALL PITCH TOP VIEW E BOTTOM VIEW (BALL SIDE UP) (BALL SIDE DOWN) 2.50 REF 0.390 0.360 0.330 SIDE VIEW COPLANARITY 0.05 0.360 0.320 0.280 SEATING PLANE 0.270 0.240 0.210 06-29-2010-B 0.660 0.600 0.540 Figure 40. 30-Ball Wafer Level Chip Scale Package [WLCSP] (CB-30-4) Dimensions shown in millimeters ORDERING GUIDE Model 1 SSM2804CBZ-RL SSM2804CBZ-R7 EVAL-SSM2804Z 1 Temperature Range −40°C to +85°C −40°C to +85°C Package Description 30-Ball Wafer Level Chip Scale Package [WLCSP] 30-Ball Wafer Level Chip Scale Package [WLCSP] Evaluation Board Z = RoHS Compliant Part. I2C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors). ©2011 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D09960-0-7/11(0) Rev. 0 | Page 36 of 36 Package Option CB-30-4 CB-30-4