AD AD9888

a
FEATURES
205 MSPS Maximum Conversion Rate
500 MHz Programmable Analog Bandwidth
0.5 V to 1.0 V Analog Input Range
Less than 450 ps p-p PLL Clock Jitter @ 205 MSPS
3.3 V Power Supply
Full Sync Processing
Sync Detect for “Hot Plugging”
2:1 Analog Input Mux
4:2:2 Output Format Mode
Midscale Clamping
Power-Down Mode
Low Power: <1 W Typical @ 205 MSPS
APPLICATIONS
RGB Graphics Processing
LCD Monitors and Projectors
Plasma Display Panels
Scan Converters
Microdisplays
Digital TV
100/140/170/205 MSPS Analog
Flat Panel Interface
AD9888
FUNCTIONAL BLOCK DIAGRAM
RIN
RIN
GIN
GIN
BIN
BIN
HSYNC
HSYNC
8
2:1
MUX
CLAMP
A/D
8
8
8
2:1
MUX
CLAMP
A/D
8
8
8
2:1
MUX
CLAMP
A/D
8
8
2
2:1
MUX
ROUTA
ROUTB
GOUTA
GOUTB
BOUTA
BOUTB
DATACK
HSOUT
VSYNC
VSYNC
SOGIN
SOGIN
COAST
2:1
MUX
2:1
MUX
VSOUT
SYNC
PROCESSING
AND
CLOCK
GENERATION
SOGOUT
REF
REF
BYPASS
CLAMP
CKINV
CKEXT
FILT
SCL
SDA
A0
GENERAL DESCRIPTION
The AD9888 is a complete 8-bit, 205 MSPS monolithic analog
interface optimized for capturing RGB graphics signals from
personal computers and workstations. Its 205 MSPS encode
rate capability and full-power analog bandwidth of 500 MHz
supports resolutions up to UXGA (1600 × 1200 at 75 Hz).
For ease of design and to minimize cost, the AD9888 is a fully
integrated interface solution for flat panel displays. The AD9888
includes an analog interface with a 205 MHz triple ADC with
internal 1.25 V reference, PLL to generate a pixel clock from
HSYNC and COAST, midscale clamping, and programmable
gain, offset, and clamp control. The user provides only a 3.3 V
power supply, analog input, and HSYNC and COAST signals.
Three-state CMOS outputs may be powered from 2.5 V to 3.3 V.
AD9888
SERIAL REGISTER
AND
POWER MANAGEMENT
The AD9888’s on-chip PLL generates a pixel clock from HSYNC
and COAST inputs. Pixel clock output frequencies range from
10 MHz to 205 MHz. PLL clock jitter is less than 450 ps p-p
typical at 205 MSPS. When the COAST signal is presented, the
PLL maintains its output frequency in the absence of HSYNC.
A sampling phase adjustment is provided. Data, HSYNC, and
Clock output phase relationships are maintained. The PLL can
be disabled and an external clock input provided as the pixel
clock. The AD9888 also offers full sync processing for composite sync and Sync-on-Green applications.
A clamp signal is generated internally or may be provided by the
user through the CLAMP input pin. This interface is fully programmable via a 2-wire serial interface.
Fabricated in an advanced CMOS process, the AD9888 is provided in a space-saving 128-lead MQFP surface mount plastic
package and is specified over the 0°C to 70°C temperature range.
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 2002
AD9888–SPECIFICATIONS
Parameter
(VD = 3.3 V, VDD = 3.3 V, ADC Clock = Maximum Conversion Rate)
Test
AD9888KS-100/-1401
Temp Level Min
Typ Max
RESOLUTION
DC ACCURACY
Differential Nonlinearity
Min
AD9888KS-170
Typ Max
Min
AD9888KS-205
Typ Max
Unit
8
8
8
Bits
± 0.5
± 0.6
± 0.8
LSB
LSB
LSB
LSB
25°C
Full
25°C
Full
25°C
I
VI
I
VI
I
25°C
25°C
25°C
25°C
Full
Full
Full
Full
Full
Full
I
I
V
IV
IV
V
IV
VI
VI
VI
Full
Full
VI
V
1.20
VI
IV
IV
VI
VI
VI
VI
VI
VI
VI
VI
IV
VI
IV
IV
IV
IV
100/140
Sampling Phase Tempco
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
25°C
Full
Full
DIGITAL INPUTS
Input Voltage, High (VIH)
Input Voltage, Low (VIL)
Input Current, High (IIH)
Input Current, Low (IIL)
Input Capacitance
Full
Full
Full
Full
25°C
VI
VI
IV
IV
V
2.5
Full
Full
VI
VI
VD – 0.1
Full
IV
44
49
55
Binary
44
49
55
Binary
44
49
55
Binary
%
Full
Full
Full
25°C
25°C
25°C
Full
Full
Full
IV
IV
IV
V
V
V
VI
VI
VI
3.0
2.2
3.0
3.3
3.3
3.3
200
50
8
850
12
40
3.0
2.2
3.0
3.3
3.3
3.3
215
55
9
920
12
40
3.0
2.2
3.0
3.3
3.3
3.3
230
60
10
990
12
40
V
V
V
mA
mA
mA
mW
mA
mW
Integral Nonlinearity
No Missing Codes
ANALOG INPUT
Input Voltage Range
Minimum
Maximum
Gain Tempco
Input Bias Current
Input Capacitance
Input Resistance
Input Offset Voltage
Input Full-Scale Matching
Offset Adjustment Range
REFERENCE OUTPUT
Output Voltage
Temperature Coefficient
SWITCHING PERFORMANCE
Maximum Conversion Rate
Minimum Conversion Rate
Data to Clock Skew
tBUFF2
tSTAH2
tDHO2
tDAL2
tDAH2
tDSU2
tSTASU2
tSTOSU2
HSYNC Input Frequency
Maximum PLL Clock Rate
Minimum PLL Clock Rate
PLL Jitter
DIGITAL OUTPUTS
Output Voltage, High (VOH)
Output Voltage, Low (VOL)
Duty Cycle
DATACK, DATACK
Output Coding
POWER SUPPLY
VD Supply Voltage
VDD Supply Voltage
PVD Supply Voltage
ID Supply Current (VD)
IDD Supply Current (VDD)5
IPVD Supply Current (PVD)
Total Power Dissipation
Power-Down Supply Current
Power-Down Dissipation
+1.25/–1.0
+1.35/–1.0
± 0.5 ± 2.0
± 2.5
Guaranteed
+1.25/–1.0
+1.50/–1.0
± 0.75 ± 2.25
± 2.75
Guaranteed
0.5
0.5
1.0
1.0
100
100
100
1
2
3
3
1
7
2.5
49
90
9.0
53
44
1.25
± 50
1.30
1.20
1
7
2.5
49
90
9.0
53
44
1.25
± 50
1.30
1.20
170
10
+1.25
110
470
1
2
3
1
–1.25
4.7
4.0
0
4.7
4.0
250
4.7
4.0
15
100/140
0.5
1.0
1
2
44
+1.50/–1.0
+1.80/–1.0
± 1.0 ± 3.75
± 4.25
Guaranteed
110
450
15
10
7004
10004
10
+1.25
110
440
0.8
–1.0
+1.0
3
3
VD – 0.1
0.1
10
7004
10004
2.5
0.8
–1.0
+1.0
3
VD – 0.1
0
–2–
1.30
15
2.5
0.8
–1.0
+1.0
1050
20
66
1.25
± 50
–1.25
4.7
4.0
0
4.7
4.0
250
4.7
4.0
15
205
15
3.6
3.6
3.6
90
9.0
53
205
10
+1.25
–1.25
4.7
4.0
0
4.7
4.0
250
4.7
4.0
15
170
10
7003
10003
7
2.5
49
.1
3.6
3.6
3.6
1150
20
66
0.1
3.6
3.6
3.6
1250
20
66
V p-p
V p-p
ppm/°C
µA
µA
pF
MΩ
mV
% FS
% FS
V
ppm/°C
MSPS
MSPS
ns
µs
µs
µs
µs
µs
ns
µs
µs
kHz
MHz
MHz
ps p-p
ps p-p
ps/°C
V
V
µA
µA
pF
V
V
REV. A
AD9888
Test
AD9888KS-100/-1401
Temp Level Min
Typ Max
Parameter
DYNAMIC PERFORMANCE
Analog Bandwidth, Full Power6
Transient Response
Overvoltage Recovery Time
Signal-to-Noise Ratio (SNR)7
(Without Harmonics)
fIN = 40.7 MHz
Crosstalk
AD9888KS-205
Min
Typ Max
Unit
500
2
1.5
44
43
500
2
1.5
42
41
MHz
ns
ns
dB
dB
25°C
25°C
25°C
25°C
Full
V
V
V
IV
V
Full
V
50
50
50
dBc
V
8.4
8.4
8.4
°C/W
V
35
35
35
°C/W
THERMAL CHARACTERISTICS
θJC–Junction-to-Case
Thermal Resistance
θJA–Junction-to-Ambient
Thermal Resistance
42
500
2
1.5
45
44
AD9888KS-170
Min
Typ Max
41
40
NOTES
1
AD9888KS-100 specifications are tested at 100 MHz. AD9888KS-140 specifications are tested at 140 MHz.
2
See Figure 23.
3
VCO Range = 10, Charge Pump Current = 100, PLL Divider = 1693.
4
VCO Range = 11, Charge Pump Current = 100, PLL Divider = 2159.
5
DEMUX = 1, DATACK and DATACK Load = 15 pF, Data Load = 5 pF.
6
Maximum bandwidth setting. Bandwidth can also be programmed to 300 MHz, 150 MHz, and 75 MHz.
7
Using External Pixel Clock.
Specifications subject to change without notice.
ABSOLUTE MAXIMUM RATINGS*
VD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.6 V
VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.6 V
Analog Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . VD to 0.0 V
VREF IN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VD to 0.0 V
Digital Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 V to 0.0 V
Digital Output Current . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA
Operating Temperature . . . . . . . . . . . . . . . . . –25°C to +85°C
Storage Temperature . . . . . . . . . . . . . . . . . . –65°C to +150°C
Maximum Junction Temperature . . . . . . . . . . . . . . . . . 150°C
Maximum Case Temperature . . . . . . . . . . . . . . . . . . . . 150°C
*Stresses above those listed under Absolute Maximum Ratings may cause permanent
damage to the device. This is a stress rating only and functional operation of the
device at these or any other conditions outside of those indicated in the operation
sections of this specification is not implied. Exposure to absolute maximum ratings
for extended periods may affect device reliability.
EXPLANATION OF TEST LEVELS
Test Level
I.
100% production tested.
II. 100% production tested at 25°C and sample tested at
specified temperatures.
III. Sample tested only.
IV. Parameter is guaranteed by design and characterization
testing.
V. Parameter is a typical value only.
VI. 100% production tested at 25°C; guaranteed by design and
characterization testing.
ORDERING GUIDE
Model
Temperature
Range
Package
Option
AD9888KS-100
AD9888KS-140
AD9888KS-170
AD9888KS-205
AD9888/PCB
0°C to 70°C
0°C to 70°C
0°C to 70°C
0°C to 70°C
25°C
S-128A
S-128A
S-128A
S-128A
Evaluation Board
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD9888 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
REV. A
–3–
WARNING!
ESD SENSITIVE DEVICE
AD9888
104 DRB6
103 DRB7
105 DRB5
106 DRB4
108 DRB2
107 DRB3
109 DRB1
111 GND
110 DRB0
112 VDD
114 DRA6
113 DRA7
115 DRA5
116 DRA4
117 DRA3
118 DRA2
119 DRA1
121 GND
120 DRA0
122 VDD
124 DATACKB
123 DATACK
126 SOGOUT
125 HSOUT
128 GND
127 VSOUT
PIN CONFIGURATION
102 VDD
VD
1
REF BYPASS
2
GND
3
GND
4
99 GND
RAIN0
5
98 VDD
PIN 1
IDENTIFIER
101 GND
100 GND
VD
6
97 DGA0
VD
7
96
DGA1
RAIN1
8
95
DGA2
RMIDSCV
9
94
DGA3
VD 10
93
DGA4
GND 11
92
DGA5
SOGIN0 12
91
DGA6
GAIN0 13
90
DGA7
VD 14
89
VDD
GND 15
88
GND
SOGIN1 16
87
DGB0
GAIN1 17
86
DGB1
VD 18
85 DGB2
AD9888
GND 19
84 DGB3
TOP VIEW
(Not to Scale)
BAIN0 20
83 DGB4
VD 21
82 DGB5
GND 22
81 DGB6
BAIN1 23
80 DGB7
BMIDSCV 24
79 VDD
VD 25
78 GND
VD 26
77 DBA0
GND 27
76 DBA1
GND 28
75 DBA2
CKINV 29
74 DBA3
CLAMP 30
73 DBA4
SDA 31
72 DBA5
SCL 32
71 DBA6
A0 33
70 DBA7
VD 34
69 VDD
GND 35
68 GND
GND 36
67 GND
–4–
DBB0 64
DBB1 63
DBB2 62
DBB3 61
DBB4 60
DBB5 59
DBB6 58
DBB7 57
VDD 56
GND 55
CKEXT 54
COAST 53
GND 51
PV D 52
FILT 50
GND 49
GND 46
PV D 47
PV D 48
HSYNC0 45
VSYNC0 44
HSYNC1 43
GND 41
VSYNC1 42
65 GND
PV D 39
66 GND
38
PVD
GND 40
VD 37
REV. A
AD9888
Table I. Complete Pinout List
Pin Type
Mnemonic
Function
Value
Pin
Number
Analog Video Inputs
RAIN0
GAIN0
BAIN0
RAIN1
GAIN1
BAIN1
Channel 0 Analog Input for Converter R
Channel 0 Analog Input for Converter G
Channel 0 Analog Input for Converter B
Channel 1 Analog Input for Converter R
Channel 1 Analog Input for Converter G
Channel 1 Analog Input for Converter B
0.0 V to 1.0 V
0.0 V to 1.0 V
0.0 V to 1.0 V
0.0 V to 1.0 V
0.0 V to 1.0 V
0.0 V to 1.0 V
5
13
20
8
17
23
Sync/Clock Inputs
HSYNC0
VSYNC0
SOGIN0
HSYNC1
VSYNC1
SOGIN1
CLAMP
COAST
CKEXT
CKINV
Channel 0 Horizontal SYNC Input
Channel 0 Vertical SYNC Input
Channel 0 Input for Sync-on-Green
Channel 1 Horizontal SYNC Input
Channel 1 Vertical SYNC Input
Channel 1 Input for Sync-on-Green
Clamp Input (External CLAMP signal)
PLL Coast Signal Input
External Pixel Clock Input (to Bypass the PLL) or 10 kΩ to Ground
ADC Sampling Clock Invert
3.3 V CMOS
3.3 V CMOS
0.0 V to 1.0 V
3.3 V CMOS
3.3 V CMOS
0.0 V to 1.0 V
3.3 V CMOS
3.3 V CMOS
3.3 V CMOS
3.3 V CMOS
45
44
12
43
42
16
30
53
54
29
Sync Outputs
HSOUT
VSOUT
SOGOUT
HSYNC Output Clock (Phase-Aligned with DATACK)
VSYNC Output Clock (Phase-Aligned with DATACK)
Sync-on-Green Slicer Output
3.3 V CMOS
3.3 V CMOS
3.3 V CMOS
125
127
126
Voltage
REF BYPASS
Internal Reference Bypass (Bypass with 0.1 µF to Ground)
1.25 V ± 10%
2
Clamp Voltages
RMIDSCV
BMIDSCV
Red Channel Midscale Clamp Voltage Bypass
Blue Channel Midscale Clamp Voltage Bypass
9
24
PLL Filter
FILT
Connection for External Filter Components for Internal PLL
50
Power Supply
VD
VDD
PVD
GND
Analog Power Supply
Output Power Supply
PLL Power Supply
Ground
3.3 V ± 10%
3.3 V ± 10%
3.3 V ± 10%
0V
Serial Port
(2-Wire
Serial Interface)
SDA
SCL
A0
Serial Port Data I/O
Serial Port Data Clock
Serial Port Address Input 1
3.3 V CMOS
3.3 V CMOS
3.3 V CMOS
31
32
33
Data Outputs
Red A[7:0]
Red B[7:0]
Green A[7:0]
Green B[7:0]
Blue A[7:0]
Blue B[7:0]
Port A Outputs of Converter “Red,” Bit 7 is the MSB.
Port B Outputs of Converter “Red,” Bit 7 is the MSB.
Port A Outputs of Converter “Green,” Bit 7 is the MSB.
Port B Outputs of Converter “Green,” Bit 7 is the MSB.
Port A Outputs of Converter “Blue,” Bit 7 is the MSB.
Port B Outputs of Converter “Blue,” Bit 7 is the MSB.
3.3 V CMOS
3.3 V CMOS
3.3 V CMOS
3.3 V CMOS
3.3 V CMOS
3.3 V CMOS
113–120
103–110
90–97
80–87
70–77
57–64
Data Clock
Output
DATACK
DATACK
Data Output Clock
Data Output Clock Complement
3.3 V CMOS
3.3 V CMOS
123
124
REV. A
–5–
AD9888
PIN FUNCTION DESCRIPTIONS
Pin
Inputs
RAIN0
GAIN0
BAIN0
RAIN1
GAIN1
BAIN1
Description
Channel 0 Analog Input for RED
Channel 0 Analog Input for GREEN
Channel 0 Analog Input for BLUE
Channel 1 Analog Input for RED
Channel 1 Analog Input for GREEN
Channel 1 Analog Input for BLUE
High-impedance inputs that accept the RED, GREEN, and BLUE channel graphics signals, respectively. (The six
channels are identical and can be used for any colors; colors are assigned for convenient reference.)
They accommodate input signals ranging from 0.5 V to 1.0 V full scale. Signals should be ac-coupled to these pins to
support clamp operation.
HSYNC0
HSYNC1
Channel 0 Horizontal Sync Input
Channel 1 Horizontal Sync Input
These inputs receive a logic signal that establishes the horizontal timing reference and provides the frequency reference
for pixel clock generation.
The logic sense of this pin is controlled by serial register 0Eh Bit 6 (Hsync Polarity). Only the leading edge of Hsync is
used by the PLL. The trailing edge is used for clamp timing only. When HSPOL = 0, the falling edge of Hsync is used.
When HSPOL = 1, the rising edge is active.
The input includes a Schmitt trigger for noise immunity, with a nominal input threshold of 1.5 V.
VSYNC0
VSYNC1
Channel 0 Vertical Sync Input
Channel 1 Vertical Sync Input
These are the inputs for vertical sync.
SOGIN0
SOGIN1
Channel 0 Sync-on-Green Input
Channel 1 Sync-on-Green Input
This input is provided to assist with processing signals with embedded sync, typically on the GREEN channel. The pin is
connected to a high-speed comparator with an internally generated, variable threshold level, which is nominally set to
0.15 V above the negative peak of the input signal.
When connected to an ac-coupled graphics signal with embedded sync, it will produce a noninverting digital output on
SOGOUT. (This is usually a composite sync signal, containing both vertical and horizontal sync information.)
When not used, this input should be left unconnected. For more details on this function and how it should be configured, refer to the Sync-on-Green section.
CLAMP
External Clamp Input
This logic input may be used to define the time during which the input signal is clamped to the reference dc level
(ground for RGB or midscale for YUV). It should be exercised when the reference dc level is known to be present on
the analog input channels, typically during the back porch of the graphics signal. The CLAMP pin is enabled by setting
the external clamp control (register 0Fh, Bit 7) to 1 (default is 0). When disabled, this pin is ignored and the clamp
timing is determined internally by counting a delay and duration from the trailing edge of the HSYNC input. The logic
sense of this pin is controlled by the clamp polarity control (register 0Fh, Bit 6). When not used, this pin must be grounded
and external clamp programmed to 0.
COAST
Clock Generator Coast Input (Optional)
This input may be used to cause the pixel clock generator to stop synchronizing with HSYNC and continue producing
a clock at its current frequency and phase. This is useful when processing signals from sources that fail to produce horizontal
sync pulses when in the vertical interval or that include equalization pulses. The Coast signal is usually not required for
PC-generated signals.
The logic sense of this pin is controlled by 0FH Bit 3 (Coast Polarity).
When not used, this pin may be grounded and Coast Polarity programmed to 1, or tied HIGH (to V D through a 10 kΩ resistor)
and Coast Polarity programmed to 0. The Coast Polarity register bit defaults to 1 at power-up.
CKEXT
External Clock Input (Optional)
This pin may be used to provide an external clock to the AD9888, in place of the clock internally generated from
HSYNC. It is enabled by programming the External clock register to 1 (15H, Bit 0). When an external clock is used, all
other internal functions operate normally. When unused, this pin should be tied through a 10 kΩ resistor to GROUND,
and the External Clock register programmed to 0. The clock phase adjustment still operates when an external clock
source is used.
–6–
REV. A
AD9888
PIN FUNCTION DESCRIPTIONS (continued)
Pin
Description
CKINV
Sampling Clock Inversion (Optional)
This pin may be used to invert the pixel sampling clock, which has the effect of shifting the sampling phase 180°. This is
in support of Alternate Pixel Sampling mode, wherein higher-frequency input signals (up to 410 Mpps) may be captured by
first sampling the odd pixels, then capturing the even pixels on the subsequent frame.
This pin should be exercised only during blanking intervals (typically vertical blanking) as it may produce several
samples of corrupted data during the phase shift.
CKINV should be grounded when not used.
Outputs
DRA7-0
DRB7-0
DGA7-0
DGB7-0
DBA7-0
DBB7-0
Data Output, Red Channel, Port A
Data Output, Red Channel, Port B
Data Output, Green Channel, Port A
Data Output, Green Channel, Port B
Data Output, Blue Channel, Port A
Data Output, Blue Channel, Port B
These are the main data outputs. Bit 7 is the MSB.
Each channel has two ports. When the part is operated in single-channel mode (Channel Mode bit (15H, Bit 7) = 0), all
data are presented to Port A, and Port B is placed in a high-impedance state.
Programming the Channel Mode bit to 1 establishes dual-channel mode, wherein alternate pixels are presented to Port A and
Port B of each channel. These will appear simultaneously; two pixels are presented at the time of every second input
pixel, when the Output Mode bit (15H, Bit 6) is set to 1 (parallel mode). When the Output Mode bit is set to 0, pixel
data appear alternately on the two ports, one new sample with each incoming pixel (interleaved mode).
In dual-channel mode, the first pixel after HSYNC is routed to Port A. The second pixel goes to Port B, the third to A,
etc. This can be reversed by setting the A/B Invert bit to 1 (15H, Bit 5).
The delay from pixel sampling time to output is fixed. When the sampling time is changed by adjusting the PHASE register, the output timing is shifted as well. The DATACK, DATACK and HSOUT outputs are also moved, so the
timing relationship among the signals is maintained.
DATACK
DATACK
Data Output Clock
Data Output Clock Complement
Differential data clock output signals to be used to strobe the output data and HSOUT into external logic.
They are produced by the internal clock generator and are synchronous with the internal pixel sampling clock.
When the AD9888 is operated in single-channel mode, the output frequency is equal to the pixel sampling frequency.
When operating in dual-channel mode, the clock frequency is one-half the pixel frequency, as is the output data frequency.
When the sampling time is changed by adjusting the PHASE register, the output timing is shifted as well. The Data,
DATACK, DATACK and HSOUT outputs are all moved, so the timing relationship among the signals is maintained.
Either or both signals may be used, depending on the timing mode and interface design employed.
HSOUT
Horizontal Sync Output
A reconstructed and phase-aligned version of the Hsync input. Both the polarity and duration of this output can be
programmed via serial bus registers.
By maintaining alignment with DATACK, DATACK, and Data, data timing with respect to horizontal sync can always
be determined.
SOGOUT
Sync-On-Green Slicer Output
This pin can be programmed to output either the output from the Sync-On-Green slicer comparator or an unprocessed but delayed version of the Hsync input. See the Sync Processing Block Diagram (Figure 25) to view how this pin is
connected. (Note: Besides slicing off SOG, the output from this pin gets no other additional processing on the AD9888.
Vsync separation is performed via the sync separator.)
REF BYPASS
Internal Reference BYPASS
Bypass for the internal 1.25 V band gap reference. It should be connected to ground through a 0.1 µF capacitor. The absolute accuracy of this reference is ± 4%, and the temperature coefficient is ± 50 ppm, which is adequate for most AD9888
applications. If higher accuracy is required, an external reference may be employed instead.
RMIDSCV
BMIDSCV
REV. A
RED Channel Midscale Voltage BYPASS
BLUE Channel Midscale Voltage BYPASS
Bypasses for the internal midscale voltage references. They should each be connected to ground through 0.1 µF
capacitors. The exact voltage varies with the gain setting of the BLUE channel.
–7–
AD9888
PIN FUNCTION DESCRIPTIONS (continued)
Pin
Description
FILT
External Filter Connection
For proper operation, the pixel clock generator PLL requires an external filter. Connect the filter shown in Figure 6 to this
pin. For optimal performance, minimize noise and parasitics on this node.
Power Supply
VD
Main Power Supply
These pins supply power to the main elements of the circuit. It should be as quiet and filtered as possible.
VDD
Digital Output Power Supply
A large number of output pins (up to 52) switching at high speed (up to 110 MHz) generates a lot of power supply
transients (noise). These supply pins are identified separately from the VD pins, so special care can be taken to minimize output noise transferred into the sensitive analog circuitry. If the AD9888 is interfacing with lower voltage logic,
VDD may be connected to a lower supply voltage (as low as 2.5 V) for compatibility.
PVD
Clock Generator Power Supply
The most sensitive portion of the AD9888 is the clock generation circuitry. These pins provide power to the clock PLL
and help the user design for optimal performance. The designer should provide “quiet,” noise-free power to these pins.
GND
Ground
The ground return for all circuitry on chip. It is recommended that the AD9888 be assembled on a single solid ground plane,
with careful attention to ground current paths.
Serial Port (2-Wire)
SDA
SCL
A0
Serial Port Data I/O
ISerial Port Data Clock
Serial Port Address Input 1
For a full description of the 2-wire serial register and how it works, refer to the Control Register section.
DESIGN GUIDE
General Description
The AD9888 is a fully integrated solution for capturing analog
RGB signals and digitizing them for display on flat panel monitors
or projectors. The circuit is ideal for providing a computer interface for HDTV monitors or as the front-end to high-performance
video scan converters.
Implemented in a high-performance CMOS process, the interface can capture signals with pixel rates of up to 205 MHz, and
with an Alternate Pixel Sampling mode, up to 340 MHz.
The AD9888 includes all necessary input buffering, signal dc
restoration (clamping), offset and gain (brightness and contrast)
adjustment, pixel clock generation, sampling phase control, and
output data formatting. All controls are programmable via a
2-wire serial interface. Full integration of these sensitive analog
functions makes system design straightforward and less sensitive
to the physical and electrical environment.
With a typical power dissipation of only 650 mW and an operating temperature range of 0°C to 70°C, the device requires no
special environmental considerations.
Input Signal Handling
The AD9888 has six high-impedance analog input pins for the
red, green, and blue channels. They will accommodate signals
ranging from 0.5 V to 1.0 V p-p.
Signals are typically brought onto the interface board via a DVI-I
connector, a 15-pin D connector, or via BNC connectors. The
AD9888 should be located as close as practical to the input
connector. Signals should be routed via matched-impedance
traces (normally 75 Ω) to the IC input pins.
At that point, the signal should be resistively terminated (to the
signal ground return) and capacitively coupled to the AD9888
inputs through 47 nF capacitors. These capacitors form part of
the dc restoration circuit.
In an ideal world of perfectly matched impedances, the best
performance can be obtained with the widest possible signal
bandwidth. The ultrawide bandwidth inputs of the AD9888
(500 MHz) can track the input signal continuously as it moves
from one pixel level to the next, and digitize the pixel during
a long, flat pixel time. In many systems, however, there are
mismatches, reflections, and noise, which can result in excessive
ringing and distortion of the input waveform. This makes it
more difficult to establish a sampling phase that provides good
image quality. The AD9888 can digitize graphics signals over a
very wide range of frequencies (10 MHz to 205 MHz). Often
characteristics that are beneficial at one frequency can be detrimental at another. Analog bandwidth is one such characteristic.
For UXGA resolutions (up to 205 MHz), a very high analog
bandwidth is desirable because of the fast input signal slew
rates. For VGA and lower resolutions (down to 12.5 MHz), a
very high bandwidth is not desirable, because it allows excess
noise to pass through. To accommodate these varying needs,
the AD9888 includes variable analog bandwidth control.
Four settings are available (75 MHz, 150 MHz, 300 MHz,
and 500 MHz), allowing the analog bandwidth to be matched
with the resolution of the incoming graphics signal.
47nF
RGB
INPUT
75⍀
RAIN
GAIN
BAIN
Figure 1. Analog Input Interface Circuit
–8–
REV. A
AD9888
a period following Hsync called the back porch where a good
black reference is provided. This is the time when clamping
should be done.
Sync Processing
The AD9888 contains circuitry that enables it to accept composite sync inputs, such as Sync-on-Green or the trilevel syncs
found in digital TV signals. A complete description of the sync
processing functionality is found in the Sync Slicer and Sync
Separator sections.
The clamp timing can be established by simply exercising the
CLAMP pin at the appropriate time (with External Clamp = 1).
The polarity of this signal is set by the Clamp Polarity (Register
0Fh, Bit 6).
Hsync, Vsync Inputs
The interface also takes a horizontal sync signal, which is used
to generate the pixel clock and clamp timing. It is possible to
operate the AD9888 without applying Hsync (using an external
clock, external clamp, and single port output mode) but a number
of features of the chip will be unavailable, so it is recommended
that Hsync be provided. This can be either a sync signal directly
from the graphics source, or a preprocessed TTL or CMOS
level signal.
A simpler method of clamp timing employs the AD9888 internal clamp timing generator. The Clamp Placement register is
programmed with the number of pixel times that should pass
after the trailing edge of HSYNC before clamping starts. A
second register (Clamp Duration, Register 06h) sets the duration
of the clamp. These are both 8-bit values, providing considerable
flexibility in clamp generation. The clamp timing is referenced
to the trailing edge of Hsync because, though Hsync duration
can vary widely, the back porch (black reference) always follows
Hsync. A good starting point for establishing clamping is to set
the clamp placement to 08h (providing 8 pixel periods for the
graphics signal to stabilize after sync) and set the clamp duration to 14h (giving the clamp 20 pixel periods to reestablish the
black reference).
The Hsync input includes a Schmitt trigger buffer for immunity
to noise and signals with long rise times. In typical PC-based
graphic systems, the sync signals are simply TTL-level drivers
feeding unshielded wires in the monitor cable. As such, no termination is required or desired.
Serial Control Port
Clamping is accomplished by placing an appropriate charge on
the external input coupling capacitor. The value of this capacitor
affects the performance of the clamp. If it is too small, there will
be a significant amplitude change during a horizontal line time
(between clamping intervals). If the capacitor is too large, then
it will take excessively long for the clamp to recover from a large
change in incoming signal offset. The recommended value (47 nF)
results in recovering from a step error of 100 mV to within
1/2 LSB in 10 lines with a clamp duration of 20 pixel periods
on a 60 Hz SXGA signal.
The serial control port is designed for 3.3 V logic. If there are
5 V drivers on the bus, these pins should be protected with
150 Ω series resistors placed between the pull-up resistors and
the input pins.
Output Signal Handling
The digital outputs are designed and specified to operate from a
3.3 V power supply (VDD). They can also work with a VDD as
low as 2.5 V for compatibility with other 2.5 V logic.
Clamping
RGB Clamping
YUV Clamping
To digitize the incoming signal properly, the dc offset of the input
must be adjusted to fit the range of the on-board A/D converters.
YUV graphic signals are slightly different from RGB signals in
that the dc reference level (black level in RGB signals) can be at
the midpoint of the video signal rather than the bottom. For
these signals it can be necessary to clamp to the midscale range
of the A/D converter range (80h) rather than bottom of the
A/D converter range (00h).
Most graphics systems produce RGB signals with black at ground
and white at approximately 0.75 V. However, if sync signals are
embedded in the graphics, the sync tip is often at ground and
black is at 300 mV. Then white is at approximately 1.0 V. Some
common RGB line amplifier boxes use emitter-follower buffers
to split signals and increase drive capability. This introduces a
700 mV dc offset to the signal, which must be removed for
proper capture by the AD9888.
Clamping to midscale rather than ground can be accomplished
by setting the clamp select bits in the series bus register. The red
and blue channels each have their own selection bit so that they
can be clamped to either midscale or ground independently. The
clamp controls are located in register 10h and are Bits 1 and 2.
The midscale reference voltage that each A/D converter clamps
to is provided independently on the RMIDSCV and BMIDSCV
pins. These two pins should be bypassed to ground with a
0.1 µF capacitor (even if midscale clamping is not required).
The key to clamping is to identify a portion (time) of the signal
when the graphic system is known to be producing black. An
offset is then introduced which results in the A/D converters
producing a black output (code 00h) when the known black
input is present. The offset then remains in place when other
signal levels are processed, and the entire signal is shifted to
eliminate offset errors.
Gain and Offset Control
The AD9888 can accommodate input signals with inputs ranging
from 0.5 V to 1.0 V full scale. The full-scale range is set in three
8-bit registers (Red Gain, Green Gain, and Blue Gain; Registers
08h, 09h, and 10h respectively).
In most graphics systems, black is transmitted between active
video lines. Going back to CRT displays, when the electron
beam has completed writing a horizontal line on the screen
(at the right side), the beam is deflected quickly to the left side
of the screen (called horizontal retrace) and a black signal is
provided to prevent the beam from disturbing the image.
Note that increasing the gain setting results in an image with
less contrast.
The offset control shifts the entire input range, resulting in a
change in image brightness. Three 7-bit registers (Red Offset,
Green Offset, Blue Offset; Registers 0Bh, 0Ch, and 0Dh respectively) provide independent settings for each channel.
In systems with embedded sync, a blacker-than-black signal
(Hsync) is produced briefly to signal the CRT that it is time to
begin a retrace. For obvious reasons, it is important to avoid
clamping on the tip of Hsync. Fortunately, there is almost always
REV. A
–9–
AD9888
The offset controls provide a ± 63 LSB adjustment range. This
range is connected with the full-scale range, so if the input range
is doubled (from 0.5 V to 1.0 V), the offset step size is also
doubled (from 2 mV per step to 4 mV per step).
Figure 2 illustrates the interaction of gain and offset controls.
The magnitude of an LSB in offset adjustment is proportional
to the full-scale range, so changing the full-scale range also
changes the offset. The change is minimal if the offset setting is
near midscale. When changing the offset, the full-scale range is
not affected, but the full-scale level is shifted by the same amount
as the zero-scale level.
OFFSET = 7Fh
The stability of this clock is a very important element in providing the clearest and most stable image. During each pixel time,
there is a period during which the signal is slewing from the old
pixel amplitude and settling at its new value. Then there is a time
when the input voltage is stable, before the signal must slew to a
new value (Figure 4). The ratio of the slewing time to the stable
time is a function of the bandwidth of the graphics DAC and the
bandwidth of the transmission system (cable and termination). It
is also a function of the overall pixel rate. Clearly, if the dynamic
characteristics of the system remain fixed, then the slewing and
settling time is likewise fixed. This time must be subtracted from
the total pixel period, leaving the stable period. At higher pixel
frequencies, the total cycle time is shorter, and the stable pixel
time becomes shorter as well.
OFFSET = 3Fh
INPUT RANGE – V
1.0
PIXEL CLOCK
INVALID SAMPLE
TIMES
OFFSET = 00h
0.5
OFFSET = 7Fh
OFFSET = 3Fh
0.0
OFFSET = 00h
00h
FFh
GAIN
Figure 2. Gain and Offset Control
Figure 4. Pixel Sampling Times
Sync-on-Green
The Sync-on-Green input operates in two steps. First, it sets a
baseline clamp level off of the incoming video signal with a
negative peak detector. Second, it sets the sync trigger level
(nominally 150 mV above the negative peak). The exact trigger
level is variable and can be programmed via register 11H. The
Sync-on-Green input must be ac-coupled to the green analog
input through its own capacitor as shown in Figure 3. The value
of the capacitor must be 1 nF ± 20%. If Sync-on-Green is not
used, this connection is not required and the SOGIN pin should be
left unconnected. (Note: the Sync-on-Green signal is always
negative polarity.) For more details, see the Sync Processing section.
Any jitter in the clock reduces the precision with which the
sampling time can be determined, and must also be subtracted
from the stable pixel time.
Considerable care has been taken in the design of the AD9888’s
clock generation circuit to minimize jitter. As indicated in Figure 5, the clock jitter of the AD9888 is less than 9% of the total
pixel time in all operating modes, making the reduction in the valid
sampling time due to jitter negligible.
14
12
47nF
10
JITTER (p-p) – %
RAIN
47nF
BAIN
47nF
GAIN
SOG
8
6
4
1nF
Figure 3. Typical Clamp Configuration for RGB/YUV
Applications
0
Clock Generation
A Phase Locked Loop (PLL) is employed to generate the pixel
clock. The Hsync input provides a reference frequency to the PLL.
A Voltage Controlled Oscillator (VCO) generates a much higher
pixel clock frequency. This pixel clock is divided by the PLL
divide value (registers 01H and 02H) and phase compared with
the Hsync input. Any error is used to shift the VCO frequency
and maintain lock between the two signals.
25.2
31.5
31.5
36.0
36.0
40.0
50.0
49.5
56.3
65.0
75.0
78.8
85.5
94.5
108.0
135.0
160.0
162.0
175.5
189.0
202.5
2
PIXEL CLOCK – MHz
Figure 5. Pixel Clock Jitter vs. Frequency
The PLL characteristics are determined by the loop filter design,
by the PLL Charge Pump Current and by the VCO range setting.
The loop filter design is illustrated in Figure 6. Recommended
settings of VCO range and charge pump current for VESA standard
display modes are listed in Table IV.
–10–
REV. A
AD9888
3. The 3-Bit Charge Pump Current Register. This register allows
the current that drives the low-pass loop filter to be varied.
The possible current values are listed in Table III.
PVD
CP
0.0039␮F
CZ
0.039␮F
RZ
3.3k⍀
Table II. VCO Frequency Ranges
PV1
PV0
Pixel Clock Range
(MHz)
KVCO Gain
(MHz/V)
0
0
1
1
0
1
0
1
10–45
45–90
90–150
150+
22.5
45
90
180
FILT
Figure 6. PLL Loop Filter Detail
Four programmable registers are provided to optimize the performance of the PLL. These registers are:
1. The 12-Bit Divisor Registers. The input Hsync frequencies
range from 15 kHz to 110 kHz. The PLL multiplies the
frequency of the Hsync signal, producing pixel clock frequencies in the range of 10 MHz to 205 MHz. The Divisor
Register controls the exact multiplication factor. This register may be set to any value between 221 and 4095. (The
divide ratio that is actually used is the programmed divide
ratio plus one.)
Table III. Charge Pump Current/Control Bits
2. The 2-Bit VCO Range Register. To lower the sensitivity of
the output frequency to noise on the control signal, the VCO
operating frequency range is divided into four overlapping
regions. The VCO Range register sets this operating range.
Because there are only four possible regions, only the two
least significant bits of the VCO Range register are used. The
frequency ranges for the lowest and highest regions are shown
in Table II.
Ip2
Ip1
Ip0
Current (␮A)
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
50
100
150
250
350
500
750
1500
Table IV. Recommended VCO Range and Charge Pump Current Settings for Standard Display Formats
Refresh
Rate (Hz)
Horizontal
Frequency (kHz)
Pixel Rate (MHz)
VCORNGE
Current
640 × 480
60
72
75
85
31.5
37.7
37.5
43.3
25.175
31.500
31.500
36.000
00
00
00
00
010
100
100
100
SVGA
800 × 600
56
60
72
75
85
35.1
37.9
48.1
46.9
53.7
36.000
40.000
50.000
49.500
56.250
00
00
01
01
01
100
101
011
011
011
XGA
1024 × 768
60
70
75
80
85
48.4
56.5
60.0
64.0
68.3
65.000
75.000
78.750
85.500
94.500
01
01
01
01
10
100
100
101
101
011
SXGA
1280 × 1024
60
75
85
64.0
80.0
91.1
108.000
135.000
157.500
10
10
11
011
100
100
UXGA
1600 × 1200
60
65
70
75
85
75.0
81.3
87.5
93.8
106.3
162.000
175.500
189.000
202.500
229.500*
11
11
11
11
10
100
100
101
101
110
QXGA
2048 × 1536
2048 × 1536
60
75
260.000*
315.000*
11
11
100
100
Standard
Resolution
VGA
*Graphics sampled at 1/2 the incoming pixel rate using Alternate Pixel Sampling mode.
REV. A
–11–
AD9888
4. The 5-Bit Phase Adjust Register. The phase of the generated
sampling clock may be shifted to locate an optimum sampling
point within a clock cycle. The Phase Adjust Register provides
32 phase-shift steps of 11.25° each. The Hsync signal with an
identical phase shift is available through the HSOUT pin.
Phase adjustment is still available if the pixel clock is being
provided externally.
O2 E2 O2 E2 O2 E2 O2 E2 O2 E2 O2 E2
O2 E2 O2 E2 O2 E2 O2 E2 O2 E2 O2 E2
O2 E2 O2 E2 O2 E2 O2 E2 O2 E2 O2 E2
O2 E2 O2 E2 O2 E2 O2 E2 O2 E2 O2 E2
O2 E2 O2 E2 O2 E2 O2 E2 O2 E2 O2 E2
O2 E2 O2 E2 O2 E2 O2 E2 O2 E2 O2 E2
O2 E2 O2 E2 O2 E2 O2 E2 O2 E2 O2 E2
The COAST pin is used to allow the PLL to continue to run
at the same frequency, in the absence of the incoming Hsync
signal. This may be used during the vertical sync period, or
any other time that the Hsync signal is unavailable. The polarity
of the COAST signal may be set through the COAST
Polarity Register. Also, the polarity of the Hsync signal may be
set through the Hsync Polarity Register.
O2 E2 O2 E2 O2 E2 O2 E2 O2 E2 O2 E2
O2 E2 O2 E2 O2 E2 O2 E2 O2 E2 O2 E2
O2 E2 O2 E2 O2 E2 O2 E2 O2 E2 O2 E2
O2 E2 O2 E2 O2 E2 O2 E2 O2 E2 O2 E2
Figure 9. Even Pixels from Frame 2
Alternate Pixel Sampling Mode
A Logic 1 input on Clock Invert (CKINV, Pin 29) inverts the
nominal ADC clock. CKINV can be switched between frames
to implement the alternate pixel sampling mode. This allows
higher effective image resolution to be achieved at lower pixel
rates but with lower frame rates.
O1 E2 O1 E2 O1 E2 O1 E2 O1 E2 O1 E2
O1 E2 O1 E2 O1 E2 O1 E2 O1 E2 O1 E2
O1 E2 O1 E2 O1 E2 O1 E2 O1 E2 O1 E2
O1 E2 O1 E2 O1 E2 O1 E2 O1 E2 O1 E2
O1 E2 O1 E2 O1 E2 O1 E2 O1 E2 O1 E2
O
E
O
E
O
E
O
E
O
E
O
E
O1 E2 O1 E2 O1 E2 O1 E2 O1 E2 O1 E2
O
E
O
E
O
E
O
E
O
E
O
E
O1 E2 O1 E2 O1 E2 O1 E2 O1 E2 O1 E2
O
E
O
E
O
E
O
E
O
E
O
E
O1 E2 O1 E2 O1 E2 O1 E2 O1 E2 O1 E2
O
E
O
E
O
E
O
E
O
E
O
E
O1 E2 O1 E2 O1 E2 O1 E2 O1 E2 O1 E2
O
E
O
E
O
E
O
E
O
E
O
E
O1 E2 O1 E2 O1 E2 O1 E2 O1 E2 O1 E2
O
E
O
E
O
E
O
E
O
E
O
E
O1 E2 O1 E2 O1 E2 O1 E2 O1 E2 O1 E2
O
E
O
E
O
E
O
E
O
E
O
E
O
E
O
E
O
E
O
E
O
E
O
E
O
E
O
E
O
E
O
E
O
E
O
E
O
E
O
E
O
E
O
E
O
E
O
E
O
E
O
E
O
E
O
E
O
E
O
E
Figure 10. Combined Frame Output from Graphics
Controller
O3 E2 O3 E2 O3 E2 O3 E2 O3 E2 O3 E2
O3 E2 O3 E2 O3 E2 O3 E2 O3 E2 O3 E2
Figure 7. Odd and Even Pixels in a Frame
O3 E2 O3 E2 O3 E2 O3 E2 O3 E2 O3 E2
On one frame, only even pixels are digitized. On the subsequent
frame, odd pixels are sampled. By reconstructing the entire frame
in the graphics controller, a complete image can be reconstructed.
This is similar to the interlacing process that is employed in
broadcast television systems, but the interlacing is vertical
instead of horizontal. The frame data is still presented to the
display at the full desired refresh rate (usually 60 Hz) so there
are no flicker artifacts added.
O3 E2 O3 E2 O3 E2 O3 E2 O3 E2 O3 E2
O3 E2 O3 E2 O3 E2 O3 E2 O3 E2 O3 E2
O3 E2 O3 E2 O3 E2 O3 E2 O3 E2 O3 E2
O3 E2 O3 E2 O3 E2 O3 E2 O3 E2 O3 E2
O3 E2 O3 E2 O3 E2 O3 E2 O3 E2 O3 E2
O3 E2 O3 E2 O3 E2 O3 E2 O3 E2 O3 E2
O3 E2 O3 E2 O3 E2 O3 E2 O3 E2 O3 E2
O3 E2 O3 E2 O3 E2 O3 E2 O3 E2 O3 E2
O1 E1 O1 E1 O1 E1 O1 E1 O1 E1 O1 E1
Figure 11. Subsequent Frame from Controller
O1 E1 O1 E1 O1 E1 O1 E1 O1 E1 O1 E1
O1 E1 O1 E1 O1 E1 O1 E1 O1 E1 O1 E1
O1 E1 O1 E1 O1 E1 O1 E1 O1 E1 O1 E1
O1 E1 O1 E1 O1 E1 O1 E1 O1 E1 O1 E1
O1 E1 O1 E1 O1 E1 O1 E1 O1 E1 O1 E1
O1 E1 O1 E1 O1 E1 O1 E1 O1 E1 O1 E1
O1 E1 O1 E1 O1 E1 O1 E1 O1 E1 O1 E1
O1 E1 O1 E1 O1 E1 O1 E1 O1 E1 O1 E1
O1 E1 O1 E1 O1 E1 O1 E1 O1 E1 O1 E1
O1 E1 O1 E1 O1 E1 O1 E1 O1 E1 O1 E1
Figure 8. Odd Pixels from Frame 1
–12–
REV. A
AD9888
TIMING
The following timing diagrams show the operation of the AD9888
analog interface in all clock modes. The part establishes timing
by having the sample that corresponds to the pixel digitized
when the leading edge of Hsync occurs sent to the “A” data
port. In dual-channel mode, the next sample is sent to the “B”
port. Future samples are alternated between the “A” and “B”
data ports. In single-channel mode, data is only sent to the “A”
data port, and the “B” port is placed in a high impedance state.
The Output Data Clock signal is created so that its rising edge
always occurs between “A” data transitions, and can be used to
latch the output data externally.
t PER
The Hsync input is used as a reference to generate the pixel
sampling clock. The sampling phase can be adjusted, with respect
to Hsync, through a full 360° in 32 steps via the Phase Adjust
register (to optimize the pixel sampling time). Display systems
use Hsync to align memory and display write cycles, so it is
important to have a stable timing relationship between Hsync
output (HSOUT) and data clock (DATACK).
Three things happen to Horizontal Sync in the AD9888. First,
the polarity of Hsync input is determined and will thus have a
known output polarity. The known output polarity can be programmed either active high or active low (Register 0EH, Bit 5).
Second, HSOUT is aligned with DATACK and data outputs.
Third, the duration of HSOUT (in pixel clocks) is set via register 07H. HSOUT is the sync signal that should be used to drive
the rest of the display system.
COAST Timing
t DCYCLE
DATACK
DATACK
t SKEW
DATA
HSOUT
Figure 12. Output Timing
Hsync Timing
Horizontal sync is processed in the AD9888 to eliminate
ambiguity in the timing of the leading edge with respect to the
phase-delayed pixel clock and data.
REV. A
In most computer systems, the Hsync signal is provided continuously on a dedicated wire. In these systems, the COAST
input and function are unnecessary, and should not be used.
In some systems, however, Hsync is disturbed during the Vertical Sync period (Vsync). In some cases, Hsync pulses disappear.
In other systems, such as those that employ Composite Sync
(Csync) signals or embedded Sync-On-Green (SOG), Hsync
includes equalization pulses or other distortions during Vsync.
To avoid upsetting the clock generator during Vsync, it is important to ignore these distortions. If the pixel clock PLL sees
extraneous pulses, it will attempt to lock to this new frequency,
and will have changed frequency by the end of the Vsync period.
It will then take a few lines of correct Hsync timing to recover at
the beginning of a new frame, resulting in a “tearing” of the
image at the top of the display.
The COAST input is provided to eliminate this problem. It is
an asynchronous input that disables the PLL input and allows
the clock to free-run at its then-current frequency. The PLL can
free-run for several lines without significant frequency drift.
–13–
AD9888
RGBIN
P0
P1
P2
P3
P4
P5
P6
P7
HSYNC
PXCK
HS
8 PIPE DELAY
ADCCK
DATACK
DOUTA
D0
HSOUT
D1
D2
D3
D4
VARIABLE DURATION
Figure 13. Single-Channel Mode
RGBIN
P0 P1 P2 P3 P4 P5 P6 P7
HSYNC
PXCK
HS
8 PIPE DELAY
ADCCK
DATACK
DOUTA
D0
HSOUT
D2
D4
D6
VARIABLE DURATION
Figure 14. Single-Channel Mode, Two Pixels/Clock (Even Pixels)
RGBIN
P0 P1 P2 P3 P4 P5 P6 P7
HSYNC
PXCK
HS
8.5 PIPE DELAY
ADCCK
DATACK
DOUTA
D1
HSOUT
D3
D5
D7
VARIABLE DURATION
Figure 15. Single-Channel Mode, Two Pixels/Clock (Odd Pixels)
–14–
REV. A
AD9888
RGBIN
P0
P1
P2
P3
P4
P5
P6
P7
HSYNC
PXCK
HS
7 PIPE DELAY
ADCCK
DATACK
DOUTA
D0
DOUTB
D2
D1
HSOUT
D4
D3
D5
VARIABLE DURATION
Figure 16. Dual-Channel Mode, Interleaved Outputs
RGBIN
P0
P1
P2
P3
P4
P5
P6
P7
HSYNC
PXCK
HS
8 PIPE DELAY
ADCCK
DATACK
DOUTA
D0
D2
D4
DOUTB
D1
D3
D5
HSOUT
VARIABLE DURATION
Figure 17. Dual-Channel Mode, Parallel Outputs
RGBIN
P0 P1 P2 P3 P4 P5 P6 P7
HSYNC
PXCK
HS
7 PIPE DELAY
ADCCK
DATACK
DOUTA
D0
D4
D2
DOUTB
HSOUT
D6
VARIABLE DURATION
Figure 18. Dual-Channel Mode, Interleaved Outputs, Two Pixels/Clock (Even Pixels)
REV. A
–15–
AD9888
RGBIN
P0 P1 P2 P3 P4 P5 P6 P7
HSYNC
PXCK
HS
7.5 PIPE DELAY
ADCCK
DATACK
DOUTA
D5
D1
DOUTB
D3
HSOUT
D7
VARIABLE DURATION
Figure 19. Dual-Channel Mode, Interleaved Outputs, Two Pixels/Clock (Odd Pixels)
RGBIN
P0 P1 P2 P3 P4 P5 P6 P7
HSYNC
PXCK
HS
8 PIPE DELAY
ADCCK
DATACK
DOUTA
D0
D4
DOUTB
D2
D6
HSOUT
VARIABLE DURATION
Figure 20. Dual-Channel Mode, Parallel Outputs, Two Pixels/Clock (Even Pixels)
RGBIN
P0 P1 P2 P3 P4 P5 P6 P7
HSYNC
PXCK
HS
6.5 PIPE DELAY
ADCCK
DATACK
GOUTA
D1
D5
ROUTA
D3
D7
HSOUT
VARIABLE DURATION
Figure 21. Dual-Channel Mode, Parallel Outputs, Two Pixels/Clock (Odd Pixels)
–16–
REV. A
AD9888
RGBIN
P0
P1
P2
P3
P4
P5
P6
P7
HSYNC
PXCK
HS
8 PIPE DELAY
ADCCK
DATACK
GOUTA
Y0
Y1
Y2
Y3
Y4
ROUTA
U0
V1
U2
V3
U4
HSOUT
VARIABLE DURATION
Figure 22. 4:2:2 Output Mode
2-WIRE SERIAL REGISTER MAP
The AD9888 is initialized and controlled by a set of registers, which determine the operating modes. An external controller is
employed to write and read the Control Registers through the 2-line serial interface port.
Table V. Control Register Map
Hex
Address
Read and
Write or
Read Only
Bits
00H
RO
01H
Default
Value
Register Name
Function
7:0
Chip Revision
An 8-bit register which represents the silicon revision level. Revision 0
= 0000 0000.
R/W
7:0
01101001 PLL Div MSB
This register is for Bits [11:4] of the PLL divider. Larger values mean the
PLL operates at a faster rate. This register should be loaded first whenever
a change is needed. (This will give the PLL more time to lock.) See Note
1.
02H
R/W
7:4
1101**** PLL Div LSB
Bits [7:4] LSBs of the PLL divider word. See Note 1.
03H
R/W
7:2
01****** VCO/CPMP
Bits [7:6] VCO Range. Selects VCO frequency range. (See PLL description.)
**001***
Bits [5:3] Charge Pump Current. Varies the current that drives the lowpass filter. (See PLL description.)
ADC Clock phase adjustment. Larger values mean more delay. (1 LSB =
T/32)
04H
R/W
7:3
10000*** Phase Adjust
05H
R/W
7:0
00001000 Clamp Placement Places the Clamp signal an integer number of clock periods after the trailing edge of the Hsync signal.
06H
R/W
7:0
00010100 Clamp Duration
Number of clock periods that the Clamp signal is actively clamping.
07H
R/W
7:0
00100000 Hsync Output
Pulsewidth
Sets the number of pixel clocks that HSOUT will remain active.
08H
R/W
7:0
10000000 Red Gain
Controls ADC input range (Contrast) of each respective channel. Bigger
values give less contrast.
09H
R/W
7:0
10000000 Green Gain
0AH
R/W
7:0
10000000 Blue Gain
0BH
R/W
7:1
1000000* Red Offset
0CH
R/W
7:1
1000000* Green Offset
0DH
R/W
7:1
1000000* Blue Offset
REV. A
Controls dc offset (Brightness) of each respective channel. Bigger values
decrease brightness.
–17–
AD9888
Table V. Control Register Map (continued)
Hex
Address
Read and
Write or
Read Only
Bits
Default
Value
0EH
R/W
7:0
0******* Sync Control
Bit 7—Hsync Polarity Override. (Logic 0 = Polarity determined by chip,
Logic 1 = Polarity set by Bit 6 in Register 0Eh.)
*1******
Bit 6—Hsync Input Polarity. Indicates to the PLL the polarity of the incoming Hsync signal. (Logic 0 = active low, Logic 1 = active high.)
**0*****
Bit 5—Hsync Output Polarity. (Logic 0 = Logic High Sync, Logic 1 =
Logic Low Sync).
***0****
Bit 4—Active Hsync Override. If set to Logic 1, the user can select the
Hsync to be used via Bit 3. If set to Logic 0, the active interface is selected
via Bit 6 in Register 14H.
****0***
Bit 3—Active Hsync select. Logic 0 selects Hsync as the active sync. Logic
1 selects Sync-on-Green as the active sync. Note: the indicated Hsync will
be used only if Bit 4 is set to Logic 1 or if both syncs are active (Bits 1, 7 =
Logic 1 in Register 14H).
*****0**
Bit 2—Vsync Output Invert. (Logic 0 = No Invert, Logic 1 = Invert.)
******0*
Bit 1—Active Vsync override. If set to Logic 1, the user can select the Vsync
to be used via Bit 0. If set to Logic 0, the active interface is selected via Bit
3 in Register 14H.
*******0
Bit 0—Active Vsync select. Logic 0 selects Raw Vsync as the output Vsync.
Logic 1 selects Sync Separated Vsync as the output Vsync. Note: the indicated Vsync will be used only if Bit 1 is set to Logic 1.
0*******
Bit 7—Clamp Function. Chooses between Hsync for Clamp signal or another external signal to be used for clamping. (Logic 0 = Hsync, Logic 1 =
Clamp.)
*1******
Bit 6—Clamp Polarity. Valid only with external Clamp signal. (Logic 0 =
active high, Logic 1 selects active low.)
**0*****
Bit 5—COAST select. Logic 0 selects the coast input pin to be used for the
PLL coast. Logic 1 selects Vsync to be used for the PLL coast.
***0****
Bit 4—COAST Polarity Override. (Logic 0 = Polarity determined by chip,
Logic 1 = Polarity set by Bit 3 in register 0Fh.)
****1***
Bit 3—COAST Polarity. Changes polarity of external COAST signal.
(Logic = 0 = active low, Logic 1 = active high.)
*****1**
Bit 2—Seek Mode Override. (Logic 1 = allow low-power mode, Logic 0 =
disallow low-power mode.)
******1*
Bit 1—PWRDN. Full Chip Power Down, active low. (Logic 0 = Full Chip
Power Down, Logic 1 = normal.)
01111*** Sync-on-Green
Threshold
Sync-on-Green Threshold – Sets the voltage level of the Sync-on-Green
slicer’s comparator.
*****0**
Bit 2—Red Clamp Select – Logic 0 selects clamp to ground. Logic 1 selects
clamp to midscale (voltage at Pin 9).
******0*
Bit 1—Blue Clamp Select – Logic 0 selects clamp to ground. Logic 1 selects
clamp to midscale (voltage at Pin 24).
*******0
Bit 0—Must be set to 1 for proper operation.
0FH
10H
R/W
R/W
7:1
7:3
Register Name
Function
11H
R/W
7:0
00100000 Sync Separator
Threshold
Sync Separator Threshold – Sets how many internal 5 MHz clock periods the
sync separator will count to before toggling high or low. This should be set to
some number greater than the maximum Hsync or equalization pulsewidth.
12H
R/W
7:0
00000000 Pre-COAST
Pre-COAST – Sets the number of Hsync periods that coast becomes active
prior to Vsync.
13H
R/W
7:0
00000000 Post-COAST
Post-COAST – Sets the number of Hsync periods that coast stays active
following Vsync.
–18–
REV. A
AD9888
Table V. Control Register Map (continued)
Hex
Address
Read and
Write or
Read Only
Bits
14H
RO
7:0
Default
Value
Register Name
Function
Sync Detect
Bit 7—Hsync Detect. It is set to Logic 1 if Hsync is present on the analog
interface, else it is set to Logic 0.
Bit 6—AHS: Active Hsync. This bit indicates which analog Hsync is being
used. (Logic 0 = Hsync input pin, Logic 1 = Hsync from sync-on-green.)
Bit 5—Input Hsync Polarity Detect. (Logic 0 = active low, Logic 1 =
active high.)
Bit 4—Vsync detect. It is set to Logic 1 if Vsync is present on the analog
interface, else it is set to Logic 0.
Bit 3—AVS: Active Vsync. This bit indicates which analog Vsync is being
used. (Logic 0 = Vsync input pin, Logic 1 = Vsync from sync separator.)
Bit 2—Output Vsync Polarity Detect. (Logic 0 = active low, Logic 1 =
active high.)
Bit 1—Sync-on-Green Detect. It is set to Logic 1 if sync is present on the
green video input, else it is set to 0.
Bit 0—Input COAST Polarity Detect. (Logic 0 = active low, Logic 1 =
active high.)
15H
R/W
7:0
1*******
Bit 7—Channel Mode. Determines single-channel or dual-channel output
mode. (Logic 0 = single-channel mode, Logic 1 = dual-channel mode.)
*1******
Bit 6—Output Mode. Determine interleaved or parallel output mode.
(Logic 0 = interleaved mode, Logic 1 = parallel mode.)
**0*****
Bit 5—A/B Invert. Determines which port outputs the first data byte after
Hsync. (Logic 0 = A port, Logic 1 = B port.)
***0****
Bit 4—4:2:2 Output Formatting Mode.
****0***
Bit 3—Input Mux Control.
*****11*
Bits [2:1]—Input Bandwidth.
*******0
Bit 0—External Clock. Shuts down PLL and allows external clock to drive the
part. (Logic 0 = use internal PLL, Logic 1 = bypassing of the internal PLL.)
16H
R/W
7:0
11111111 Test Register
Must be set to 11111110 for proper operation.
17H
R/W
7:3
00000000 Test Register
Must be set to default for proper operation.
18H
RO
7:0
Test Register
19H
RO
7:0
Test Register
NOTE
1. The AD9888 only updates the PLL divide ratio when the LSBs are written to (Register 02h).
REV. A
–19–
AD9888
2-WIRE SERIAL CONTROL REGISTER DETAIL CHIP
IDENTIFICATION
00
7-0 Chip Revision
Table VI. VCO Ranges
An 8-bit register that represents the silicon revision.
Revision 0 = 0000 0000, Revision 1 = 0000 0001.
PLL DIVIDER CONTROL
01
7-0 PLL Divide Ratio MSBs
The eight most significant bits of the 12-bit PLL divide ratio
PLLDIV. (The operational divide ratio is PLLDIV + 1.)
03
5-3
CURRENT
Current (␮A)
000
001
010
011
100
101
110
111
50
100
150
250
350
500
750
1500
CURRENT must be set to correspond with the desired
operating frequency (incoming pixel rate).
The power-up default value is CURRENT = 001.
04
7-3
Clock Phase Adjust
A five-bit value that adjusts the sampling phase in 32 steps
across one pixel time. Each step represents an 11.25° shift
in sampling phase.
CLAMP TIMING
05
7-0 Clamp Placement
The AD9888 updates the full divide ratio only when the
LSBs are changed. Writing to this register by itself will
not trigger an update.
An 8-bit register that sets the position of the internally
generated clamp.
PLL Divide Ratio LSBs
When the external clamp control bit is set to 0, a clamp
signal is generated internally, at a position established by
the clamp placement and for a duration set by the clamp
duration. Clamping is started (Clamp Placement) pixel
periods after the trailing edge of Hsync. The clamp placement may be programmed to any value up to 255, except 0.
The four least significant bits of the 12-bit PLL divide
ratio PLLDIV. The operational divide ratio is PLLDIV + 1.
The power-up default value of PLLDIV is 1693
(PLLDIVM = 69h, PLLDIVL = Dxh).
The AD9888 updates the full divide ratio only when this
register is written to.
The clamp should be placed during a time that the input
signal presents a stable black-level reference, usually the
back porch period between Hsync and the image.
CLOCK GENERATOR CONTROL
03
7-6 VCO Range Select
VCORNGE must be set to correspond with the desired
operating frequency (incoming pixel rate).
Charge Pump Current
The power-up default value is 16.
The power-up default value of PLLDIV is 1693
(PLLDIVM = 69h, PLLDIVL = Dxh).
Two bits that establish the operating range of the clock
generator.
10–45
45–90
90–150
150+
Table VII. Charge Pump Currents
VESA has established standard timing specifications, which
will assist in determining the value for PLLDIV as a function of horizontal and vertical display resolution and frame
rate (Table IV).
7-4
00
01
10
11
Three bits that establish the current driving the loop filter
in the clock generator.
The 12-bit value of the PLL divider supports divide ratios
from 2 to 4095. The higher the value loaded in this register, the higher the resulting clock frequency with respect
to a fixed Hsync frequency.
02
Pixel Rate Range
The power-up default value is 01.
The PLL derives a master clock from an incoming Hsync
signal. The master clock frequency is then divided by an
integer value, such that the output is phase-locked to Hsync.
This PLLDIV value determines the number of pixel times
(pixels plus horizontal blanking overhead) per line. This is
typically 20% to 30% more than the number of active pixels
in the display.
However, many computer systems do not conform precisely to the recommendations, and these numbers should
be used only as a guide. The display system manufacturer
should provide automatic or manual means for optimizing
PLLDIV. An incorrectly set PLLDIV will usually produce
one or more vertical noise bars on the display. The greater
the error, the greater the number of bars produced.
VCORNGE
When the external clamp control bit is set to 1, this register is ignored.
06
7-0
Clamp Duration
An 8-bit register that sets the duration of the internally
generated clamp.
The PLL gives the best jitter performance at high frequencies. For this reason, in order to output low pixel
rates and still get good jitter performance, the PLL actually operates at a higher frequency but then divides down
the clock rate afterwards. Table VI shows the pixel rates
for each VCO range setting. The PLL output divisor is
automatically selected with the VCO range setting.
When the external clamp control bit is set to 0, a clamp
signal is generated internally, at a position established by
the clamp placement and for a duration set by the clamp
duration. Clamping is started (Clamp Placement) pixel
periods after the trailing edge of Hsync, and continues for
(Clamp Duration) pixel periods. The clamp duration may
–20–
REV. A
AD9888
be programmed to any value between 1 and 255. A value
of 0 is not supported.
0D
For the best results, the clamp duration should be set to
include the majority of the black reference signal time that
follows the Hsync signal trailing edge. Insufficient clamping time can produce brightness changes at the top of the
screen, and a slow recovery from large changes in the
Average Picture Level (APL), or brightness.
0E
7
Hsync Input Polarity Override
Table VIII. Hsync Input Polarity Override Settings
Hsync PULSEWIDTH
7-0
Blue Channel Offset Adjust
This register is used to override the internal circuitry that
determines the polarity of the Hsync signal going into the PLL.
When the external clamp control bit is set to 1, this register is ignored.
07
7-1
A 7-bit offset binary word that sets the dc offset of the
BLUE channel. See REDOFST (0B).
Hsync Output Pulsewidth
Override Bit
Result
0
1
Hsync Polarity Determined by Chip
Hsync Polarity Determined by User
The default for Hsync polarity override is 0 (polarity
determined by chip).
An 8-bit register that sets the duration of the Hsync
output pulse.
0E
The leading edge of the Hsync output is triggered by the
internally generated, phase-adjusted PLL feedback clock.
The AD9888 then counts a number of pixel clocks equal
to the value in this register. This triggers the trailing edge
of the Hsync output, which is also phase-adjusted.
6
HSPOL
Table IX. Hsync Input Polarity Settings
INPUT GAIN
08
7-0 Red Channel Gain Adjust
An 8-bit word that sets the gain of the RED channel.
The AD9888 can accommodate input signals with a
full-scale range of between 0.5 V and 1.0 V p-p. Set
ting REDGAIN to 255 corresponds to an input range
of 1.0 V. A REDGAIN of 0 establishes an input range
of 0.5 V. Note that INCREASING REDGAIN results
in the picture having LESS CONTRAST (the input
signal uses fewer of the available converter codes). See
Figure 2.
09
7-0
7-0
Blue Channel Gain Adjust
Active LOW
Active HIGH
The power-up default value is HSPOL = 1.
0E
5
Hsync Output Polarity
One bit that determines the polarity of the Hsync output
and the SOG output. Table X shows the effect of this
option. SYNC indicates the logic state of the sync pulse.
A 7-bit offset binary word that sets the dc offset of the
RED channel. One LSB of offset adjustment equals ap
proximately one LSB change in the ADC offset. There
fore, the absolute magnitude of the offset adjustment
scales as the gain of the channel is changed. A nominal
setting of 63 results in the channel nominally clamping
the back porch (during the clamping interval) to code 00.
An offset setting of 127 results in the channel clamping to
code 64 of the ADC. An offset setting of 0 clamps to code
–63 (off the bottom of the range). Increasing the value of
Red Offset decreases the brightness of the channel.
Table X. Hsync Output Polarity Settings
Setting
SYNC
0
1
Logic 1 (Positive Polarity)
Logic 0 (Negative Polarity)
The default setting for this register is 0.
0E
Green Channel Offset Adjust
A 7-bit offset binary word that sets the dc offset of the
GREEN channel. See REDOFST (0B).
REV. A
0
1
The device will operate if this bit is set incorrectly, but the
internally generated clamp position, as established by
Clamp Placement (Register 05h), will not be placed as
expected, which may generate clamping errors.
Green Channel Gain Adjust
INPUT OFFSET
0B 7-1 Red Channel Offset Adjust
7-1
Function
Active HIGH means the leading edge of the Hsync pulse
is positive-going. This means that timing will be based on
the leading edge of Hsync, which is now the rising edge.
An 8-bit word that sets the gain of the BLUE channel.
See REDGAIN (08).
0C
HSPOL
Active LOW means the leading edge of the Hsync pulse is
negative-going. All timing is based on the leading edge
of Hsync, which is the falling edge. The rising edge has
no effect.
An 8-bit word that sets the gain of the GREEN channel.
See REDGAIN (08).
0A
Hsync Input Polarity
A bit that must be set to indicate the polarity of the Hsync
signal that is applied to the PLL Hsync input.
–21–
4
Active Hsync Override
This bit is used to override the automatic Hsync selection.
To override, set this bit to Logic 1. When overriding, the
active Hsync is set via Bit 3 in this register.
AD9888
Table XI. Active Hsync Override Settings
Table XVI. Clamp Input Signal Source Settings
Override
Result
External Clamp
Function
0
1
Auto determines the active interface.
Override, Bit 3 determines the active interface.
0
1
Internally Generated Clamp
Externally Provided Clamp Signal
The default for this register is 0.
0E
3
A 0 enables the clamp timing circuitry controlled by clamp
placement and clamp duration. The clamp position and
duration is counted from the leading edge of Hsync.
Active Hsync Select
This bit is used under two conditions. It is used to select
the active Hsync when the override bit is set (Bit 4). Alternately, it is used to determine the active Hsync when not
overriding but both Hsyncs are detected.
A 1 enables the external CLAMP input pin. The three
channels are clamped when the CLAMP signal is active.
The polarity of CLAMP is determined by the Clamp
Polarity bit (Register 0Fh, Bit 6).
Table XII. Active Hsync Select Settings
Select
0
1
The power-up default value is External Clamp = 0.
Result
0F
2
Hsync Input
Sync-on-Green Input
Table XVII. Clamp Input Signal Polarity Settings
Vsync Output Invert
A bit that inverts the polarity of the Vsync output. Table
XIII shows the effect of this option.
Table XIII. Vsync Output Polarity Settings
0E
Setting
SYNC
1
0
Invert
Don’t Invert
Function
1
0
Active LOW
Active HIGH
The default setting for this register is 0.
A Logic 0 means that the circuit will clamp when CLAMP
is HIGH, and it will pass the signal to the ADC when
CLAMP is LOW.
1
The power-up default value is Clamp Polarity = 1.
Active Vsync Override
0F
Override
Result
0
1
Auto determines the active Vsync.
Override, Bit 0 determines the active Vsync.
5
Table XVIII. COAST Source Selection Settings
The default for this register is 0.
0
Active Vsync Select
This bit is used to select the active Vsync when the override bit is set (Bit 1).
Table XV. Active Vsync Select Settings
Result
0
1
Vsync Input
Sync Separator Output
Select
Result
0
1
COAST Input Pin
Vsync (See above text.)
The default for this register is 0.
0F
Select
COAST Select
This bit is used to select the active coast source. The
choices are the coast input pin or Vsync. If Vsync is selected,
the additional decision of using the Vsync input pin or the
output from the sync separator needs to be made (Register
0E, Bits 1, 0).
Table XIV. Active Vsync Override Settings
0F
Clamp Polarity
A Logic 1 means that the circuit will clamp when CLAMP
is LOW, and it will pass the signal to the ADC when
CLAMP is HIGH.
This bit is used to override the automatic Vsync selection.
To override, set this bit to Logic 1. When overriding, the
active interface is set via Bit 0 in this register.
0E
Clamp Input Signal Polarity
A bit that determines the polarity of the externally provided CLAMP signal.
The default for this register is 0.
0E
6
4
COAST Input Polarity Override
This register is used to override the internal circuitry that
determines the polarity of the coast signal going into the
PLL.
Table XIX. COAST Input Polarity Override Settings
The default for this register is 0.
Override Bit
Result
7
0
1
COAST Polarity Determined by Chip
COAST Polarity Determined by User
Clamp Input Signal Source
A bit that determines the source of clamp timing.
The default for coast polarity override is 0.
–22–
REV. A
AD9888
0F
3
The default setting is 15 and corresponds to a threshold
value of 0.16 V.
COAST Input Polarity
A bit to indicate the polarity of the COAST signal that is
applied to the PLL COAST input.
10
Function
0
1
Active LOW
Active HIGH
Active LOW means that the clock generator will ignore
Hsync inputs when COAST is LOW, and continue
operating at the same nominal frequency until COAST
goes HIGH.
Table XXIII. Red Clamp Select Settings
Active HIGH means that the clock generator will ignore
Hsync inputs when COAST is HIGH, and continue
operating at the same nominal frequency until COAST
goes LOW.
10
Seek Mode Override
1
0
Allow Seek Mode
Disallow Seek Mode
1
11
PWRDN
12
Power-Down
Normal Operation
7-3
7:0
Sync Separator Threshold
7-0
Pre-COAST
7-0
Post-COAST
This register allows the COAST signal to be applied
following to the Vsync signal. This is necessary in cases
where post-equalization pulses are present. The step size
for this control is one Hsync period.
The default is 0.
Sync-on-Green Slicer Threshold
This register allows the comparator threshold of the Syncon-Green slicer to be adjusted. This register adjusts it in
steps of 10 mV, with the minimum setting equaling 10 mV
and the maximum setting equaling 330 mV.
REV. A
Clamp to Ground
Clamp to Midscale (Pin 24)
The default is 0.
The default for this register is 1.
10
0
1
This register allows the COAST signal to be applied prior
to the Vsync signal. This is necessary in cases where preequalization pulses are present. The step size for this
control is one Hsync period.
13
0
1
Function
The default for this register is 32.
Table XXII. Power-Down Settings
Result
Clamp
This register is used to set the responsiveness of the sync
separator. It sets how many internal 5 MHz clock periods
the sync separator must count to before toggling high or
low. It works like a low-pass filter to ignore Hsync pulses
in order to extract the Vsync signal. This register should
be set to some number greater than the maximum Hsync
pulsewidth. Note: the sync separator threshold uses an
internal dedicated clock with a frequency of approximately 5 MHz.
This bit is used to put the chip in power-down mode. In this
mode the chip’s power dissipation is reduced to a fraction
of the typical power (see the Electrical Characteristics
table for exact power dissipation). When in power-down,
the HSOUT, VSOUT, DATACK, DATACK, and all 48
of the data outputs are put into a high impedance state.
(Note: the SOGOUT output is not put into high impedance.) Circuit blocks that continue to be active during
power-down include the voltage references, sync processing, sync detection, and the serial register. These blocks
facilitate a fast start-up from power-down.
Select
Blue Clamp Select
The default setting for this register is 0.
The default for this register is 1.
0F
Clamp to Ground
Clamp to Midscale (Pin 9)
Table XXIV. Blue Clamp Select Settings
Table XXI. Seek Mode Override Settings
Result
0
1
1
This bit is used to either allow or disallow the low-power
mode. The low-power mode (seek mode) occurs when
there are no signals on any of the Sync inputs.
Select
Function
A bit that determines whether the blue channel is clamped
to ground or to midscale. Clamping to midscale actually
clamps to Pin 24.
The power-up default value is CSTPOL = 1.
2
Clamp
The default setting for this register is 0.
This function needs to be used along with the COAST
polarity override bit (Bit 4).
0F
Red Clamp Select
A bit that determines whether the red channel is clamped
to ground or to midscale. For RGB video, all three channels are referenced to ground. For YcbCr (or YUV), the
Y channel is referenced to ground, but the CbCr channels
are referenced to midscale. Clamping to midscale actually
clamps to Pin 9.
Table XX. COAST Input Polarity Settings
CSTPOL
2
–23–
AD9888
14
7
The sync processing block diagram (Figure 25) shows where
this function is implemented.
Hsync Detect
This bit is used to indicate when activity is detected on
the selected Hsync input pin. If HSYNC is held high or
low, activity will not be detected.
14
3
Table XXV. Hsync Detection Results
Detect
Function
0
1
No Activity Detected
Activity Detected
The sync processing block diagram shows where this
function is implemented.
14
6
Table XXIX. Active Vsync Results
AHS – Active Hsync
This bit indicates which Hsync input source is being used
by the PLL (Hsync input or Sync-on-Green). Bits 7 and 1
in this register are what determine which source is used. If
both Hsync and SOG are detected, the user can determine
which has priority via Bit 3 in Register 0EH. The user can
override this function via Bit 4 in Register 0EH. If the
override bit is set to Logic 1, then this bit will be forced to
whatever the state of Bit 3 in register 0EH is set to.
Table XXVI. Active Hsync Results
Bit 7
(Hsync
Detect)
Bit 1
(SOG
Detect)
Bit 4, Reg
OEH
(Override)
AHS
0
0
1
1
X
0
1
0
1
X
0
0
0
0
1
Bit 3 in 0EH
1
0
Bit 3 in 0EH
Bit 3 in 0EH
Override
AVS
0
1
X
0
0
1
1
0
Bit 0 in 0EH
AVS = 0 means Vsync input.
The override bit is in Register 0EH, Bit 1.
14
2
Detected Vsync Output Polarity Status
This bit reports the status of the Vsync output polarity
detection circuit. It can be used to determine the polarity
of the Vsync input. The detection circuit’s location is
shown in the Sync Processing Block Diagram (Figure 25).
Table XXX. Detected Vsync Input Polarity Status
14
AHS = 1 means use the SOG pin input for HSYNC.
Vsync Polarity Status
Result
0
1
Vsync Polarity is Active Low
Vsync Polarity is Active High
1
Sync-on-Green Detect
This bit is used to indicate when Sync activity is detected
on the selected Sync-on-Green input pin.
The override bit is in Register 0EH, Bit 4.
5
Bit 5 (Vsync Detect)
AVS = 1 means Sync separator.
AHS = 0 means use the HSYNC pin input for HSYNC.
14
AVS – Active Vsync
This bit indicates which Vsync source is being used; the
Vsync input or the output from the sync separator. Bit 4
in this register is what determines which is active. If both
Vsync and SOG are detected, the user can determine
which has priority via Bit 0 in Register 0EH. The user can
override this function via Bit 1 in Register 0EH. If the
override bit is set to Logic 1, this bit will be forced to
whatever the state of Bit 0 in Register 0EH is set to.
Detected Hsync Input Polarity Status
This bit reports the status of the HSYNC input polarity
detection circuit. It can be used to determine the polarity
of the HSYNC input. The detection circuit’s location is
shown in the Sync Processing Block Diagram (Figure 25).
Table XXXI. Sync-on-Green Detection Results
Detect
Function
0
1
No Activity Detected
Activity Detected
Table XXVII. Detected Hsync Input Polarity Status
14
HSYNC Polarity Status
Result
0
1
Hsync Polarity is Negative.
Hsync Polarity is Positive.
4
The Sync Processing Block Diagram (Figure 25) shows
where this function is implemented.
14
0
Vsync Detect
This bit is used to indicate when activity is detected on
the selected Vsync input pin. If Vsync is held high or low,
activity will not be detected.
Table XXXII. Detected COAST Input Polarity Status
Table XXVIII. Vsync Detection Results
Detect
Function
0
1
No Activity Detected
Activity Detected
Detected COAST Polarity Status
This bit reports the status of the coast input polarity detection circuit. It can be used to determine the polarity
of the COAST input. The detection circuit’s location is
shown in Figure 25.
–24–
HSYNC Polarity Status
Result
0
1
COAST Polarity is Negative.
COAST Polarity is Positive.
REV. A
AD9888
is shown in Figure 12. Recommended input and output
configurations are shown in Table XXXVII. In 4:2:2
mode, the red and blue channels can be interchanged to
help satisfy board layout or timing requirements, but the
green channel must be configured for Y.
MODE CONTROL 1
15
7
Channel Mode
A bit that determines whether all pixels are presented to a
single port (A), or alternating pixels are demultiplexed to
Ports A and B.
Table XXXIII. Channel Mode Settings
Table XXXVI. 4:2:2 Output Mode Select
DEMUX
Function
Select
Output Mode
0
1
All data goes to Port A.
Alternate pixels go to Port A and Port B.
0
1
4:4:4
4:2:2
When DEMUX = 0, Port B outputs are in a highimpedance state. The maximum data rate for single-port
mode is 110 MHz. The timing diagrams starting with
Figure 13 show the effects of this option.
Table XXXVII. 4:2:2 Input/Output Configuration
The power-up default value is 1.
15
6
Output Mode
A bit that determines whether all pixels are presented to Port A
and Port B simultaneously on every second DATACK
rising edge, or alternately on Port A and Port B on successive
DATACK rising edges.
15
Channel
Input Connection
Output Format
Red
Green
Blue
V
Y
U
U/V
Y
High Impedance
3
Input Mux Control
A bit that selects either analog inputs from Channel 0 or
the analog inputs from Channel 1.
Table XXXIV. Output Mode Settings
PARALLEL
Function
0
1
Data is interleaved.
Data is simultaneous on every other data
clock.
Table XXXVIII. Input Mux Control
15
When in single port mode (DEMUX = 0), this bit is
ignored. The timing diagrams (Figure 17) show the effects
of this option.
2-1
Control
Channel Selected
0
1
Channel 0
Channel 1
Analog Bandwidth Control
Two bits that select the analog bandwidth.
Table XXXIX. Analog Bandwidth Control
The power-up default value is PARALLEL = 1.
15
5
Output Port Phase
One bit that determines whether even pixels or odd pixels
go to Port A.
Table XXXV. Output Port Phase Settings
OUTPHASE
0
1
First Pixel after Hsync
15
Port A
Port B
1
1
0
0
1
0
1
0
500 MHz
300 MHz
150 MHz
75 MHz
External Clock Select
EXTCLK
Function
0
1
Internally Generated Clock
Externally Provided Clock Signal
A Logic 0 enables the internal PLL that generates the
pixel clock from an externally provided HSYNC.
A Logic 1 enables the external CKEXT input pin. In this
mode, the PLL Divide Ratio (PLLDIV) is ignored. The
clock phase adjust (PHASE) is still functional.
When DEMUX = 0, this bit is ignored as data always
comes out of only Port A.
4:2:2 Output Mode Select
A bit that configures the output data in 4:2:2 mode. This
mode can be used to reduce the number of data lines used
from 24 down to 16 for applications using YUV, YCbCr,
or YPbPr graphics signals. A timing diagram for this mode
REV. A
Analog Bandwidth
Table XL. External Clock Select Settings
When OUTPHASE = 1, these ports are reversed and the
first sample goes to Port B.
4
Bit 1
A bit that determines the source of the pixel clock.
In normal operation (OUTPHASE = 0), when operating
in dual-port output mode (DEMUX = 1), the first sample
after the Hsync leading edge is presented at Port A. Every
subsequent ODD sample appears at Port A. All EVEN
samples go to Port B.
15
0
Bit 2
–25–
The power-up default value is EXTCLK = 0.
AD9888
2-WIRE SERIAL CONTROL PORT
A 2-wire serial interface control interface is provided. Up to two
AD9888 devices may be connected to the 2-wire serial interface,
with each device having a unique address.
The 2-wire serial interface comprises a clock (SCL) and a bidirectional data (SDA) pin. The AD9888 acts as a slave for receiving
and transmitting data over the serial interface. When the serial
interface is not active, the logic levels on SCL and SDA are
pulled HIGH by external pull-up resistors.
data written after the data byte intended for the base address. If
more bytes are transferred than there are available addresses, the
address will not increment and remain at its maximum value of
19h. Any base address higher than 19h will not produce an
ACKnowledge signal.
Data are read from the control registers of the AD9888 in a
similar manner. Reading requires two data transfer operations.
The base address must be written with the R/W bit of the slave
address byte LOW to set up a sequential read operation.
Data received or transmitted on the SDA line must be stable for
the duration of the positive-going SCL pulse. Data on SDA must
change only when SCL is LOW. If SDA changes state while SCL is
HIGH, the serial interface interprets that action as a start or stop
sequence.
Reading (the R/W bit of the slave address byte HIGH) begins at
the previously established base address. The address of the read
register autoincrements after each byte is transferred.
To terminate a read/write sequence to the AD9888, a stop signal must be sent. A stop signal comprises a LOW-to-HIGH
transition of SDA while SCL is HIGH.
There are six components to serial bus operation:
Start signal
Slave address byte
Base register address byte
Data byte to read or write
Stop signal
A repeated start signal occurs when the master device driving
the serial interface generates a start signal without first generating a stop signal to terminate the current communication. This
is used to change the mode of communication (read, write)
between the slave and master without releasing the serial interface lines.
When the serial interface is inactive (SCL and SDA are HIGH),
communications are initiated by sending a start signal. The start
signal is a HIGH-to-LOW transition on SDA while SCL is HIGH.
This signal alerts all slaved devices that a data transfer sequence
is coming.
Serial Interface Read/Write Examples
Write to One Control Register
The first eight bits of data transferred after a start signal comprise
a 7-bit slave address (the first seven bits) and a single R/W bit
(the eighth bit). The R/W bit indicates the direction of data transfer,
read from (1) or write to (0) the slave device. If the transmitted slave
address matches the address of the device (set by the state of the A0
input pin in Table XLI), the AD9888 acknowledges by bringing
SDA LOW on the ninth SCL pulse. If the addresses do not match,
the AD9888 does not acknowledge
Write to Four Consecutive Control Registers
Start Signal
Slave Address Byte (R/W Bit = LOW)
Base Address Byte
Data Byte to Base Address
Stop Signal
Start Signal
Slave Address Byte (R/W Bit = LOW)
Base Address Byte
Data Byte to Base Address
Data Byte to (Base Address + 1)
Data Byte to (Base Address + 2)
Data Byte to (Base Address + 3)
Stop Signal
Table XLI. Serial Port Addresses
Bit 7
(MSB)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
A6
A5
A4
A3
A2
A1
A0
1
1
0
0
0
0
1
1
1
1
0
0
0
1
Read from One Control Register
Start Signal
Slave Address Byte (R/W Bit = LOW)
Base Address Byte
Start Signal
Slave Address Byte (R/W Bit = HIGH)
Data Byte from Base Address
Stop Signal
Data Transfer via Serial Interface
For each byte of data read or written, the MSB is the first bit of
the sequence.
If the AD9888 does not acknowledge the master device during a
write sequence, the SDA remains HIGH so the master can
generate a stop signal. If the master device does not acknowledge
the AD9888 during a read sequence, the AD9888 interprets this
as “end of data.” The SDA remains HIGH so the master can
generate a stop signal.
Read from Four Consecutive Control Registers
Writing data to specific control registers of the AD9888 requires
that the 8-bit address of the control register of interest be written after the slave address has been established. This control
register address is the base address for subsequent write operations. The base address autoincrements by one for each byte of
–26–
Start Signal
Slave Address Byte (R/W bit = LOW)
Base Address Byte
Start Signal
Slave Address Byte (R/W Bit = HIGH)
Data Byte from Base Address
Data Byte from (Base Address + 1)
Data Byte from (Base Address + 2)
Data Byte from (Base Address + 3)
Stop Signal
REV. A
AD9888
composite sync, the counter will also count up. However, since
the Vsync signal is much longer, it will count to a higher number M. For most video modes, M will be at least 255. So, Vsync
can be detected on the composite sync signal by detecting when
the counter counts to higher than N. The specific count that
triggers detection (T) can be programmed through the serial
register (0fh).
Sync Processing
Table XLII. Control of the Sync Block Muxes via the
Serial Register
Mux
Serial Bus Control Bit
Number(s) Control Bit State
Result
1 and 2
0EH: Bit 3
0
1
Pass HSYNC
Pass Sync-on-Green
3
0FH: Bit 5
0
1
Pass COAST
Pass Vsync
4
0EH: Bit 0
0
1
Pass Vsync
Pass Sync Separator
Signal
Once Vsync has been detected, there is a similar process to
detect when it goes inactive. At detection, the counter first
resets to 0, then starts counting up when Vsync goes away.
Similar to the previous case, it will detect the absence of Vsync
when the counter reaches the threshold count (T). In this
way, it will reject noise and/or serration pulses. Once Vsync is
detected to be absent, the counter resets to 0 and begins the
cycle again.
5
15H: Bit 3
0
1
Pass Channel 0 Inputs
Pass Channel 1 Inputs
PCB LAYOUT RECOMMENDATIONS
Sync Slicer
The purpose of the sync slicer is to extract the sync signal from
the green graphics channel. A sync signal is not present on all
graphics systems, only those with Sync-on-Green. The sync
signal is extracted from the green channel in a two-step process.
First, the SOG input is clamped to its negative peak (typically
0.3 V below the black level). Next, the signal goes to a comparator
with a variable trigger level, nominally 0.15 V above the clamped
level. The “sliced” sync is typically a composite sync signal
containing both Hsync and Vsync.
Sync Separator
A sync separator extracts the Vsync signal from a composite sync
signal. It does this through a low-pass filter-like or integratorlike operation. It works on the idea that the Vsync signal stays
active for a much longer time than the Hsync signal. So, it rejects
any signal shorter than a threshold value, which is somewhere
between an Hsync pulsewidth and a Vsync pulsewidth.
The sync separator on the AD9888 is an 8-bit digital counter
with a 5 MHz clock. It works independently of the polarity of
the composite sync signal. (Polarities are determined elsewhere
on the chip.) The basic idea is that the counter counts up when
Hsync pulses are present. But since Hsync pulses are relatively
short in width, the counter only reaches a value of N before the
pulse ends. It then starts counting down eventually reaching 0
before the next Hsync pulse arrives. The specific value of N will
vary for different video modes, but will always be less than 255.
For example, with a 1 µs width Hsync, the counter will only
reach 5 (1 µs/200 ns = 5). Now, when Vsync is present on the
The AD9888 is a high-precision, high-speed analog device. To
get the maximum performance out of the part, it is important to
have a well laid-out board. The following is a guide for designing a board using the AD9888.
Analog Interface Inputs
Using the following layout techniques on the graphics inputs is
extremely important.
Minimize the trace length running into the graphics inputs. This
is accomplished by placing the AD9888 as close as possible to
the graphics (VGA) connector. Long input trace lengths are
undesirable because they will pick up more noise from the board
and other external sources.
Place the 75 Ω termination resistors (see Figure 1) as close to
the AD9888 chip as possible. Any additional trace length between
the termination resistors and the input of the AD9888 increases the
magnitude of reflections, which will corrupt the graphics signal.
Use 75 Ω matched impedance traces. Trace impedances other
than 75 Ω will also increase the chance of reflections.
The AD9888 has very high input bandwidth (500 MHz). While
this is desirable for acquiring a high resolution PC graphics signal
with fast edges, it means that it will also capture any highfrequency noise present. Therefore, it is important to reduce the
amount of noise that gets coupled to the inputs. Avoid running
any digital traces near the analog inputs.
SDA
t BUFF
t STAH
t DHO
t STASU
t DSU
t DAL
SCL
t DAH
Figure 23. Serial Port Read/Write Timing
REV. A
–27–
t STOSU
AD9888
BIT 7
SDA
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
ACK
SCL
Figure 24. Serial Interface—Typical Byte Transfer
ACTIVITY
DETECT
SYNC SLICER
MUX5
SOGIN0
NEGATIVE PEAK
CLAMP
SYNC SEPARATOR
COMP
SYNC
INTEGRATOR
VSYNC
1/S
SOGIN1
MUX1
HSYNC0
SOGOUT
HSYNC1
MUX5
PLL
ACTIVITY
DETECT
POLARITY
DETECT
HSYNCOUT
PIXEL CLOCK
CLOCK
GENERATOR
MUX2
COAST
MUX3
POLARITY
DETECT
VSYNC0
VSYNCOUT
VSYNC1
MUX5
ACTIVITY
DETECT
POLARITY
DETECT
MUX4
Figure 25. Sync Processing Block Diagram
The AD9888 can digitize graphics signals over a very wide range
of frequencies (10 MHz to 205 MHz). Often characteristics that
are beneficial at one frequency can be detrimental at another.
Analog bandwidth is one such characteristic. For UXGA resolutions (up to 205 MHz), a very high analog bandwidth is desirable
because of the fast input signal slew rates. For VGA and lower
resolutions (down to 12.5 MHz), a very high bandwidth is not
desirable, because it allows excess noise to pass through. To
accommodate these varying needs, the AD9888 includes variable analog bandwidth control. Four settings are available
(75 MHz, 150 MHz, 300 MHz, and 500 MHz), allowing the
analog bandwidth to be matched with the resolution of the
incoming graphics signal.
Power Supply Bypassing
It is recommended to bypass each power supply pin with a 0.1 µF
capacitor. The exception is in the case where two or more supply
pins are adjacent to each other. For these groupings of powers/
grounds, it is only necessary to have one bypass capacitor. The
fundamental idea is to have a bypass capacitor within about
0.5 cm of each power pin. Also, avoid placing the capacitor on
the opposite side of the PC board from the AD9888, as that
interposes resistive vias in the path.
The bypass capacitors should be physically located between the
power plane and the power pin. Current should flow from the
power plane => capacitor => power pin. Do not make the power
connection between the capacitor and the power pin. Placing a
via underneath the capacitor pads, down to the power plane, is
generally the best approach.
It is particularly important to maintain low noise and good
stability of PVd (the clock generator supply). Abrupt changes in
PVd can result in similarly abrupt changes in sampling clock
phase and frequency. This can be avoided by careful attention
to regulation, filtering, and bypassing. It is highly desirable to
provide separate regulated supplies for each of the analog circuitry groups (Vd and PVd).
Some graphic controllers use substantially different levels of
power when active (during active picture time) and when idle
(during horizontal and vertical sync periods). This can result in
a measurable change in the voltage supplied to the analog supply
regulator, which can in turn produce changes in the regulated
–28–
REV. A
AD9888
analog supply voltage. This can be mitigated by regulating the
analog supply, or at least PVd, from a different, cleaner, power
source (for example, from a 12 V supply).
Outputs (Both Data and Clocks)
It is also recommended to use a single ground plane for the
entire board. Experience has repeatedly shown that the noise
performance is the same or better with a single ground plane.
Using multiple ground planes can be detrimental because each
separate ground plane is smaller, and long ground loops can result.
In some cases, using separate ground planes is unavoidable. For
those cases, it is recommended to at least place a single ground
plane under the AD9888. The location of the split should be at
the receiver of the digital outputs. For this case it is even more
important to place components wisely because the current loops
will be much longer (current takes the path of least resistance).
An example of a current loop: power plane => AD9888 =>
digital output trace => digital data receiver => digital ground
plane => analog ground plane.
PLL
Shorter traces reduce the possibility of reflections.
Adding a series resistor of value 50 Ω–200 Ω can suppress
reflections, reduce EMI, and reduce the current spikes inside
the AD9888. If series resistors are used, place them as close to
the AD9888 pins as possible (although try not to add vias or extra
length to the output trace in order to get the resistors closer).
If possible, limit the capacitance that each of the digital outputs
drives to less than 10 pF. This can easily be accomplished by
keeping traces short and by connecting the outputs to only one
device. Loading the outputs with excessive capacitance will
increase the current transients inside of the AD9888 creating
more digital noise on its power supplies.
Digital Inputs
The digital inputs on the AD9888 were designed to work with
3.3 V signals, but are tolerant of 5.0 V signals. So, no extra
components need to be added if using 5.0 V logic.
Place the PLL loop filter components as close to the FILT pin
as possible.
Do not place any digital or other high-frequency traces near these
components.
Use the values suggested in the data sheet with 10% tolerances
or less.
Try to minimize the trace length that the digital outputs have to
drive. Longer traces have higher capacitance, requiring more
current and causing more internal digital noise.
Any noise that gets onto the Hsync input trace will add jitter to
the system. Therefore, minimize the trace length and do not run
any digital or other high-frequency traces near it.
Voltage Reference
Bypass with a 0.1 µF capacitor. Place as close to the AD9888
pin as possible. Make the ground connection as short as possible.
REV. A
–29–
AD9888
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
128-Lead Plastic Quad Flatpack (MQFP)
(S-128A)
0.685 (17.40)
0.677 (17.20)
0.669 (17.00)
0.555 (14.10)
0.551 (14.00)
0.547 (13.90)
0.134 (3.40)
MAX
0.041 (1.03)
0.035 (0.88)
0.031 (0.78)
128
1
103
102
SEATING
PLANE
0.791 (20.10)
0.787 (20.00)
0.783 (19.90)
TOP VIEW
(PINS DOWN)
0.921 (23.40)
0.913 (23.20)
0.906 (23.00)
0.003 (0.08)
MAX
0.010 (0.25)
MIN
38
39
0.110 (2.80)
0.106 (2.70)
0.102 (2.60)
65
64
0.020 (0.50)
BSC*
0.011 (0.27)
0.009 (0.22)
0.007 (0.17)
* THE ACTUAL POSITION OF EACH LEAD IS WITHIN 0.00315 (0.08) FROM ITS IDEAL
POSITION WHEN MEASURED IN THE LATERAL DIRECTION. CENTER FIGURES ARE
TYPICAL UNLESS OTHERWISE NOTED.
THE CONTROLLING DIMENSIONS ARE IN MM.
–30–
REV. A
AD9888
Revision History
Location
Page
Data Sheet changed from REV. 0 to REV. A.
Change to TITLE—PART NAME . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Change to PIN FUNCTION DETAIL, CKINV section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Change to Figure 13 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Change to Figure 14 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Change to Figure 15 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Change to Figure 16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Change to Figure 17 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Change to Figure 18 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Change to Figure 21 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Change to Figure 22 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
REV. A
–31–
–32–
PRINTED IN U.S.A.
C02442–0–2/02(A)