廖 R 19 ， 51 8 71 44 QQ : CAT9883C 深 圳 市 金 合 讯 科 技 有 限 公 司 ， Te l: 18 66 4 34 1 58 5 150MSPS Triple 8-bit Video Analog-to-Digital Data Converter CAT9883C adjustment for the sake of color balancing. FEATURES 0.5 V to 1.0 V Analog Input Range Ultra Wide Range Conversion Rate (480i~1080P) Adjustable Analog Input Bandwidth 4:2:2 Output Format Mode Digital Output Tri-State 3.3 V Power Supply Full Sync Processing Midscale Clamping Power-Down Mode Max. Power Dissipation under 800mW @ SXGA The CAT9883C also offers full sync processing for composite sync and sync-on-green applications. Clamp and COAST signals are generated internally or may be provided by the user through Clamp and COAST pin. 廖 R RAIN 71 44 51 8 19 ， The CAT9883C is fabricated in 0.35um mixed-mode CMOS process and available in 80-lead LQFP package. OFFSET GAIN CONTROL (1280x1024x75Hz) Automatic Gain Balance Built-In Analog AGC (iGOTM) Built-In smart de-macrovision Green Package (Optional) HSYNC 34 1 COAST CLAMP 66 4 18 SCL SDA 8 BLUE[7:0] OFFSET GAIN CONTROL MIDSCV DTACK SYNC PROCESSING & CLOCK GENERATION HSOUT VSOUT SOGOUT FILT Applications 8 GREEN[7:0] OFFSET GAIN CONTROL A/D CLAMP 58 5 BAIN Automatic Offset Calibration RED[7:0] A/D CLAMP QQ : GAIN 8 A/D CLAMP SERIAL REGISTER & POWER MANAGEMENT REF REF BYPASS LCD Monitors and TV Projectors Rear Projection TV Plasma Display Panels Digital TV Set-Top Box Figure 1. CAT9883C Functional Block Diagram 讯 科 技 有 限 公 司 ， Te RGB/YUV Signal Conversion Processing l: A0 GENERAL DESCRIPTION 圳 市 金 合 A top-notch video analog front-end, the CAT9883C converts RGB or YUV triple analog video inputs into 8-bit digital outputs. Specifically, it works to convert analog inputs to digital outputs at up to 8 bits/150MSPS, which means it supports 1080P video format out of the box. 深 The CAT9883C integrates three ADCs with programmable gain control, PLL, clamp control and offset cancellation. The robust PLL design, which delivers high precision and low jitter, generates pixel clocks from 12MHz to 150MHz. It also supports full sync processing for composite sync and sync-on-green graphic applications. Equipped with auto-calibration function for ADC inter-channel offset and gain mismatch, the CAT9883C is free of any external The CAT logo is a registered trademark of Chip Advanced Technology 2007 Chip Advanced Technology Inc. – All Right Reserved. Aug-2007 Rev:1.0 2/23 CAT9883C Analog Interface (VD = 3.3 V, VDD = 3.3 V, ADC Clock = Maximum Conversion Rate, unless otherwise noted.) Full Full Full Full Full Full 25°C Full Full Full Full 25°C 司 公 Full Full Full VD Supply Voltage VDD Supply Voltage PVD Supply Voltage ID Supply Current (VD) 2 IDD Supply Current (VDD) IPVD Supply Current (PVD) Total Power Dissipation Power-Down Supply Current Power-Down Dissipation 技 有 Full Full Full 25°C 25°C 25°C Full Full Full Signal-to-Noise Ratio (SNR) (Without Harmonics) Crosstalk 25°C Full Full 圳 市 金 合 讯 科 限 Output Voltage, High (VO H ) Output Voltage, Low (VOL) Duty Cycle DATACK Output Coding θJC Junction-to-Case Thermal Resistance θJA Junction-to-Ambient Thermal Resistance 51 8 Unit Bits 71 44 LSB LSB 1 V p-p V p-p µA 1.28 0.5 V ppm/°C 10 +2.0 110 10 0.8 –1.0 +1.0 ， Input Voltage, High (VI H ) Input Voltage, Low (VI L ) Input Current, High (II H ) Input Current, Low (II L ) Input Capacitance 0.5 QQ : Full Full 58 5 Output Voltage Temperature Coefficient VI VI 1.0 IV REFERENCE OUTPUT VI 1.16 1.22 V ±50 SWITCHING PERFORMANCE VI 150 IV IV –0.5 IV 15 VI 150 IV 1 IV 400 DIGITAL INPUTS VI 2.5 VI V V V 3 DIGITAL OUTPUTS VI Vdd– 0.1 VI IV 45 50 Binary POWER SUPPLY IV 3.15 3.3 IV 2.5 3.3 IV 3.15 3.3 V TBD V TBD V TBD VI TBD VI TBD VI TBD DYNAMIC PERFORMANCE V 43 V 42 V 55 THERMAL CHARACTERISTICS 34 1 Full Full 25°C ±0.5 ±1.25 ±0.5 ±2.0 Guaranteed 66 4 Input Voltage Range Minimum Maximum Input Bias Current DC ACCURACY I I VI ANALOG INPUT 18 25°C 25°C Full CAT9883C-150 Typ Max 8 Min l: Differential Nonlinearity Integral Nonlinearity No Missing Codes Maximum Conversion Rate Minimum Conversion Rate Clock to Data Skew HSYNC Input Frequency Maximum PLL Clock Rate Minimum PLL Clock Rate PLL Jitter 深 Test Level Temp Te Parameter RESOLUTION 19 ， Table 1. Electrical Characteristics 0.1 55 3.6 3.6 3.6 廖 R SPECIFICATIONS MSPS MSPS ns kHz MHz MHz ps p-p V V µA µA pF V V % V V V mA mA mA mW mA mW dB dB dBc V 16 °C/W V 35 °C/W CAT9883C NOTES 2 1280x1024 @ 75Hz, delay triggered 1uS. Integrated 1000 cycles. DATACK Load = 15 pF, Data Load = 5 pF. 廖 R 1 EXPLANATION OF TEST LEVELS 18 *Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions outside of those indicated in the operation sections of this specification is not implied. Exposure to absolute maximum ratings for extended periods may affect device reliability. 58 5 V. VI. 71 44 III. IV. 5 V to 0.0 V 20 mA 0°C to +70°C –65°C to +150°C 150°C 150°C 2000 V 100% production tested. 100% production tested at 25°C and sample teste d at specified temperatures. Sample tested only. Parameter is guaranteed by design and characterization testing. Parameter is a typical value only. 100% production tested at 25°C; guaranteed by design and characterization testing 34 1 Digital Inputs Digital Output Current Operating Temperature Storage Temperature Maximum Junction Temperature Maximum Case Temperature ESD Human Body Mode I. II. QQ : 3.6 V 3.6 V VD to 0.0 V VD to 0.0 V 66 4 VD VDD Analog Inputs VREF IN 51 8 ABSOLUTE MAXIMUM RATINGS* 19 ， *Specifications subject to change without notice 深 圳 市 金 合 讯 科 技 有 限 公 司 ， Te l: WARNING: CAT9883C is an ESD sensitive device. Though it has protection circuit, however, it may be damaged by much higher discharged voltage. To prevent any possible damage of performance and reliability, please handle it with care and make sure of your environment to meet regulations to avoid such ESD damage. The CAT logo is a registered trademark of Chip Advanced Technology 2007 Chip Advanced Technology Inc. – All Right Reserved. Aug-2007 Rev:1.0 4/23 CAT9883C 廖 R 19 ， VD GND GND SOGOUT VSOUT HSOUT GND DATACK VDD RED<7> RED<5> RED<6> RED<4> RED<3> RED<1> RED<2> RED<0> VDD VDD GND Pin Configuration 60 GND 59 VD 3 58 REF BYPASS GREEN <5> 4 57 SDA GREEN <4> 5 56 SCL GREEN <3> 6 55 A0 GREEN <2> 7 54 RAIN GREEN <1> 8 53 GND GREEN <0> 9 52 VD VD GREEN <7> 2 GREEN <6> VDD 11 51 48 QQ : 10 CAT9883C GND PIN 1 IDENTIFIER 71 44 1 14 47 GND BLUE <4> 15 46 BLUE <3> 16 45 VD VD BLUE <2> 17 44 GND BLUE <1> 18 43 BLUE <0> 19 42 BAIN VD 41 GND BLUE <6> 13 BLUE <5> 49 20 66 4 GND 50 58 5 12 34 1 BLUE <7> 51 8 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 GND GND SOGIN GAIN GND VD CLAMP MIDSCV GND PVD PVD FILT GND VSYNC 18 HSYNC COAST GND PVD PVD GND GND VDD VDD GND 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 l: Figure 2. CAT9883C Pin Configuration Table 2. Complete Pinout List Function Te Mnemonic VDD Output Power Supply 3.3 V PVD GND PLL Power Supply Ground 3.3 V 0V SDA SCL A0 Serial Port Data I/O Serial Port Data Clock (100 kHz Maximum) Serial Port Address Input 1 3.3 V CMOS 3.3 V CMOS 3.3 V CMOS 司 ， 0.0 V to 1.0 V 0.0 V to 1.0 V 0.0 V to 1.0 V 3.3 V CMOS 3.3 V CMOS 0.0 V to 1.0 V 3.3 V CMOS 3.3 V CMOS 3.3 V CMOS 3.3 V CMOS 3.3 V CMOS 3.3 V CMOS 3.3 V CMOS 3.3 V CMOS 3.3 V CMOS 1.25 V 技 有 合 讯 科 Outputs 市 金 References 深 圳 Power Supply Control Value Analog Input for Converter R Analog Input for Converter G Analog Input for Converter B Horizontal SYNC Input Vertical SYNC Input Input for Sync-on-Green Clamp Input (External CLAMP Signal) PLL COAST Signal Input Outputs of Converter Red, Bit 7 is the MSB Outputs of Converter Green, Bit 7 is the MSB Outputs of Converter Blue, Bit 7 is the MSB Data Output Clock HSYNC Output (Phase-Aligned with DATACK) VSYNC Output (Phase-Aligned with DATACK) Sync-on-Green Slicer Output Internal Reference Bypass Internal Midscale Voltage Bypass Connection for External Filter Components for Internal PLL Analog Power Supply 限 RAIN GAIN BAIN HSYNC VSYNC SOGIN CLAMP COAST Red [7:0] Green [7:0] Blue [7:0] DATACK HSOUT VSOUT SOGOUT REF BYPASS MIDSCV FILT VD 公 Pin Type Inputs 3.3 V Pin No. 54 48 43 30 31 49 38 29 70–77 2–9 12–19 67 66 64 65 58 37 33 39, 42, 45, 46, 51, 52, 59, 62 11, 22, 23, 69, 78, 79 26, 27, 34, 35 1, 10, 20, 21, 24, 25, 28, 32, 36, 40, 41, 44, 47, 50, 53, 60, 61, 63, 68, 80 57 56 55 CAT9883C PIN FUNCTION DESCRIPTIONS 廖 R 19 ， REFERENCES 34 1 58 5 QQ : 71 44 51 8 REF BYPASS: Internal Reference BYPASS. Bypass for the internal 1.22 V band gap reference. It should be connected to ground through a 0.1 µF capacitor. The absolute accuracy of this reference is ±4%, and the temperature coefficient is ±50 ppm, which is adequate for most CAT9883C applications. If higher accuracy is required, an external reference may be employed instead. MIDSCV: Midscale Voltage Reference BYPASS. Bypass for the internal midscale voltage reference. It should be connected to ground through a 0.1 µF capacitor. The exact voltage varies with the gain setting of the Blue channel. FILT: External Filter Connection. For proper operation, the pixel clock generator PLL requires an external filter. Connect the filter shown in Figure 6 to this pin. For optimal performance, minimize noise and parasitics on this node. OUTPUTS HSOUT: Horizontal Sync Output. A reconstructed and phase-aligned version of the Hsync input. Both the polarity and duration of this output can be programmed via serial bus registers. By maintaining alignment with DATACK and Data, data timing with respect to horizontal sync can always be determined. VSOUT: Vertical Sync Output. A reconstructed and phase-aligned version of the video Vsync. The polarity of this output can be controlled via a serial bus bit. The placement and duration in all modes is set by the graphics transmitter. SOGOUT: Sync-On-Green Slicer Output. This pin outputs either the signal from the Sync-on-Green slicer comparator or an unprocessed but delayed version of the Hsync input. (Note: Besides slicing off SOG, the output from this pin gets no other additional processing on the CAT9883C. Vsync separation is performed via the sync separator.) 深 圳 市 金 合 讯 科 技 有 限 公 司 ， Te l: 18 RAIN: Analog Input for Red Channel GAIN: Analog Input for Green Channel BAIN: Analog Input for Blue Channel High impedance inputs that accept the Red, Green, and Blue channel graphics signals, respectively. (The three channels are identical, and can be used for any colors, but colors are assigned for convenient reference.) They accommodate input signals ranging from 0.5 V to 1.0 V full scale. Signals should be ac-coupled to these pins to support clamp operation. HSYNC: Horizontal Sync Input. This input receives a logic signal that establishes the horizontal timing reference and provides the frequency reference for pixel clock generation. The logic sense of this pin is controlled by serial register 0EH Bit 6 (Hsync Polarity). Only the leading edge of Hsync is active; the trailing edge is ignored. When Hsync Polarity = 0, the falling edge of Hsync is used. When Hsync Polarity = 1, the rising edge is active. The input includes a Schmitt trigger for noise immunity, with a nominal input threshold of 1.5 V. VSYNC: Vertical Sync Input. This is the input for vertical sync. SOGIN: Sync-on-Green Input. This input is provided to assist with processing signals with embedded sync, typically on the Green channel. The pin is connected to a high speed comparator with an internally generated threshold. The threshold level can be programmed in 10 mV steps to any voltage between 10 mV and 330 mV above the negative peak of the input signal. The default voltage threshold is 150 mV. When connected to an ac-coupled graphics signal with embedded sync, it will produce a noninverting digital output on SOGOUT. (This is usually a composite sync signal, containing both vertical and horizontal sync information that must be separated before passing the horizontal sync signal to Hsync.) When not used, this input should be left unconnected. For more details on this function and how it should be configured, refer to the Sync-on-Green section. CLAMP: External Clamp Input. This logic input may be used to define the time during which the input signal is clamped to ground. It should be exercised when the reference dc level is known to be present on the analog input channels, typically during the back porch of the graphics signal. The CLAMP pin is enabled by setting control bit Clamp Function to 1, (register 0FH, Bit 7, default is 0). When disabled, this pin is ignored and the clamp timing is determined internally by counting a delay and duration from the trailing edge of the Hsync input. The logic sense of this pin is controlled by Clamp Polarity register 0FH, Bit 6. When not used, this pin must be grounded and Clamp Function programmed to 0. COAST:Clock Generator Coast Input (Optional). This input may be used to cause the pixel clock generator to stop synchronizing with Hsync and continue producing a clock at its current frequency and phase. This is useful when processing signals from sources that fail to produce horizontal sync pulses during the vertical interval. The COAST signal is generally not required for PC-generated signals. The logic sense of this pin is controlled by Coast Polarity (register 0FH, Bit 3). When not used, this pin may be grounded and Coast Polarity programmed to 1, or tied HIGH (to VD through a 10 k~ resistor) and Coast Polarity programmed to 0. Coast Polarity defaults to 1 at power-up. 66 4 INPUTS The CAT logo is a registered trademark of Chip Advanced Technology 2007 Chip Advanced Technology Inc. – All Right Reserved. DATA OUTPUTS RED: Data Output, Red Channel. GREEN: Data Output, Green Channel. BLUE: Data Output, Blue Channel. The main data outputs. Bit 7 is the MSB. The delay from pixel sampling time to output is fixed. When the sampling time is changed by adjusting the PHASE register, the output timing is shifted as well. The DATACK and HSOUT outputs are also moved, so the timing relationship among the signals is maintained. For exact timing information, refer to Figures 7, and 8. DATA CLOCK OUTPUTS DATACK: Data Output Clock. This is the main clock output signal used to strobe the output data and HSOUT into external logic. It is produced by the Aug-2007 Rev:1.0 6/23 CAT9883C 廖 R 19 ， 51 8 SERIAL PORT (2-Wire) SDA: Serial Port Data I/O. SCL: Serial Port Data Clock. A0: Serial Port Address Input 1. For a full description of the 2-wire serial register and how it works, refer to the 2-Wire Serial Control Port section. 深 圳 市 金 合 讯 科 技 有 限 公 司 ， Te l: 18 66 4 34 1 58 5 VD: Main Power Supply. These pins supply power to the main elements of the circuit. They should be filtered and as quiet as possible. VDD: Digital Output Power Supply. A large number of output pins (up to 25) switching at high speed (up to 110 MHz) generates a lot of power supply transients (noise). These supply pins are identified separately from the VD pins so special care can be taken to minimize output noise transferred into the sensitive analog circuitry. If the CAT9883C is interfacing with lower voltage logic, VDD may be connected to a lower supply voltage (as low as 2.5 V) for compatibility. 71 44 POWER SUPPLY PVD: Clock Generator Power Supply. The most sensitive portion of the CAT9883C is the clock generation circuitry. These pins provide power to the clock PLL and help the user design for optimal performance. The designer should provide quiet, noise-free power to these pins. GND: Ground. The ground return for all circuitry on-chip. It is recommended that the CAT9883C be assembled on a single solid ground plane, with careful attention given to ground current paths. QQ : internal clock generator and is synchronous with the internal pixel sampling clock. When the sampling time is changed by adjusting the PHASE register, the output timing is shifted as well. The Data, DATACK, and HSOUT outputs are all moved, so the timing relationship among the signals is maintained. The CAT logo is a registered trademark of Chip Advanced Technology 2007 Chip Advanced Technology Inc. – All Right Reserved. Aug-2007 Rev:1.0 7/23 CAT9883C General Description 75Ω 51 8 71 44 Hsync, Vsync Inputs QQ : The interface also takes a horizontal sync signal, which is used to generate the pixel clock and clamp timing. This can be either a sync signal directly from the graphics source, or a preprocessed TTL or CMOS level signal. The Hsync input includes a Schmitt trigger buffer for immunity to noise and signals with long rise times. In typical PC based graphic systems, the sync signals are simply TTL-level drivers feeding unshielded wires in the monitor cable. As such, no termination is required. 34 1 The CAT9883C includes all necessary input buffering, signal dc restoration (clamping), offset and gain (brightness and contrast) adjustment, pixel clock generation, sampling phase control, and output data formatting. All controls are programmable via a 2-wire serial interface. Full integration of these sensitive analog functions makes system design straightforward and less sensitive to the physical and electrical environment. Figure 3. Analog Input Interface Circuit 58 5 The CAT9883C is a fully integrated solution for capturing analog RGB signals and digitizing them for display on flat panel monitors or projectors. The circuit is ideal for providing a computer interface for high-resolution monitors or as the front end to high performance video scan converters. Implemented in a high performance CMOS process, the interface can capture signals with pixel rates up to 150 MHz. RAIN GAIN BAIN 廖 R RGB INPUT 19 ， 47nF Design Guide Digital Inputs The serial control port is designed for 3.3V logic. If there are 5V drivers on the bus, these pins should be protected with 150 Ω series resistors placed between the pull-up resistors and the input pins. 18 All digital inputs on the CAT9883C operate to 3.3 V CMOS levels. However, all digital inputs are 5 V tolerant. Applying 5 V to them will not cause any damage. 66 4 Serial Control Port Te l: Input Signal Handling 限 公 司 ， The CAT9883C has three high impedance analog input pins for the Red, Green, and Blue channels. They will accommodate signals ranging from 0.5 V to 1.0 V p-p. Signals are typically brought onto the interface board via a DVI-I connector, a 15-pin D connector, BNC connectors, or RCA connectors. 讯 科 技 有 As a sample-data system without input gain amplifier, the ultrawide bandwidth inputs of the CAT9883C (300 MHz) can sample incoming video signals without gain loss and thus provide very sharp image outputs. 深 圳 市 金 合 In many systems, however, there are mismatches, reflections, and noise, which can result in excessive ringing and distortion of the input waveform. This makes it more difficult to establish a sampling phase that provides good image quality. It has been shown that a simple low-pass circuit like a small inductor in series with the input is effective to provide a high quality signal over a wider range of conditions. Output Signal Handling The digital outputs are designed and specified to operate from a 3.3 V power supply (VDD). They can also work with a VDD as low as 2.5 V for compatibility with other 2.5 V logic. Clamping RGB Clamping To properly digitize the incoming signal, the dc offset of the input must be adjusted to fit the range of the on-board A/D converters. The key to clamping is to identify a portion (time) of the signal when the graphic system is known to be producing black. An offset is then introduced which results in the A/D converters producing a black output (code 00h) when the known black input is present. The offset then remains in place when other signal levels are processed, and the entire signal is shifted to eliminate offset errors. In most PC graphics systems, black is transmitted between active video lines. In systems with embedded sync, a blacker-than-black signal (Hsync) is produced briefly to signal the CRT that it is time to begin a retrace. For obvious The CAT logo is a registered trademark of Chip Advanced Technology 2007 Chip Advanced Technology Inc. – All Right Reserved. Aug-2007 Rev:1.0 8/23 CAT9883C ranging from 0.5 V to 1.0 V full scale. The full-scale range is set in three 8-bit registers (Red Gain, Green Gain, and Blue Gain). Larger gain setting maps output code to larger input range. The clamp timing can be established by simply exercising the CLAMP pin at the appropriate time (with External Clamp = 1). The polarity of this signal is set by the Clamp Polarity bit. The offset control shifts the entire input range. Three 7-bit registers (Red Offset, Green Offset, Blue Offset) provide independent settings for each channel. The offset controls provide a ±63 LSB adjustment range. This range is connected with the gain setting, so 1 offset code maps to 1 LSB regardless how much the gain code is. 19 ， 51 8 71 44 QQ : 58 5 OFFSET = 127 OFFSET = 0 l: 18 0.5 OFFSET = 127 OFFSET = 64 0 Te 司 ， YUV Clamping OFFSET = 0 0 255 Gain Figure 4. Gain and Offset Control 技 有 限 公 YUV graphic signals are slightly different from RGB signals in that the dc reference level (black level in RGB signals) can be at the midpoint of the graphics signal rather than at the bottom. For these signals, it can be necessary to clamp to the midscale range of the A/D converter range (80H) rather than at the bottom of the A/D converter range (00H). OFFSET = 64 34 1 1.0 Input Range Clamping is accomplished by placing an appropriate charge on the external input coupling capacitor. The value of this capacitor affects the performance of the clamp. If it is too small, there will be a significant amplitude change during a horizontal line time (between clamping intervals). If the capacitor is too large, then it will take excessively long for the clamp to recover from a large change in incoming signal offset. Figure 4 illustrates the interaction of gain and offset controls. The magnitude of an LSB in offset adjustment is proportional to the full-scale range, so changing the full-scale range also changes the offset. The change is minimal if the offset setting is near midscale. When changing the offset, the full-scale range is not affected, but the full-scale level is shifted by the same amount as the zero scale level. 66 4 A simpler method of clamp timing employs the CAT9883C internal clamp timing generator. The Clamp Placement register is programmed with the number of pixel times that should pass after the trailing edge of HSYNC before clamping starts. A second register (Clamp Duration) sets the duration of the clamp. These are both 8-bit values, providing considerable flexibility in clamp generation. The clamp timing is referenced to the trailing edge of Hsync because, though Hsync duration can vary widely, the back porch (black reference) always follows Hsync. A good starting point for establishing clamping is to set the clamp placement to 09H (providing 9 pixel periods for the graphics signal to stabilize after sync) and set the clamp duration to 14H (giving the clamp 20 pixel periods to reestablish the black reference). 廖 R reasons, it is important to avoid clamping on the tip of Hsync. Fortunately, there is virtually always a period following Hsync, called the back porch, where a good black reference is provided. This is the time when clamping should be done. 深 圳 市 金 合 讯 科 Clamping to midscale rather than to ground can be accomplished by setting the clamp select bits in the serial bus register. Each of the three converters has its own selection bit so that they can be clamped to either midscale or ground independently. These bits are located in register 10H and are Bits 0~2. The midscale reference voltage that each A/D converter clamps to is provided on the MIDSCV pin, (Pin 37). This pin should be bypassed to ground with a 0.1µF capacitor, (even if midscale clamping is not required). Sync-on-Green The Sync-on-Green input operates in two steps. First, it sets a baseline clamp level off of the incoming video signal with a negative peak detector. Second, it sets the sync trigger level to a programmable level (typically 150 mV) above the negative peak. The Sync-on-Green input must be ac-coupled to the Green analog input through its own capacitor, as shown in Figure 5. The value of the capacitor must be 1nF±20%. If Sync-on-Green is not used, this connection is not required. Note that the Sync-on-Green signal is always negative polarity. Gain and Offset Control The CAT9883C can accommodate input signals with inputs The CAT logo is a registered trademark of Chip Advanced Technology 2007 Chip Advanced Technology Inc. – All Right Reserved. Aug-2007 Rev:1.0 9/23 CAT9883C RAIN 3. The 3-Bit Charge Pump Current Register. This register allows the current that drives the low-pass loop filter to be varied. The possible current values are listed in Table IV. GAIN 4. The 5-Bit Phase Adjust Register. The phase of the generated sampling clock may be shifted to locate an optimum sampling point within a clock cycle. The Phase Adjust Register provides 32 phase-shift steps of 11.25 degrees each. The Hsync signal with an identical phase shift is available through the HSOUT pin. 47nF 廖 R 47nF BAIN 19 ， 47nF SOG 51 8 1nF The COAST pin is used to allow the PLL to continue to run at the same frequency, in the absence of the incoming Hsync signal or during disturbances in Hsync (such as equalization pulses). This may be used during the vertical sync period, or any other time that the Hsync signal is unavailable. The polarity of the COAST signal may be set through the Coast Polarity Register. Also, the polarity of the Hsync signal may be set through the Hsync Polarity Register. If not using automatic polarity detection, the Hsync and COAST Polarity bits should be set to match the respective polarities of the input signals. 18 66 4 PVD 58 5 The PLL characteristics are determined by the loop filter design, by the PLL Charge Pump Current, and by the VCO range setting. The loop filter design is illustrated in Figure 6. Recommended settings of VCO range and charge pump current for VESA standard display modes and TV modes are listed in Table II. 34 1 Clock Generation QQ : 71 44 Figure 5. Typical Clamp Configuration C1 0.082uF l: C2 0.0082uF ， 公 司 FILT (PIN #33) Te R1 2.7KΩ 技 有 限 Figure 6. PLL Loop Filter Four programmable registers are provided to optimize the The 12-Bit Divisor Register. The input Hsync frequencies range from 15 kHz to 110 kHz. The PLL multiplies the frequency of the Hsync signal, producing pixel clock frequencies in the range of 12 MHz to 150 MHz. The Divisor Register controls the exact multiplication factor. This register may be set to any value between 221 and 4095. (The divide ratio that is actually used is the programmed divide ratio plus one.) 深 圳 市 金 合 1. 讯 科 performance of the PLL. These registers are: 2. The 2-Bit VCO Range Register. To improve the noise performance of the CAT9883C, the VCO operating frequency range is divided into three overlapping regions. The VCO Range Register sets this operating range. The frequency ranges for the lowest and highest regions are shown in Table III. The CAT logo is a registered trademark of Chip Advanced Technology 2007 Chip Advanced Technology Inc. – All Right Reserved. Aug-2007 Rev:1.0 10/23 CAT9883C Table 3. Recommended VCO Range and Charge Pump Current Settings for Standard Display Formats Standard Resolution Refresh Rate Horizontal Frequency Pixel Rate CAT9883C VCORNGE Current 25.175 MHz 31.500 MHz 31.500 MHz 36.000 MHz 36.000 MHz 40.000 MHz 50.000 MHz 49.500 MHz 56.250 MHz 65.000 MHz 75.000 MHz 78.750 MHz 85.500 MHz 94.500 MHz 108.000 MHz 135.000 MHz 00 00 00 01 01 01 01 01 01 10 10 10 10 10 10 11 110 110 110 100 100 100 101 101 101 101 100 100 101 101 110 110 1024 × 768 SXGA 1280 × 1024 15.75 kHz 31.47 kHz 45.00 kHz 33.75 kHz 67.5 kHz 010 110 100 100 110 司 ， Pixel Clock Range (MHz) 12 - 32 32 - 64 64 - 110 110 - 150 技 有 限 公 PV0 0 1 0 1 00 00 10 10 11 Te Table 4. VCO Frequency Range PV1 0 0 1 1 13.50 MHz 27.00 MHz 74.25 MHz 74.25 MHz 148.5 MHz 66 4 60 Hz 60 Hz 60 Hz 60 Hz 60 Hz 18 640x480 640x480 1280x720 1920x1080 1920x1080 l: 480i 480P 720P 1080i 1080P 34 1 TV Mode 廖 R XGA 19 ， 800 × 600 31.5 kHz 37.7 kHz 37.5 kHz 43.3 kHz 35.1 kHz 37.9 kHz 48.1 kHz 46.9 kHz 53.7 kHz 48.4 kHz 56.5 kHz 60.0 kHz 64.0 kHz 68.3 kHz 64.0 kHz 80.0 kHz 51 8 SVGA 60 Hz 72 Hz 75 Hz 85 Hz 56 Hz 60 Hz 72 Hz 75 Hz 85 Hz 60 Hz 70 Hz 75 Hz 80 Hz 85 Hz 60 Hz 75 Hz 71 44 640 × 480 58 5 VGA QQ : PC Mode Table 5. Charge Pump Current/Control Bits 讯 科 Ip1 0 0 1 1 0 0 1 1 Ip0 0 1 0 1 0 1 0 1 Current(μ μA) 50 100 150 250 350 500 750 1500 深 圳 市 金 合 Ip2 0 0 0 0 1 1 1 1 Power Management The CAT9883C uses the activity detect circuits, the active interface bits in the serial bus, the active interface override bits, and the power-down bit to determine the correct power state. There are three power states, full-power, seek mode, and The CAT logo is a registered trademark of Chip Advanced Technology 2007 Chip Advanced Technology Inc. – All Right Reserved. power-down. Table IV summarizes how the CAT9883C determines what power mode to be in and which circuitry is powered on/off in each of these modes. The power-down command has priority over the automatic circuitry. Aug-2007 Rev:1.0 11/23 CAT9883C Table 6. Power-Down Mode Descriptions other systems, such as those that employ Composite Sync (Csync) signals or embedded Sync-on- Green (SOG), Hsync includes equalization pulses or other distortions during Vsync. To avoid upsetting the clock generator during Vsync, it is important to ignore these distortions. If the pixel clock PLL sees extraneous pulses, it will attempt to lock to this new frequency, and will have changed frequency by the end of the Vsync period. It will then take a few lines of correct Hsync timing to recover at the beginning of a new frame, resulting in a “tearing” of the image at the top of the display. Reg of Sync Active Circuitry 1 PWRDN Detect Full-Power 1 1 Whole chip Serial Bus, Sync Activity Seek Mode 1 0 Detect, S0G, BandGap Reference Serial Bus, Sync Activity Power-Down 0 X Detect, S0G, BandGap Reference 51 8 19 ， 廖 R Mode NOTES 1 Power-down is controlled via Bit1 in serial bus register 0FH 2 Sync detect is determined by OR-ing Bits 7, 4, and 1 in serial bus register 14H 71 44 The COAST input is provided to eliminate this problem. It is an asynchronous input that disables the PLL input and allows the clock to free-run at its then-current frequency. The PLL can free-run for several lines without significant frequency drift. Sync Slicer Timing The purpose of the sync slicer is to extract the sync signal from Sync-on-Green. The sync signal is extracted from the Green channel in a two-step process. First, the SOG input is clamped to its negative peak (typically 0.3 V below the black level). Next, the signal goes to a comparator with an adjustable trigger level, nominally 0.15 V above the clamped level. The “sliced” sync is typically a composite sync signal containing both Hsync and Vsync. QQ : The following timing diagrams show the operation of the CAT9883C. 58 5 The output data clock signal is created so that its rising edge always occurs between data transitions, and can be used to latch the output data externally. 66 4 34 1 There is a pipeline in the CAT9883C, which must be flushed before valid data becomes available. This means four data sets are presented before valid data is available. Sync Separator A sync separator extracts the Vsync signal from a composite sync signal. It does this through a low-pass filter-like or integrator-like operation. It works on the fact that the Vsync signal stays active for a much longer time than the Hsync signal, so it rejects any signal shorter than a threshold value, which is somewhere between an Hsync pulsewidth and a Vsync pulsewidth. 18 Hsync Timing Te l: Horizontal Sync (Hsync) is processed in the CAT9883C to eliminate ambiguity in the timing of the leading edge with respect to the phase-delayed pixel clock and data. 技 有 限 公 司 ， The Hsync input is used as a reference to generate the pixel sampling clock. The sampling phase can be adjusted, with respect to Hsync, through a full 360° in 32 steps via the Ph ase Adjust Register (to optimize the pixel sampling time). Display systems use Hsync to align memory and display write cycles, so it is important to have a stable timing relationship between Hsync output (HSOUT) and data clock (DATACK). 圳 市 金 合 讯 科 Three things happen to Horizontal Sync in the CAT9883C. First, the polarity of Hsync input is determined and will thus have a known output polarity. The known output polarity can be programmed either active high or active low (register 0EH, Bit 5). Second, HSOUT is aligned with DATACK and data outputs. Third, the duration of HSOUT (in pixel clocks) is set via register 07H. HSOUT is the sync signal that should be used to drive the rest of the display system. 深 Coast Timing In most computer systems, the Hsync signal is provided continuously on a dedicated wire. In these systems, the COAST input and functions are unnecessary, and should not be used and the pin should be permanently connected to the inactive state. In some systems, however, Hsync is disturbed during the Vertical Sync period (Vsync). In some cases, Hsync pulses disappear. In The CAT logo is a registered trademark of Chip Advanced Technology 2007 Chip Advanced Technology Inc. – All Right Reserved. The sync separator on the CAT9883C is simply an 8-bit digital counter with an internal clock. It works independently of the polarity of the composite sync signal. (Polarities are determined elsewhere on the chip.) The basic idea is that the counter counts up when Hsync pulses are present. But since Hsync pulses are relatively short in width, the counter only reaches a value of N before the pulse ends. It then starts counting down eventually reaching 0 before the next Hsync pulse arrives. The specific value of N will vary for different video modes, but will always be less than 255. For example with a 1 µs width Hsync, the counter will only reach 5 (1 µs/200 ns = 5). Now, when Vsync is present on the composite sync the counter will also count up. However, since the Vsync signal is much longer, it will count to a higher number M. For most video modes, M will be at least 255. So, Vsync can be detected on the composite sync signal by detecting when the counter counts to higher than N. The specific count that triggers detection (T) can be programmed through the serial register (11H). Once Vsync has been detected, there is a similar process to detect when it goes inactive. At detection, the counter first resets to 0, then starts counting up when Vsync goes away. Similar to the previous case, it will detect the absence of Vsync when the counter reaches the threshold count (T). In this way, it will reject Aug-2007 Rev:1.0 12/23 CAT9883C Sometimes because the ground of the system board is noisy, the offset after calibration might drift to 2~4LSB. Under this situation, user can do calibration longer but only once. Details please reference our design-in quick guide. noise and/or serration pulses. Once Vsync is detected to be absent, the counter resets to 0 and begins the cycle again. Tri-State the Data Output User can set the gain and offset as wish after the calibration. That mean the system designer can adjust the color analogly to get largest dynamic range. 19 ， 廖 R CAT9883C data output disable (tri-state output) is controlled through bit 6 of register 85H. One can only tri-state the output using this bit. Power down this chip using bit 1 of 0FH will not make the data output tri-state. Input anti-aliasing filter Auto offset/color/gain calibration 51 8 To prevent from input signal path noise, CAT9883C equipped with analog anti-aliasing filter. Default cut off frequency is 300MHz. If user needs to change the cutoff frequency, please check our design-in quick guide. 71 44 CAT9883C offset/color/gain calibration can be done automatically by setting registers. If it is only offset or offset/color calibration that is needed, CAT9883C also offer the option. RG B IN P0 P1 P2 P3 P4 P5 P6 QQ : After calibration, the CAT9883C can be viewed as a pseudo-ideal ADC free of gain and offset error. P7 58 5 HSYNC 34 1 PxCK 66 4 HS 5 PIPE DELA Y 18 ADCCK DATACK D0 D1 l: D OUTA Te HSOUT D2 D3 D4 D5 D6 D7 讯 科 PxCK P1 P2 P3 P4 P5 P6 P7 限 HSYNC P0 Figure 7. 4:4:4 Mode (For RGB and YUV) 技 有 RGB IN 公 司 ， VARIABLE DURATION HS 5 PIPE DELAY 市 金 合 ADCCK 深 圳 DATACK G OUTA Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 R OUTA U0 V1 U2 V3 U4 V5 U6 V7 HSOUT VARIABLE DURATION Figure 8. 4:2:2 Mode (For YUV Only) The CAT logo is a registered trademark of Chip Advanced Technology 2007 Chip Advanced Technology Inc. – All Right Reserved. Aug-2007 Rev:1.0 13/23 CAT9883C 2-WIRE SERIAL CONTROL PORT erate a stop signal. If the master device does not acknowledge the CAT9883C during a read sequence, the CAT9883C interprets this as “end of data.” The SDA remains high so the master can generate a stop signal. Data received or transmitted on the SDA line must be stable for the duration of the positive-going SCL pulse. Data on SDA must change only when SCL is low. If SDA changes state while SCL is high, the serial interface interprets that action as a start or stop sequence. There are five components to serial bus operation: Start Signal Slave Address Byte Base Register Address Byte Data Byte to Read or Write Stop Signal 廖 R 19 ， Data is read from the control registers of the CAT9883C in a similar manner. Reading requires two data transfer operations: QQ : The base address must be written with the R/W Bit of the slave address byte low to set up a sequential read operation. Reading (the R/W Bit of the slave address byte high) begins at the previously established base address. The address of the read register auto increments after each byte is transferred. 58 5 I. II. III. IV. V. Writing data to specific control registers of the CAT9883C requires that the 8-bit address of the control register of interest be written after the slave address has been established. This control register address is the base address for subsequent write operations. The base address auto-increments by one for each byte of data written after the data byte intended for the base address. If more bytes are transferred than there are available addresses, the address will not increment and remains at its maximum value of 14H. Any base address higher than 14H will not produce an acknowledge signal. 51 8 The 2-wire serial interface comprises a clock (SCL) and a bidirectional data (SDA) pin. The analog flat panel interface acts as a slave for receiving and transmitting data over the serial interface. When the serial interface is not active, the logic levels on SCL and SDA are pulled high by external pull-up resistors. 71 44 A 2-wire serial interface control interface is provided. Up to two CAT9883C devices may be connected to the 2-wire serial interface, with each device having a unique address. To terminate a read/write sequence to the CAT9883C, a stop signal must be sent. A stop signal comprises a low-to-high transition of SDA while SCL is high. 66 4 34 1 When the serial interface is inactive (SCL and SDA are high) communications are initiated by sending a start signal. The start signal is a high-to-low transition on SDA while SCL is high. This signal alerts all slaved devices that a data transfer sequence is coming. 18 A repeated start signal occurs when the master device driving the serial interface generates a start signal without first generating a stop signal to terminate the current communication. This is used to change the mode of communication (read, write) between the slave and master without releasing the serial interface lines. 公 司 ， Te l: The first eight bits of data transferred after a start signal comprise a 7-bit slave address (the first seven bits) and a single R/W Bit (the eighth bit). The R/W Bit indicates the direction of data transfer, read from (1) or write to (0) the slave device. If the transmitted slave address matches the address of the device (set by the state of the SA1-0 input pins in Table VI, the CAT9883C acknowledges by bringing SDA low on the ninth SCL pulse. If the addresses do not match, the CAT9883C does not acknowledge. Bit 6 Bit 5 Bit 4 A6(MSB) A5 A4 1 0 0 1 0 0 Bit 3 Bit 2 Bit 1 A3 A2 A1 A0 1 1 0 0 1 1 0 1 合 讯 科 技 有 Bit 7 限 Table 7. Serial Port Addresses 市 金 Data Transfer via Serial Interface 圳 For each byte of data read or written, the MSB is the first bit of the sequence. 深 If the CAT9883C does not acknowledge the master device during a write sequence, the SDA remains high so the master can gen- The CAT logo is a registered trademark of Chip Advanced Technology 2007 Chip Advanced Technology Inc. – All Right Reserved. Serial Interface Read/Write Examples Write to one control register I. II. III. IV. V. Start Signal Slave Address Byte (R/W Bit = Low) Base Address Byte Data Byte to Base Address Stop Signal Write to four consecutive control registers I. II. III. IV. V. VI. VII. VIII. Start Signal Slave Address Byte (R/W Bit = Low) Base Address Byte Data Byte to Base Address Data Byte to (Base Address + 1) Data Byte to (Base Address + 2) Data Byte to (Base Address + 3) Stop Signal Aug-2007 Rev:1.0 14/23 I. II. III. IV. V. VI. VII. Start Signal Slave Address Byte (R/W Bit = Low) Base Address Byte Start Signal Slave Address Byte (R/W Bit = High) Data Byte from Base Address Stop Signal Slave Address Byte (R/W Bit = Low) Base Address Byte Start Signal Slave Address Byte (R/W Bit = High) Data Byte from Base Address Data Byte from (Base Address + 1) Data Byte from (Base Address + 2) Data Byte from (Base Address + 3) Stop Signal BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0 71 44 SDA 51 8 Read from four consecutive control registers ~ Start Signal ACK SCL 58 5 QQ : Fig 9. Serial Interface-Typical Byte Transfer SDA tBUFF tDSU 34 1 tDHO tSTAH 19 ， I. II. III. IV. V. VI. VII. VIII. IX. Read from one control register 廖 R CAT9883C tSTOSU 66 4 tDAL tSTASU SCL 18 tDAH Te 公 司 Unit µS µS µS µS µS µS µS µS 限 技 有 Min. Value 4.7 4.0 0.3 4.7 4.0 0.3 4.0 4.0 深 圳 市 金 合 讯 科 Parameter tBUFF tSTAH tDHO tDAL tDAH tDSU tSTASU tSTOSU ， Table 8. Serial Port Read/Write Timing l: Figure 10. Serial Port Read/Write Timing The CAT logo is a registered trademark of Chip Advanced Technology 2007 Chip Advanced Technology Inc. – All Right Reserved. Aug-2007 Rev:1.0 15/23 CAT9883C PCB Layout Design Guide C AT9883 PCB LAYOUT RECOMMENDATIONS 廖 R P o w e r P la n e Analog Interface Inputs II. Place the 75Ohm termination resistors as close to the CAT9883C chip as possible. A n a lo g G N D P la n e D ig ita l O u tp u t T ra c e D ig ita l G N D p la n e D ig ita l D a ta R e c e iv e r 19 ， Place the CAT9883C as close as possible to the video connector(s). 51 8 I. III. Use 75Ohm matched impedance traces. PLL V. I. Place the PLL loop filter components as close to the FILT pin as possible. II. It is recommended that the PLL loop filter components should be on the same layer where the chip resides. VI. Avoid running any digital traces near the analog inputs. VII. Low-pass filtering the analog inputs can sometimes help to reduce noise. This can be achieved by: Placing a 100Ohm to 120Ohm resistor between the 75Ohm termination resistor and the input coupling capacitor. 58 5 B. III. Do not place any digital or other high frequency traces near these components. IV. Use the values suggested in the data sheet with 10% tolerances or less. 34 1 Placing a series ferrite bead prior to the 75Ohm termination resistor. 66 4 A. QQ : Reduce the amount of noise that gets coupled to the inputs. 71 44 IV. It is recommended that the R, G and B signal traces from video connectors to chip inputs should be on the same layer where the chip resides. Outputs (Both Data and Clocks) Try to minimize the trace length that the digital outputs have to drive. It is recommended to bypass each group of power supply pin with a 0.1µF capacitor. II. It’s recommended to add a series resistor of value 22Ohm to 100Ohm to suppress reflections, reduce EMI, and reduce the current spikes inside the CAT9883C. II. It is also recommended that the bypass capacitor be located within about 0.5cm distance of each power pin. ， Te l: I. 司 III. Avoid placing the capacitor on the opposite side of the PC board from the CAT9883C. 限 公 IV. Do not make the power connection between the capacitor and the power pin. It is particularly important to maintain low noise and good stability of PVD (better to provide separate regulated supplies for VD and PVD). 技 有 V. I. 18 Power Supply Bypassing 讯 科 VI. It is also recommended to use a single ground plane for the entire board (at least place a single ground plane under the CAT9883C). 深 圳 市 金 合 VII. Notice the longest current loop as shown in the following graph. Shorter loop makes better performance. III. The series resistors should be place as close to the CAT9883C pins as possible. IV. Try not to add vias or extra length to the output trace in order to get the resistors closer. V. If possible, limit the capacitance that each of the digital outputs drives less than 10pF. Digital Inputs I. Minimize the Hsync/Vsync trace length and do not run any digital or other high frequency traces near it. Voltage Reference I. Bypass with a 0.1 µF capacitor. II. It is recommended that the Midscv and Ref_Bypass pin bypass capacitors should be on the same layer where the chip resides. III. Place as close to the CAT9883C pin as possible. IV. Make the ground connection as short as possible. The CAT logo is a registered trademark of Chip Advanced Technology 2007 Chip Advanced Technology Inc. – All Right Reserved. Aug-2007 Rev:1.0 16/23 CAT9883C 2-Wire Serial Register Map The CAT9883C is initialized and controlled by a set of registers, two-line serial interface port, which determine the operating modes. An external controller is employed to write and read the control registers through the employed to write and read the control registers through 廖 R the two-line serial interface port. Hex Address 00H Write and Read or Read Only RO Bits 7:0 01H* R/W 7:0 01101001 02H* R/W 7:4 1101**** 03H R/W 7:3 01****** **001*** 04H R/W 7:3 10000*** 05H R/W 7:0 10000000 06H R/W 7:0 10000000 07H R/W 7:0 00100000 08H 09H 0AH 0BH 0CH 0DH 0EH R/W R/W R/W R/W R/W R/W R/W 7:0 7:0 7:0 7:1 7:1 7:1 7:0 10000000 10000000 10000000 1000000* 1000000* 1000000* 0******* 51 8 Register Name Chip Revision Te l: 18 66 4 34 1 58 5 QQ : 71 44 Function An 8-bit register that represents the silicon revision level. Revision 0 = 0000 0000. PLL Div MSB This register is for Bits [11:4] of the PLL divider. Greater values mean the PLL operates at a faster rate. This register should be loaded first whenever a change is needed. This will give the PLL more time to lock. PLL Div LSB Bits [7:4] of this word are written to the LSBs [3:0] of the PLL divider word. Bits [7:6] VCO Range. Selects VCO frequency range. Bits [5:3] Charge Pump Current. Varies the current that drives the low-pass filter. Phase Adjust ADC Clock Phase Adjustment. Larger values mean more delay. (1 LSB = T/32) Clamp Places the Clamp signal an integer number of clock periods Placement after the trailing edge of the Hsync signal. Clamp Duration Number of clock periods that the Clamp signal is actively clamping. Hsync Output Sets the number of pixel clocks that HSOUT will remain active. Pulsewidth Controls ADC input range (contrast) of each respective Red Gain channel. Greater values give less contrast. Green Gain Blue Gain Red Offset Controls dc offset (brightness) of each respective channel. Greater values decrease brightness. Green Offset Blue Offset Sync Control Bit 7 – Hsync Polarity Override. (Logic 0 = Polarity determined by chip, Logic 1 = Polarity set by Bit 6 in register 0EH.) Bit 6 – Hsync Input Polarity. Indicates polarity of incoming Hsync signal to the PLL. (Logic 0 = Active Low, Logic 1 = Active High.) Bit 5 – Hsync Output Polarity. (Logic 0 = Logic High Sync, Logic 1 = Logic Low Sync.) Bit 4 – Active Hsync Override. If set to Logic 1, the user can select the Hsync to be used via Bit 3. If set to Logic 0, the active interface is selected via Bit 6 in register 14H. Bit 3 – Active Hsync Select. Logic 0 selects Hsync as the active sync. Logic 1 selects Sync-on-Green as the active sync. Note that the indicated Hsync will be used only if Bit 4 is set to Logic 1 or if both syncs are active. (Bits 1, 7 = Logic 1 in register 14H.) Bit 2 – Vsync Output Invert. (Logic 1 = No Invert, Logic 0 = Invert.) Bit 1 – Active Vsync Override. If set to Logic 1, the user can select the Vsync to be used via Bit 0. If set to Logic 0, the active interface is selected via Bit 3 in register 14H. ， 司 公 限 技 有 讯 科 合 *1****** **0***** ***0**** ****0*** 深 圳 市 金 Default Value 19 ， Table 9. Control Register Map *****0** ******0* The CAT logo is a registered trademark of Chip Advanced Technology 2007 Chip Advanced Technology Inc. – All Right Reserved. Aug-2007 Rev:1.0 17/23 CAT9883C R/W 7:1 10H R/W 7:3 11H R/W 7:0 12H R/W 7:0 13H R/W 7:0 14H RO 限 技 有 讯 科 合 市 金 圳 深 公 司 ， Te l: 18 66 4 34 1 58 5 QQ : 71 44 51 8 19 ， 0FH Bit 0 – Active Vsync Select. Logic 0 selects Raw Vsync as the output Vsync. Logic 1 selects Sync Separated Vsync as the output Vsync. Note that the indicated Vsync will be used only if Bit 1 is set to Logic 1 0******* Bit 7 – Clamp Function. Chooses between Hsync for Clamp signal or another external signal to be used for clamping. (Logic 0 = Hsync, Logic 1 = Clamp.) *1****** Bit 6 – Clamp Polarity. Valid only with external Clamp signal. (Logic 0 = Active High, Logic 1 Selects Active Low.) **0***** Bit 5 – Coast Select. Logic 0 selects the coast input pins to be used for the PLL coast. Logic 1 selects Vsync to be used for the PLL coast. ***0**** Bit 4 – Coast Polarity Override. (Logic 0 = Polarity determined by chip, Logic 1 = Polarity set by Bit 3 in register 0FH.) ****1*** Bit 3 – Coast Polarity. Selects polarity of external Coast signal. (Logic 0 = Active Low, Logic 1 = Active High.) *****1** Bit 2 – Seek Mode Override. (Logic 1 = Allow Low Power Mode, Logic 0 = Disallow Low Power Mode.) ****** 1* Bit 1 – PWRDN. Full Chip Power-Down, Active Low. (Logic 0 = Full Chip Power-Down, Logic 1 = Normal.) 10111 *** Sync-on-Green Sync-on-Green Threshold. Sets the voltage level of the Sync-on-Green slicer’s comparator. *****0** Threshold Bit 2 – Red Clamp Select. Logic 0 selects clamp to ground. Logic 1 selects clamp to midscale (voltage at Pin 37). ******0* Bit 1 – Green Clamp Select. Logic 0 selects clamp to ground. Logic 1 selects clamp to midscale (voltage at Pin 37). *******0 Bit 0 – Blue Clamp Select. Logic 0 selects clamp to ground. Logic 1 selects clamp to midscale (voltage at Pin 37). 00100000 Sync Separator Sync Separator Threshold. Sets how many internal 5 MHz Threshold clock periods the sync separator will count to before toggling high/low. This should be set to some number greater than the maximum Hsync or equalization pulsewidth. 00000000 Pre-Coast Pre-Coast. Sets the number of Hsync periods that Coast becomes active prior to Vsync. 00000000 Post-Coast Post-Coast. Sets the number of Hsync periods that Coast stays active following Vsync. Sync Detect Bit 7 – Hsync detect. It is set to Logic 1 if Hsync is present on the analog interface; otherwise it is set to Logic 0. Bit 6 – AHS: Active Hsync. This bit indicates which analog Hsync is being used. (Logic 0 = Hsync Input Pin, Logic 1 = Hsync from Sync-on-Green.) Bit 5 – Input Hsync Polarity Detect. (Logic 0 = Active Low, Logic 1 = Active High.) Bit 4 – Vsync Detect. It is set to Logic 1 if Vsync is present on the analog interface; otherwise it is set to Logic 0. Bit 3 – AVS: Active Vsync. This bit indicates which analog Vsync is being used. (Logic 0 = Vsync Input Pin, Logic 1 = Vsync from Sync Separator.) Bit 2 – Output Vsync Polarity Detect. (Logic 0 = Active Low, Logic 1 = Active High.) Bit 1 – Sync-on-Green Detect. It is set to Logic 1 if sync is present on the Green video input; otherwise it is set to 0. Bit 0 – Input Coast Polarity Detect. (Logic 0 = Active Low, Logic 廖 R *******0 7:0 The CAT logo is a registered trademark of Chip Advanced Technology 2007 Chip Advanced Technology Inc. – All Right Reserved. Aug-2007 Rev:1.0 18/23 CAT9883C 1 = Active High.) 1111**** Test Register Bits [7:4] Reserved for future use. ****1*** Bit 3 – Reserved for future use. *****1** Bit 2 – Reserved for future use. ******1* Bit 1 – 4:2:2 Output Formatting Mode (Logic 0 = 4:2:2 mode, 廖 R 7:0 19 ， R/W 15H Logic 1=4:4:4 mode) 16H R/W 7:0 Test Register Reserved for future use. 17H RO 7:0 Test Register Reserved for future use. 18H RO 7:0 Test Register Reserved for future use. R/W 7:0 Default Setting; Must set to 0000 for proper operation. Calibration Mode Setting: “00” for no calibration; “01” for offset calibration; “10” for white balance calibration; “11” for AGC control on TV signal; Default Setting; Must set to 11 for proper operation. Data output Data output Enable; Logic 0=Tri-State Output ****00** ******11 R/W 85H 6:6 *1****** 58 5 84H Calibration QQ : 0000**** 34 1 Enable Reserved for future use or customerization. Please contact CAT for more details. 深 圳 市 金 合 讯 科 技 有 限 公 司 ， Te l: 18 66 4 80H~85H 51 8 Bit 0 – Reserved for future use. 71 44 *******1 The CAT logo is a registered trademark of Chip Advanced Technology 2007 Chip Advanced Technology Inc. – All Right Reserved. Aug-2007 Rev:1.0 19/23 CAT9883C 深 圳 市 金 合 讯 科 技 有 限 公 司 ， Te l: 18 66 4 34 1 58 5 QQ : 71 44 51 8 19 ， 廖 R PACKAGE OUTLINE DIMENSION The CAT logo is a registered trademark of Chip Advanced Technology 2007 Chip Advanced Technology Inc. – All Right Reserved. Aug-2007 Rev:1.0 20/23 CAT9883C Classification Reflow Profiles Reflow Profile Pb-Free Assembly 19 ， Preheat -Temperature Min(Tsmin) -Temperature Max(Tsmax) -Time(tsmin to ts tsmax) 廖 R 3℃/second max. Average Ramp-Up Rate (Tsmax to Tp) 51 8 150℃ 200℃ 71 44 60-180 seconds Time maintained above: -Temperature(TL) -Time(tL) 217℃ QQ : 60-150 seconds 260 +0 /-5℃ Peak Temperature(Tp) Time within 5 ℃ of actual Peak 58 5 20-40 seconds Temperature(tp) 34 1 Ramp-Down Rate 66 4 Time 25℃ to Peak Temperature 6℃/second max. 8 minutes max. 深 圳 市 金 合 讯 科 技 有 限 公 司 ， Te l: 18 Note: All Temperature refer to topside of the package, measured on the package body surface. The CAT logo is a registered trademark of Chip Advanced Technology 2007 Chip Advanced Technology Inc. – All Right Reserved. Aug-2007 Rev:1.0 21/23 CAT9883C 深 圳 市 金 合 讯 科 技 有 限 公 司 ， Te l: 18 66 4 34 1 58 5 QQ : 71 44 51 8 19 ， 廖 R Carrier Tray Dimensions The CAT logo is a registered trademark of Chip Advanced Technology 2007 Chip Advanced Technology Inc. – All Right Reserved. Aug-2007 Rev:1.0 22/23 34 1 58 5 QQ : 71 44 51 8 19 ， 廖 R CAT9883C Te l: 18 66 4 HEADQUARTERS: 3F, No.1, Jin-Shan 8th St., Hsin-Chu City 300, Taiwan (R.O.C.) Tel: +886-3-666-8301 Fax: +886-3-666-8630 Website: http://www.chipadvanced.com 技 有 限 公 司 ， TAIPEI OFFICE: 4F, No.112, Jhouzih St., Neihu District, Taipei City 114, Taiwan (R.O.C.) Tel: +886-2-87516119 Fax: +886-2-87516359 深 圳 市 金 合 讯 科 Information furnished is believed to be accurate and reliable. However, CAT Inc. assumes no responsibility for the consequences for use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of CAT Inc. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information if previously supplied. CAT Inc. products are not authorized for use as critical components in life support devices or systems without the express written approval of CAT Inc. The CAT logo is a registered trademark of Chip Advanced Technology 2007 Chip Advanced Technology Inc. – All Right Reserved. Aug-2007 Rev:1.0 23/23