High Voltage Latch-Up Proof, Dual SPDT Switches ADG5236 Data Sheet FEATURES FUNCTIONAL BLOCK DIAGRAMS Latch-up proof 2.5 pF off source capacitance 12 pF off drain capacitance −0.6 pC charge injection Low leakage: 0.4 nA maximum at 85°C ±9 V to ±22 V dual-supply operation 9 V to 40 V single-supply operation 48 V supply maximum ratings Fully specified at ±15 V, ±20 V, +12 V, and +36 V VSS to VDD analog signal range ADG5236 S1A D1 S1B IN1 IN2 S2A D2 APPLICATIONS Automatic test equipment Data acquisition Instrumentation Avionics Audio and video switching Communication systems SWITCHES SHOWN FOR A LOGIC 1 INPUT. 09769-001 S2B Figure 1. TSSOP Package ADG5236 S1A S2A D2 D1 S2B S1B IN1 IN2 EN SWITCHES SHOWN FOR A LOGIC 1 INPUT. 09769-002 LOGIC Figure 2. LFCSP Package GENERAL DESCRIPTION PRODUCT HIGHLIGHTS The ADG5236 is a monolithic CMOS device containing two independently selectable single-pole/double throw (SPDT) switches. An EN input on the LFCSP package enables or disables the device. When disabled, all channels switch off. Each switch conducts equally well in both directions when on and has an input signal range that extends to the supplies. In the off condition, signal levels up to the supplies are blocked. Both switches exhibit break-before-make switching action for use in multiplexer applications. 1. The ultralow capacitance and charge injection of these switches make them ideal solutions for data acquisition and sample-andhold applications, where low glitch and fast settling are required. Fast switching speed together with high signal bandwidth make the device suitable for video signal switching. 2. 3. 4. 5. 6. Trench Isolation Guards Against Latch-Up. A dielectric trench separates the P and N channel transistors thereby preventing latch-up even under severe overvoltage conditions. Ultralow Capacitance and <1 pC Charge Injection. Dual-Supply Operation. For applications where the analog signal is bipolar, the ADG5236 can be operated from dual supplies up to ±22 V. Single-Supply Operation. For applications where the analog signal is unipolar, the ADG5236 can be operated from a single rail power supply up to 40 V. 3 V Logic-Compatible Digital Inputs. VINH = 2.0 V, VINL = 0.8 V. No VL Logic Power Supply Required. Rev. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2011–2012 Analog Devices, Inc. All rights reserved. ADG5236 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Absolute Maximum Ratings ............................................................8 Applications ....................................................................................... 1 ESD Caution...................................................................................8 Functional Block Diagrams ............................................................. 1 Pin Configurations and Function Descriptions ............................9 General Description ......................................................................... 1 Truth Tables for Switches .............................................................9 Product Highlights ........................................................................... 1 Typical Performance Characteristics ........................................... 10 Revision History ............................................................................... 2 Test Circuits..................................................................................... 14 Specifications..................................................................................... 3 Terminology .................................................................................... 16 ±15 V Dual Supply ....................................................................... 3 Trench Isolation .............................................................................. 17 ±20 V Dual Supply ....................................................................... 4 Applications Information .............................................................. 18 12 V Single Supply ........................................................................ 5 Outline Dimensions ....................................................................... 19 36 V Single Supply ........................................................................ 6 Ordering Guide .......................................................................... 19 Continuous Current per Channel, Sx or Dx ............................. 7 REVISION HISTORY 4/12—Rev. 0 to Rev. A Updated Outline Dimensions ....................................................... 19 Changes to Ordering Guide .......................................................... 19 7/11—Revision 0: Initial Version Rev. A | Page 2 of 20 Data Sheet ADG5236 SPECIFICATIONS ±15 V DUAL SUPPLY VDD = +15 V ± 10%, VSS = −15 V ± 10%, GND = 0 V, unless otherwise noted. Table 1. Parameter ANALOG SWITCH Analog Signal Range On Resistance, RON On-Resistance Match Between Channels, ∆RON On-Resistance Flatness, RFLAT (ON) LEAKAGE CURRENTS Source Off Leakage, IS (Off ) Drain Off Leakage, ID (Off ) Channel On Leakage, ID (On), IS (On) 25°C 160 200 1.4 8 38 50 0.01 0.1 0.01 0.1 0.02 0.2 −40°C to +85°C −40°C to +125°C Unit Test Conditions/Comments VDD to VSS V max Ω typ Ω max Ω typ VS = ±10 V, IS = −1 mA, see Figure 25 VDD = +13.5 V, VSS = −13.5 V VS = ±10 V, IS = −1 mA 250 280 9 10 65 70 0.2 0.4 0.4 1.2 0.4 1.2 Ω max Ω typ Ω max nA typ nA max nA typ nA max nA typ nA max VS = ±10 V, IS = −1 mA VDD = +16.5 V, VSS = −16.5 V VS = ±10 V, VD = 10 V, see Figure 27 VS = ±10 V, VD = 10 V, see Figure 27 VS = VD = ±10 V, see Figure 24 DIGITAL INPUTS Input High Voltage, VINH Input Low Voltage, VINL Input Current, IINL or IINH 2.0 0.8 0.002 ±0.1 Digital Input Capacitance, CIN DYNAMIC CHARACTERISTICS 1 Transition Time, tTRANSITION 3 V min V max µA typ µA max pF typ Break-Before-Make Time Delay, tD 150 230 170 215 160 185 75 Charge Injection, QINJ −0.6 ns typ ns max ns typ ns max ns typ ns max ns typ ns min pC typ Off Isolation −85 dB typ Channel-to-Channel Crosstalk −85 dB typ −3 dB Bandwidth Insertion Loss 266 −7 MHz typ dB typ CS (Off ) CD (Off ) CD (On), CS (On) 2.5 12 15 pF typ pF typ pF typ tON tOFF 280 315 265 300 205 225 30 Rev. A | Page 3 of 20 VIN = VGND or VDD RL = 300 Ω, CL = 35 pF VS = 10 V, see Figure 30 RL = 300 Ω, CL = 35 pF VS = 10 V, see Figure 32 RL = 300 Ω, CL = 35 pF VS = 10 V, see Figure 32 RL = 300 Ω, CL = 35 pF VS1 = VS2 = 10 V, see Figure 31 VS = 0 V, RS = 0 Ω, CL = 1 nF, see Figure 33 RL = 50 Ω, CL = 5 pF, f = 1 MHz, see Figure 28 RL = 50 Ω, CL = 5 pF, f = 1 MHz, see Figure 26 RL = 50 Ω, CL = 5 pF, see Figure 29 RL = 50 Ω, CL = 5 pF, f = 1 MHz, see Figure 29 VS = 0 V, f = 1 MHz VS = 0 V, f = 1 MHz VS = 0 V, f = 1 MHz ADG5236 Parameter POWER REQUIREMENTS IDD ISS Data Sheet 25°C −40°C to +85°C 45 55 0.001 −40°C to +125°C 70 1 VDD/VSS 1 ±9/±22 Unit µA typ µA max µA typ µA max V min/V max Test Conditions/Comments VDD = +16.5 V, VSS = −16.5 V Digital inputs = 0 V or VDD Digital inputs = 0 V or VDD GND = 0 V Guaranteed by design; not subject to production test. ±20 V DUAL SUPPLY VDD = +20 V ± 10%, VSS = −20 V ± 10%, GND = 0 V, unless otherwise noted. Table 2. Parameter ANALOG SWITCH Analog Signal Range On Resistance, RON On-Resistance Match Between Channels, ∆RON On-Resistance Flatness, RFLAT (ON) LEAKAGE CURRENTS Source Off Leakage, IS (Off ) Drain Off Leakage, ID (Off ) Channel On Leakage, ID (On), IS (On) DIGITAL INPUTS Input High Voltage, VINH Input Low Voltage, VINL Input Current, IINL or IINH 25°C 140 160 1.3 8 33 45 0.01 0.1 0.01 0.1 0.02 0.2 −40°C to +85°C −40°C to +125°C Unit Test Conditions/Comments VDD to VSS V max Ω typ Ω max Ω typ VS = ±15 V, IS = −1 mA, see Figure 25 VDD = +18 V, VSS = −18 V VS = ±15 V, IS = −1 mA 200 230 9 10 55 60 0.2 0.4 0.4 1.2 0.4 1.2 2.0 0.8 0.002 ±0.1 Digital Input Capacitance, CIN DYNAMIC CHARACTERISTICS 1 Transition Time, tTRANSITION 3 Ω max Ω typ Ω max nA typ nA max nA typ nA max nA typ nA max V min V max µA typ µA max pF typ Break-Before-Make Time Delay, tD 150 210 150 190 155 180 60 Charge Injection, QINJ −0.6 ns typ ns max ns typ ns max ns typ ns max ns typ ns min pC typ Off Isolation −85 dB typ Channel-to-Channel Crosstalk −85 dB typ −3 dB Bandwidth Insertion Loss 266 −7 MHz typ dB typ tON tOFF 260 290 235 267 200 215 30 Rev. A | Page 4 of 20 VS = ±15 V, IS = −1 mA VDD = +22 V, VSS = −22 V VS = ±15 V, VD = 15 V, see Figure 27 VS = ±15 V, VD = 15 V, see Figure 27 VS = VD = ±15 V, see Figure 24 VIN = VGND or VDD RL = 300 Ω, CL = 35 pF VS = 10 V, see Figure 30 RL = 300 Ω, CL = 35 pF VS = 10 V, see Figure 32 RL = 300 Ω, CL = 35 pF VS = 10 V, see Figure 32 RL = 300 Ω, CL = 35 pF VS1 = VS2 = 10 V, see Figure 31 VS = 0 V, RS = 0 Ω, CL = 1 nF, see Figure 33 RL = 50 Ω, CL = 5 pF, f = 1 MHz, see Figure 28 RL = 50 Ω, CL = 5 pF, f = 1 MHz, see Figure 26 RL = 50 Ω, CL = 5 pF, see Figure 29 RL = 50 Ω, CL = 5 pF, f = 1 MHz, see Figure 29 Data Sheet Parameter CS (Off ) CD (Off ) CD (On), CS (On) POWER REQUIREMENTS IDD ISS ADG5236 25°C 2.5 12 15 −40°C to +85°C 50 70 0.001 −40°C to +125°C ±9/±22 µA typ µA max µA typ µA max V min/V max −40°C to +125°C Unit 0 V to VDD V max Ω typ 110 1 VDD/VSS 1 Unit pF typ pF typ pF typ Test Conditions/Comments VS = 0 V, f = 1 MHz VS = 0 V, f = 1 MHz VS = 0 V, f = 1 MHz VDD = +22 V, VSS = −22 V Digital inputs = 0 V or VDD Digital inputs = 0 V or VDD GND = 0 V Guaranteed by design; not subject to production test. 12 V SINGLE SUPPLY VDD = 12 V ± 10%, VSS = 0 V, GND = 0 V, unless otherwise noted. Table 3. Parameter ANALOG SWITCH Analog Signal Range On Resistance, RON On-Resistance Match Between Channels, ∆RON On-Resistance Flatness, RFLAT (ON) 25°C −40°C to +85°C 350 610 700 Ω max Ω typ 20 145 280 21 22 VS = 0 V to 10 V, IS = −1 mA 335 370 Ω max Ω typ Ω max nA typ VDD = 13.2 V, VSS = 0 V VS = 1 V/10 V, VD = 10 V/1 V, see Figure 27 0.01 0.2 Drain Off Leakage, ID (Off ) 0.1 0.01 0.1 0.02 0.2 0.4 1.2 0.4 1.2 DIGITAL INPUTS Input High Voltage, VINH Input Low Voltage, VINL Input Current, IINL or IINH 0.4 2.0 0.8 0.002 ±0.1 Digital Input Capacitance, CIN DYNAMIC CHARACTERISTICS 1 Transition Time, tTRANSITION 3 Break-Before-Make Time Delay, tD 220 390 275 380 160 195 145 Charge Injection, QINJ −0.6 tON tOFF VS = 0 V to 10 V, IS = −1 mA, see Figure 25 VDD = 10.8 V, VSS = 0 V VS = 0 V to 10 V, IS = −1 mA 500 3 LEAKAGE CURRENTS Source Off Leakage, IS (Off ) Channel On Leakage, ID (On), IS (On) Test Conditions/Comments 430 490 440 510 225 245 65 Rev. A | Page 5 of 20 nA max nA typ VS = 1 V/10 V, VD = 10 V/1 V, see Figure 27 nA max nA typ nA max VS = VD = 1 V/10 V, see Figure 24 V min V max µA typ µA max pF typ VIN = VGND or VDD ns typ ns max ns typ ns max ns typ ns max ns typ ns min pC typ RL = 300 Ω, CL = 35 pF VS = 8 V, see Figure 30 RL = 300 Ω, CL = 35 pF VS = 8 V, see Figure 32 RL = 300 Ω, CL = 35 pF VS = 8 V, see Figure 32 RL = 300 Ω, CL = 35 pF VS1 = VS2 = 8 V, see Figure 31 VS = 6 V, RS = 0 Ω, CL = 1 nF, see Figure 33 ADG5236 Parameter Off Isolation Data Sheet 25°C −90 −40°C to +85°C −40°C to +125°C Channel-to-Channel Crosstalk −90 dB typ −3 dB Bandwidth Insertion Loss 185 −11 MHz typ dB typ 3 16 16 pF typ pF typ pF typ CS (Off ) CD (Off ) CD (On), CS (On) POWER REQUIREMENTS IDD 40 9/40 µA typ µA max V min/V max −40°C to +125°C Unit 0 V to VDD V max Ω typ 65 VDD 1 Unit dB typ Test Conditions/Comments RL = 50 Ω, CL = 5 pF, f = 1 MHz, see Figure 28 RL = 50 Ω, CL = 5 pF, f = 1 MHz, see Figure 26 RL = 50 Ω, CL = 5 pF, see Figure 29 RL = 50 Ω, CL = 5 pF, f = 1 MHz, see Figure 29 VS = 6 V, f = 1 MHz VS = 6 V, f = 1 MHz VS = 6 V, f = 1 MHz VDD = 13.2 V Digital inputs = 0 V or VDD GND = 0 V, VSS = 0 V Guaranteed by design; not subject to production test. 36 V SINGLE SUPPLY VDD = 36 V ± 10%, VSS = 0 V, GND = 0 V, unless otherwise noted. Table 4. Parameter ANALOG SWITCH Analog Signal Range On Resistance, RON On-Resistance Match Between Channels, ∆RON On-Resistance Flatness, RFLAT(ON) 25°C −40°C to +85°C 150 215 245 Ω max Ω typ 8 35 50 9 10 VS = 0 V to 30 V, IS = −1 mA 60 65 Ω max Ω typ Ω max nA typ VDD = 39.6 V, VSS = 0 V VS = 1 V/30 V, VD = 30 V/1 V, see Figure 27 0.01 0.1 0.01 0.2 Drain Off Leakage, ID (Off ) 0.1 0.02 0.2 0.4 1.2 0.4 1.2 DIGITAL INPUTS Input High Voltage, VINH Input Low Voltage, VINL Input Current, IINL or IINH 0.4 2.0 0.8 0.002 ±0.1 Digital Input Capacitance, CIN DYNAMIC CHARACTERISTICS 1 Transition Time, tTRANSITION tON VS = 0 V to 30 V, IS = −1 mA, see Figure 25 VDD = 32.4 V, VSS = 0 V VS = 0 V to 30 V, IS = −1 mA 170 1.4 LEAKAGE CURRENTS Source Off Leakage, IS (Off ) Channel On Leakage, ID (On), IS (On) Test Conditions/Comments 3 180 250 170 225 275 305 265 295 Rev. A | Page 6 of 20 nA max nA typ VS = 1 V/30 V, VD = 30 V/1 V, see Figure 27 nA max nA typ nA max VS = VD = 1 V/30 V, see Figure 24 V min V max µA typ µA max pF typ VIN = VGND or VDD ns typ ns max ns typ ns max RL = 300 Ω, CL = 35 pF VS = 18 V, see Figure 30 RL = 300 Ω, CL = 35 pF VS = 18 V, see Figure 32 Data Sheet Parameter tOFF ADG5236 Break-Before-Make Time Delay, tD 25°C 170 215 75 −40°C to +85°C −40°C to +125°C Charge Injection, QINJ −0.6 Unit ns typ ns max ns typ ns min pC typ 215 225 Off Isolation −85 dB typ Channel-to-Channel Crosstalk −85 dB typ −3 dB Bandwidth Insertion Loss 266 −7 MHz typ dB typ CS (Off ) CD (Off ) CD (On), CS (On) POWER REQUIREMENTS IDD 2.5 12 15 pF typ pF typ pF typ 35 85 100 VDD 1 µA typ µA max V min/V max 130 9/40 Test Conditions/Comments RL = 300 Ω, CL = 35 pF VS = 18 V, see Figure 32 RL = 300 Ω, CL = 35 pF VS1 = VS2 = 18 V, see Figure 31 VS = 18 V, RS = 0 Ω, CL = 1 nF, see Figure 33 RL = 50 Ω, CL = 5 pF, f = 1 MHz, see Figure 28 RL = 50 Ω, CL = 5 pF, f = 1 MHz, see Figure 26 RL = 50 Ω, CL = 5 pF, see Figure 29 RL = 50 Ω, CL = 5 pF, f = 1 MHz, see Figure 29 VS = 18 V, f = 1 MHz VS = 18 V, f = 1 MHz VS = 18 V, f = 1 MHz VDD = 39.6 V Digital inputs = 0 V or VDD GND = 0 V, VSS = 0 V Guaranteed by design; not subject to production test. CONTINUOUS CURRENT PER CHANNEL, SxA, SxB, OR Dx Table 5. Parameter CONTINUOUS CURRENT, SxA, SxB, or Dx VDD = +15 V, VSS = −15 V TSSOP (θJA = 112.6°C/W) LFCSP (θJA = 30.4°C/W) VDD = +20 V, VSS = −20 V TSSOP (θJA = 112.6°C/W) LFCSP (θJA = 30.4°C/W) VDD = 12 V, VSS = 0 V TSSOP (θJA = 112.6°C/W) LFCSP (θJA = 30.4°C/W) VDD = 36 V, VSS = 0 V TSSOP (θJA = 112.6°C/W) LFCSP (θJA = 30.4°C/W) 25°C 85°C 125°C Unit 19 30 7 7.7 2.8 2.8 mA max mA max 21 31 7 7.7 2.8 2.8 mA max mA max 14 22.5 6.3 7.3 2.7 2.8 mA max mA max 24 35 7.4 7.8 2.8 2.8 mA max mA max Rev. A | Page 7 of 20 ADG5236 Data Sheet ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. Table 6. Parameter VDD to VSS VDD to GND VSS to GND Analog Inputs1 Digital Inputs1 Peak Current, SxA, SxB, or Dx Pin Continuous Current, SxA, SxB, or Dx2 Temperature Range Operating Storage Junction Temperature Thermal Impedance, θJA 16-Lead TSSOP (4-Layer Board) 16-Lead LFCSP Reflow Soldering Peak Temperature, Pb Free 1 2 Rating 48 V −0.3 V to +48 V +0.3 V to −48 V VSS − 0.3 V to VDD + 0.3 V or 30 mA, whichever occurs first VSS − 0.3 V to VDD + 0.3 V or 30 mA, whichever occurs first 63 mA (pulsed at 1 ms, 10% duty cycle maximum) Data + 15% Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Only one absolute maximum rating can be applied at any one time. ESD CAUTION −40°C to +125°C −65°C to +150°C 150°C 112°C/W 30.4°C/W 260(+0/−5)°C Overvoltages at the INx, SxA, SxB, and Dx pins are clamped by internal diodes. Limit the current to the maximum ratings given. See Table 5. Rev. A | Page 8 of 20 Data Sheet ADG5236 D2 NC 7 10 S2A NC 8 9 IN2 NC = NO CONNECT S1B 2 ADG5236 11 VDD VSS 3 TOP VIEW (Not to Scale) 10 S2B GND 4 9 D2 NC 5 11 09769-003 GND 6 12 EN D1 1 VDD TOP VIEW VSS 5 (Not to Scale) 12 S2B 13 NOTES 1. EXPOSED PAD TIED TO SUBSTRATE, VSS. 2. NC = NO CONNECT. Figure 3. TSSOP Pin Configuration 09769-004 ADG5236 14 NC NC S1B 4 13 NC 14 NC 7 NC D1 3 S2A 8 NC 15 16 S1A 16 IN2 6 IN1 1 S1A 2 15 IN1 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS Figure 4. LFCSP Pin Configuration Table 7. Pin Function Descriptions Pin No. TSSOP LFCSP 1 15 2 16 3 1 4 2 5 3 6 4 7, 8, 14 to 16 5, 7, 13, 14 9 6 10 8 11 9 12 10 13 11 N/A1 12 Mnemonic IN1 S1A D1 S1B VSS GND NC IN2 S2A D2 S2B VDD EN N/A1 Exposed Pad 1 EP Description Logic Control Input 1. Source Terminal 1A. This pin can be an input or output. Drain Terminal 1. This pin can be an input or output. Source Terminal 1B. This pin can be an input or output. Most Negative Power Supply Potential. Ground (0 V) Reference. No Connect. These pins are open. Logic Control Input 2. Source Terminal 2A. This pin can be an input or output. Drain Terminal 2. This pin can be an input or output. Source Terminal 2B. This pin can be an input or output. Most Positive Power Supply Potential. Active High Digital Input. When this pin is low, the device is disabled and all switches are off. When this pin is high, the INx logic inputs determine the on switches. Exposed Pad. The exposed pad is connected internally. For increased reliability of the solder joints and maximum thermal capability, it is recommended that the pad be soldered to the substrate, VSS. N/A means not applicable. TRUTH TABLES FOR SWITCHES Table 8. TSSOP Truth Table INx 0 1 SxA Off On SxB On Off Table 9. LFCSP Truth Table EN 0 1 1 1 INx X1 0 1 SxA Off Off On X means don’t care. Rev. A | Page 9 of 20 SxB Off On Off ADG5236 Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS 160 TA = 25°C TA = 25°C VDD = +18V VSS = –18V 120 ON RESISTANCE (Ω) 120 100 VDD = +20V VSS = –20V 80 VDD = +22V VSS = –22V 60 100 60 40 20 20 0 –25 –20 –15 –10 –5 0 5 10 15 20 25 VS, VD (V) 0 0 5 10 15 20 25 30 35 40 VS, VD (V) Figure 5. On Resistance vs. VS, VD (Dual Supply) 250 VDD = 39.6V VSS = 0V VDD = 36V VSS = 0V 80 40 09769-105 ON RESISTANCE (Ω) VDD = 32.4V VSS = 0V 140 140 09769-108 160 Figure 8. On Resistance vs. VS, VD (Single Supply) 250 TA = 25°C VDD = +15V VSS = –15V VDD = +9V VSS = –9V 200 200 ON RESISTANCE (Ω) 150 VDD = +13.2V VSS = –13.2V 100 VDD = +16.5V VSS = –16.5V VDD = +15V VSS = –15V 50 TA = +25°C 100 TA = –40°C –10 –5 0 5 10 15 20 VS, VD (V) 0 –15 09769-106 –15 5 10 15 Figure 9. On Resistance vs. VD or VS for Different Temperatures, ±15 V Dual Supply VDD = 9V VSS = 0V 180 VDD = 10.8V VSS = 0V 400 160 300 ON RESISTANCE (Ω) VDD = 12V VSS = 0V VDD = 13.2V VSS = 0V 350 250 200 150 140 TA = +25°C 80 TA = –40°C 60 20 6 8 10 12 VS, VD (V) 14 09769-107 50 4 Figure 7. On Resistance vs. VS, VD (Single Supply) TA = +85°C 100 40 0 TA = +125°C 120 100 2 0 200 TA = 25°C 450 0 –5 VS, VD (V) Figure 6. On Resistance vs. VS, VD (Dual Supply) 500 –10 09769-109 50 0 –20 ON RESISTANCE (Ω) TA = +85°C 150 VDD = +20V VSS = –20V 0 –20 –15 –10 –5 0 5 10 15 20 VS, VD (V) Figure 10. On Resistance vs. VD or VS for Different Temperatures, ±20 V Dual Supply Rev. A | Page 10 of 20 09769-110 ON RESISTANCE (Ω) TA = +125°C Data Sheet ADG5236 100 500 I I (ON) + + IS (OFF) + – D, S 400 TA = +125°C 340 TA = +85°C 300 TA = +25°C 250 200 ID (OFF) – + 50 LEAKAGE CURRENT (pA) TA = –40°C 150 0 IS (OFF) – + –50 ID (OFF) + – –100 ID, IS (ON) – – 100 –150 50 VDD = 12V VSS = 0V 0 2 4 6 8 10 12 VS, VD (V) –200 09769-111 0 VDD = +20V VSS = –20V VBIAS = +15V/–15V 0 20 40 60 80 100 120 TEMPERATURE (°C) Figure 11. On Resistance vs. VD or VS for Different Temperatures, 12 V Single Supply 09769-114 ON RESISTANCE (Ω) 450 Figure 14. Leakage Current vs. Temperature, ±20 V Single Supply 40 250 VDD = 36V VSS = 0V IS (OFF) + – ID (OFF) – + 20 LEAKAGE CURRENT (pA) ON RESISTANCE (Ω) 200 TA = +125°C 150 TA = +85°C TA = +25°C 100 TA = –40°C 0 IS (OFF) – + –20 ID, IS (ON) + + –40 ID (OFF) + – –60 ID, IS (ON) – – –80 5 10 15 20 25 30 35 VS, VD (V) ID (OFF) – + ID, IS (ON) + + 120 50 IS (OFF) + – ID, IS (ON) + + LEAKAGE CURRENT (pA) IS (OFF) – + ID (OFF) + – ID, IS (ON) – – –30 –40 –50 IS (OFF) + – ID (OFF) – + IS (OFF) – + –50 –100 ID (OFF) + – –150 ID, IS (ON) – – –200 60 80 100 120 TEMPERATURE (°C) 09769-113 LEAKAGE CURRENT (pA) 100 0 –10 –60 VDD = +15V VSS = –15V VBIAS = +10V/–10V –70 0 20 40 80 Figure 15. Leakage Current vs. Temperature, 12 V Single Supply 0 –20 60 TEMPERATURE (°C) Figure 12. On Resistance vs. VS or VD for Different Temperatures, 36 V Single Supply 10 40 VDD = 36V VSS = 0V VBIAS = 1V/30V –250 0 20 40 60 80 100 120 TEMPERATURE (°C) Figure 16. Leakage Current vs. Temperature, 36 V Single Supply Figure 13. Leakage Current vs. Temperature, ±15 V Dual Supply Rev. A | Page 11 of 20 09769-116 0 09769-112 0 –100 VDD = 12V VSS = 0V VBIAS = 1V/10V –120 0 20 09769-115 50 ADG5236 0 –20 Data Sheet 0 TA = 25°C VDD = +15V VSS = –15V –20 –40 ACPSRR (dB) –40 IL (dB) TA = 25°C VDD = +15V VSS = –15V –60 NO DECOUPLING CAPACITORS –60 –80 –80 –100 –100 –120 10k –120 1k 1M 10M 100M 1G FREQUENCY (Hz) 10k 100k 1M 10M FREQUENCY (Hz) Figure 17. Off Isolation vs. Frequency 09769-120 100k 09769-117 DECOUPLING CAPACITORS Figure 20. ACPSRR vs. Frequency 0 0 TA = 25°C –2 VDD = +15V VSS = –15V TA = 25°C VDD = +15V –20 VSS = –15V –4 ATTENUATION (dB) CROSSTALK (dB) –40 BETWEEN SA AND SB –60 –80 –100 –6 –8 –10 –12 –14 –16 BETWEEN S1 AND S2 –120 1M 10M 100M 1G FREQUENCY (Hz) –20 100k 09769-118 100k 1M Figure 18. Crosstalk vs. Frequency Figure 21. Bandwidth VDD = +20V VSS = –20V 1.0 300 250 0.5 TIME (ns) VDD = +15V VSS = –15V 0 VDD = +36V VSS = 0V –0.5 VDD = +12V VSS = 0V 200 VDD = +36V VSS = 0V 150 VDD = +12V VSS = 0V –1.0 100 –1.5 50 –10 0 10 20 30 VS (V) 40 09769-119 CHARGE INJECTION (pC) 1G 350 TA = 25°C –2.0 –20 100M Figure 19. Charge Injection vs. Source Voltage 0 –40 VDD = +15V VSS = –15V VDD = +20V VSS = –20V –20 0 20 40 60 80 100 TEMPERATURE (°C) Figure 22. tTRANSITION Time vs. Temperature Rev. A | Page 12 of 20 120 09769-123 1.5 10M FREQUENCY (Hz) 09769-122 –18 –140 10k Data Sheet ADG5236 TA = 25°C VDD = +15V VSS = –15V 20 DRAIN OFF 10 5 SOURCE OFF 0 –15 –10 –5 0 5 10 VS (V) 15 09769-124 CAPACITANCE (pF) SOURCE/DRAIN ON 15 Figure 23. Capacitance vs. Source Voltage, Dual Supply Rev. A | Page 13 of 20 ADG5236 Data Sheet TEST CIRCUITS ID (ON) IS (OFF) A A Dx NC = NO CONNECT VD SxA/SxB Dx ID (OFF) A VS VD Figure 24. On Leakage Figure 27. Off Leakage VDD VSS 0.1µF 0.1µF VDD NETWORK ANALYZER VSS SxA INx NC SxB 50Ω 50Ω VS V Dx VIN GND 09769-023 IDS VS OFF ISOLATION = 20 log Figure 25. On Resistance VDD 0.1µF VDD VDD SxA VSS 0.1µF VSS VDD RL 50Ω SxB VS VS VSS 0.1µF VOUT VOUT Figure 28. Off Isolation 0.1µF NETWORK ANALYZER Dx RL 50Ω INx NETWORK ANALYZER VSS SxA NC SxB 50Ω 50Ω VS Dx INx VIN GND RL 50Ω VOUT VS 09769-032 GND CHANNEL-TO-CHANNEL CROSSTALK = 20 log VOUT 09769-030 Dx RL 50Ω INSERTION LOSS = 20 log Figure 26. Channel-to-Channel Crosstalk VOUT WITH SWITCH VOUT WITHOUT SWITCH Figure 29. Bandwidth Rev. A | Page 14 of 20 VOUT 09769-031 SxA/SxB 09769-024 SxA/SxB 09769-025 NC Data Sheet ADG5236 VDD 0.1µF VSS VDD VIN 50% 50% VIN 50% 50% VSS SxB VS 0.1µF Dx SxA VOUT RL 300Ω INx CL 35pF 90% VOUT 90% tON TRANSITION 09769-026 GND VIN tOFF TRANSITION Figure 30. Switching Times 0.1µF VDD VSS VDD VSS SxB VS 0.1µF VIN Dx VOUT SxA RL 300Ω INx VOUT CL 35pF 80% tD tD 09769-027 GND VIN Figure 31. Break-Before-Make Time Delay tD 3V ENABLE DRIVE (VIN) 50% 50% VDD VSS VDD VSS INx SxA VS SxB 0V tON (EN) tOFF (EN) OUTPUT 0.9VOUT Dx EN OUTPUT VIN 50Ω 300Ω 0.1VOUT Figure 32. Enable Delay, tON (EN), tOFF (EN) VS VDD VSS VDD VSS VIN (NORMALLY CLOSED SWITCH) SxB Dx SxA INx VIN 0.1µF GND ON OFF NC VOUT CL 1nF VIN (NORMALLY OPEN SWITCH) VOUT ∆VOUT Figure 33. Charge Injection Rev. A | Page 15 of 20 QINJ = CL × ∆VOUT 09769-029 0.1µF 35pF 09769-028 GND ADG5236 Data Sheet TERMINOLOGY IDD IDD represents the positive supply current. CIN CIN is the digital input capacitance. ISS ISS represents the negative supply current. tON tON represents the delay between applying the digital control input and the output switching on. VD, VS VD and VS represent the analog voltage on Terminal D and Terminal S, respectively. RON RON represents the ohmic resistance between Terminal D and Terminal S. ∆RON ∆RON represents the difference between the RON of any two channels. RFLAT (ON) Flatness that is defined as the difference between the maximum and minimum value of on resistance measured over the specified analog signal range is represented by RFLAT (ON). IS (Off) IS (Off) is the source leakage current with the switch off. ID (Off) ID (Off) is the drain leakage current with the switch off. ID (On), IS (On) ID (On) and IS (On) represent the channel leakage currents with the switch on. VINL VINL is the maximum input voltage for Logic 0. tOFF tOFF represents the delay between applying the digital control input and the output switching off. tD tD represents the off time measured between the 80% point of both switches when switching from one address state to another. Off Isolation Off isolation is a measure of unwanted signal coupling through an off switch. Charge Injection Charge injection is a measure of the glitch impulse transferred from the digital input to the analog output during switching. Crosstalk Crosstalk is a measure of unwanted signal that is coupled through from one channel to another as a result of parasitic capacitance. Bandwidth Bandwidth is the frequency at which the output is attenuated by 3 dB. On Response On response is the frequency response of the on switch. VINH VINH is the minimum input voltage for Logic 1. Insertion Loss Insertion loss is the loss due to the on resistance of the switch. IINL, IINH IINL and IINH represent the low and high input currents of the digital inputs. CD (Off) CD (Off) represents the off switch drain capacitance, which is measured with reference to ground. CS (Off) CS (Off) represents the off switch source capacitance, which is measured with reference to ground. AC Power Supply Rejection Ratio (ACPSRR) ACPSRR is the ratio of the amplitude of signal on the output to the amplitude of the modulation. This is a measure of the ability of the device to avoid coupling noise and spurious signals that appear on the supply voltage pin to the output of the switch. The dc voltage on the device is modulated by a sine wave of 0.62 V p-p. CD (On), CS (On) CD (On) and CS (On) represent on switch capacitances, which are measured with reference to ground. Rev. A | Page 16 of 20 Data Sheet ADG5236 TRENCH ISOLATION NMOS PMOS P WELL N WELL In the ADG5236, an insulating oxide layer (trench) is placed between the NMOS and the PMOS transistors of each CMOS switch. Parasitic junctions, which occur between the transistors in junction isolated switches, are eliminated, and the result is a completely latch-up proof switch. Rev. A | Page 17 of 20 TRENCH BURIED OXIDE LAYER HANDLE WAFER Figure 34. Trench Isolation 09769-045 In junction isolation, the N and P wells of the PMOS and NMOS transistors form a diode that is reverse-biased under normal operation. However, during overvoltage conditions, this diode can become forward-biased. A silicon controlled rectifier (SCR) type circuit is formed by the two transistors causing a significant amplification of the current that, in turn, leads to latch-up. With trench isolation, this diode is removed, and the result is a latch-up proof switch. ADG5236 Data Sheet APPLICATIONS INFORMATION The ADG52xx family of switches and multiplexers provide a robust solution for instrumentation, industrial, automotive, aerospace, and other harsh environments that are prone to latch-up, which is an undesirable high current state that can lead to device failure and persists until the power supply is turned off. The ADG5236 high voltage switches allow singlesupply operation from 9 V to 40 V and dual supply operation from ±9 V to ±22 V. Rev. A | Page 18 of 20 Data Sheet ADG5236 OUTLINE DIMENSIONS 5.10 5.00 4.90 16 9 4.50 4.40 4.30 6.40 BSC 1 8 PIN 1 1.20 MAX 0.15 0.05 0.20 0.09 0.30 0.19 0.65 BSC COPLANARITY 0.10 0.75 0.60 0.45 8° 0° SEATING PLANE COMPLIANT TO JEDEC STANDARDS MO-153-AB Figure 35. 16-Lead Thin Shrink Small Outline Package [TSSOP] (RU-16) Dimensions shown in millimeters PIN 1 INDICATOR 4.10 4.00 SQ 3.90 0.35 0.30 0.25 0.65 BSC 16 13 PIN 1 INDICATOR 12 1 EXPOSED PAD 4 2.70 2.60 SQ 2.50 9 0.80 0.75 0.70 0.45 0.40 0.35 8 0.05 MAX 0.02 NOM COPLANARITY 0.08 0.20 REF SEATING PLANE 0.20 MIN BOTTOM VIEW FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. COMPLIANT TO JEDEC STANDARDS MO-220-WGGC. 08-16-2010-C TOP VIEW 5 Figure 36. 16-Lead Lead Frame Chip Scale Package [LFCSP_WQ] 4 mm × 4 mm Body, Very Very Thin Quad (CP-16-17) Dimensions shown in millimeters ORDERING GUIDE Model1 ADG5236BRUZ ADG5236BRUZ-RL7 ADG5236BCPZ-RL7 1 Temperature Range −40°C to +125°C −40°C to +125°C −40°C to +125°C Package Description 16-Lead Thin Shrink Small Outline Package [TSSOP] 16-Lead Thin Shrink Small Outline Package [TSSOP] 16-Lead Lead Frame Chip Scale Package [LFCSP_WQ] Z = RoHS Compliant Part. Rev. A | Page 19 of 20 Package Option RU-16 RU-16 CP-16-17 ADG5236 Data Sheet NOTES ©2011–2012 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D09769-0-4/12(A) Rev. A | Page 20 of 20