AD ADV7401

10-Bit, Integrated, Multiformat SDTV/HDTV
Video Decoder and RGB Graphics Digitizer
ADV7401
FEATURES
GENERAL DESCRIPTION
Four 10-bit ADCs sampling up to 140 MHz
(140 MHz speed grade only)
12 analog input channel mux
SCART fast blank support
Internal antialias filters
NTSC/PAL/SECAM color standards support
525p-/625p-component progressive scan support
720p-/1080i-component HDTV support
Digitizes RGB graphics up to 1280 × 1024 @ 75 Hz (SXGA)
(140 MHz speed grade only)
24-bit digital input port supports data from DVI/HDMI Rx IC
Any-to-any, 3 × 3 color-space conversion matrix
Industrial temperature range (−40°C to +85°C)
12-bit 4:4:4/8-bit 4:2:2 DDR pixel output interface
Programmable interrupt request output pin
VBI data slicer (including teletext)
The ADV7401 is a high quality, single chip, multiformat video
decoder and graphics digitizer. This multiformat decoder
supports the conversion of PAL, NTSC, and SECAM standards
in the form of composite or S-video into a digital ITU-R BT.656
format. The ADV7401 also supports the decoding of a
component RGB/YPrPb video signal into a digital YCrCb or
RGB pixel output stream. The support for component video
includes standards such as 525i, 625i, 525p, 625p, 720p, 1080i,
1250i, and many other HD and SMPTE standards. Graphic
digitization is also supported by the ADV7401; it is capable of
digitizing RGB graphics signals from VGA to SXGA rates and
converting them into a digital RGB or YCrCb pixel output
stream. SCART and overlay functionality are enabled by the
ADV7401’s ability to simultaneously process CVBS and
standard definition RGB signals. The mixing of these signals is
controlled by the fast blank pin.
APPLICATIONS
LCD/DLP™ rear projection HDTVs
PDP HDTVs
CRT HDTVs
LCD/DLP front projectors
LCD TV (HDTV ready)
HDTV STBs with PVR
Hard-disk-based video recorders
Multiformat scan converters
DVD recorders with progressive scan input support
AVR receiver
The ADV7401 contains two main processing sections. The first
is the standard definition processor (SDP), which processes all
PAL, NTSC, and SECAM signal types. The second is the
component processor (CP), which processes YPrPb and RGB
component formats, including RGB graphics. For more specific
descriptions of the ADV7401 features, see the Detailed
Functionality and Detailed Description sections.
Rev. SpA
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
© 2005 Analog Devices, Inc. All rights reserved.
ADV7401
TABLE OF CONTENTS
Functional Block Diagram .............................................................. 3
CP Pixel Data Output Modes ................................................... 13
Electrical Characteristics ................................................................. 4
Composite and S-Video Processing......................................... 13
Video Specifications ......................................................................... 6
Component Video Processing .................................................. 14
Timing Characteristics..................................................................... 7
RGB Graphics Processing ......................................................... 14
Analog Specifications....................................................................... 8
Digital Video Input Port............................................................ 14
Absolute Maximum Ratings............................................................ 9
General Features......................................................................... 14
Stress Ratings ................................................................................ 9
Detailed Description ...................................................................... 15
Package Thermal Performance................................................... 9
Analog Front End....................................................................... 15
Thermal Specifications ................................................................ 9
Standard Definition Processor (SDP)...................................... 15
ESD Caution.................................................................................. 9
Component Processor ............................................................... 15
Pin Configuration and Function Descriptions........................... 10
Pixel Input/Output Formatting .................................................... 17
Timing Diagrams............................................................................ 12
Recommended External Loop Filter Components.................... 18
Detailed Functionality ................................................................... 13
Typical Connection Diagram ....................................................... 19
Analog Front End ....................................................................... 13
Outline Dimensions ....................................................................... 20
SDP Pixel Data Output Modes ................................................. 13
Ordering Guide .......................................................................... 20
REVISION HISTORY
9/05—Rev. Sp 0 to Rev. SpA
Deleted EDTV.....................................................................Universal
Added AVR Receiver to Applications Section.............................. 1
Changes to Table 3............................................................................ 7
Changes to Figure 2........................................................................ 10
Changes to Function Descriptions of Pin 37 and Pin 38 .......... 11
Change Pin 70 Type........................................................................ 11
Change to Crystal MHz Unit Value ............................................. 13
Added Pixel Input Information to Table 9 and Table 10 ........... 17
4/05—Revision Sp0: Initial Version
Rev. SpA | Page 2 of 20
Figure. 1.
Rev. SpA | Page 3 of 20
05340-001
P40–P31
P29–P20 24
P11–P10
P1–P0
SOG
SOY
DE_IN
HS_IN
VS_IN
DCLK_IN
SCLK
SCLK2
SDA
SDA2
ALSB
FB
CVBS
S-VIDEO
YPrPb
SCART–
(RGB + CVBS)
GRAPHICS RGB
AIN1 12
TO
AIN12
A/D
ANTIALIAS
FILTER
CLAMP
STDI
DVI or HDMI
DIGITAL INPUT
PORT
XTAL XTAL1
SSPD
SYNC PROCESSING AND
CLOCK GENERATION
8
8
8
A/D
ANTIALIAS
FILTER
A/D
A/D
CLAMP
CLAMP
ANTIALIAS
FILTER
SERIAL INTERFACE
CONTROL AND VBI DATA
INPUT
MUX
CLAMP
ANTIALIAS
FILTER
ADV7401
10
10
10
10
10
COLORSPACE
CONVERSION
10
10
DECIMATION
AND
DOWNSAMPLING 10
FILTERS
DATA
PREPROCESSOR
10
10
10
Cb
Cr
C
CVBS
DIGITAL
FINE
CLAMP
ACTIVE PEAK
AND
AGC
CHROMA
DEMOD
FSC
RECOVERY
CVBS/Y
MACROVISION
DETECTION
CHROMA
RESAMPLE
RESAMPLE
CONTROL
LUMA
RESAMPLE
CHROMA
2D COMB
(4H MAX)
LUMA
2D COMB
(5H MAX)
GAIN
CONTROL
OFFSET
CONTROL
CGMS DATA
EXTRACTION
Cb
Cr
Y
Cb
Cr
Y
AV CODE
INSERTION
FAST
BLANK
OVERLAY
CONTROL
AND
AV CODE
INSERTION
VBI DATA RECOVERY
COMPONENT PROCESSOR
MACROVISION
DETECTION
CHROMA
FILTER
SYNC
EXTRACT
LUMA
FILTER
STANDARD
AUTODETECTION
STANDARD DEFINITION PROCESSOR
24
16
8
8
8
INT
SFL/
SYNCOUT
LLC1
FIELD/DE
VS
HS
PIXEL
DATA
P29–P22
P19–P12
P9–P2
ADV7401
FUNCTIONAL BLOCK DIAGRAM
OUTPUT FIFO AND FORMATTER
ADV7401
ELECTRICAL CHARACTERISTICS
@ AVDD = 3.15 V to 3.45 V, DVDD = 1.65 V to 2.0 V, DVDDIO = 3.0 V to 3.6 V, PVDD = 1.71 V to 1.89 V, nominal input range 1.6 V.
Operating temperature range, unless otherwise noted.
Table 1.
Parameter 1, 2 , 3
STATIC PERFORMANCE 4 , 5
Resolution (each ADC)
Integral Nonlinearity
Integral Nonlinearity
Integral Nonlinearity
Integral Nonlinearity
Integral Nonlinearity
Differential Nonlinearity
Differential Nonlinearity
Differential Nonlinearity
Differential Nonlinearity
Differential Nonlinearity
DIGITAL INPUTS 8
Input High Voltage 9
Input Low Voltage 10
Input High Voltage
Input Low Voltage
Input Current
Symbol
Test Conditions
N
INL
INL
INL
INL
INL
DNL
DNL
DNL
DNL
DNL
BSL at 27 MHz (at a 10-bit level)
BSL at 54 MHz (at a 10-bit level)
BSL at 74 MHz (at a 10-bit level)
BSL at 110 MHz (at an 8-bit level) 6
BSL at 135 MHz (at an 8-bit level) 7
At 27 MHz (at a 10-bit level)
At 54 MHz (at a 10-bit level)
At 74 MHz (at a 10-bit level)
At 110 MHz (at an 8-bit level)6
At 135 MHz (at an 8-bit level)7
Input Capacitance8
DIGITAL OUTPUTS
Output High Voltage 12
Output Low Voltage12
High Impedance Leakage Current
CIN
Output Capacitance8
POWER REQUIREMENTS8
Digital Core Power Supply
Digital I/O Power Supply
PLL Power Supply
Analog Power Supply
Digital Core Supply Current
VIH
VIL
VIH
VIL
IIN
VOH
VOL
ILEAK
Min
Typ
±0.6
−0.6/+0.7
±1.4
±0.9
±1.5
−0.2/+0.25
−0.2/+0.25
±0.9
−0.2/+1.5
−0.9/+3.0
Digital I/O Supply Current
IDVDDIO
PLL Supply Current
IPVDD
Analog Supply Current 14
IAVDD
Power-Down Current
Green Mode Power-Down
Power-Up Time
IPWRDN
IPWRDNG
TPWRUP
Unit
10
±2.5
Bits
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
−0.99/+2.5
2
0.3
+60
+10
10
V
V
V
V
μA
μA
pF
0.4
60
10
20
V
V
μA
μA
pF
0.8
HS_IN, VS_IN low trigger mode
HS_IN, VS_IN low trigger mode
Pins listed in Note 11
All other input pins
ISOURCE = 0.4 mA
ISINK = 3.2 mA
Pins listed in Note 13
All other output pins
0.7
−60
−10
2.4
COUT
DVDD
DVDDIO
PVDD
AVDD
IDVDD
Max
1.65
3.0
1.71
3.15
CVBS input sampling at 54 MHz
Graphics RGB sampling at 135 MHz
SCART RGB FB sampling at 54 MHz
CVBS input sampling at 54 MHz
Graphics RGB sampling at 135 MHz
CVBS input sampling at 54 MHz
Graphics RGB sampling at 135 MHz
CVBS input sampling at 54 MHz
Graphics RGB sampling at 135 MHz
SCART RGB FB sampling at 54 MHz
Sync bypass function
1
1.8
3.3
1.8
3.3
105
137
106
4
19
11
12
99
242
269
2.25
16
20
2
3.6
1.89
3.45
V
V
V
V
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
ms
The min/max specifications are guaranteed over this range.
Temperature range TMIN to TMAX: −40°C to +85°C (0°C to 70°C temperature range for ADV7401KSTZ-140).
3
All specifications obtained using programming scripts with the following sequence included: Addr 0x0E - data 0x80, Addr 0x54 - data 0x00, Addr 0x0E - data 0x00.
4
All ADC linearity tests performed at input range of full scale – 12.5%, and at zero scale + 12.5%.
2
Rev. SpA | Page 4 of 20
ADV7401
5
Max INL and DNL specifications obtained with part configured for component video input.
Specification for ADV7401BSTZ-110 and ADV7401KSTZ-140 only.
7
Specification for ADV7401KSTZ-140 only.
8
Guaranteed by characterization.
9
To obtain specified VIH level on Pin 38, Register 0x13 (wo) must be programmed with value 0x04. If Register 0x13 is programmed with value 0x00,
then VIH on Pin 38 = 1.2 V.
10
To obtain specified VIL level on Pin 38, Register 0x13 (wo) must be programmed with value 0x04. If Register 0x13 is programmed with value 0x00,
then VIL on Pin 38 = 0.4 V.
11
Pins 1, 2, 13, 14, 16, 19, 24, 29, 30, 31, 32, 33, 34, 35, 45, 79, 83, 84, 87, 88, 95, 96, 97, 100.
12
VOH and VOL levels obtained using default drive strength value (0xD5) in Register Subaddress 0xF4.
13
Pins 3, 13, 14, 19, 24, 29, 30, 31, 32, 33, 34, 45.
14
Analog current measurements for CVBS made with ADC0 powered up only, For RGB, ADC0, ADC1 and ADC2 powered up only, for SCART FB, all ADCs powered up.
6
Rev. SpA | Page 5 of 20
ADV7401
VIDEO SPECIFICATIONS
@ AVDD= 3.15 V to 3.45 V, DVDD = 1.65 V to 2.0 V, DVDDIO = 3.0 V to 3.6 V, PVDD = 1.71 V to 1.89 V. Operating temperature range,
unless otherwise noted.
Table 2.
Parameter 1, 2 , 3
NONLINEAR SPECIFICATIONS
Differential Phase
Differential Gain
Luma Nonlinearity
NOISE SPECIFICATIONS
SNR Unweighted
SNR Unweighted
Analog Front End Crosstalk
LOCK TIME SPECIFICATIONS
Horizontal Lock Range
Vertical Lock Range
FSC Subcarrier Lock Range
Color Lock in Time
Sync Depth Range 4
Color Burst Range
Vertical Lock Time
Horizontal Lock Time
CHROMA SPECIFICATIONS
Hue Accuracy
Color Saturation Accuracy
Color AGC Range
Chroma Amplitude Error
Chroma Phase Error
Chroma Luma Intermodulation
LUMA SPECIFICATIONS
Luma Brightness Accuracy
Luma Contrast Accuracy
Symbol
Test Conditions
DP
DG
LNL
CVBS input, modulated 5 step
CVBS input, modulated 5 step
CVBS input, 5 step
Luma ramp
Luma flat field
Min
54
58
Typ
Max
0.5
0.5
0.5
degree
%
%
56
60
60
dB
dB
dB
−5
40
+5
70
±1.3
60
20
5
200
200
2
100
HUE
CL_AC
1
1
1
The min/max specifications are guaranteed over this range.
Temperature range TMIN to TMAX: −40°C to +85°C (0°C to 70°C temperature range for ADV7401KSTZ-140).
3
Guaranteed by characterization.
4
Nominal sync depth is 300 mV at 100% sync depth range.
2
Rev. SpA | Page 6 of 20
%
Hz
kHz
line
%
%
field
line
0.5
0.4
0.2
degree
%
%
%
degree
%
1
1
%
%
5
CVBS, 1 V input
CVBS, 1 V input
Unit
400
ADV7401
TIMING CHARACTERISTICS
@ AVDD = 3.15 V to 3.45 V, DVDD = 1.65 V to 2.0 V, DVDDIO = 3.0 V to 3.6 V, PVDD = 1.71 V to 1.89 V. Operating temperature range,
unless otherwise noted.
Table 3.
Parameter 1, 2 , 3
SYSTEM CLOCK AND CRYSTAL
Crystal Nominal Frequency
Crystal Frequency Stability
Horizontal Sync Input Frequency
LLC1 Frequency Range 4
I2C PORT 5
SCLK Frequency
SCLK Min Pulse Width High
SCLK Min Pulse Width Low
Hold Time (Start Condition)
Setup Time (Start Condition)
SDA Setup Time
SCLK and SDA Rise Time
SCLK and SDA Fall Time
Setup Time for Stop Condition
RESET FEATURE
Reset Pulse Width
CLOCK OUTPUTS
LLC1 Mark Space Ratio
DATA and CONTROL OUTPUTS
Data Output Transition Time SDR (SDP) 6
Symbol
Test Conditions
Min
Typ
Max
Unit
±50
110
140
MHz
ppm
kHz
MHz
28.63636
14.8
12.825
400
t1
t2
t3
t4
t5
t6
t7
t8
0.6
1.3
0.6
0.6
100
300
300
0.6
5
t9:t10
t11
Data Output Transition Time SDR (SDP)6
t12
Data Output Transition Time SDR (CP) 7
t13
Data Output Transition Time SDR (CP)7
t14
Data Output Transition Time DDR (CP)7, 8
t15
Data Output Transition Time DDR (CP)7, 8
t16
Data Output Transition Time DDR (CP)7, 8
t17
Data Output Transition Time DDR (CP)7, 8
t18
DATA and CONTROL INPUTS5
Input Setup Time (Digital Input Port)
t19
Input Hold Time (Digital Input Port)
t20
45:55
Negative clock edge
to start of valid data
End of valid data to
negative clock edge
End of valid data to
negative clock edge
Negative clock edge
to start of valid data
Positive clock edge to
end of valid data
Positive clock edge to
start of valid data
Negative clock edge
to end of valid data
Negative clock edge
to start of valid data
HS_IN, VS_IN
DE_IN, data inputs
HS_IN, VS_IN
DE_IN, data inputs
1
Rev. SpA | Page 7 of 20
ms
55:45
% duty cycle
3.6
ns
2.4
ns
2.8
ns
0.1
ns
−4 + TLLC1/4
ns
0.25 + TLLC1/4
ns
−2.95 + TLLC1/4
ns
−0.5 + TLLC1/4
ns
9
2.2
7
2
ns
ns
ns
ns
The min/max specifications are guaranteed over this range.
Temperature range TMIN to TMAX: −40°C to +85°C (0°C to 70°C temperature range for ADV7401KSTZ-140).
3
Guaranteed by characterization.
4
Maximum LLC1 frequency is 80 MHz for ADV7401BSTZ-80 and is 110 MHz for ADV7401BSTZ-110.
5
TTL input values are 0 V to 3 V, with rise/fall times ≤3 ns, measured between the 10% and 90% points.
6
SDP timing figures obtained using default drive strength value (0xD5) in Register Subaddress 0xF4.
7
CP timing figures obtained using max drive strength value (0xFF) in register subaddress 0xF4.
8
DDR timing specifications dependent on LLC1 output pixel clock; TLCC1/4 = 9.25 ns at LLC1 = 27 MHz.
2
kHz
μs
μs
μs
μs
ns
ns
ns
μs
ADV7401
ANALOG SPECIFICATIONS
@ AVDD = 3.1.5 V to 3.45 V, DVDD = 1.65 V to 2.0 V, DVDDIO = 3.0 V to 3.6 V, PVDD = 1.71 V to 1.89 V. Operating temperature
range, unless otherwise noted. Recommended analog input video signal range: 0.5 V to 1.6 V, typically 1 V p-p.
Table 4.
Parameter 1, 2 , 3
CLAMP CIRCUITRY
External Clamp Capacitor
Input Impedance 4
Input Impedance of Pin 51 (FB)
CML
ADC Full-Scale Level
ADC Zero-Scale level
ADC Dynamic Range
Clamp Level (When Locked)
Large Clamp Source Current
Large Clamp Sink Current
Fine Clamp Source Current
Fine Clamp Sink Current
Test Conditions
Clamps switched off
CVBS input
SCART RGB input (R, G, B signals)
S-Video input (Y signal)
S-Video input (C signal)
Component input (Y, Pr, Pb signals)
PC RGB input (R, G, B signals)
SDP only
SDP only
SDP only
SDP only
1
The min/max specifications are guaranteed over this range.
Temperature range TMIN to TMAX: −40°C to +85°C (0°C to 70°C temperature range for ADV7401KSTZ-140).
Guaranteed by characterization.
4
Except Pin 51 (FB).
2
3
Rev. SpA | Page 8 of 20
Min
Typ
0.1
10
20
1.86
CML + 0.8 V
CML − 0.8 V
1.6
CML – 0.292 V
CML – 0.4 V
CML – 0.292 V
CML – 0 V
CML – 0.3 V
CML – 0.3 V
0.75
0.9
17
17
Max
Unit
μF
MΩ
kΩ
V
V
V
V
V
V
V
V
V
V
mA
mA
μA
μA
ADV7401
ABSOLUTE MAXIMUM RATINGS
Table 5.
Parameter
AVDD to AGND
DVDD to DGND
PVDD to AGND
DVDDIO to DGND
DVDDIO to AVDD
PVDD to DVDD
DVDDIO to PVDD
DVDDIO to DVDD
AVDD to PVDD
AVDD to DVDD
Digital Inputs Voltage to
DGND
Digital Outputs Voltage to
DGND
Analog Inputs to AGND
Maximum Junction
Temperature (TJ MAX)
Storage Temperature Range
Infrared Reflow Soldering
(20 sec)
STRESS RATINGS
Rating
4V
2.2 V
2.2 V
4V
−0.3 V to +0.3 V
−0.3 V to +0.3 V
−0.3 V to +2 V
−0.3 V to +2 V
−0.3 V to +2 V
−0.3 V to +2 V
DGND − 0.3 V to DVDDIO + 0.3 V
DGND − 0.3 V to DVDDIO + 0.3 V
AGND − 0.3 V to AVDD + 0.3 V
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
PACKAGE THERMAL PERFORMANCE
To reduce power consumption when using the part the user is
advised to turn off any unused ADCs .
The junction temperature must always stay below the
maximum junction temperature (TJ MAX) of 125°C. This
equation shows how to calculate the junction temperature:
TJ = TA Max + (θJA × WMax)
125°C
−65°C to +150°C
where:
TA Max = 85°C.
θJA = 30°C/W.
WMax = ((AVDD × IAVDD) + (DVDD × IDVDD) +
(DVDDIO × IDVDDIO) + (PVDD × IPVDD)).
260°C
THERMAL SPECIFICATIONS
Table 6.
Thermal Characteristics
Junction-to-Case Thermal Resistance
Junction-to-Ambient Thermal Resistance
Symbol
θJC
θJA
Test Conditions
4-layer PCB with solid ground plane
4-layer PCB with solid ground plane (still air)
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the
human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Rev. SpA | Page 9 of 20
Typ
7
30
Unit
°C/W
°C/W
ADV7401
1
P31
2
INT
P39
P40
SCLK1
SDA1
ALSB
84
83
82
81
80
SOY
VS_IN
85
AIN6
HS_IN/CS_IN
86
76
P38
87
77
P37
88
DE_IN
DGND
89
RESET
DVDD
90
78
P19
91
79
P17
P16
94
P18
P36
95
92
P35
96
93
FIELD/DE
P34
97
VS
98
P33
100
P32
99
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
75
AIN12
74
AIN5
3
73
AIN11
CS/HS
4
72
AIN4
DGND
5
71
AIN10
DVDDIO
6
70
TEST0
P15
7
69
CAPC2
P14
8
68
CAPC1
P13
9
67
BIAS
66
AGND
PIN 1
ADV7401
P12
10
DGND
11
65
CML
DVDD
12
64
REFOUT
LQFP
TOP VIEW
(Not to Scale)
44
45
46
47
48
49
50
P0
P20
ELPF
PVDD
PVDD
AGND
AGND
05340-002
43
P1
FB
42
51
P2
25
41
SOG
P7
P3
52
40
24
DGND
AIN7
P27
39
53
DVDD
23
38
AIN1
P8
XTAL
54
37
22
XTAL1
AIN8
P9
36
55
35
21
LLC1
AIN2
P10
DCLK_IN
56
34
20
P21
AIN9
P11
33
57
P22
19
32
AIN3
SDA2
P23
58
31
18
30
TEST1
DVDDIO
P25
59
P24
17
29
AGND
DGND
P26
60
28
16
P4
CAPY1
SCLK2
27
61
SFL/SYNC_OUT
26
CAPY2
15
14
P6
AVDD
13
P28
P5
63
62
P29
Figure 2. Pin Configuration
Table 7. Pin Function Descriptions
Pin No.
5, 11, 17, 40, 89
49, 50, 60, 66
6, 18
12, 39, 90
63
47, 48
51
Mnemonic
DGND
AGND
DVDDIO
DVDD
AVDD
PVDD
FB
Type
G
G
P
P
P
P
I
54, 56, 58, 72, 74, 76, 53, 55,
57, 71, 73, 75
42, 41, 28, 27, 26, 25, 23, 22,
10, 9, 8, 7, 94, 93, 92, 91
33, 32, 31, 30, 29, 24, 14, 13
44, 43, 21, 20, 45, 34, 2, 1,
100, 97, 96, 95, 88, 87, 84, 83
3
AIN1 to AIN12
I
Function
Digital Ground.
Analog Ground.
Digital I/O Supply Voltage (3.3 V).
Digital Core Supply Voltage (1.8 V).
Analog Supply Voltage (3.3 V).
PLL Supply Voltage (1.8 V).
Fast Switch Overlay Input. This pin switches between CVBS and RGB
analog signals.
Analog Video Input Channels.
P2 to P9, P12 to P19
O
Video Pixel Output Port.
P22 to P29
P0 to P1, P10 to P11,
P20 to P21, P31 to P40
INT
I/O
I
Video Input/Output Port
Video Pixel Input Port.
O
Interrupt. This pin can be active low or active high. When SDP/CP status
bits change this pin triggers. The set of events that triggers an interrupt
is under user control.
Rev. SpA | Page 10 of 20
ADV7401
Pin No.
4
Mnemonic
HS/CS
Type
O
99
98
VS
FIELD/DE
O
O
81, 19
SDA1, SDA2
I/O
82, 16
SCLK1, SCLK2
I
80
ALSB
I
78
RESET
I
36
LLC1
O
38
XTAL
I
37
XTAL1
O
46
70
59
15
ELPF
TEST0
TEST1
SFL/SYNC_OUT
O
NC
O
O
64
65
61, 62
68, 69
67
REFOUT
CML
CAPY1, CAPY2
CAPC1, CAPC2
BIAS
O
O
I
I
O
86
HS_IN/CS_IN
I
85
79
VS_IN
DE_IN
I
I
35
DCLK_IN
I
52
77
SOG
SOY
I
I
Function
HS is a Horizontal Synchronization Output Signal (SDP and CP modes).
CS is a Digital Composite Synchronization Signal (and can be selected
while in CP mode).
Vertical Synchronization Output Signal (SDP and CP modes).
Field Synchronization Output Signal (all interlaced video modes). This
pin also can be enabled as a Data Enable signal (DE) in CP mode to allow
direct connection to a HDMI/DVI Tx IC.
I2C Port Serial Data Input/Output Pins. SDA1 is the data line for the
control port and SDA2 is the data line for the VBI readback port.
I2C Port Serial Clock Input (max clock rate of 400 kHz). SCLK1 is the clock
line for the control port and SCLK2 is the clock line for the VBI data
readback port.
This pin selects the I2C address for the ADV7401 control and VBI
readback ports. ALSB set to Logic 0 sets the address for a write to control
port of 0x40 and the readback address for the VBI port of 0x21. ALSB set
to a logic high sets the address for a write to control port of 0x42 and the
readback address for the VBI port of 0x23.
System Reset Input, Active Low. A minimum low reset pulse width of 5
ms is required to reset the ADV7401 circuitry.
LLC1 is a line-locked output clock for the pixel data (range is 12.825 MHz
to 140 MHz for ADV7401KSTZ-140; 12.825 MHz to 110 MHz for
ADV7401BSTZ-110; 12.825 MHz to 80 MHz for ADV7401BSTZ-80).
Input pin for 28.63636 MHz crystal, or can be overdriven by an external
3.3 V 28.63636 MHz clock oscillator source to clock the ADV7401.
This pin should be connected to the 28.63636 MHz crystal or left as a no
connect if an external 3.3 V 28.63636 MHz clock oscillator source is used
to clock the ADV7401. In crystal mode, the crystal must be a
fundamental crystal.
The recommend external loop filter must be connected to this ELPF pin.
This pin should be left unconnected or alternatively tied to AGND.
This pin should be left unconnected.
Subcarrier Frequency Lock (SFL). This pin contains a serial output stream
which can be used to lock the subcarrier frequency when this decoder is
connected to any Analog Devices digital video encoder. SYNC_OUT is
the sliced sync output signal available only in CP mode.
Internal Voltage Reference Output.
Common-Mode Level Pin (CML) for the internal ADCs.
ADC Capacitor Network.
ADC Capacitor Network.
External Bias Setting Pin. Connect the recommended resistor (1.35 kΩ)
between pin and ground.
Can be configured in CP mode to be either a digital HS input signal or a
digital CS input signal used to extract timing in a 5-wire or 4-wire RGB
mode.
VS Input Signal. Used in CP mode for 5-wire timing mode.
Data Enable Input Signal. Used in 24-bit digital input port mode (for
example, processing 24-bit RGB data from a DVI Rx IC).
Clock Input Signal. Used in 24-bit digital input mode (for example,
processing 24-bit RGB data from a DVI Rx IC) and also in digital CVBS
input mode.
Sync on Green Input. Used in embedded sync mode.
Sync on Luma Input. Used in embedded sync mode.
Rev. SpA | Page 11 of 20
ADV7401
TIMING DIAGRAMS
t3
t5
t3
SDA1/SDA2
t1
SCLK1/SCLK2
t2
t7
t4
t8
05340-003
t6
Figure 3. I2C Timing
t9
t10
LLC1
t11
t12
05340-004
P2–P9, P12–P19,
P22–P29, VS, HS,
FIELD/DE,
SFL/SYNC_OUT
Figure 4. Pixel Port and Control SDR Output Timing (SD Core)
t9
t10
LLC1
t13
05340-005
t14
P2–P9, P12–P19,
P22–P29
Figure 5. Pixel Port and Control SDR Output Timing (CP Core)
LLC1
t18
t15
t17
P6–P9,
P12–P19
05340-006
t16
Figure 6. Pixel Port and Control DDR Output Timing (CP Core)
DCLK_IN
t9
t20
HS_IN
VS_IN
DE_IN
P0–P1, P10–P11,
P20–P21, P22–P29,
P31–P32, P33–P40
t19
Figure 7. Digital Input Port and Control Input Timing
Rev. SpA | Page 12 of 20
05340-008
CONTROL
INPUTS
t10
ADV7401
DETAILED FUNCTIONALITY
•
Four high quality 10-bit ADCs enable true 8-bit video
decoder
Proprietary architecture for locking to weak, noisy, and
unstable sources from VCRs and tuners
•
12 analog input channel mux enables multisource
connection without the requirement of an external mux
IF filter block compensates for high frequency luma
attenuation due to tuner SAW filter
•
Chroma transient improvement (CTI)
•
Luminance digital noise reduction (DNR)
•
Color controls include hue, brightness, saturation, contrast,
and Cr and Cb offset controls
•
Certified Macrovision copy protection detection on
composite and S-video for all worldwide formats
(PAL/NTSC/SECAM)
•
4× oversampling (54 MHz) for CVBS, S-video, and YUV
modes
•
Line-locked clock output (LLC)
•
Letterbox detection supported
•
Free-run output mode provides stable timing when no
video input is present
•
Vertical blanking interval data processor
ANALOG FRONT END
•
•
•
Four current and voltage clamp control loops ensure any
dc offsets are removed from the video signal
•
SCART functionality and SD RGB overlay on CVBS
controlled by fast blank input
•
Four internal antialias filters to remove out-of-band noise
on standard definition input video signals
SDP PIXEL DATA OUTPUT MODES
•
8-bit ITU-R BT.656 4:2:2 YCrCb with embedded time
codes and/or HS, VS, and FIELD
•
16-bit YCrCb with embedded time codes and/or HS, VS,
and FIELD
•
24-bit YCrCb with embedded time codes and/or HS, VS,
and FIELD
CP PIXEL DATA OUTPUT MODES
•
Single data rate (SDR) 8-bit 4:2:2 YCrCb for 525i, 625i
•
Single data rate (SDR) 16-bit 4:2:2 YCrCb for all standards
•
Single data rate (SDR) 24-bit 4:4:4 YCrCb/RGB for all
standards
•
Double data rate (DDR) 8-bit 4:2:2 YCrCb for all standards
•
Double data rate (DDR) 12-bit 4:4:4 YCrCb/RGB for all
standards
TeleText
Video Programming System (VPS)
Vertical Interval Time Codes (VITC)
Closed captioning (CC) and extended data service (EDS)
Wide screen signaling (WSS)
Copy generation management system (CGMS)
Gemstar™ 1×/2× electronic program guide compatible
•
Clocked from a single 28.63636 MHz crystal
•
Subcarrier frequency lock (SFL) output for downstream
video encoder
•
Differential gain typically 0.5%
•
Differential phase typically 0.5°
COMPOSITE AND S-VIDEO PROCESSING
•
Support for NTSC (J, M, 4.43), PAL (B, D, I, G, H, M, N,
60) and SECAM B/D/G/K/L standards in the form of
CVBS and S-video
•
Superadaptive 2D 5-line comb filters for NTSC and PAL
give superior chrominance and luminance separation for
composite video
•
Full automatic detection and autoswitching of all
worldwide standards (PAL/NTSC/SECAM)
•
Automatic gain control with white peak mode ensures the
video is always processed without loss of the video
processing range
•
Adaptive digital line length tracking (ADLLT™)
Rev. SpA | Page 13 of 20
ADV7401
COMPONENT VIDEO PROCESSING
DIGITAL VIDEO INPUT PORT
•
Formats supported include 525i, 625i, 525p, 625p, 720p,
1080i, and many other HDTV formats
•
Supports raw 8-bit CVBS data from digital tuner
•
•
Automatic adjustments include gain (contrast) and offset
(brightness); manual adjustment controls are also
supported
Support for 24-bit RGB input data from DVI Rx chip,
output converted to YCrCb 4:2:2
•
Support for 24-bit 4:4:4, 16-bit 4:2:2 525i, 625i, 525p, 625p,
1080i, 720p, VGA to SXGA @ 60 Hz input data from
HDMI Rx chip, output converted to 16-bit 4:2:2 YCrCb
•
Support for analog component YPrPb/RGB video formats
with embedded sync or with separate HS, VS, or CS
•
Any-to-any, 3 × 3 color space conversion matrix supports
YCrCb-to-RGB and RGB-to-YCrCb
•
HS, VS, and FIELD output signals with programmable
position, polarity, and width
•
Standard identification (STDI) enables system level
component format detection
•
Programmable interrupt request output pin, INT, signals
SDP/CP status changes
•
Synchronization source polarity detector (SSPD) determines the source and polarity of the synchronization
signals that accompany the input video
•
Supports two I2C host port interfaces (control and VBI)
•
Low power consumption: 1.8 V digital core, 3.3 V analog
and digital I/O, low power power-down mode, and green
PC mode
•
Industrial temperature range (−40°C to +85°C)
(except ADV7401KSTZ-140)
•
140 MHz speed grade (ADV7401KST-140)
•
100-lead, 14 mm × 14 mm, Pb-free LQFP
•
Certified Macrovision copy protection detection on
component formats (525i, 625i, 525p, and 625p)
•
Free-run output mode provides stable timing when no
video input is present
•
Arbitrary pixel sampling support for nonstandard video
sources
GENERAL FEATURES
RGB GRAPHICS PROCESSING
•
140 MSPS conversion rate supports RGB input resolutions
up to 1280 × 1024 @ 75 Hz (SXGA); (110 MSPS conversion
rate for ADV7401BSTZ-110); (80 MSPS conversion rate for
ADV7401BSTZ-80)
•
Automatic or manual clamp and gain controls for graphics
modes
•
Contrast and brightness controls
•
32-phase DLL allows optimum pixel clock sampling
•
Automatic detection of sync source and polarity by SSPD
block
•
Standard identification is enabled by STDI block
•
RGB can be color space converted to YCrCb and
decimated to a 4:2:2 format for video centric backend IC
interfacing
•
Data enable (DE) output signal supplied for direct
connection to HDMI/DVI Tx IC
•
Arbitrary pixel sampling support for nonstandard video
sources
Rev. SpA | Page 14 of 20
ADV7401
DETAILED DESCRIPTION
ANALOG FRONT END
The ADV7401 analog front end comprises four 10-bit ADCs
that digitize the analog video signal before applying it to the
SDP or CP (see Table 8 for sampling rates). The analog front
end uses differential channels to each ADC to ensure high
performance in a mixed-signal application.
The front end also includes a 12-channel input mux that enables
multiple video signals to be applied to the ADV7401. Current
and voltage clamps are positioned in front of each ADC to
ensure that the video signal remains within the range of the
converter. Fine clamping of the video signals is performed
downstream by digital fine clamping in either the CP or SDP.
Optional antialiasing filters are positioned in front of each
ADC. These filters can be used to band-limit standard
definition video signals, removing spurious, out-of-band noise.
The ADCs are configured to run in 4× oversampling mode
when decoding composite and S-video inputs; 2× oversampling
is performed for component 525i, 625i, 525p, and 625p sources.
All other video standards are 1× oversampled. Oversampling
the video signals reduces the cost and complexity of external
anti-aliasing filters with the benefit of an increased signal-tonoise ratio (SNR).
The ADV7401 can support simultaneous processing of CVBS
and RGB standard definition signals to enable SCART compatibility and overlay functionality. A combination of CVBS and
RGB inputs can be mixed and output under control of I2C
registers and the fast blank pin.
Table 8. Maximum ADC Sampling Rates
Model
ADV7401BSTZ-80
ADV7401BSTZ-110
ADV7401KSTZ-140
The SDP has an IF filter block that compensates for attenuation
in the high frequency luma spectrum due to tuner SAW filter.
The SDP has specific luminance and chrominance parameter
control for brightness, contrast, saturation, and hue.
The ADV7401 implements a patented adaptive-digital-linelength-tracking (ADLLT) algorithm to track varying video
line lengths from sources such as a VCR. ADLLT enables the
ADV7401 to track and decode poor quality video sources
such as VCRs, noisy sources from tuner outputs, VCD players,
and camcorders. The SDP also contains a chroma transient
improvement (CTI) processor. This processor increases the
edge rate on chroma transitions, resulting in a sharper
video image.
The SDP can process a variety of VBI data services, such as
TeleText, closed captioning (CC), wide screen signaling (WSS),
video programming system (VPS), vertical interval time codes
(VITC), copy generation management system (CGMS),
Gemstar 1×/2×, and extended data service (XDS). The
ADV7401 SDP section has a Macrovision 7.1 detection circuit
that allows it to detect Types I, II, and III protection levels. The
decoder is also fully robust to all Macrovision signal inputs.
COMPONENT PROCESSOR
The CP section is capable of decoding/digitizing a wide range of
component video formats in any color space. Component video
standards supported by the CP are 525i, 625i, 525p, 625p, 720p,
1080i, 1250i, VGA up to SXGA @ 75 Hz (ADV7401KSTZ-140
only), and many other standards not listed here.
The CP section of the ADV7401 contains an AGC block.
When no embedded sync is present, the video gain can be set
manually. The AGC section is followed by a digital clamp
circuit that ensures the video signal is clamped to the correct
blanking level. Automatic adjustments within the CP include
gain (contrast) and offset (brightness); manual adjustment
controls are also supported.
Maximum ADC Sampling Rate
80 MHz
110 MHz
140 MHz
STANDARD DEFINITION PROCESSOR (SDP)
The SDP section is capable of decoding a large selection of
baseband video signals in composite S-video and YUV formats.
The video standards supported by the SDP include PAL
B/D/I/G/H, PAL60, PAL M, PAL N, NTSC M/J, NTSC 4.43, and
SECAM B/D/G/K/L. The ADV7401 can automatically detect
the video standard and process it accordingly.
A fully programmable, any-to-any, 3 × 3 color space conversion
matrix is placed between the analog front end and the CP
section. This enables YPrPb-to-RGB and RGB-to-YCrCb
conversions. Many other standards of color space can be
implemented using the color space converter.
The SDP has a 5-line superadaptive 2D comb filter that gives
superior chrominance and luminance separation when decoding a composite video signal. This highly adaptive filter automatically adjusts its processing mode according to video
standard and signal quality with no user intervention required.
Rev. SpA | Page 15 of 20
ADV7401
The output section of the CP is highly flexible. It can be configured in single data rate mode (SDR) with one data packet per
clock cycle or in a double data rate (DDR) mode where data is
presented on the rising and falling edges of the clock. In SDR
mode, a 16-bit 4:2:2 or 24-bit 4:4:4 output is possible. In these
modes HS, VS, and FIELD/DE (where applicable) timing reference signals are provided. In DDR mode, the ADV7401 can be
configured in an 8-bit 4:2:2 YCrCb or 12-bit 4:4:4 RGB/ YCrCb
pixel output interface with corresponding timing signals.
The ADV7401 is capable of supporting an external DVI/
HDMI receiver. The digital interface expects 24-bit 4:4:4 or
16-bit 4:2:2 bit data (either graphics RGB or component video
YCrCb), accompanied by HS, VS, DE, and a fully synchronous
clock signal. The data is processed in the CP and output as
16-bit 4:2:2 YCrCb data.
The CP section contains circuitry to enable the detection of
Macrovision encoded YPrPb signals for 525i, 625i, 525p, and
625p. It is designed to be fully robust when decoding these
types of signals.
VBI extraction of CGMS data is performed by the CP section
of the ADV7401 for interlaced, progressive, and high definition
scanning rates. The data extracted can be read back over the
I2C interface. For more detailed product information about the
ADV7401, contact your local ADI sales office or email
[email protected]
Rev. SpA | Page 16 of 20
ADV7401
PIXEL INPUT/OUTPUT FORMATTING
Table 9. SDP, CP Pixel Input/Output Pin Map (P19 to P0)
Processor, Format,
and Mode
19
SDP
Video out, 8-bit,
4:2:2
SDP
Video out,
16-bit, 4:2:2
SDP
Video out,
24-bit, 4:4:4
SM-SDP
Digital tuner
input[1]
CP
8-bit, 4:2:2, DDR D7
CP
12-bit, 4:4:4, RGB D7
DDR
CP
Video out,
16-bit, 4:2:2
CP
Video out,
24-bit, 4:4:4
SM-CP
HDMI receiver
support, 24-bit,
4:4:4 input
SM-CP
HDMI receiver
support, 16-bit,
pass-through
18
17
16 15 14
YCrCb[7:0]OUT
13
12
Pixel Port Pins P[19:0]
11 10 9
8
7
-
6
5
-
4
-
3
-
2
-
-
1
CP
CP
CP
SM-CP
SM-CP
12-bit, 4:4:4, RGB
DDR
Video out, 16-bit,
4:2:2
Video out, 24-bit,
4:4:4 input
HDMI receiver
support, 24-bit,
4:4:4 input
HDMI receiver
support, 16-bit,
pass-through
40
-
0
-
Y[7:0]OUT
-
-
CrCb[7:0]OUT
-
-
Y[7:0]OUT
-
-
Cb[7:0]OUT
-
-
-
-
Output choices are the same as video out 16-bit or pseudo 8-bit DDR
D6
D6
D5
D5
D4
D4
D3
D3
D2
D2
D1
D1
D0
D0
-
-
CHA[7:0]OUT (for example, Y[7:0])
-
-
CHB/C[7:0]OUT (for example, Cr/Cb[7:0])
-
-
CHA[7:0]OUT (for example, G[7:0])
-
-
CHB[7:0]OUT (for example, B[7:0])
-
-
CHA[7:0]OUT (for example, Y[7:0])
D11
R[5:4]IN
CHA[7:0]OUT (for example, Y[7:0])
-
-
D10
D9
D8
-
-
-
-
CHB/C[7:0]OUT (for example, Cr/Cb[7:0])
R[1:0]IN
CHB/C[7:0]OUT (for example, Cr/Cb[7:0])
-
Table 10. SDP, CP Pixel Input/Output Pin Map (P40 to P20)
Processor, Format,
and Mode
SDP
Video out, 8-bit,
4:2:2
SDP
Video out, 16-bit,
4:2:2
SDP
Video out, 24-bit,
4:4:4
SM-SDP Digital tuner
input[1]
CP
8-bit, 4:2:2, DDR
-
39 38 37
-
36
-
35
-
Pixel Port Pins P[40:31], P[29:20]
34 33 32 31 29 28 27 26 25 24 23 22
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
DCVBS[7:0]IN
-
-
-
-
-
-
-
-
21 20
-
-
-
-
-
-
-
Cr[7:0]OUT
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
G[7:0]IN
CHA[7:0]IN
R[7:6]IN
-
-
Rev. SpA | Page 17 of 20
CHC[7:0]OUT (for example, R[7:0])
B[7:0]IN
CHB/C[7:0]IN
R[3:2]IN
-
-
-
ADV7401
RECOMMENDED EXTERNAL LOOP FILTER
COMPONENTS
The external loop filter components for the ELPF pin should
be placed as close as possible to the respective pins. Figure 8
shows the recommended component values.
PIN 46–ELPF
1.69kΩ
10nF
PVDD = 1.8V
05340-007
82nF
Figure 8. ELPF Components
Rev. SpA | Page 18 of 20
Rev. SpA | Page 19 of 20
05340-009
RGB
GRAPHICS
F_BLNK
BLUE
GREEN
RED/C
3
1LOAD
AGND
2
4
Y
C
AGND
19Ω
AGND
0.1 μF
0.1μF
0.1μF
0.1μF
0.1μF
0.1μF
0.1μF
0.1μF
0.1μF
AGND
10nF
Y
19Ω
75Ω
0.1μF
75Ω
Pb/Pr
75Ω
0.1μF
75Ω
Pr/Pb
56Ω
CAP VALUES ARE DEPENDANT ON CRYSTAL ATTRIBUTES
56Ω
1
2
3
4
0.1μF
MINI-DIN-4
1
P7
1
2
3
4
5
6
20 CVBS/Y
16
2
11
15
75Ω
PHONO3
AGND
RED
S-VIDEO
19
17
15
13
11
9
7
5
3
1
75Ω
GREEN
BLUE
CVBS 19Ω
P9
P8
20
18
16
14
12
10
8
6
4
2
21
P4
SCART_21_PIN
VS_IN
P5–14
P6–5
P6–6
P5–7
P5–8
P5–10
HS_IN
P5–13
P5–1
P5–3
P5–2
75Ω
AGND
75Ω
0.1 μF
75Ω
0.1μF
AGND
10nF
AGND
AGND
0.1 μF
Y2
SDA
10nF
47pF1
RESET
SCLK
47pF1
1MΩ
0.1 μF
0.1 μF
C22
1nF
+ 10 μF
1nF
D1
BZX399-C3V3
100Ω
100Ω
1.69kΩ
82nF
PVDD_1.8V
AGND
+ 10 μF
C94
10nF
DGND
0.1 μF
U1 BYPASS CAPACITORS
10nF
DVDD_1.8V
0.1 μF
28.63636MHz
10nF
10nF
DGND
0.1 μF
DVDDIO
10 μF
5.6kΩ
0.1 μF
10 μF
10nF
0.1 μF
0.1 μF
DGND
0.1 μF
10nF
U1 BYPASS CAPACITORS
2.7k Ω
DVDDIO
AIN4
AIN5
AIN6
SOY
SOG
AIN1
AIN2
AIN3
U1
ELPF
RESET
59
TEST1
51 FB
78
19
SDA2
16
SCLK2
80
ALSB
81
SDA
82
SCLK
46
38
XTAL
37
XTAL1
65
CML
64
REFOUT
67
BIAS
62
CAPY2
61
CAPY1
10nF
DVDD_1.8V
AVDD_3.3V
PVDD_1.8V
69
CAPC2
68
CAPC1
53
AIN7
55 AIN8
57 AIN9
71 AIN10
73 AIN11
75
AIN12
72
74
76
77
52
54
56
58
0.1 μF
AGND
100Ω
100Ω
100Ω
100Ω
100Ω
100Ω
33Ω
36
HS 4
VS 99
FIELD 98
HREF/HS_IN 86
VREF/VS_IN 85
15
LLC1
DGND
BAT54C
K2
10kΩ
DVDDIO
VP19
VP18
VP17
VP16
VP15
VP14
VP13
VP12
VP11
VP10
VP09
VP08
VP07
VP06
VP05
VP04
VP03
VP02
VP01
VP00
33Ω
33Ω
33Ω
33Ω
33Ω
33Ω
33Ω
33Ω
33Ω
33Ω
33Ω
33Ω
33Ω
33Ω
33Ω
33Ω
33Ω
33Ω
33Ω
33Ω
91
92
93
94
7
8
9
10
20
21
22
23
25
26
27
28
41
42
43
44
P19
P18
P17
P16
P15
P14
P13
P12
P11
P10
P9
P8
P7
P6
P5
P4
P3
P2
P1
P0
VP29
VP28
VP27
VP26
VP25
VP24
VP23
VP22
VP21
VP20
K1
VP41
VP40
VP39
VP38
VP37
VP36
VP35
VP34
VP33
VP32
VP31
VP30
VP[00:41]
SFL/SYNC_OUT
HS
VS
FIELD
HS_IN
VS_IN
LLC1
INT
DCLCK_IN
33Ω
33Ω
33Ω
33Ω
33Ω
33Ω
33Ω
33Ω
33Ω
33Ω
33Ω
33Ω
33Ω
33Ω
33Ω
33Ω
33Ω
33Ω
33Ω
33Ω
33Ω
33Ω
35
79
83
84
87
88
95
96
97
100
1
2
3
13
14
24
29
30
31
32
33
34
45
P29
P28
P27
P26
P25
P24
P23
P22
P21
P20
DCLK_IN
DE_IN
P40
P39
P38
P37
P36
P35
P34
P33
P32
P31
INT
DVDDIO
SFL/SYNC_OUT
ADV7401
AVDD 63
49
PVSS
50
PVSS
PVDD_1.8V
2.7k Ω
DVDD 12
DVDD 39
90
DVDD
5
DVSSIO
17
DVSSIO
6
DVDDIO 18
DVDDIO
AVDD_3.3V
47
PVDD
PVDD 48
70
TEST0
66
AVSS
60
AVSS
Figure 9. ADV7401
11
DVSS
40
DVSS
89
DVSS
U1 BYPASS CAPACITORS
ADV7401
TYPICAL CONNECTION DIAGRAM
ADV7401
OUTLINE DIMENSIONS
16.20
16.00 SQ
15.80
1.60 MAX
0.75
0.60
0.45
100
1
76
75
PIN 1
14.20
14.00 SQ
13.80
TOP VIEW
(PINS DOWN)
0.15
0.05
SEATING
PLANE
0.20
0.09
7°
3.5°
0°
0.08
COPLANARITY
51
50
25
26
VIEW A
0.50
BSC
LEAD PITCH
VIEW A
ROTATED 90° CCW
0.27
0.22
0.17
COMPLIANT TO JEDEC STANDARDS MS-026-BED
051706-A
1.45
1.40
1.35
Figure 10. 100-Lead Low Profile Quad Flat Package [LQFP]
(ST-100)
Dimensions shown in millimeters
ORDERING GUIDE
Model1
ADV7401BSTZ-802
ADV7401BSTZ-1102
ADV7401KSTZ-1402
EVAL-ADV7401EBM
Temperature Range
−40°C to +85°C
−40°C to +85°C
0°C to 70°C
Package Description
100-Lead Low Profile Quad Flat Package (LQFP)
100-Lead Low Profile Quad Flat Package (LQFP)
100-Lead Low Profile Quad Flat Package (LQFP)
Evaluation Board
Package Option
ST-100
ST-100
ST-100
1
The ADV7401 is a Pb-free, environmentally friendly product. It is manufactured using the most up-to-date materials and processes. The coating on the leads of each
device is 100% pure Sn electroplate. The device is suitable for Pb-free applications, and is able to withstand surface-mount soldering at up to 255°C (±5°C). In addition,
it is backward compatible with conventional SnPb soldering processes. This means that the electroplated Sn coating can be soldered with SnPb solder pastes at
conventional reflow temperatures of 220°C to 235°C.
2
Z = Pb-free part.
Purchase of licensed I2C components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips I2C Patent
Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips.
© 2005 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D05340–0–9/05(SpA)
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