a FEATURES ADOPT™ Optimal Positioning Technology for Superior Load Transient Response and Fewest Output Capacitors Complies with VRM 9.0 with Lowest System Cost Active Current Balancing between Both Output Phases 5-Bit Digitally Programmable 1.1 V to 1.85 V Output Dual Logic-Level PWM Outputs for Interface to External High Power Drivers Total Output Accuracy ⴞ0.8% over Temperature Current-Mode Operation Short Circuit Protection Power Good Output Overvoltage Protection Crowbar Protects Microprocessors with No Additional External Components APPLICATIONS Desktop PC Power Supplies for: Intel Pentium® 4 Processors AMD Athlon™ Processors VRM Modules 5-Bit Programmable 2-Phase Synchronous Buck Controller ADP3160/ADP3167 FUNCTIONAL BLOCK DIAGRAM VCC SET UVLO AND BIAS PWM1 RESET CROWBAR REF 3.0V REFERENCE 2-PHASE DRIVER LOGIC PWM2 CMP3 GND DAC+24% PWRGD CT OSCILLATOR CMP CMP2 DAC–18% CS– CMP CS+ CMP1 COMP gm ADP3160/ADP3167 FB VID DAC VID4 GENERAL DESCRIPTION The ADP3160 and ADP3167 are highly efficient, dual output, synchronous buck switching regulator controllers optimized for converting a 5 V or 12 V main supply into the core supply voltage required by high-performance processors, such as Pentium 4 and Athlon. The ADP3160 uses an internal 5-bit DAC to read a voltage identification (VID) code directly from the processor that is used to set the output voltage between 1.1 V and 1.85 V. The devices use a current-mode PWM architecture to drive two logiclevel outputs at a programmable switching frequency that can be optimized for VRM size and efficiency. The output signals are 180 degrees out of phase, allowing for the construction of two complementary buck switching stages. These two stages share the dc output current to reduce overall output voltage ripple. An active current balancing function ensures that both phases carry equal portions of the total load current, even under large transient loads, to minimize the size of the inductors. The ADP3160 control VID3 VID2 VID1 VID0 loop has been optimized for conversion from 12 V, while the ADP3167 is designed for conversion from a 5 V supply. The ADP3160 and ADP3167 also use a unique supplemental regulation technique called active voltage positioning to enhance load transient performance. Active voltage positioning results in a dc/dc converter that meets the stringent output voltage specifications for high-performance processors, with the minimum number of output capacitors and smallest footprint. Unlike voltage-mode and standard current-mode architectures, active voltage positioning adjusts the output voltage as a function of the load current so that it is always optimally positioned for a system transient. They also provide accurate and reliable short circuit protection and adjustable current limiting. The ADP3160 is specified over the commercial temperature range of 0∞C to 70∞C and is available in a 16-lead narrow body SOIC package. ADOPT is a trademark of Analog Devices, Inc. Athlon is a trademark of Advanced Micro Devices, Inc. Pentium is a registered trademark of Intel Corporation. REV. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 2002 ADP3160/ADP3167–SPECIFICATIONS1 Parameter FEEDBACK INPUT Accuracy 1.1 V Output 1.475 V Output 1.85 V Output Line Regulation Input Bias Current Crowbar Trip Threshold Crowbar Reset Threshold Crowbar Response Time REFERENCE Output Voltage Output Current VID INPUTS Input Low Voltage Input High Voltage Input Current Pull-Up Resistance Internal Pull-Up Voltage Symbol ⌬VFB IFB VCROWBAR tCROWBAR VIL(VID) VIH(VID) IVID RVID ERROR AMPLIFIER Output Resistance Transconductance Output Current Maximum Output Voltage Output Disable Threshold RO(ERR) gm(ERR) IO(ERR) VCOMP(MAX) VCOMP(OFF) BWERR VCS(CL) Current Limit Foldback Voltage VCS(FOLD) DVCOMP /DVCS nI Input Bias Current Response Time ICS+, ICS– tCS POWER GOOD COMPARATOR Undervoltage Threshold Overvoltage Threshold Output Voltage Low Response Time Min See Figure 1 See Figure 1 See Figure 1 VCC = 10 V to 14 V 1.091 1.1 1.463 1.475 1.835 1.85 0.05 5 114 124 50 60 300 Percent of Nominal Output Percent of Nominal Output Overvoltage to PWM Going Low Typ 2.952 3.0 300 VREF IREF fCT(MAX) ⌬fCT ICT CURRENT SENSE Current Limit Threshold Voltage Conditions Max Unit 1.109 1.487 1.865 V V V % nA % % ns VFB OSCILLATOR Maximum Frequency2 Frequency Variation CT Charge Current –3 dB Bandwidth (VCC = 12 V, IREF = 150 A, TA = 0ⴗC to 70ⴗC, unless otherwise noted.) VPWRGD(UV) VPWRGD(OV) VOL(PWRGD) 50 134 70 3.048 V mA 0.6 180 28 5.0 250 20 4.5 5.5 V V mA kW V 2000 430 130 26 500 150 36 570 170 46 kHz kHz mA mA 2.2 VID(X) = 0 V TA = 25∞C, CT = 91 pF TA = 25∞C, VFB in Regulation TA = 25∞C, VFB = 0 V 2.0 VFB = 0 V FB Forced to VOUT – 3% ADP3160 ADP3167 COMP = Open ADP3160, CS+ = VCC FB Forced to VOUT – 3% ADP3167, CS+ = VCC FB Forced to VOUT – 3% 0.8 V £ COMP £ 1 V ADP3160, FB £ 375 mV ADP3167, FB £ 750 mV ADP3160, 1 V £ VCOMP £ 3 V ADP3167, 1 V £ VCOMP £ 3 V CS+ = CS– = VCC ADP3160, CS+ – (CS–) ≥ 172 mV to PWM Going Low ADP3167, CS+ – (CS–) ≥ 89 mV to PWM Going Low % Nominal Output % Nominal Output IPWRGD(SINK) = 100 mA FB Going High FB Going Low –2– 560 640 200 2.2 1 3.0 720 800 500 2.45 800 880 kW mmho mA V mV mV kHz 142 157 172 mV 69 79 89 mV 0 95 47 12.5 25 0.5 50 15 115 58 mV mV mV V/V V/V mA ns 75 37 5 50 76 114 82 124 30 2 200 ns 88 134 200 % % mV ms ns REV. B ADP3160/ADP3167 Parameter Symbol Conditions PWM OUTPUTS Output Voltage Low Output Voltage High Output Current Duty Cycle Limit2 VOL(PWM) VOH(PWM) IPWM DMAX IPWM(SINK) = 400 mA IPWM(SOURCE) = 400 mA SUPPLY DC Supply Current Normal Mode UVLO Mode UVLO Threshold Voltage UVLO Hysteresis ICC ICC(UVLO) VUVLO Min 4.0 0.4 Max Unit 100 500 50 mV V mA % 5.5 400 6.9 0.6 mA mA V V 1 Per Phase, Relative to fCT VCC £ VUVLO, VCC Rising 5.9 0.1 NOTES 1 All limits at temperature extremes are guaranteed via correlation using standard Statistical Quality Control (SQC) methods. 2 Guaranteed by design, not tested in production. Specifications subject to change without notice. REV. B Typ –3– 3.8 220 6.4 0.4 ADP3160/ADP3167 ABSOLUTE MAXIMUM RATINGS* PIN FUNCTION DESCRIPTIONS VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +15 V CS+, CS– . . . . . . . . . . . . . . . . . . . . . . –0.3 V to VCC + 0.3 V All Other Inputs and Outputs . . . . . . . . . . . . –0.3 V to +10 V Operating Ambient Temperature Range . . . . . . . 0∞C to 70∞C Operating Junction Temperature . . . . . . . . . . . . . . . . . . 125∞C Storage Temperature Range . . . . . . . . . . . . –65∞C to +150∞C JA Two-Layer Board . . . . . . . . . . . . . . . . . . . . . . . . . . 125∞C/W Four-Layer Board . . . . . . . . . . . . . . . . . . . . . . . . . . 81∞C/W Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . . 300∞C Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . 215∞C Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220∞C Pin Mnemonic Function *This is a stress rating only; operation beyond these limits can cause the device to be permanently damaged. Unless otherwise specified, all voltages are referenced to GND. PIN CONFIGURATION VID4 1 16 VCC VID3 2 15 REF VID2 3 14 CS– VID1 4 ADP3160/ ADP3167 13 PWM1 TOP VIEW VID0 5 (Not to Scale) 12 PWM2 COMP 6 1–5 VID4– VID0 6 COMP 7 FB 8 CT 9 GND 10 PWRGD 11 CS+ 12 13 14 PWM2 PWM1 CS– 15 16 REF VCC 11 CS+ FB 7 10 PWRGD CT 8 9 GND Voltage Identification DAC Inputs. These pins are pulled up to an internal reference, providing a Logic 1 if left open. The DAC output programs the FB regulation voltage from 1.1 V to 1.85 V. Leaving all five DAC inputs open results in the ADP3160/ADP3167 going into a “No CPU” mode, shutting off its PWM outputs. Error Amplifier Output and Compensation Point. The voltage at this output programs the output current control level between CS+ and CS–. Feedback Input. Error amplifier input for remote sensing of the output voltage. External Capacitor CT Connection to ground sets the frequency of the device. Ground. All internal signals of the ADP3160/ ADP3167 are referenced to this ground. Open-Drain Output that signals when the output voltage is in the proper operating range. Current Sense Positive Node. Positive input for the current comparator. The output current is sensed as a voltage at this pin with respect to CS–. Logic-Level Output for Phase 2 Driver Logic-Level Output for Phase 1 Driver Current Sense Negative Node. Negative input for the current comparator. 3.0 V Reference Output Supply Voltage for the ADP3160/ADP3167. ORDERING GUIDE Model Temperature Range Package Description Package Option ADP3160JR ADP3167JR 0∞C to 70∞C 0∞C to 70∞C Narrow Body SOIC Narrow Body SOIC R-16A (SO-16) R-16A (SO-16) CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the ADP3160/ADP3167 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. –4– WARNING! ESD SENSITIVE DEVICE REV. B ADP3160/ADP3167 ADP3160/ADP3167 100⍀ 100nF VID4 VCC 16 2 VID3 REF 15 3 VID2 CS– 14 4 VID1 PWM1 13 5 VID0 PWM2 12 6 COMP 7 FB PWRGD 10 8 CT GND 9 12V + 1F 100nF 4.05 20k⍀ SUPPLY CURRENT – mA 5-BIT CODE 1 4.10 CS+ 11 4.00 3.95 3.90 VFB AD820 3.85 1.2V 0 Figure 1. Closed-Loop Output Voltage Accuracy Test Circuit 1000 500 750 1250 1500 OSCILLATOR FREQUENCY – kHz 1750 2000 Figure 3. Supply Current vs. Oscillator Frequency 10000 16 TA = 25ⴗC VOUT = 1.6V NUMBER OF PARTS – % OSCILLATOR FREQUENCY – kHz 250 1000 100 0 100 200 300 CT CAPACITOR – pF 400 8 4 0 –1 500 Figure 2. Oscillator Frequency vs. Timing Capacitor REV. B 12 0 OUTPUT ACCURACY – % of Nominal Figure 4. Output Accuracy Distribution –5– 1 ADP3160/ADP3167 THEORY OF OPERATION Active Voltage Positioning The ADP3160 and ADP3167 combine a current-mode, fixed frequency PWM controller with antiphase logic outputs in a controller for a 2-phase synchronous buck power converter. Two-phase operation is important for switching the high currents required by high-performance microprocessors. Handling the high current in a single-phase converter would place difficult requirements on the power components such as inductor wire size, MOSFET ON resistance, and thermal dissipation. Their high-side current sensing topology ensures that the load currents are balanced in each phase, such that neither phase has to carry more than half of the power. An additional benefit of high-side current sensing over output current sensing is that the average current through the sense resistor is reduced by the duty cycle of the converter, allowing the use of a lower power, lower cost resistor. The outputs of the ADP3160/ADP3167 are logic drivers only and are not intended to drive external power MOSFETs directly. Instead, the ADP3160/ADP3167 should be paired with drivers such as the ADP3414 or ADP3417. A system level block diagram of a 2-phase power supply for high current CPUs is shown in Figure 5. The ADP3160 and ADP3167 use Analog Devices Optimal Positioning Technology (ADOPT), a unique supplemental regulation technique that uses active voltage positioning and provides optimal compensation for load transients. When implemented, ADOPT adjusts the output voltage as a function of the load current, so that it is always optimally positioned for a load transient. Standard (passive) voltage positioning has poor dynamic performance, rendering it ineffective under the stringent repetitive transient conditions required by high-performance processors. ADOPT, however, provides optimal bandwidth for transient response that yields optimal load transient response with the minimum number of output capacitors. Reference Output A 3.0 V reference is available and is commonly used to set the voltage positioning accurately using a resistor divider to the COMP pin. In addition, the reference can be used for other functions such as generating a regulated voltage with an external amplifier. The reference is bypassed with a 1 nF capacitor to ground. It is not intended to supply current to large capacitive loads, and it should not be used to provide more than 1 mA of output current. The frequency of the device is set by an external capacitor connected to the CT pin. Each output phase operates at half of the frequency set by the CT pin. The error amplifier and current sense comparator control the duty cycle of the PWM outputs to maintain regulation. The maximum duty cycle per phase is inherently limited to 50% because the PWM outputs toggle in 2-phase operation. While one phase is on, the other phase is off. In no case can both outputs be high at the same time. Cycle-by-Cycle Operation During normal operation (when the output voltage is regulated), the voltage-error amplifier and the current comparator are the main control elements. The voltage at the CT pin of the oscillator ramps between 0 V and 3 V. When that voltage reaches 3 V, the oscillator sets the driver logic, which sets PWM1 high. During the ON time of Phase 1, the driver IC turns on the high-side MOSFET. The CS+ and CS– pins monitor the current through the sense resistor that feeds both high-side MOSFETs. When the voltage between the two pins exceeds the threshold level set by the voltage error amplifier (gm), the driver logic is reset and the PWM output goes low. This signals the driver IC to turn off the high-side MOSFET and turn on the low-side MOSFET. On the next cycle of the oscillator, the driver logic toggles and sets PWM2 high. On each following cycle of the oscillator, the outputs toggle between PWM1 and PWM2. In each case, the current comparator resets the PWM output low when the current comparator threshold is reached. As the load current increases, the output voltage starts to decrease. This causes an increase in the output of the gm amplifier, which in turn leads to an increase in the current comparator threshold, thus programming more current to be delivered to the output so that voltage regulation is maintained. Output Voltage Sensing The output voltage is sensed at the FB pin allowing for remote sensing. To maintain the accuracy of the remote sensing, the GND pin should also be connected close to the load. A voltage error amplifier (gm) amplifies the difference between the output voltage and a programmable reference voltage. The reference voltage is programmed between 1.1 V and 1.85 V by an internal 5-bit DAC that reads the code at the voltage identification (VID) pins. Refer to Table I for the output voltage versus VID pin code information. 5V OR 12V 5V IL1 PWM1 ADP3412 IOUT VID INPUTS SYNCHRONOUS DRIVER IL2 ADP3160/ ADP3167 IL1 2-PHASE SYNCHRONOUS BUCK CONTROLLER 5V 5V OR 12V + IL2 PWM2 ADP3412 OUT PWM2 PWM1 SYNCHRONOUS DRIVER Figure 5. 2-Phase CPU Supply System Level Block Diagram –6– REV. B ADP3160/ADP3167 When the load current exceeds the current limit, the excess current discharges the output capacitor. When the output voltage is below the foldback threshold VFB(LOW), the maximum deliverable output current is cut by reducing the current sense threshold from the current limit threshold, VCS(CL), to the foldback threshold, VCS(FOLD). Along with the resulting current foldback, the oscillator frequency is reduced by a factor of 5 when the output is 0 V. This further reduces the average current in short circuit. Active Current Sharing The ADP3160 and ADP3167 ensure current balance in the two phases by actively sensing the current through a single sense resistor. During one phase’s ON time, the current through the respective high-side MOSFET and inductor is measured through the sense resistor (R4 in Figure 6). When the comparator (CMP1 in the Functional Block Diagram) threshold programmed by the gm amplifier is reached, the high-side MOSFET turns off. In the next cycle, the device switches to the second phase. The current is measured with the same sense resistor and the same internal comparator, ensuring accurate matching. This scheme is immune to imbalances in the MOSFETs’ RDS(ON) and inductors’ parasitic resistances. Power Good Monitoring The Power Good comparator monitors the output voltage of the supply via the FB pin. The PWRGD pin is an open-drain output whose high level (when connected to a pull-up resistor) indicates that the output voltage is within the specified range of the nominal output voltage requested by the VID DAC. PWRGD will go low if the output is outside this range. If for some reason one of the phases fails, the other phase will still be limited to its maximum output current (one-half of the short circuit current limit). If this is not sufficient to supply the load, the output voltage will droop and cause the PWRGD output to signal that the output voltage has fallen out of its specified range. Output Crowbar The ADP3160 and ADP3167 include a crowbar comparator that senses when the output voltage rises higher than the specified trip threshold, VCROWBAR. This comparator overrides the control loop and sets both PWM outputs low. The driver ICs turn off the high-side MOSFETs and turn on the low-side MOSFETs, thus pulling the output down as the reversed current builds up in the inductors. If the output overvoltage is due to a short of the highside MOSFET, this action will current limit the input supply or blow its fuse, protecting the microprocessor from destruction. The crowbar comparator releases when the output drops below the specified reset threshold, and the controller returns to normal operation if the cause of the overvoltage failure does not persist. Short Circuit Protection The ADP3160 and ADP3167 have multiple levels of short circuit protection to ensure fail-safe operation. The sense resistor and the maximum current sense threshold voltage given in the specifications set the peak current limit. Table I. Output Voltage vs. VID Code VID4 VID3 VID2 VID1 VID0 VOUT(NOM) 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 No CPU 1.100 V 1.125 V 1.150 V 1.175 V 1.200 V 1.225 V 1.250 V 1.275 V 1.300 V 1.325 V 1.350 V 1.375 V 1.400 V 1.425 V 1.450 V 1.475 V 1.500 V 1.525 V 1.550 V 1.575 V 1.600 V 1.625 V 1.650 V 1.675 V 1.700 V 1.725 V 1.750 V 1.775 V 1.800 V 1.825 V 1.850 V REV. B Output Disable The ADP3160 and ADP3167 include an output disable function that turns off the control loop to bring the output voltage to 0 V. Because an extra pin is not available, the disable feature is accomplished by pulling the COMP pin to ground. When the COMP pin drops below 0.56 V for the ADP3160 and 0.64 V for the ADP3167, the oscillator stops and both PWM signals are driven low. This function does not place the part in a low quiescent current shutdown state, and the reference voltage is still available. The COMP pin should be pulled down with an open collector or open-drain type of output capable of sinking at least 2 mA. APPLICATION INFORMATION A VRM 9.0-Compliant Design Example The design parameters for a typical high-performance Intel CPU application (see Figure 6) are as follows: Input Voltage (VIN) = 12 V Nominal Output Voltage (VOUT) = 1.7 V Static Output Tolerance (V⌬) = (V+) – (V–) = 0 mV – (–130 mV) = 130 mV Average Output Tolerance (VAVG ) = (V+) + (V–) VOUT + = 1.635 V 2 Maximum Output Current (IO) = 53.4 A Output Current di/di < 50 A/s –7– ADP3160/ADP3167 R7 20⍀ 270F ⴛ 4 OS-CON 16V VIN 12V C11 C12 C13 VIN RTN R4 4m⍀ C14 R6 10⍀ U1 RA 26.1k⍀ RB 11.0k⍀ C9 1F D1 MBR052LTI R5 2.4k⍀ U2 Q5 2N3904 Z1 ZMM5236BCT ADP3414 1 BST DRVH 8 2 IN 1 VID4 VCC 16 2 VID3 REF 15 3 NC PGND 6 3 VID2 CS– 14 4 VCC DRVL 5 4 VID1 PWM1 13 5 VID0 PWM2 12 6 COMP COC 3.3nF C26 4.7F C4 4.7F ADP3160 FROM CPU C23 15nF C25 1nF 7 FB PWRGD 10 8 CT GND U3 1 BST DRVH 8 2 IN 3 NC C2 100pF Q2 FDB8030L 2200F ⴛ 9 RUBYCON MBZ 6.3V 13m⍀ ESR (EACH) ADP3414 9 L1 600nH C10 1F D2 MBR052LTI C1 150pF 4 VCC R1 1k⍀ SW 7 C5 1F CS+ 11 Q1 FDB7030L Q3 FDB7030L SW 7 PGND 6 DRVL 5 C6 1F L2 600nH C23 C15 C16 C17 C18 C19 C20 C21 C22 VCC(CORE) 1.1V – 1.85V 53.4A VCC(CORE) RTN Q4 FDB8030L NC = NO CONNECT Figure 6. 53.4 A Intel CPU Supply Circuit, VRM 9.0 FMB Design CT Selection—Choosing the Clock Frequency L= The ADP3160 and ADP3167 use a fixed-frequency control architecture. The frequency is set by an external timing capacitor, CT. The value of CT for a given clock frequency can be selected using the graph in Figure 2. (VIN – VAVG ) ¥ VAVG VIN ¥ fSW ¥ IL ( RIPPLE ) (1) For 12.5 A peak-to-peak ripple current, which corresponds to just under 50% of the 26.7 A full-load dc current in an inductor, Equation 1 yields an inductance of: The clock frequency determines the switching frequency, which relates directly to switching losses and the sizes of the inductors and input and output capacitors. A clock frequency of 400 kHz sets the switching frequency of each phase, fSW, to 200 kHz, which represents a practical trade-off between the switching losses and the sizes of the output filter components. From Figure 2, for 400 kHz the required timing capacitor value is 150 pF. For good frequency stability and initial accuracy, it is recommended to use a capacitor with a low temperature coefficient and tight tolerance, e.g., an MLC capacitor with NPO dielectric and with 5% or less tolerance. L= (12 V – 1.635 V ) ¥ 1.635 V = 565 nH 12 V ¥ 400 kHz / 2 ¥ 12.5 A A 600 nH inductor can be used, which gives a calculated ripple current of 12.2 A at no load. The inductor should not saturate at the peak current of 32.8 A and should be able to handle the sum of the power dissipation caused by the average current of 26.7 A in the winding and the core loss. The output ripple current is smaller than the inductor ripple current due to the two phases partially canceling. This can be calculated as follows: Inductance Selection The choice of inductance determines the ripple current in the inductor. Less inductance leads to more ripple current, which increases the output ripple voltage and the conduction losses in the MOSFETs, but allows using smaller size inductors and, for a specified peak-to-peak transient deviation, output capacitors with less total capacitance. Conversely, a higher inductance means lower ripple current and reduced conduction losses, but requires larger size inductors and more output capacitance for the same peak-to-peak transient deviation. In a 2-phase converter a practical value for the peak-to-peak inductor ripple current is under 50% of the dc current in the same inductor. A choice of 46% for this particular design example yields a total peak-to-peak output ripple current of 23% of the total dc output current. The following equation shows the relationship between the inductance, oscillator frequency, peak-to-peak ripple current in an inductor, and input and output voltages. IOD = 2 ¥ V AVG (VIN – 2 ¥ V AVG ) VIN ¥ L ¥ fOSC = 2 ¥ 1.635V (12V – 2 ¥ 1.635V ) = 9.9 A 12V ¥ 600 nH ¥ 400 kHz (2) Designing an Inductor Once the inductance is known, the next step is either to design an inductor or find a standard inductor that comes as close as possible to meeting the overall design goals. The first decision in designing the inductor is to choose the core material. There are several possibilities for providing low core loss at high frequencies. Two examples are the powder cores (e.g., Kool-Mm® from Magnetics) and the gapped soft ferrite cores (e.g., 3F3 or 3F4 from Philips). Low-frequency powdered iron cores should be avoided due to their high core loss, especially when the inductor value is relatively low and the ripple current is high. –8– REV. B ADP3160/ADP3167 Two main core types can be used in this application. Open magnetic loop types, such as beads, beads on leads, and rods and slugs, provide lower cost but do not have a focused magnetic field in the core. The radiated EMI from the distributed magnetic field may create problems with noise interference in the circuitry surrounding the inductor. Closed-loop types, such as pot cores, PQ, U, and E cores, or toroids, cost more, but have much better EMI/RFI performance. A good compromise between price and performance are cores with a toroidal shape. Some error sources, such as initial voltage accuracy and ripple voltage, can be directly deducted from the available regulation window. Other error sources scale proportionally to the amount of voltage positioning used, which, for an optimal design, should use the maximum that the regulation window will allow. The error determination is a closed-loop calculation, but it can be closely approximated. To maintain a conservative design while avoiding an impractical design, various error sources should be considered and summed statistically. There are many useful references for quickly designing a power inductor. Table II gives some examples. The output ripple voltage can be factored into the calculation by summing the output ripple current with the maximum output current to determine an effective maximum dynamic current change. The remaining errors are summed separately according to the formula: Table II. Magnetics Design References Magnetic Designer Software Intusoft (www.intusoft.com) VWIN = (VD – (VVID ¥ 2 kVID )) ¥ Ê IO Á1 – IO + IOD Á Ë Designing Magnetic Components for High-Frequency DC-DC Converters McLyman, Kg Magnetics ISBN 1-883107-00-08 where kVID = 0.7% is the initial programmed voltage tolerance from the graph of Figure 4, kRCS = 2% is the tolerance of the current sense resistor, kCSF = 20% is the summed tolerance of the current sense filter components, kRT = 2% is the tolerance of the two termination resistors added at the COMP pin, and kEA = 8% accounts for the IC current loop gain tolerance including the gm tolerance. Selecting a Standard Inductor The companies listed in Table III can provide design consultation and deliver power inductors optimized for high power applications upon request. Table III. Power Inductor Manufacturers The remaining window is then divided by the maximum output current plus the ripple to determine the maximum allowed ESR and output resistance: Coilcraft (847) 639-6400 www.coilcraft.com Coiltronics (561) 752-5000 www.coiltronics.com RE(MAX ) = ROUT (MAX ) = VWIN IO + IOD 94 mV RE(MAX ) = = 1.5 mW 53.4 A + 9.9 A Sumida Electric Company (510) 668-0660 www.sumida.com (4) The output filter capacitor bank must have an ESR of less than 1.5 mW. One can, for example, use nine MBZ-type capacitors from Rubycon, with 2.2 mF capacitance, a 6.3 V voltage rating, and 13 mW ESR. The nine capacitors have a maximum total ESR of 1.44 mW when connected in parallel. Without ADOPT voltage positioning, the ESR would need to be less than 0.9 mW, yielding a 50% increase to 14 MBZ-type output capacitors. COUT Selection—Determining the ESR The required equivalent series resistance (ESR) and capacitance drive the selection of the type and quantity of the output capacitors. The ESR must be small enough to contain the voltage deviation caused by a maximum allowable CPU transient current within the specified voltage limits, giving consideration also to the output ripple and the regulation tolerance. The capacitance must be large enough that the voltage across the capacitor, which is the sum of the resistive and capacitive voltage deviations, does not deviate beyond the initial resistive deviation while the inductor current ramps up or down to the value corresponding to the new load current. The maximum allowed ESR also represents the maximum allowed output resistance, ROUT. COUT—Checking the Capacitance As long as the capacitance of the output capacitor is above a critical value and the regulating loop is compensated with ADOPT, the actual value has no influence on the peak-to-peak deviation of the output voltage to a full step change in the load current. The critical capacitance can be calculated as follows: IO ¥L RE ¥ VOUT 2 53.4 A 600 nH ¥ = 6.5 mF COUT (CRIT ) = 1.44 mW ¥ 1.7 2 COUT (CRIT ) = The cumulative errors in the output voltage regulations cut into the available regulation window, VWIN. When considering dynamic load regulation this relates directly to the ESR. When considering dc load regulation, this relates directly to the programmed output resistance of the power converter. REV. B 2 ˆ (3) Êk ˆ 2 2 2 kRCS + Á CSF ˜ + kRT + kEA ˜ = 94 mV ˜ Ë 2 ¯ ¯ (5) The critical capacitance for the nine Rubycon capacitors with an equivalent ESR of 1.44 mW is 6.5 mF, while the equivalent capacitance of those nine capacitors is 9 ¥ 2.2 mF = 19.8 mF. Therefore, the capacitance is safely above the critical value. –9– ADP3160/ADP3167 that in each phase one of the two MOSFETs is always conducting the average inductor current. For VIN = 12 V and VOUT = 1.6 V, the duty ratio of the high-side MOSFET is: RSENSE The value of RSENSE is based on the maximum required output current. The current comparator of the ADP3160 has a minimum current limit threshold of 142 mV. Note that the 142 mV value cannot be used for the maximum specified nominal current, as headroom is needed for ripple current and tolerances. DHSF = DLSF = 1 – DHSF = 86.7% IHSF ( MAX ) = Once RSENSE has been chosen, the output current at the point where current limit is reached, IOUT(CL), can be calculated using the maximum current sense threshold of 172 mV: RSENSE – I L(RIPPLE ) = (7) 172 mV 2¥ – 12.2 A = 73.8 A 4 mW At output voltages below 425 mV, the current sense threshold is reduced to 95 mV, and the ripple current is negligible. Therefore, at dead short the output current is reduced to: IOUT ( SC ) = 2 ¥ 95 mV = 47.5 A 4 mW (8) To safely carry the current under maximum load conditions, the sense resistor must have a power rating of at least: 2 PRSENSE = ISENSE ( RMS ) ¥ RSENSE IO V ¥ OUT n h ¥ VIN Power MOSFETs In the standard 2-phase application, two pairs of N-channel power MOSFETs must be used with the ADP3160 and ADP3412, one pair as the main (control) switches and the other pair as the synchronous rectifier switches. The main selection parameters for the power MOSFETs are VGS(TH) and RDS(ON). The minimum gate drive voltage (the supply voltage to the ADP3412) dictates whether standard threshold or logic-level threshold MOSFETs must be used. Since VGATE < 8 V, logic-level threshold MOSFETs (VGS(TH) < 2.5 V) are strongly recommended. The maximum output current IO determines the RDS(ON) requirement for the power MOSFETs. When the ADP3160 is operating in continuous mode, the simplifying assumption can be made (15) RDS(ON )HS(MAX ) = PMOSFET (TOTAL) RDS(ON )LS(MAX ) = PMOSFET (TOTAL) 8 ¥ I 2HSF(MAX ) 8.4 W = 11 mW RDS(ON )HS(MAX ) = 8 ¥ (9.8 A)2 (10) 2 (14) Allocating half of the total dissipation for the pair of high-side MOSFETs and half for the pair of low-side MOSFETs, and assuming that the resistive and switching losses of the high-side MOSFET are equal, the required maximum MOSFET resistances will be: (9) 53.4 A 1.7 V ¥ ¥ 4 mW = 950 mW 2 0.85 ¥ 12V DLSF = 25 A DHSF PMOSFET (TOTAL) = 0.1 ¥ VMIN ¥ IO PMOSFET (TOTAL) = 0.1 ¥ 1.57 V ¥ 53.4 A = 8.4 W (16) 4 ¥ I 2LSF(MAX ) 8.4 W = 3.4 mW RDS(ON )LS(MAX ) = 4 ¥ (25 A)2 In this formula, n is the number of phases, and is the converter efficiency, in this case assumed to be 85%. Combining Equations 9 and 10 yields: PRSENSE = (13) The RDS(ON) for each MOSFET can be derived from the allowable dissipation. If 10% of the maximum output power is allowed for MOSFET dissipation, the total dissipation in the four MOSFETs of the 2-phase converter will be: 2 2 Ê I2 ) ˆ DHSF ¥ Á1 + L ( RIPPLE = 9.8 A 2 3 ¥ I O ˜¯ Ë I LSF ( MAX ) = I HSF ( MAX ) where: ISENSE ( RMS ) = IO 2 The maximum rms current of the low-side MOSFET during normal operation is: In this case, 4 mW was chosen as the closest standard value. VCS (CL )( MAX ) (12) The maximum rms current of the high-side MOSFET during normal operation is: VCS ( CL )( MIN ) 142 mV = = 4.3 mW (6) IO I L ( RIPPLE ) 26.7 A + 6.1 A + 2 2 IOUT (CL ) = 2 ¥ (11) The duty ratio of the low-side (synchronous rectifier) MOSFET is: The current comparator threshold sets the peak of the inductor current yielding a maximum output current, IO, which equals twice the peak inductor current value less half of the peak-topeak inductor ripple current. From this the maximum value of RSENSE is calculated as: RSENSE £ VOUT = 13.3% VIN (17) Note that there is a trade-off between converter efficiency and cost. Larger MOSFETs reduce the conduction losses and allow higher efficiency, but increase the system cost. If efficiency is not a major concern, a Fairchild FDB7030L (RDS(ON) = 7 mW nominal, 10 mW worst case) for the high-side and a Fairchild FDB8030L (RDS(ON) = 3.1 mW nominal, 5.6 mW worst case) for the low-side are good choices. The high-side MOSFET dissipation is: ( ) PHSF = RDS (ON )HS ¥ I 2 HFS ( MAX ) + VIN ¥ I L(PK ) ¥ QG ¥ fSW 2 ¥ IG + (VIN ¥ QRR ¥ fSW ) (18) where the second term represents the turn-off loss of the MOSFET and the third term represents the turn-on loss due to the stored charge in the body diode of the low-side MOSFET. (In the second term, QG is the gate charge to be removed from the gate for turn-off and IG is the gate turn-off current. From –10– REV. B ADP3160/ADP3167 the data sheet for the FDB7030L, the value of QG is about 35 nC and the peak gate drive current provided by the ADP3412 is about 1 A. In the third term, QRR is the charge stored in the body diode of the low-side MOSFET at the valley of the inductor current. The data sheet of the FDB8030L does not give that information, so an estimated value of 150 nC is used. The estimate is based on information found on the data sheet of a similar device, the IRF7809. In both terms, fSW is the actual switching frequency of the MOSFETs, or 200 kHz. IL(PK) is the peak current in the inductor, or 32.8 A. Substituting the above data in Equation 19, and using the worstcase value for the MOSFET resistance yields a conduction loss of 0.96 W, a turn-off loss of 2.75 W, and a turn-on loss of 0.72 W. Thus the worst-case total loss in a high-side MOSFET is 4.43 W. The worst-case low-side MOSFET dissipation is: PLSF = RDS (ON )LS ¥ I 2 LSF ( MAX ) PLSF = 5.6 mW ¥ (25 A)2 = 3.5 W (19) (Note that there are no switching losses in the low-side MOSFET.) CIN Selection and Input Current di/dt Reduction In continuous inductor-current mode, the source current of the high-side MOSFET is approximately a square wave with a duty ratio equal to VOUT/VIN and an amplitude of one-half of the maximum output current. To prevent large voltage transients, a low ESR input capacitor sized for the maximum rms current must be used. The maximum rms capacitor current is given by: IO 2 ¥ DHSF - (2 ¥ DHSF )2 2 (20) 53.4 A IC(RMS ) = 2 ¥ 0.133 – (2 ¥ 0.133)2 = 11.9 A 2 IC(RMS ) = Note that the capacitor manufacturer’s ripple current ratings are often based on only 2000 hours of life. This makes it advisable to further derate the capacitor, or to choose a capacitor rated at a higher temperature than required. Several capacitors may be placed in parallel to meet size or height requirements in the design. In this example, the input capacitor bank is formed by four 270 mF, 16 V OS-CON capacitors. The ripple voltage across the three paralleled capacitors is: The optimal implementation of voltage positioning, ADOPT, will create an output impedance of the power converter that is entirely resistive over the widest possible frequency range, including dc, and equal to the maximum acceptable ESR of the output capacitor array. With the resistive output impedance, the output voltage will droop in proportion with the load current at any load current slew rate; this ensures the optimal positioning and allows the minimization of the output capacitor. With an ideal current-mode controlled converter, where the average inductor current would respond without delay to the command signal, the resistive output impedance could be achieved by having a single-pole roll-off of the voltage gain of the voltage-error amplifier. The pole frequency must coincide with the ESR zero of the output capacitor. The devices use constant frequency current-mode control, which is known to have a nonideal, frequency dependent command signal to inductor current transfer function. The frequency dependence manifests in the form of a pair of complex conjugate poles at one-half of the switching frequency. A purely resistive output impedance could be achieved by canceling the complex conjugate poles with zeros at the same complex frequencies and adding a third pole equal to the ESR zero of the output capacitor. Such a compensating network would be quite complicated. Fortunately, in practice it is sufficient to cancel the pair of complex conjugate poles with a single real zero placed at one-half of the switching frequency. Although the end result is not a perfectly resistive output impedance, the remaining frequency dependence causes only a small percentage of deviation from the ideal resistive response. The single-pole and single-zero compensation can be easily implemented by terminating the gm error amplifier with the parallel combination of a resistor and a series RC network. The first step in the design of the feedback loop compensation is to determine the targeted output resistance, RE(MAX), of the power converter using Equation 4. The compensation can then be tailored to create that output impedance for the power converter, and the quantity of output capacitors can be chosen to create a net ESR that is less than or equal to RE(MAX). The next step is to determine the total termination resistance of the gm amplifier that will yield the correct output resistance: nI ¥ RSENSE g m ¥ RE(MAX ) ¥ 2 12.5 ¥ 4 mW RT = = 7.57 kW 2.2 mmho ¥ 1.5 mW ¥ 2 RT = ˆ IO Ê ESRC DHSF ¥Á + ˜ n Ë nC nC ¥ CIN ¥ fSW ¯ (21) ˆ 53.4 A Ê 18 mW 0 133 . VC(RIPPLE ) = ¥Á + ˜ = 137 mV 2 4 ¥ 270 mF ¥ 200 kHz ¯ Ë 4 VC(RIPPLE ) = To reduce the input current di/dt to below the recommended maximum of 0.1 A/ms, an additional small inductor (L > 1 mH @ 15 A) should be inserted between the converter and the supply bus. That inductor also acts as a filter between the converter and the primary power source. Feedback Loop Compensation Design for ADOPT Optimized compensation of the ADP3160 and ADP3167 allow the best possible containment of the peak-to-peak output voltage deviation. Any practical switching power converter is inherently limited by the inductor in its output current slew rate to a value much less than the slew rate of the load. Therefore, any sudden change of load current will initially flow through the output capacitors, and assuming that the capacitance of the output capacitor is larger than the critical value defined by Equation 5, this will produce a peak output voltage deviation equal to the ESR of the output capacitor times the load current change. REV. B (22) where nI is the division ratio from the output voltage signal of the gm amplifier to the PWM comparator (CMP1), gm is the transconductance of the gm amplifier itself, and the factor of 2 is the result of the 2-phase configuration. Note that the internal current multiplier (nI) is 12.5 for the ADP3160, but is 25 for the ADP3167. For this example, assume that we use the Rubycon capacitors at the output with their ESR of 1.44 mW. Once RT is known, the two resistors that make up the divider from the REF pin to output of the gm amplifier (COMP pin) must be calculated. The resistive divider introduces an offset to the output of the gm amplifier that, when reflected back through the gain of the gm stage, accurately positions the output voltage near its allowed maximum at light load. Furthermore, the output of the gm amplifier sets the current sense threshold voltage. At no load, the current sense threshold is increased by the peak of the ripple current in the inductor and reduced by the delay between –11– ADP3160/ADP3167 sensing when the current threshold has been reached and when the high-side MOSFET actually turns off. These two factors are combined with the inherent voltage at the output of gm amplifier that commands a current sense threshold of 0 mV (VGNL0): VGNL = VGNL0 + I L(RIPPLE ) ¥ RSENSE ¥ nI Choosing the nearest 1% resistor value gives RB = 11.0 kW. Finally, RA is calculated: - 2 (23) Again, choosing the nearest 1% resistor value gives RA = 26.1 kW. The compensating capacitor can be calculated from the equation: The output voltage at no load (VONL) can be calculated by starting with the VID setting, adding in the positive offset (V+), subtracting half the ripple voltage, and then subtracting the dominant error terms: VONL = VVID + V + - VONL RB = COC = 19.8 mF ¥ 1.5 mW 7.57 kW (27) The resistance of the zero-setting resistor in series with the compensating capacitor is: RZ = (24) 1.38 mW ¥ 9.9 A = 1.7 V + 0 V – 2 RZ = 2 COC 2 ¥ p ¥ fOSC 2 = 482 W 3.3 nF ¥ p ¥ 400 kHz (28) The nearest standard 5% resistor value is 470 W. Note that this resistor is only required when COUT approaches CCRIT (within 25% or less). In this example, COUT > CCRIT, and RZ can therefore be omitted. = 1.681V With these two terms calculated, the divider resistors (RA for the upper and RB for the lower) can be calculated. Assuming that the internal resistance of the gm amplifier (ROGM) is 200 kW: RB = COUT ¥ RE ( MAX ) 2 p ¥ fOSC ¥ RT RT The closest standard value for COC is 3.3 nF. 2 Ê 94 mV ˆ 1.7 V ¥ (0.007 )2 + Á 0.02 ¥ ˜ 1.7 V ¯ Ë COC = 2 = 3.5 nF p ¥ 400 kHz ¥ 7.57 kW RE IOD - VVID ¥ 2 ˆ V 2 Ê kVID + Á kRT ¥ WIN ˜ VVID ¯ Ë (26) 1 = 25.86 kW RA = 1 1 1 7.57 kW 200 kW 11.3 kW VIN - V AVG ¥ (2 ¥ tD ¥ RSENSE ¥ nI ) L 12.2 A ¥ 4 mW ¥ 12.5 VGNL = 1V + – 2 12 V – 1.635 V ¥ 2 ¥ 60 ns ¥ 4 mW ¥ 12.5 = 1.201V 600 nH 1 1 1 1 RT ROGM RB RA = VREF VREF – VGNL - g m ¥ (VONL - VVID ) RT (25) 3V 3V - 1.2V - 2.2 mmho ¥ (1.681V – 1.7 V ) 7.57 kW = 10.73 kW –12– REV. B ADP3160/ADP3167 LAYOUT AND COMPONENT PLACEMENT GUIDELINES The following guidelines are recommended for optimal performance of a switching regulator in a PC system. General Recommendations 1. For good results, at least a four-layer PCB is recommended. This should allow the needed versatility for control circuitry interconnections with optimal placement, a signal ground plane, power planes for both power ground and the input power (e.g., 5 V), and wide interconnection traces in the rest of the power delivery current paths. Keep in mind that each square unit of 1 ounce copper trace has a resistance of ~0.53 mW at room temperature. 1 2 Ch1 500mV Ch2 20mV M 200s Ch1 2. Whenever high currents must be routed between PCB layers, vias should be used liberally to create several parallel current paths so that the resistance and inductance introduced by these current paths is minimized and the via current rating is not exceeded. 700mV Figure 7. Transient Response of the 53.4 A Design Example of Figure 6 AMD Athlon Design Example 3. If critical signal lines (including the voltage and current sense lines of the ADP3160) must cross through power circuitry, it is best if a signal ground plane can be interposed between those signal lines and the traces of the power circuitry. This serves as a shield to minimize noise injection into the signals at the expense of making signal ground a bit noisier. The design parameters for a typical high-performance AMD CPU application (see Figure 8) are as follows: Input Voltage (VIN) = 5 V Nominal Output Voltage (VOUT) = 1.7 V Static Output Tolerance (V⌬) = (V+) – (V–) = 50 mV – (–50 mV) = 100 mV 4. The power ground plane should not extend under signal components, including the ADP3160 itself. If necessary, follow the preceding guideline to use the signal ground plane as a shield between the power ground plane and the signal circuitry. Average Output Voltage (VAVG ) = (V+) + (V–) VOUT + = 1.7 V 2 Maximum Output Current (IO) = 45 A 5. The GND pin of the ADP3160 should be connected first to the timing capacitor (on the CT pin), and then into the signal ground plane. In cases where no signal ground plane can be used, short interconnections to other signal ground circuitry in the power converter should be used. Output Current di/dt < 50 A/s Using the design procedure previously shown, the final values for this application were calculated, and are shown in Figure 8. 1800F ⴛ 4 RUBYCON MBZ SERIES VIN 5V C12 C13 C14 R7 20⍀ C15 VIN RTN R4 4m⍀ 12V VCC 12V VCC RTN R6 10⍀ U1 ADP3167 FROM CPU R2 20.6k⍀ R3 16.5k⍀ C4 4.7F C9 1F D1 MBR052LTI R5 2.4k⍀ U2 Q5 2N3904 Z1 ZMM5236BCT ADP3412 1 BST 2 IN DRVH 8 2 VID3 REF 15 3 DLY PGND 6 3 VID2 CS– 14 4 VCC DRVL 5 4 VID1 PWM1 13 5 VID0 PWM2 12 C22 1nF C5 1F D2 MBR052LTI CS+ 11 7 FB PWRGD 10 8 CT GND 9 C7 15pF C10 1F L1 600nH Q2 FDB7035L 2200F ⴛ 10 RUBYCON 6.3V MBZ SERIES 13m ESR (EACH) U3 ADP3412 1 BST 2 IN C2 100pF C6 1F C8 15pF DRVH 8 SW 7 3 DLY PGND 6 4 VCC DRVL 5 Q3 FDB7030L L2 600nH C28 C11 C16 C17 C18 C19 C20 C24 C25 C27 Q4 FDB7035L Figure 8. 45 A Athlon Duron CPU Supply Circuit REV. B Q1 FDB7030L SW 7 VCC 16 C1 150pF R1 1k⍀ C26 4.7F 1 VID4 6 COMP COC 1.8nF C21 15nF –13– VCC(CORE) 1.1V – 1.85V 45A VCC(CORE) RTN ADP3160/ADP3167 6. The output capacitors of the power converter should be connected to the signal ground plane even though power current flows in the ground of these capacitors. For this reason, it is advisable to avoid critical ground connections (e.g., the signal circuitry of the power converter) in the signal ground plane between the input and output capacitors. It is also advisable to keep the planar interconnection path short (i.e., have input and output capacitors close together). momentarily has a high voltage forced across it, which translates into added power dissipation in the upper MOSFET. The Schottky diode minimizes this problem by carrying a majority of the circulating current when the lower MOSFET is turned off, and by virtue of its essentially nonexistent reverse recovery time. The Schottky diode has to be connected with very short copper traces to the MOSFET to be effective. 7. The output capacitors should also be connected as closely as possible to the load (or connector) that receives the power (e.g., a microprocessor core). If the load is distributed, the capacitors should also be distributed, and generally in proportion to where the load tends to be more dynamic. 8. Absolutely avoid crossing any signal lines over the switching power path loop, described next. Power Circuitry 9. The switching power path should be routed on the PCB to encompass the smallest possible area to minimize radiated switching noise energy (i.e., EMI). Failure to take proper precautions often results in EMI problems for the entire PC system as well as noise-related operational problems in the power converter control circuitry. The switching power path is the loop formed by the current path through the input capacitors, the power MOSFETs, and the power Schottky diode, if used (see next), including all interconnecting PCB traces and planes. The use of short and wide interconnection traces is especially critical in this path for two reasons: it minimizes the inductance in the switching loop, which can cause high-energy ringing, and it accommodates the high current demand with minimal voltage loss. 10. An optional power Schottky diode (3 A–5 A dc rating) from each lower MOSFET’s source (anode) to drain (cathode) will help to minimize switching power dissipation in the upper MOSFETs. In the absence of an effective Schottky diode, this dissipation occurs through the following sequence of switching events. The lower MOSFET turns off in advance of the upper MOSFET turning on (necessary to prevent cross-conduction). The circulating current in the power converter, no longer finding a path for current through the channel of the lower MOSFET, draws current through the inherent body diode of the MOSFET. The upper MOSFET turns on, and the reverse recovery characteristic of the lower MOSFET’s body diode prevents the drain voltage from being pulled high quickly. The upper MOSFET then conducts very large current while it 11. A small ferrite bead inductor placed in series with the drain of the lower MOSFET can also help to reduce this previously described source of switching power loss. 12. Whenever a power dissipating component (e.g., a power MOSFET) is soldered to a PCB, the liberal use of vias, both directly on the mounting pad and immediately surrounding it, is recommended. Two important reasons for this are: improved current rating through the vias, and improved thermal performance from vias extended to the opposite side of the PCB where a plane can more readily transfer the heat to the air. 13. The output power path, though not as critical as the switching power path, should also be routed to encompass a small area. The output power path is formed by the current path through the inductor, the current sensing resistor, the output capacitors, and back to the input capacitors. 14. For best EMI containment, the power ground plane should extend fully under all the power components except the output capacitors. These components are: the input capacitors, the power MOSFETs and Schottky diodes, the inductors, the current sense resistor, and any snubbing element that might be added to dampen ringing. Avoid extending the power ground under any other circuitry or signal lines, including the voltage and current sense lines. Signal Circuitry 15. The output voltage is sensed and regulated between the FB pin and the GND pin (which connects to the signal ground plane). The output current is sensed (as a voltage) by the CS+ and CS– pins. In order to avoid differential mode noise pickup in the sensed signal, the loop area should be small. Thus the FB trace should be routed atop the signal ground plane and the CS+ and CS– pins (the CS+ pin should be over the signal ground plane as well). 16. The CS+ and CS– traces should be Kelvin-connected to the current sense resistor, so that the additional voltage drop due to current flow on the PCB at the current sense resistor connections does not affect the sensed voltage. –14– REV. B ADP3160/ADP3167 OUTLINE DIMENSIONS Dimensions shown in millimeters and (inches) 16-Lead Standard Small Outline Package [SOIC] Narrow Body (R-16A/SO-16) 10.00 (0.3937) 9.80 (0.3858) 4.00 (0.1575) 3.80 (0.1496) 16 9 1 8 PIN 1 1.27 (0.0500) BSC COPLANARITY 0.25 (0.0098) 0.10 (0.0039) 6.20 (0.2441) 5.80 (0.2283) 1.75 (0.0689) 1.35 (0.0531) 0.50 (0.0197) ⴛ 45ⴗ 0.25 (0.0098) 8ⴗ 0.51 (0.0201) SEATING 0.25 (0.0098) 0ⴗ 1.27 (0.0500) 0.33 (0.0130) PLANE 0.40 (0.0157) 0.19 (0.0075) CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN REV. B –15– ADP3160/ADP3167 Revision History Location Page 05/02—Data Sheet changed from REV. A to REV. B. 2/01—Data Sheet changed from REV. 0 to REV. A. Changes to Reference section of SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Edits to Figure 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Replacement of Figure 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Edits to CT Selection—Choosing the Clock Frequency section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 C02806–0–5/02(B) Addition of ADP3167 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Universal Edits to Figure 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Changes to Equations 4, 6, and 24–28 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9, 10, 12 Edits to COUT—Checking the Capacitance section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Edits to Power MOSFETs Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 PRINTED IN U.S.A. Changes to Figure 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 –16– REV. B