LMD18200QML LMD18200QML 2.4A, 55V H-Bridge Literature Number: SNOSAS1 LMD18200QML 2.4A, 55V H-Bridge General Description The LMD18200 is a 2.4A H-Bridge designed for motion control applications. The device is built using a multi-technology process which combines bipolar and CMOS control circuitry with DMOS power devices on the same monolithic structure. Ideal for driving DC and stepper motors; the LMD18200 accommodates peak output currents up to 6A. An innovative circuit which facilitates low-loss sensing of the output current has been implemented. Features ■ ■ ■ ■ Delivers up to 2.4A continuous output Operates at supply voltages up to 55V Low RDS(On) typically 0.3Ω per switch TTL and CMOS compatible inputs ■ ■ ■ ■ ■ ■ No “shoot-through” current Thermal warning flag output at 145°C Thermal shutdown (outputs off) at 170°C Internal clamp diodes Shorted load protection Internal charge pump with external bootstrap capability Applications ■ ■ ■ ■ ■ DC and stepper motor drives Position and velocity servomechanisms Factory automation robots Numerically controlled machinery Computer printers and plotters Ordering Information NS Part Number SMD Part Number NS Package Number Package Description LMD18200-2D/883 5962-9232501MXA DA24B 24LD Ceramic Dip Connection Diagrams and Ordering Information 20160925 24-Lead Dual-in-Line Package Top View See NS Package DA24B © 2010 National Semiconductor Corporation 201609 www.national.com LMD18200QML 2.4A, 55V H-Bridge November 30, 2010 LMD18200QML Functional Diagram 20160901 FIGURE 1. Functional Block Diagram of LMD18200 www.national.com 2 LMD18200QML Absolute Maximum Ratings (Note 1) Total Supply Voltage (VS, Pin 6 & 7) Voltage at Pins 3, 4, 5, 9, 10, 15, 16, 17, 21 and 22 Voltage at Bootstrap Pins (Pins 1, 12, 13 and 24) Peak Output Current (200 mS) Continuous Output Current (Note 4) Power Dissipation (Note 2), (Note 3) Power Dissipation (TA = 25°C, Free Air) Junction Temperature (TJmax) Thermal Resistance 60V 12V VO +16V 6A 2.4A 25W 3W 150°C θJA Still Air 500LF/Min Air flow 40.5°C/W 13°C/W 1.4°C/W θJC (Note 3) ESD Susceptibility (Note 5) Storage Temperature (TStg) 1500V −65°C ≤ TA ≤ +150°C 300°C Lead Temperature (Soldering, 10 sec.) Operating Ratings (Note 1) −55°C ≤ TJ ≤ +125°C +12V to +55V Junction Temperature, TJ VS Supply Voltage Quality Conformance Inspection Mil-Std-883, Method 5005 - Group A Subgroup Description 1 Static tests at Temp (°C) +25 2 Static tests at +125 3 Static tests at -55 4 Dynamic tests at +25 5 Dynamic tests at +125 6 Dynamic tests at -55 7 Functional tests at +25 8A Functional tests at +125 8B Functional tests at -55 9 Switching tests at +25 10 Switching tests at +125 11 Switching tests at -55 12 Settling time at +25 13 Settling time at +125 14 Settling time at -55 3 www.national.com LMD18200QML LMD18200 Electrical Characteristics DC Parameters The following conditions apply, unless otherwise specified. Symbol Parameter VS = 42V Conditions Notes RDS On Switch On Resistance Output current = 2.4A (Note 6) VClamp Clamp Diode Forward Drop Clamp current = 2.4A (Note 6) VIL Logic Low Input Voltage IIL Logic Low Input Current VIH Logic High Input Voltage IIH Logic High Input Current VI = 12V IO Sense Current Sense Output IO = 1A IO Sense Current Sense Output IO = 1A ILI Sense Current Sense Linearity 1A ≤ IO≤ 2.4A Undervoltage Lockout Outputs turn Off IF Off Flag Output Leakage VF = 12V IS Quiescent Supply Current All Logic Inputs Low (Note 8) VI = -0.1V Min -0.1 (Note 8) (Note 8) Units 0.6 Ω 1 0.7 1.70 Ω V 2, 3 1, 2, 3 0.8 V 1, 2, 3 -10 µA 1, 2, 3 2.0 12 V 1, 2, 3 10 µA 1, 2, 3 250 500 µA 1 225 525 µA 2, 3 -20 20 % 1, 2, 3 9.0 15 V 1, 2, 3 10 µA 1, 2, 3 25 mA 1, 2, 3 (Note 8) (Note 7) Subgroups Max Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test conditions. Note 2: The maximum power dissipation must be derated at elevated temperatures and is dictated by TJmax (maximum junction temperature), θJA (package junction to ambient thermal resistance), and TA (ambient temperature). The maximum allowable power dissipation at any temperature is PDmax = (TJmax - TA)/ θJA or the number given in the Absolute Maximum Ratings, whichever is lower. Note 3: The package material for these devices allows much improved heat transfer over our standard ceramic packages. In order to take full advantage of this improved heat transfer, heat sinking must be provided between the package base (directly beneath the die), and either metal traces on, or thermal vias through, the printed circuit board. Without this additional heat sinking, device power dissipation must be calculated using θJA, rather than θJC, thermal resistance. It must not be assumed that the device leads will provide substantial heat transfer out of the package, since the thermal resistance of the leadframe material is very poor, relative to the material of the package base. The stated θJC thermal resistance is for the package material only, and does not account for the additional thermal resistance between the package base and the printed circuit board. The user must determine the value of the additional thermal resistance and must combine this with the stated value for the package, to calculate the total allowed power dissipation for the device. Note 4: See Application Information for details regarding current limiting. Note 5: Human-body model, 100 pF discharged through a 1.5 kΩ resistor. Except Bootstrap pins (pins 1, 12, 13 and 24) which are protected to 1000V of ESD. Note 6: Output currents are pulsed (Duty Cycle < 5%). Note 7: Linearity is calculated relative to the current sense output value with 1A load. Note 8: Pins 3, 4, 5, 15, 16 and 17 www.national.com 4 LMD18200QML Typical Performance Characteristics VSat vs Flag Current RDS(On) vs Temperature 20160916 20160917 RDS(On) vs Supply Voltage Supply Current vs Supply Voltage 20160919 20160918 Supply Current vs Frequency (VS = 42V) Supply Current vs Temperature (VS = 42V) 20160921 20160920 5 www.national.com LMD18200QML Current Sense Output vs Load Current Current Sense Operating Region 20160923 20160922 Test Circuit 20160908 www.national.com 6 LMD18200QML Switching Time Definitions 20160909 Pinout Description (See Connection Diagram) Pin 1, BOOTSTRAP 1 Input: Bootstrap capacitor pin for half H-bridge number 1. The recommended capacitor (10 nF) is connected between pins 1 and 2. Pin 2, OUTPUT 1: Half H-bridge number 1 output. Pin 3, DIRECTION Input: See Table 1. This input controls the direction of current flow between OUTPUT 1 and OUTPUT 2 (pins 2 and 10) and, therefore, the direction of rotation of a motor load. Pin 4, BRAKE Input: See Table 1. This input is used to brake a motor by effectively shorting its terminals. When braking is desired, this input is taken to a logic high level and it is also necessary to apply logic high to PWM input, pin 5. The drivers that short the motor are determined by the logic level at the DIRECTION input (Pin 3): with Pin 3 logic high, both current sourcing output transistors are ON; with Pin 3 logic low, both current sinking output transistors are ON. All output transistors can be turned OFF by applying a logic high to Pin 4 and a logic low to PWM input Pin 5; in this case only a small bias current (approximately −1.5 mA) exists at each output pin. Pin 5, PWM Input: See Table 1. How this input (and DIRECTION input, Pin 3) is used is determined by the format of the PWM Signal. Pin 6, VS Power Supply Pin 7, GROUND Connection: This pin is the ground return, and is internally connected to the mounting tab. Pin 8, CURRENT SENSE Output: This pin provides the sourcing current sensing output signal, which is typically 377 μA/A. Pin 9, THERMAL FLAG Output: This pin provides the thermal warning flag output signal. Pin 9 becomes active-low at 145°C (junction temperature). However the chip will not shut itself down until 170°C is reached at the junction. Pin 10, OUTPUT 2: Half H-bridge number 2 output. Pin 11, BOOTSTRAP 2 Input: Bootstrap capacitor pin for Half H-bridge number 2. The recommended capacitor (10 nF) is connected between pins 10 and 11. 7 www.national.com LMD18200QML Sign/magnitude PWM consists of separate direction (sign) and amplitude (magnitude) signals (see Figure 3). The (absolute) magnitude signal is duty-cycle modulated, and the absence of a pulse signal (a continuous logic low level) represents zero drive. Current delivered to the load is proportional to pulse width. For the LMD18200, the DIRECTION input (pin 3) is driven by the sign signal and the PWM input (pin 5) is driven by the magnitude signal. TABLE 1. Logic Truth Table PWM Dir Brake H H L H H L H L X H L X L L L H H H Active Output Drivers Source 1, Sink 2 Sink 1, Source 2 Source 1, Source 2 Source 1, Source 2 Sink 1, Sink 2 None Application Information TYPES OF PWM SIGNALS The LMD18200 readily interfaces with different forms of PWM signals. Use of the part with two of the more popular forms of PWM is described in the following paragraphs. Simple, locked anti-phase PWM consists of a single, variable duty-cycle signal in which is encoded both direction and amplitude information (see Figure 2). A 50% duty-cycle PWM signal represents zero drive, since the net value of voltage (integrated over one period) delivered to the load is zero. For the LMD18200, the PWM signal drives the direction input (pin 3) and the PWM input (pin 5) is tied to logic high. 20160905 FIGURE 3. Sign/Magnitude PWM Control SIGNAL TRANSITION REQUIREMENTS To ensure proper internal logic performance, it is good practice to avoid aligning the falling and rising edges of input signals. A delay of at least 1 µsec should be incorporated between transitions of the Direction, Brake, and/or PWM input signals. A conservative approach is be sure there is at least 500ns delay between the end of the first transition and the beginning of the second transition. See Figure 4. 20160904 FIGURE 2. Locked Anti-Phase PWM Control 20160924 FIGURE 4. Transitions in Brake, Direction, or PWM Must Be Separated By At Least 1 µsec www.national.com 8 INTERNAL CHARGE PUMP AND USE OF BOOTSTRAP CAPACITORS To turn on the high-side (sourcing) DMOS power devices, the gate of each device must be driven approximately 8V more positive than the supply voltage. To achieve this an internal charge pump is used to provide the gate drive voltage. As shown in Figure 5, an internal capacitor is alternately switched to ground and charged to about 14V, then switched to V supply thereby providing a gate drive voltage greater than V supply. This switching action is controlled by a continuously running internal 300 kHz oscillator. The rise time of this drive voltage is typically 20 μs which is suitable for operating frequencies up to 1 kHz. USING THE THERMAL WARNING FLAG The THERMAL FLAG output (pin 9) is an open collector transistor. This permits a wired OR connection of thermal warning flag outputs from multiple LMD18200's, and allows the user to set the logic high level of the output signal swing to match system requirements. This output typically drives the interrupt input of a system controller. The interrupt service routine would then be designed to take appropriate steps, such as reducing load currents or initiating an orderly system shutdown. The maximum voltage compliance on the flag pin is 12V. SUPPLY BYPASSING During switching transitions the levels of fast current changes experienced may cause troublesome voltage transients across system stray inductance. It is normally necessary to bypass the supply rail with a high quality capacitor(s) connected as close as possible to the VS Power Supply (Pin 6) and GROUND (Pin 7). A 1 μF highfrequency ceramic capacitor is recommended. Care should be taken to limit the transients on the supply pin below the Absolute Maximum Rating of the device. When operating the chip at supply voltages above 40V a voltage suppressor (transorb) such as P6KE62A is recommended from supply to ground. Typically the ceramic capacitor can be eliminated in the presence of the voltage suppressor. Note that when driving high load currents a greater amount of supply bypass capacitance (in general at least 100 μF per Amp of load current) is required to absorb the recirculating currents of the inductive loads. 20160906 FIGURE 5. Internal Charge Pump Circuitry For higher switching frequencies, the LMD18200 provides for the use of external bootstrap capacitors. The bootstrap principle is in essence a second charge pump whereby a large value capacitor is used which has enough energy to quickly charge the parasitic gate input capacitance of the power device resulting in much faster rise times. The switching action is accomplished by the power switches themselves Figure 6. External 10 nF capacitors, connected from the outputs to the bootstrap pins of each high-side switch provide typically less than 100 ns rise times allowing switching frequencies up to 500 kHz. CURRENT LIMITING Current limiting protection circuitry has been incorporated into the design of the LMD18200. With any power device it is important to consider the effects of the substantial surge currents through the device that may occur as a result of shorted loads. The protection circuitry monitors this increase in current (the threshold is set to approximately 10 Amps) and shuts off the power device as quickly as possible in the event of an overload condition. In a typical motor driving application the most common overload faults are caused by shorted motor windings and locked rotors. Under these conditions the inductance of the motor (as well as any series inductance in the VCC supply line) serves to reduce the magnitude of a current surge to a safe level for the LMD18200. Once the device is shut down, the control circuitry will periodically try to turn the power device back on. This feature allows the immediate return to normal operation in the event that the fault condition has been removed. While the fault remains however, the device will cycle in and out of thermal shutdown. This can create voltage transients on the VCC supply line and therefore proper supply bypassing techniques are required. The most severe condition for any power device is a direct, hard-wired (“screwdriver”) long term short from an output to ground. This condition can generate a surge of current 9 www.national.com LMD18200QML through the power device on the order of 15 Amps and require the die and package to dissipate up to 500 Watts of power for the short time required for the protection circuitry to shut off the power device. This energy can be destructive, particularly at higher operating voltages (>30V) so some precautions are in order. Proper heat sink design is essential and it is normally necessary to heat sink the VCC supply pin (pin 6) with 1 square inch of copper on the PCB. USING THE CURRENT SENSE OUTPUT The CURRENT SENSE output (pin 8) has a sensitivity of 377 μA per ampere of output current. For optimal accuracy and linearity of this signal, the value of voltage generating resistor between pin 8 and ground should be chosen to limit the maximum voltage developed at pin 8 to 5V, or less. The maximum voltage compliance is 12V. It should be noted that the recirculating currents (free wheeling currents) are ignored by the current sense circuitry. Therefore, only the currents in the upper sourcing outputs are sensed. LMD18200QML The reverse recovery characteristics of these diodes, once the transient has subsided, is important. These diodes must come out of conduction quickly and the power switches must be able to conduct the additional reverse recovery current of the diodes. The reverse recovery time of the diodes protecting the sourcing power devices is typically only 70 ns with a reverse recovery current of 1A when tested with a full 6A of forward current through the diode. For the sinking devices the recovery time is typically 100 ns with 4A of reverse current under the same conditions. Typical Applications FIXED OFF-TIME CONTROL This circuit controls the current through the motor by applying an average voltage equal to zero to the motor terminals for a fixed period of time, whenever the current through the motor exceeds the commanded current. This action causes the motor current to vary slightly about an externally controlled average level. The duration of the Off-period is adjusted by the resistor and capacitor combination of the LM555. In this circuit the Sign/Magnitude mode of operation is implemented (see Types of PWM Signals). 20160907 FIGURE 6. Bootstrap Circuitry INTERNAL PROTECTION DIODES A major consideration when switching current through inductive loads is protection of the switching power devices from the large voltage transients that occur. Each of the four switches in the LMD18200 have a built-in protection diode to clamp transient voltages exceeding the positive supply or ground to a safe diode voltage drop across the switch. 20160910 FIGURE 7. Fixed Off-Time Control www.national.com 10 LMD18200QML 20160911 FIGURE 8. Switching Waveforms LM3524D is a general purpose PWM controller. The relationship of peak motor current to adjustment voltage is shown in Figure 10. TORQUE REGULATION Locked Anti-Phase Control of a brushed DC motor. Current sense output of the LMD18200 provides load sensing. The 20160912 FIGURE 9. Locked Anti-Phase Control Regulates Torque 11 www.national.com LMD18200QML 20160913 FIGURE 10. Peak Motor Current vs Adjustment Voltage of motor speed to the speed adjustment control voltage is shown in Figure 12. VELOCITY REGULATION Utilizes tachometer output from the motor to sense motor speed for a locked anti-phase control loop. The relationship 20160914 FIGURE 11. Regulate Velocity with Tachometer Feedback www.national.com 12 LMD18200QML 20160915 FIGURE 12. Motor Speed vs Control Voltage 13 www.national.com LMD18200QML Revision History Released 11/30/2010 www.national.com Revision A Section Changes New Release, Corporate format 14 1 MDS data sheet converted into one Corp. data sheet format. The drift table was eliminated from the 883 section since it did not apply; MNLM18200-2-X Rev 1A1 will be archived. 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