SEMICONDUCTOR TECHNICAL DATA ! The MC10H/100H646 is a single supply, low skew translating 1:8 clock driver. Devices in the Motorola H600 translator series utilize the 28–lead PLCC for optimal power pinning, signal flow through and electrical performance. The single supply H646 is similar to the H643, which is a dual supply 1:8 version of the same function. • • • • • • • • • • PENTIUM MICROPROCESSOR PECL/TTL–TTL CLOCK DRIVER PECL/TTL–TTL Version of Popular ECLinPS E111 Low Skew Guaranteed Skew Spec Tri–State Enable Differential Internal Design VBB Output Single Supply Extra TTL and ECL Power/Ground Pins Matched High and Low Output Impedance Meets Specifications Required to Drive the Pentium Microprocessor FN SUFFIX PLASTIC PACKAGE The H646 was designed specifically to drive series terminated CASE 776–02 transmission lines. Special techniques were used to match the HIGH and LOW output impedances to about 7ohms. This simplifies the choice of the termination resistor for series terminated applications. To match the HIGH and LOW output impedances, it was necessary to remove the standard IOS limiting resistor. As a result, the user should take care in preventing an output short to ground as the part will be permanently damaged. The H646 device meets all of the requirements for driving the 60 and 66MHz Pentium Microprocessor. The device has no PLL components, which greatly simplifies its implementation into a digital design. The eight copies of the clock allows for point–to–point clock distribution to simplify board layout and optimize signal integrity. The H646 provides differential PECL inputs for picking up LOW skew PECL clocks from the backplane and distributing it to TTL loads on a daughter board. When used in conjunction with the MC10/100E111, very low skew, very wide clock trees can be designed. In addition, a TTL level clock input is provided for flexibility. Note that only one of the inputs can be used on a single chip. For correct operation, the unused input pins should be left open. The Output Enable pin forces the outputs into a high impedance state when a logic 0 is applied. The output buffers of the H646 can drive two series terminated, 50Ω transmission lines each. This capability allows the H646 to drive up to 16 different point–to–point clock loads. Refer to the Applications section for a more detailed discussion in this area. The 10H version is compatible with MECL 10H ECL logic levels. The 100H version is compatible with 100K levels. MECL 10H and ECLinPS are trademarks of Motorola, Inc. Pentium is a trademark of Intel Corporation. 8/94 Motorola, Inc. 1996 1 REV 1 Q4 OGND Q5 OVT Q6 OGND Q7 25 24 23 22 21 20 19 PIN NAMES PIN Q3 26 18 EN OGND 27 17 IVT Q2 28 16 IGND 15 VCCE Pinout: 28–Lead PLCC (Top View) OVT 1 Q1 2 14 VCCE OGND 3 13 VBB Q0 4 12 ECLK TTL Output Ground (0V) TTL Output VCC (+5.0V) Internal TTL GND (0V) Internal TTL VCC (+5.0V) ECL VEE (0V) ECL Ground (5.0V) Differential Signal Input (PECL) VBB Reference Output Signal Outputs (TTL) Tri–State Enable Input (TTL) OGND OVT IGND IVT VEE VCCE ECLK, ECLK VBB Q0–Q7 EN 11 IVT01 INTERNAL TTL POWER ECLK 10 VEE 9 VEE 8 VEE 7 IGND 6 IVT TCLK 5 FUNCTION OVT01 Q0A LOGIC DIAGRAM EN Q0 OGND0 INTERNAL TTL GROUND Q1 IGND01 Figure 1. Output Structure Q2 Power versus Frequency per Bit 700 TCLK Q3 PDynamic = CL ƒ VSwing VCC PTotal = PStatic + PDynamic 600 ECLK 300pF 500 ECLK POWER, mW Q4 Q5 200pF 400 300 100pF 200 Q6 50pF 100 Q7 No Load 0 0 20 40 60 80 100 120 FREQUENCY, MHz Figure 2. Power versus Frequency (Typical) TRUTH TABLE TCLK ECLK ECLK EN Q GND GND H L X L H GND GND X H L GND GND X H H H H L L H H L Z L = Low Voltage Level; H = High Voltage Level; Z = Tristate MOTOROLA 2 TIMING SOLUTIONS BR1333 — Rev 6 DC CHARACTERISTICS (IVT = OVT = VCCE = 5.0V ±5%) 0°C Symbol Characteristic 25°C 85°C Min Max Min Max Min Max Unit Condition VOH Output HIGH Voltage 2.6 – – 2.6 – – 2.6 – – V IOH = 24mA VOL Output LOW Voltage – 0.5 – 0.5 – 0.5 V IOL = 48mA IOS Output Short Circuit Current – – – – – – mA See Note 1 1. The outputs must not be shorted to ground, as this will result in permanent damage to the device. The high drive outputs of this device do not include a limiting IOS resistor. TTL DC CHARACTERISTICS (VT = VE = 5.0 V ±5%) 0°C Symbol Characteristic VIH VIL Input HIGH Voltage Input LOW Voltage IIH Min 25°C Max Min 2.0 85°C Max 2.0 Min Max 2.0 Unit Condition V 0.8 0.8 0.8 Input HIGH Current 20 100 20 100 20 100 µA VIN = 2.7 V VIN = 7.0 V IIL Input LOW Current –0.6 –0.6 –0.6 mA VIN = 0.5 V VOH Output HIGH Voltage VOL Output LOW Voltage 0.5 0.5 VIK Input Clamp Voltage –1.2 –1.2 IOS Output Short Circuit Current 2.5 2.0 2.5 2.0 –100 –225 –100 2.5 2.0 –225 –100 V IOH = –3.0 mA IOH = –24 mA 0.5 V IOL = 24 mA –1.2 V IIN = –18 mA –225 mA VOUT = 0 V 10H PECL DC CHARACTERISTICS (IVT = OVT = VCCE = 5.0V ±5%) 0°C Symbol Characteristic Min Typ 25°C Max Min Typ 225 85°C Max Min Typ 175 Max Unit 175 µA Notes IIH Input HIGH Current IIL Input LOW Current 0.5 VIH Input HIGH Voltage 3.83 4.16 3.87 4.19 3.94 4.28 V IVT = IVO = VCCE = 5.0V (1) VIL Input LOW Voltage 3.05 3.52 3.05 3.52 3.05 3.555 V IVT = IVO = VCCE = 5.0V (1) VBB Output Reference Voltage 3.62 3.73 3.65 3.75 3.69 3.81 V IVT = IVO = VCCE = 5.0V (1) Max Unit Notes 175 µA 0.5 µA 0.5 100H PECL DC CHARACTERISTICS (IVT = OVT = VCCE = 5.0V ±5%) 0°C Symbol Characteristic Min Typ 25°C Max Min 225 Typ 85°C Max Min 175 Typ IIH Input HIGH Current IIL Input LOW Current 0.5 VIH Input HIGH Voltage 3.835 4.12 3.835 4.12 3.835 3.835 V IVT = IVO = VCCE = 5.0V (1) VIL Input LOW Voltage 3.19 3.525 3.19 3.525 3.19 3.525 V IVT = IVO = VCCE = 5.0V (1) VBB Output Reference Voltage 3.62 3.74 3.62 3.74 3.62 3.74 V IVT = IVO = VCCE = 5.0V (1) 0.5 µA 0.5 1. ECL VIH, VIL and VBB are referenced to VCCE and will vary 1:1 with the power supply. The levels shown are for IVT = IVO = VCCE = 5.0V TIMING SOLUTIONS BR1333 — Rev 6 3 MOTOROLA DC CHARACTERISTICS (IVT = OVT = VCCE = 5.0V ±5%) 0°C Symbol Min Max 185 166 ICCH 175 154 ICCZ 210 Power Supply Current Max Min 85°C Typ ICCL Characteristic 25°C Min Max Unit 185 185 mA 175 175 mA 210 210 Condition Total all OVT, IVT, and VCCE pins AC CHARACTERISTICS (IVT = OVT = VCCE = 5.0V ±5%) 0°C Symbol 1. 2. 3. 4. 5. 6. Characteristic 25°C 85°C Min Max Min Max Min Max Unit tPLH Propagation Delay ECLK to Q TCLK to Q 4.8 5.1 5.8 6.4 5.0 5.3 6.0 6.4 5.6 5.7 6.6 7.0 ns tPHL Propagation Delay ECLK to Q TCLK to Q 4.4 4.7 5.4 6.0 4.4 4.8 5.4 5.9 4.8 5.2 5.8 6.5 ns tSK(O) Output Skew tSK(PR) Process Skew tSK(P) Pulse Skew tr, tf Rise/Fall Time tPW Output Pulse Width tStability Clock Stability ±75 ±75 FMAX Maximum Input Frequency 80 80 Condition Q0, Q3, Q4, Q7 Q1, Q2, Q5 Q0–Q7 350 350 500 350 350 500 350 350 500 ps Note 1, 6 ECLK to Q TCLK to Q 1.0 1.3 1.0 1.1 1.0 1.3 ns Note 2, 6 ∆tPLH – tPHL 1.0 1.0 1.0 ns 1.5 ns 0.3 66MHz @ 2.0V 66MHz @ 0.8V 60MHz @ 2.0V 60MHz @ 0.8V 1.5 5.5 5.5 6.0 6.0 0.3 1.5 5.5 5.5 6.0 6.0 0.3 5.5 5.5 6.0 6.0 ns Note 3, 6 ±75 ps Note 4, 6 80 MHz Note 5, 6 Output skew defined for identical output transitions. Process skew is valid for VCC = 5.0V ±5%. Parameters guaranteed by tSK(P) and tr, tf specification limits. Clock stability is the period variation between two successive rising edges. For series terminated lines. See Applications section for FMAX enhancement techniques. All AC specifications tested driving 50Ω series terminated transmission lines at 80MHz. MOTOROLA 4 TIMING SOLUTIONS BR1333 — Rev 6 OUTLINE DIMENSIONS FN SUFFIX PLASTIC PLCC PACKAGE CASE 776–02 ISSUE D 0.007 (0.180) B T L–M M N S T L–M S S Y BRK –N– 0.007 (0.180) U M N S D Z –M– –L– W 28 D X G1 0.010 (0.250) T L–M S N S S V 1 VIEW D–D A 0.007 (0.180) R 0.007 (0.180) M T L–M S N S C M T L–M S N 0.007 (0.180) H Z M T L–M N S S S K1 E 0.004 (0.100) G J S K SEATING PLANE F VIEW S G1 0.010 (0.250) –T– T L–M S N S M T L–M S N S VIEW S NOTES: 1. DATUMS –L–, –M–, AND –N– DETERMINED WHERE TOP OF LEAD SHOULDER EXITS PLASTIC BODY AT MOLD PARTING LINE. 2. DIMENSION G1, TRUE POSITION TO BE MEASURED AT DATUM –T–, SEATING PLANE. 3. DIMENSIONS R AND U DO NOT INCLUDE MOLD FLASH. ALLOWABLE MOLD FLASH IS 0.010 (0.250) PER SIDE. 4. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 5. CONTROLLING DIMENSION: INCH. 6. THE PACKAGE TOP MAY BE SMALLER THAN THE PACKAGE BOTTOM BY UP TO 0.012 (0.300). DIMENSIONS R AND U ARE DETERMINED AT THE OUTERMOST EXTREMES OF THE PLASTIC BODY EXCLUSIVE OF MOLD FLASH, TIE BAR BURRS, GATE BURRS AND INTERLEAD FLASH, BUT INCLUDING ANY MISMATCH BETWEEN THE TOP AND BOTTOM OF THE PLASTIC BODY. 7. DIMENSION H DOES NOT INCLUDE DAMBAR PROTRUSION OR INTRUSION. THE DAMBAR PROTRUSION(S) SHALL NOT CAUSE THE H DIMENSION TO BE GREATER THAN 0.037 (0.940). THE DAMBAR INTRUSION(S) SHALL NOT CAUSE THE H DIMENSION TO BE SMALLER THAN 0.025 (0.635). TIMING SOLUTIONS BR1333 — Rev 6 0.007 (0.180) 5 DIM A B C E F G H J K R U V W X Y Z G1 K1 INCHES MIN MAX 0.485 0.495 0.485 0.495 0.165 0.180 0.090 0.110 0.013 0.019 0.050 BSC 0.026 0.032 0.020 ––– 0.025 ––– 0.450 0.456 0.450 0.456 0.042 0.048 0.042 0.048 0.042 0.056 ––– 0.020 2_ 10_ 0.410 0.430 0.040 ––– MILLIMETERS MIN MAX 12.32 12.57 12.32 12.57 4.20 4.57 2.29 2.79 0.33 0.48 1.27 BSC 0.66 0.81 0.51 ––– 0.64 ––– 11.43 11.58 11.43 11.58 1.07 1.21 1.07 1.21 1.07 1.42 ––– 0.50 2_ 10_ 10.42 10.92 1.02 ––– MOTOROLA Motorola reserves the right to make changes without further notice to any products herein. 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How to reach us: USA / EUROPE / Locations Not Listed: Motorola Literature Distribution; P.O. Box 5405; Denver, Colorado 80217. 303–675–2140 or 1–800–441–2447 JAPAN: Nippon Motorola Ltd.; Tatsumi–SPD–JLDC, 6F Seibu–Butsuryu–Center, 3–14–2 Tatsumi Koto–Ku, Tokyo 135, Japan. 81–3–3521–8315 Mfax: [email protected] – TOUCHTONE 602–244–6609 INTERNET: http://www.mot.com/sps/ ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd.; 8B Tai Ping Industrial Park, 51 Ting Kok Road, Tai Po, N.T., Hong Kong. 852–26629298 MOTOROLA ◊ 6 *MC10H646/D* MC10H646/D TIMING SOLUTIONS BR1333 — Rev 6