ONSEMI MC100H642

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
68030/040 PECL-TTL Clock Driver
MC10H642
MC100H642
The MC10H/100H642 generates the necessary clocks for the 68030,
68040 and similar microprocessors. It is guaranteed to meet the clock
specifications required by the 68030 and 68040 in terms of part–to–part
skew, within–part skew and also duty cycle skew.
The user has a choice of using either TTL or PECL (ECL referenced to
+5.0V) for the input clock. TTL clocks are typically used in present MPU
systems. However, as clock speeds increase to 50MHz and beyond, the
inherent superiority of ECL (particularly differential ECL) as a means of
clock signal distribution becomes increasingly evident. The H642 also
uses differential PECL internally to achieve its superior skew
characteristic.
The H642 includes divide–by–two and divide–by–four stages, both to
achieve the necessary duty cycle skew and to generate MPU clocks as
required. A typical 50MHz processor application would use an input clock
running at 100MHz, thus obtaining output clocks at 50MHz and 25MHz
(see Logic Diagram).
The 10H version is compatible with MECL 10H ECL logic levels,
while the 100H version is compatible with 100K levels (referenced to
+5.0V).
•
•
•
•
•
•
68030/040
PECL–TTL CLOCK
DRIVER
11
26
4
Generates Clocks for 68030/040
5
FN SUFFIX
PLASTIC PACKAGE
CASE 776–02
Meets 030/040 Skew Requirements
TTL or PECL Input Clock
Extra TTL and PECL Power/Ground Pins
Asynchronous Reset
Single +5.0V Supply
Function
Reset(R):
Select(SEL):
LOW on RESET forces all Q outputs LOW.
LOW selects the ECL input source (DE/DE).
HIGH selects the TTL input source (DT).
The H642 also contains circuitry to force a stable input state of the ECL differential input pair, should both sides be left open. In
this Case, the DE side of the input is pulled LOW, and DE goes HIGH.
Power Up:
The device is designed to have positive edges of the ÷2 and ÷4 outputs synchronized at Power Up.
VT
VT
Q1
GT
GT
Q0
VT
25
24
23
22
21
20
19
Q2
26
18
VBB
GT
27
17
DE
GT
28
16
DE
15
VE
Pinout: 28–Lead PLCC
(Top View)
Q3
1
VT
2
14
R
VT
3
13
GE
Q4
4
12
DT
5
6
7
8
9
10
11
Q5
GT
GT
Q6
Q7
VT
SEL
9/96
 Motorola, Inc. 1996
2–1
REV 4
MC10H642 MC100H642
LOGIC DIAGRAM
TTL Outputs
Q7
Q6
TTL/ECL Clock Inputs
VBB
DE
DE
Q5
MUX
÷4
Q4
DT
Q3
SEL
Q2
TTL Control Inputs
÷2
Q1
Q0
R
PIN NAMES
Pin
Symbol
81
82
83
84
85
86
87
88
89
10
11
12
13
14
Q3
VT
VT
Q4
Q5
GT
GT
Q6
Q7
VT
SEL
DT
GE
R
Description
Pin
Symbol
Signal Output (TTL)**
TTL VCC (+5.0V)
TTL VCC (+5.0V)
Signal Output (TTL)**
Signal Output (TTL)**
TTL Ground (0V)
TTL Ground (0V)
Signal Output (TTL)**
Signal Output (TTL)**
TTL VCC (+5.0V)
Input Select (TTL)
TTL Signal Input
ECL Ground (0V)
Reset (TTL)
15
16
17
18
19
20
21
22
23
24
25
26
27
28
VE
DE
DE
VBB
VT
Q0
GT
GT
Q1
VT
VT
Q2
GT
GT
Description
ECL VCC (+5.0V)
ECL Signal Input (Non–Inverting)
ECL Signal Input (Inverting)
VBB Reference Output
TTL VCC (+5.0V)
Signal Output (TTL)*
TTL Ground (0V)
TTL Ground (0V)
Signal Output (TTL)*
TTL VCC (+5.0V)
TTL VCC (+5.0V)
Signal Output (TTL)**
TTL Ground (0V)
TTL Ground (0V)
**Divide by 2
**Divide by 4
MOTOROLA
2–2
MECL Data
DL122 — Rev 6
MC10H642 MC100H642
AC CHARACTERISTICS (VT = VE = 5.0V ±5%)
TA = 0°C
Symbol
tPLH
Characteristic
Propagation Delay
D to Output
Q2–Q7
C ECL
C TTL
TA = 25°C
TA = 85°C
Min
Max
Min
Max
Min
Max
4.70
4.70
5.70
5.70
4.75
4.75
5.75
5.75
4.60
4.50
5.60
5.50
Unit
ns
tskpp
Part–to–Part Skew
tskwd*
Within–Device Skew
tPLH
Propagation Delay
D to Output
Q0, Q1
C ECL
C TTL
tskpp
Part–to–Part Skew
All
Outputs
tskwd
Within–Device Skew
tPD
Propagation Delay
R to Output
All
Outputs
tR
tF
Output Rise/Fall Time
0.8 V to 2.0 V
All
Outputs
fMAX**
Maximum Input Frequency
100
100
RPW
Reset Pulse Width
1.5
RRT
Reset Recovery Time
1.25
4.30
4.30
4.3
1.0
1.0
1.0
ns
0.5
0.5
0.5
ns
5.30
5.30
4.50
4.50
5.50
5.50
4.25
4.25
Condition
CL = 25pF
ns
CL = 25pF
5.25
5.25
2.0
2.0
2.0
ns
CL = 25pF
1.0
1.0
1.0
ns
CL = 25pF
6.5
ns
CL = 25pF
2.5
2.5
ns
CL = 25pF
100
MHz
CL = 25pF
1.5
1.5
ns
1.25
1.25
ns
6.3
4.0
2.5
2.5
6.0
4.5
2.5
2.5
* Within–Device Skew defined as identical transactions on similar paths through a device.
** NOTE: MAX Frequency is 135MHz.
10H PECL CHARACTERISTICS (VT = VE = 5.0V ±5%)
TA = 0°C
Symbol
IIH
IIL
Characteristic
Input HIGH Current
Input LOW Current
Min
TA = 25°C
Max
Min
225
Max
TA = 85°C
Min
175
0.5
0.5
Max
Unit
175
µA
Condition
0.5
* NOTE
VIH
VIL
Input HIGH Voltage
Input LOW Voltage
3.83
3.05
4.16
3.52
3.87
3.05
4.19
3.52
3.94
3.05
4.28
3.555
V
3.62
3.73
3.65
3.75
3.69
3.81
V
VEE = 5.0V
* NOTE
VBB
Output Reference Voltage
100H PECL CHARACTERISTICS (VT = VE = 5.0V ±5%)
TA = 0°C
Symbol
IIH
IIL
Characteristic
Input HIGH Current
Input LOW Current
Min
TA = 25°C
Max
Min
225
Max
TA = 85°C
Min
175
0.5
0.5
Max
Unit
175
µA
Condition
0.5
* NOTE
VIH
VIL
Input HIGH Voltage
Input LOW Voltage
3.835
3.190
4.120
3.525
3.835
3.190
4.120
3.525
3.835
3.190
4.120
3.525
V
3.620
3.740
3.620
3.740
3.620
3.740
V
VEE = 5.0V
* NOTE
VBB
Output Reference Voltage
*NOTE: PECL LEVELS are referenced to VCC and will vary 1:1 with the power supply. The VALUES shown are for VCC = 5.0V.
MECL Data
DL122 — Rev 6
2–3
MOTOROLA
MC10H642 MC100H642
10H/100H DC CHARACTERISTICS (VT = VE = 5.0V ±5%)
TA = 0°C
Symbol
IEE
Characteristic
Power Supply Current
ICCH
Min
TA = 25°C
Max
Unit
PECL
57
57
57
mA
VE Pin
TTL
30
30
30
mA
Total All VT Pins
30
30
30
mA
ICCL
Max
Min
Max
TA = 85°C
Min
Condition
10H/100H TTL DC CHARACTERISTICS (VT = VE = 5.0V ±5%)
TA = 0°C
Symbol
Characteristic
VIH
VIL
Input HIGH Voltage
Input LOW Voltage
IIH
Min
TA = 25°C
Max
Min
2.0
Max
2.0
TA = 85°C
Min
Max
2.0
Unit
Condition
V
0.8
0.8
0.8
Input HIGH Current
20
100
20
100
20
100
µA
VIN = 2.7V
VIN = 7.0V
IIL
Input LOW Current
–0.6
–0.6
–0.6
mA
VIN = 0.5V
VOH
Output HIGH Voltage
VOL
Output LOW Voltage
0.5
0.5
VIK
Input Clamp Voltage
–1.2
–1.2
IOS
Output Short Circuit Current
2.5
2.0
–100
2.5
2.0
–225
–100
2.5
2.0
–225
–100
V
IOH = –3.0mA
IOH = –15mA
0.5
V
IOL = 24mA
–1.2
V
IIN = –18mA
–225
mA
VOUT = 0V
10/100H642
DUTY CYCLE CONTROL
To maintain a duty cycle of ±5% at 50 MHz, limit the load capacitance and/or power supply variation as shown in Figures 1 and 2.
For a ±2.5% duty cycle limit, see Figures 3 and 4. Figures 5 and 6 show duty cycle variation with temperature. Figure 7 shows typical
TPD versus load. Figure 8 shows reset recovery time. Figure 9 shows output states after power up.
Best duty cycle control is obtained with a single µP load and minimum line length.
MOTOROLA
2–4
MECL Data
DL122 — Rev 6
MC10H642 MC100H642
11
NEGATIVE PULSE WIDTH (ns)
POSITIVE PULSE WIDTH (ns)
11
4.75
10
5.00
5.25
4.75
5.00
5.25
10
9
0
9
0
10
20
30
40
50
10
60
20
30
40
50
CAPACITIVE LOAD (pF)
60
CAPACITIVE LOAD (pF)
Figure 2. MC10H642 Negative PW versus
Load
@ ±5% VCC, TA = 25°C
10.6
10.8
10.4
10.6
NEGATIVE PULSE WIDTH (ns)
POSITIVE PULSE WIDTH (ns)
Figure 1. MC10H642 Positive PW versus Load
@ ±5% VCC, TA = 25°C
10.2
4.875
10.0
5.00
9.8
5.125
9.6
5.00
10.0
5.125
9.8
9.4
0
10
20
30
40
CAPACITIVE LOAD (pF)
50
60
0
10
20
30
40
50
60
CAPACITIVE LOAD (pF)
Figure 4. MC10H642 Negative PW versus Load
@ ±2.5% VCC, TA = 25°C
Figure 3. MC10H642 Positive PW versus Load
@ ±2.5% VCC, TA = 25°C
10.5
NEGATIVE PULSE WIDTH (ns)
10.4
POSITIVE PULSE WIDTH (ns)
4.875
10.2
9.6
9.4
9.2
10.4
10.2
10.0
0 pF
25 pF
50 pF
9.8
9.6
10.3
10.1
0 pF
25 pF
50 pF
9.9
9.7
9.5
9.4
0
20
40
60
TEMPERATURE (°C)
80
0
100
40
60
80
100
TEMPERATURE (°C)
Figure 5. MC10H642 Positive PW versus Temperature,
VCC = 5.0V
MECL Data
DL122 — Rev 6
20
Figure 6. MC10H642 Negative PW versus
Temperature, VCC = 5.0V
2–5
MOTOROLA
MC10H642 MC100H642
6.2
Tpd (ns)
6.0
5.8
4.75
5.00
5.6
5.25
5.4
5.2
0
10
20
30
40
50
60
CAPACITIVE (pF)
Figure 7. MC10H642 + Tpd versus Load, VCC ±5%, TA = 25°C
(Overshoot at 50 MHz with no load makes graph non linear)
DT
RESET, R
Q0
Q1
Q2
Q7
R
tpw
R
trec
MC10/100H642
Figure 8. Clock Phase and Reset Recovery Time After Reset Pulse
MC10/100H642
Din
Q0.Q1
Q4 & Q5
Q2
Q7
After Power Up
Figure 9. Outputs Q2
MOTOROLA
Q7 will Synchronize with Pos Edges of Din & Q0
2–6
Q1
MECL Data
DL122 — Rev 6
MC10H642 MC100H642
SWITCHING CIRCUIT AND WAVEFORMS
Switching Circuit PECL:
VEE
PECL
VCC & VCCO
TTL
USE 0.1 µF CAPACITORS
FOR DECOUPLING.
+7 V
50 Ω COAX
PULSE
GENERATOR
IN
DEVICE
UNDER
TEST
OUT
ALL
OTHERS
450 Ω
50 Ω COAX
50 Ω COAX
tPZL, tPLZ
OC
CH A
R1
500 Ω
DEVICE
UNDER
TEST
50 pF
USE OSCILLOSCOPE
INTERNAL 50 Ω LOAD
FOR TERMINATION.
OPEN
R2
500 Ω
CH B
OSCILLOSCOPE
WAVEFORMS: Rise and Fall Times
Propagation Delay — Single Ended
PECL/TTL
PECL/TTL
80%/2.0 V
50%/1.5 V
Vin
20%/0.8 V
Vout
Tpd++
Tpd––
50%/1.5 V
Trise
MECL Data
DL122 — Rev 6
Tfall
Vout
2–7
MOTOROLA
MC10H642 MC100H642
OUTLINE DIMENSIONS
FN SUFFIX
PLASTIC PLCC PACKAGE
CASE 776–02
ISSUE D
0.007 (0.180)
B
T L–M
M
N
S
T L–M
S
S
Y BRK
–N–
0.007 (0.180)
U
M
N
S
D
Z
–M–
–L–
W
28
D
X
G1
0.010 (0.250)
T L–M
S
N
S
S
V
1
VIEW D–D
A
0.007 (0.180)
R
0.007 (0.180)
M
T L–M
S
N
S
C
M
T L–M
S
N
0.007 (0.180)
H
Z
M
T L–M
N
S
S
S
K1
E
0.004 (0.100)
G
J
S
K
SEATING
PLANE
F
VIEW S
G1
0.010 (0.250)
–T–
T L–M
S
N
S
M
T L–M
S
N
S
VIEW S
NOTES:
1. DATUMS –L–, –M–, AND –N– DETERMINED
WHERE TOP OF LEAD SHOULDER EXITS
PLASTIC BODY AT MOLD PARTING LINE.
2. DIMENSION G1, TRUE POSITION TO BE
MEASURED AT DATUM –T–, SEATING PLANE.
3. DIMENSIONS R AND U DO NOT INCLUDE
MOLD FLASH. ALLOWABLE MOLD FLASH IS
0.010 (0.250) PER SIDE.
4. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
5. CONTROLLING DIMENSION: INCH.
6. THE PACKAGE TOP MAY BE SMALLER THAN
THE PACKAGE BOTTOM BY UP TO 0.012
(0.300). DIMENSIONS R AND U ARE
DETERMINED AT THE OUTERMOST
EXTREMES OF THE PLASTIC BODY
EXCLUSIVE OF MOLD FLASH, TIE BAR
BURRS, GATE BURRS AND INTERLEAD
FLASH, BUT INCLUDING ANY MISMATCH
BETWEEN THE TOP AND BOTTOM OF THE
PLASTIC BODY.
7. DIMENSION H DOES NOT INCLUDE DAMBAR
PROTRUSION OR INTRUSION. THE DAMBAR
PROTRUSION(S) SHALL NOT CAUSE THE H
DIMENSION TO BE GREATER THAN 0.037
(0.940). THE DAMBAR INTRUSION(S) SHALL
NOT CAUSE THE H DIMENSION TO BE
SMALLER THAN 0.025 (0.635).
MOTOROLA
0.007 (0.180)
2–8
DIM
A
B
C
E
F
G
H
J
K
R
U
V
W
X
Y
Z
G1
K1
INCHES
MIN
MAX
0.485
0.495
0.485
0.495
0.165
0.180
0.090
0.110
0.013
0.019
0.050 BSC
0.026
0.032
0.020
–––
0.025
–––
0.450
0.456
0.450
0.456
0.042
0.048
0.042
0.048
0.042
0.056
–––
0.020
2_
10_
0.410
0.430
0.040
–––
MILLIMETERS
MIN
MAX
12.32
12.57
12.32
12.57
4.20
4.57
2.29
2.79
0.33
0.48
1.27 BSC
0.66
0.81
0.51
–––
0.64
–––
11.43
11.58
11.43
11.58
1.07
1.21
1.07
1.21
1.07
1.42
–––
0.50
2_
10_
10.42
10.92
1.02
–––
MECL Data
DL122 — Rev 6
MC10H642 MC100H642
Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and
specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters which may be provided in Motorola
data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals”
must be validated for each customer application by customer’s technical experts. Motorola does not convey any license under its patent rights nor the rights of
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applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury
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arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that
Motorola was negligent regarding the design or manufacture of the part. Motorola and
are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal
Opportunity/Affirmative Action Employer.
How to reach us:
USA/EUROPE/Locations Not Listed: Motorola Literature Distribution;
P.O. Box 20912; Phoenix, Arizona 85036. 1–800–441–2447 or 602–303–5454
JAPAN: Nippon Motorola Ltd.; Tatsumi–SPD–JLDC, 6F Seibu–Butsuryu–Center,
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51 Ting Kok Road, Tai Po, N.T., Hong Kong. 852–26629298
◊
MECL Data
DL122 — Rev 6
2–9
*MC10H642/D*
MC10H642/D
MOTOROLA