TRIQUINT TQ8015

T
R
I
Q
U
I
N
T
S E M I C O N D U C T O R, I N C .
TQ8015
16 x 16
Crosspoint
Switch
Matrix
Input
Buffers
D0..15
D0..15
Output
Buffers
O0..15
O0..15
1.25 Gigabit/sec
16x16 Digital ECL
Crosspoint Switch
64
CONFIGURE
(R2)
Sixteen 4-Bit Latches
RESET
LOAD
IA0..3
4
(R1)
Sixteen 4-Bit Addressable
Output Select Latches
SWITCHING
PRODUCTS
64
VCC
VEE
OA0..3
4
4:16
Decoder
TQ8015
GND
The TQ8015 is a non-blocking 16 x 16 digital crosspoint switch capable of
data rates greater than 1.25 Gigabits per second per port. Utilizing a fully
differential internal data path and ECL I/O, the TQ8015 offers a high data
rate with exceptional signal fidelity. The symmetrical switching and noise
rejection characteristics inherent in differential logic result in low jitter and
signal skew. The TQ8015 is ideally suited for digital video, data
communications and telecommunication switching applications.
Typical output waveform with all
channels driven
Features
• >20 Gb/s aggregate BW
• 1.25 Gb/s/port NRZ data rate
• Non-blocking architecture
The non-blocking architecture uses 16 fully independent 16:1 multiplexers
(see diagram on page 2), allowing each output port to be independently
programmed to any input port. The switch is configured by sequentially
loading each multiplexer’s 4-bit program latch (OA0:3) with the desired
input port address (IA0:3) and enabling the LOAD pin. When complete, the
CONFIGURE pin is strobed and all new configurations are simultaneously
transferred into the switch multiplexers. Data integrity is maintained on all
unchanged data paths.
• Differential ECL-level data
I/O; CMOS-level control inputs
• Low jitter and signal skew
• Fully differential data path
• Double buffered configuration
latches
• 132-pin MQFP package
Electrical Characteristics
Min
Data Rate/Port
• 500 ps delay match
Max
1.25
Units
Gb/s
Jitter
150
ps peak-peak
Channel Propagation Delay
2000
ps
Ch-to-Ch Propagation Delay Skew
500
ps
Applications
Telecom/Datacom Switching
Hubs and Routers
Video Switching
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1
TQ8015
Figure 1. TQ8015 architecture.
16 X 1-BIT
MULTIPLEXER
.
16 X 1-BIT
MULTIPLEXER
DATA IN 0
(I0)
.
.
.
.
.
DATA
OUT 15
(O15)
Input
Buffers
.
.
DATA
OUT 0
(O0)
.
.
.
.
DATA IN 15
(I15)
Configuration
Register
CONFIGURE
RESET
LOAD
4:16
4 DECODE
OUTPUT
SELECT ADDRESS
(OA0:3)
5
Program Register
4
INPUT ADDRESS
(IA0:3)
Table 1. Absolute Maximum Ratings5
Symbol
Absolute Max. Rating
Notes
TSTOR
Storage Temperature
–65° C to +150° C
TCH
Junction (Channel) Temperature
–65° C to +150° C
TC
Case Temperature Under Bias
–65° C to +125° C
2
VCC
Supply Voltage
0 V to +7 V
3
VEE
Supply Voltage
–7 V to 0 V
3
VTT
Load Termination Supply Voltage
VEE to 0 V
4
VIN
Voltage Applied to Any ECL Input; Continuous
IIN
Current Into Any ECL Input; Continuous
–1.0 mA to +1.0 mA
VIN
Voltage Applied to Any CMOS Input; Continuous
–0.5 V to VCC +0.5 V
IIN
Current Into Any CMOS Input; Continuous
–1.0 mA to +1.0 mA
VOUT
Voltage Applied to Any ECL Output
VEE –0.5 V to +0.5 V
IOUT
Current From Any ECL Output; Continuous
–40 mA
PD
Power Dissipation per Output POUT = (GND – VOUT) x IOUT
50 mW
Notes:
2
Parameter
1
VEE –0.5 V to +0.5 V
1. For die applications.
2. TC is measured at case top.
3. All voltages specified with respect to GND, defined as 0V.
4. Subject to IOUT and power dissipation limitations.
5. Absolute maximum ratings, as detailed in this table, are the ratings beyond which the device's performance may be impaired
and/or permanent damage to the device may occur.
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4
TQ8015
Table 2. Recommended Operating Conditions3
Symbol
Parameter
Min
Typ
Max
Units
Notes
1
TC
Case Operating Temperature
0
85
°C
VCC
Supply Voltage
4.5
5.5
V
VEE
Supply Voltage
–5.5
VTT
Load Termination Supply Voltage
RLOAD
Output Termination Load Resistance
ΘJC
Thermal Resistance Junction to Case
–4.5
V
–2.0
V
2
50
Ω
2
7
°C/W
SWITCHING
PRODUCTS
Notes: 1. TC measured at case top. Use of adequate heatsink is required.
2. The VTT and RLOAD combination is subject to maximum output current and power restrictions.
3. Functionality and/or adherence to electrical specifications is not implied when the device is subjected to conditions that exceed,
singularly or in combination, the operating range specified.
Table 3. Pin Descriptions
Signal
Name/Level
Description
I0 to I15,
NI0 to NI15
Data input true and complement.
Differential ECL
Differential data input ports.
O0 to O15,
NO0 to NO15
Data output true and complement.
Differential ECL
Differential data output ports.
IA0:3
Input address, CMOS
Input port selection address that is written into the selected output port
program latches (OA0:3).
IA3
IA2
IA1
IA0
Input port
0
0
0
0
0
0
0
0
1
1
0
0
1
0
2
:
:
:
:
:
1
1
1
1
15
OA0:3
Output select address, CMOS
Output port selection address. Selects the output port program latches to
which the input port selection address (IA0:3) is written.
OA3
OA2
OA1
OA0
Output port
0
0
0
0
0
0
0
0
1
1
0
0
1
0
2
:
:
:
:
:
1
1
1
1
15
LOAD
CMOS
Enables the selected output port program latches while set ‘high’.
Latches the data when set to a 'low' level.
CONFIGURE
CMOS
Transfers the program latches data to the configuration latches and
implements the switch changes while set ‘high’. Latches the data when
set to a ‘low’ level.
RESET
CMOS
Sets the switch into broadcast or pass-through configuration, overwriting
existing configurations.
Broadcast mode: All output ports are connected to data input port 0. This
mode is selected by applying a RESET “high” pulse with CONFIGURE held “low”.
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3
TQ8015
Table 4. DC Characteristics1 – Within recommended operating conditions, unless otherwise indicated.
Symbol
Parameter
Min
Max
Units
Test Cond.
VIH
ECL Input Voltage High
–1100
–500
mV
VIL
ECL Input Voltage Low
VTT
–1500
mV
IIH
ECL Input Current High
+30
µA
VIH = –0.7 V
IIL
ECL Input Current Low
µA
VIL = –2.0 V
VICM
ECL Input Common Mode Voltage
VIDIF
VIH
–30
–1500
–1100
mV
ECL Input Differential Voltage (pk-pk)
400
1200
mV
CMOS Input Voltage High
3.5
VCC
V
VIL
CMOS Input Voltage Low
0
1.5
V
IIH
CMOS Input Current High
+100
µA
VIH = VCC
IIL
CMOS Input Current Low
–100
µA
VIL = 0 V
VOCM
ECL Output Common Mode
–1100
mV
VODIF
ECL Output Differential Voltage
VOH
ECL Output Voltage High
–1000
–600
mV
VOL
ECL Output Voltage Low
VTT
–1600
mV
IOH
ECL Output Current High
20
27
mA
IOL
ECL Output Current Low
0
8
mA
ICC
Power Supply Current (+)
20
mA
IEE
Power Supply Current (–)
–950
mA
–1500
600
Notes
mV
Notes: 1. Test conditions unless otherwise indicated: VTT = –2.0 V, RLOAD = 50 W to VTT.
Table 5. AC Characteristics1 – Within recommended operating conditions, unless otherwise indicated.
Symbol
Parameter
Min
Typ
Max
Units
Notes
Maximum Data Rate/Port
1.25
Gb/s
1,2
Jitter
150
ps pk-pk
1
T1
Channel Propagation Delay
2000
ps
T2
Ch-to-Ch Propagation Delay Skew
500
ps
T3
CONFIG to Data Out (Oi) Delay
T4
LOAD Pulse Width
T5
CONFIG Pulse Width
7
ns
T6
IAi to LOAD High Setup Time
0
ns
T7
LOAD to IAi Low Hold Time
3
ns
T8
OAi to LOAD High Setup Time
0
ns
T9
LOAD to OAi Low Hold Time
3
ns
T10
Load ↑ to CONFIG ↑
0
ns
T11
RESET Pulse Width
10
TR,F
Output Rise or Fall Time
5
7
ns
ns
ns
250
400
ps
3
Notes: 1. Test conditions: VTT = –2.0 V, RLOAD = 50 W to VTT; ECL inputs: VIH = –1.1 V; VIL = –1.5 V; CMOS inputs: VIH = 3.5 V, VIL = 1.5 V;
ECL outputs: VOH > –1.0 V, VOL < –1.6 V; ECL inputs rise and fall times < 1 ns; CMOS inputs rise and fall times < 20 ns. A bit error
rate of 1E–13 BER or better for 223–1PRBS pattern, jitter and rise/fall times are guaranteed through characterization.
2. 1.2 Gb/s Non-Return-Zero (NRZ) data equivalent to 600 MHz clock signal.
3. Rise and fall times are measured at the 20% and 80% points of the transition from VOL max to VOL min.
4
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TQ8015
Figure 2. Switch Configuration Timing
RESET
Input
Address
SWITCHING
PRODUCTS
Output
Address
LOAD
T4
T10
CONFIGURE
T8
T7
Data1
In
DA
T5
T9
T6
DB
DE
DD
DC
T1
Data1
Out
DF
DG
T3
OA
OB
OC
OE
OD
OF
OG
Invalid
Data Out
Note:1 No data loss on nchanged data paths
Notes: 1. No data loss on unchanged paths.
Figure 5. Reset Timing
RESET
T11
T3
CONFIGURE
Output
Data
Broadcast
Pass-through
Notes: 1. LOAD input must remain LOW to insure correct programming of the switch.
2. “Broadcast” is defined as data input 0 to all data outputs (0…15).
3. “Pass-through” is defined as data input 0 to data output 0, data input 1 to data output 1, and so on.
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5
TQ8015
Typical Performance Data
Figure 4. Data Eye Closure
Percent RMS vs. Data Rate (typical)
12
8
6
4
Figure 5. Data Eye Closure
Time & Amplitude vs Data Rate (typical)
2
0
0.5
0.7
0.9
1.1
1.3
1.5
100
1.7
Data Rate (Gb/s)
90
➤
Data Eye Period (%)
10
➤
80
Percent (%)
70
% Recoverable Data Eye
Period – (P-P Jitter) x 100 / Period
60
Inner Eye Amplitude
V (inner eye) x 100 / V (inner eye @ 400 Mb/s)
50
40
30
20
Figure 6. RMS Jitter vs. Data Rate (typical)
10
0
45
0.5
0.3
0.7
0.5
0.9
0.7
40
Jitter (ps)
35
30
25
20
15
10
0.5
0.7
0.9
1.1
1.3
1.5
1.7
Data Rate (Gb/s)
6
1.1
0.9
1.3
1.1
Data Rate (Gb/s)
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1.5
1.3
1.7
1.5
TQ8015
Top View
132-Pin Package
Note: Unmarked pins are not connected.
NOTE: All unmarked pins are not connected.
ND11
D11
GND
ND10
D10
GND
ND9
D9
GND
ND8
D8
GND
ND7
D7
GND
VCC
VEE
ND6
D6
GND
ND5
D5
GND
ND4
D4
GND
ND3
D3
GND
ND2
D2
SWITCHING
PRODUCTS
Pin 1 Index
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
GND
NO1
O1
GND
NO0
O0
GND
IADD3
IADD2
GND
IADD1
IADD0
VEE
VCC
GND
CONFIGURE
LOAD
GND
OADD3
OADD2
GND
OADD1
OADD0
GND
D0
ND0
GND
D1
ND1
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
NO11
O11
GND
NO10
O10
GND
NO9
O9
GND
NO8
O8
GND
NO7
O7
VCC
VEE
GND
NO6
O6
GND
NO5
O5
GND
NO4
O4
GND
NO3
O3
GND
NO2
O2
➤
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
GND
O12
NO12
GND
O13
NO13
GND
O14
NO14
GND
O15
NO15
GND
RESET
VEE
ND15
D15
GND
ND14
D14
GND
ND13
D13
GND
ND12
D12
GND
Figure 7. Package Pinout
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7
TQ8015
Figure 8. Mechanical Dimensions (in inches)
Top view
PIN 1
INDEX
Bottom view
CL
PIN 1
INDEX
17
117
18
0.010
PIN WIDTH
TYP.
TQ8015-Q
A
XXXX
YYWW
116
A
TQ8015-Q
0.400
0.540 0.467 REF. SQ.
± .003 ± .003
0.550
± .003
50
XXXX
YYWW
84
51
LOT CODE
DATE CODE
CL
83
Notes: 1. Part is symmetrical about the center axes.
2. Centerline bisects center pin in both directions.
3. See pad detail below.
Section A-A
0.140 ± .005
0.170 ± .010
0.025 TYP.
0.015
CL
SEATING PLANE
0.010
0.020
MIN.
0.053
0.512
CL
PAD LAYOUT DETAIL
Ordering Information
TQ8015-Q
1.25 16x16 Gb/s ECL Crosspoint Switch
Additional Information
For latest specifications, additional product information,
worldwide sales and distribution locations, and information about TriQuint:
Web: www.triquint.com
Email: [email protected]
Tel: (503) 615-9000
Fax: (503) 615-8900
For technical questions and additional information on specific applications:
Email: [email protected]
The information provided herein is believed to be reliable; TriQuint assumes no liability for inaccuracies or omissions.
TriQuint assumes no responsibility for the use of this information, and all such information shall be entirely at the
user's own risk. Prices and specifications are subject to change without notice. No patent rights or licenses to any of
the circuits described herein are implied or granted to any third party. TriQuint does not authorize or warrant any
TriQuint product for use in life-support devices and/or systems.
Copyright © 1997 TriQuint Semiconductor, Inc. All rights reserved.
Revision 1.1.A
November 1997
8
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