Dual Ultrafast Voltage Comparator ADCMP565 FEATURES 300 ps propagation delay input to output 50 ps propagation delay dispersion Differential ECL compatible outputs Differential latch control Robust input protection Input common-mode range −2.0 V to +3.0 V Input differential range ±5 V Power supply sensitivity greater than 65 dB 200 ps minimum pulsewidth 5 GHz equivalent input rise time bandwidth Typical output rise/fall of 160 ps SPT 9689 replacement APPLICATIONS High speed instrumentation Scope and logic analyzer front ends Window comparators High speed line receivers and signal restoration Threshold detection Peak detection High speed triggers Patient diagnostics Disk drive read channel detection Hand-held test instruments Zero-crossing detectors Clock drivers Automatic test equipment FUNCTIONAL BLOCK DIAGRAM NONINVERTING INPUT INVERTING INPUT Q OUTPUT ADCMP565 Q OUTPUT LATCH ENABLE INPUT LATCH ENABLE INPUT 02820-0-001 Figure 1. GENERAL DESCRIPTION The ADCMP565 is an ultrafast voltage comparator fabricated on Analog Devices’ proprietary XFCB process. The device features 300 ps propagation delay with less than 50 ps overdrive dispersion. Overdrive dispersion, a particularly important characteristic of high speed comparators, is a measure of the difference in propagation delay under differing overdrive conditions. A fast, high precision differential input stage permits consistent propagation delay with a wide variety of signals in the common-mode range from −2.0 V to +3.0 V. Outputs are complementary digital signals fully compatible with ECL 10 K and 10 KH logic families. The outputs provide sufficient drive current to directly drive transmission lines terminated in 50 Ω to −2 V. A latch input is included, which permits tracking, track-and-hold, or sample-and-hold modes of operation. The ADCMP565 is available in a 20-lead PLCC package. Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.326.8703 © 2003 Analog Devices, Inc. All rights reserved. ADCMP565 TABLE OF CONTENTS Specifications..................................................................................... 3 Optimizing High Speed Performance ........................................9 Absolute Maximum Ratings............................................................ 5 Comparator Propagation Delay Dispersion ..............................9 Thermal Considerations.............................................................. 5 Comparator Hysteresis .............................................................. 10 ESD Caution.................................................................................. 5 Minimum Input Slew Rate Requirement ................................ 10 Pin Configuration and Function Descriptions............................. 6 Typical Application Circuits ..................................................... 11 Timing Information ......................................................................... 8 Typical Performance Characteristics ........................................... 12 Application Information.................................................................. 9 Outline Dimensions ....................................................................... 14 Clock Timing Recovery ............................................................... 9 Ordering Guide .......................................................................... 14 REVISION HISTORY Revision 0: Initial Version Rev. 0 | Page 2 of 16 ADCMP565 SPECIFICATIONS Table 1. ADCMP565 ELECTRICAL CHARACTERISTICS (VCC = +5.0 V, VEE = −5.2 V, TA = 25°C, unless otherwise noted.) Parameter DC INPUT CHARACTERISTICS (See Note) Input Common-Mode Range Input Differential Voltage Input Offset Voltage Input Offset Voltage Channel Matching Offset Voltage Tempco Input Bias Current Input Bias Current Tempco Input Offset Current Input Capacitance Input Resistance, Differential Mode Input Resistance, Common Mode Open Loop Gain Common-Mode Rejection Ratio Hysteresis LATCH ENABLE CHARACTERISTICS Latch Enable Common-Mode Range Latch Enable Differential Input Voltage Input High Current Input Low Current Latch Setup Time Latch to Output Delay Latch Pulse Width Latch Hold Time OUTPUT CHARACTERISTICS Output Voltage—High Level Output Voltage—Low Level Rise Time Fall Time AC PERFORMANCE Propagation Delay Propagation Delay Propagation Delay Tempco Prop Delay Skew—Rising Transition to Falling Transition Within Device Propagation Delay Skew— Channel to Channel Propagation Delay Dispersion vs. Duty Cycle Propagation Delay Dispersion vs. Overdrive Propagation Delay Dispersion vs. Overdrive Propagation Delay Dispersion vs. Slew Rate Symbol VCM Min −2.0 −5 −6.0 −8 VOS DVOS/dT IBC −10.0 −5.0 CIN CMRR VCM = −2.0 V to +3.0 V VLCM VLD Unit +3.0 +5 +6.0 +8 V V mV mV µV/°C µA nA/°C µA pF kΩ kΩ dB dB mV +40.0 +5.0 −0.81 −1.61 160 145 V V ps ps 310 375 0.5 ±10 ps ps ps/°C ps ±10 ps 1 MHz, 1 ns tR, tF ±10 ps 50 mV to 1.5 V 20 mV to 1.5 V 0 V to 1 V swing, 20% to 80%, 50 ps and 600 ps tR, tF 1 V swing, −1.5 V to 2.5 VCM 0 V to 1 V swing, 20% to 80%, 50 ps tR, tF 50 50 50 ps ps ps 5 ps 5000 MHz VOH VOL tR tF ECL 50 Ω to −2.0 V ECL 50 Ω to −2.0 V 20% to 80% 20% to 80% tPD tPD 1 V overdrive 20 mV overdrive BW ±1.5 +1 5.0 +24 17 ±0.5 1.75 100 600 60 69 ±1.0 Max V V µA µA ps ps ps ps tS tPLOH, tPLOL tPL tH Rev. 0 | Page 3 of 16 −2.0 0.4 −10 −10 Typ 0 2.0 +10 +10 @ 0.0 V @ −2.0 V 250 mV overdrive 250 mV overdrive 250 mV overdrive 250 mV overdrive Propagation Delay Dispersion vs. Common-Mode Voltage Equivalent Input Rise Time Bandwidth Condition +6 +6 50 280 150 10 −1.08 −1.95 ADCMP565 Parameter AC PERFORMANCE (continued) Toggle Rate Minimum Pulse Width Unit to Unit Propagation Delay Skew POWER SUPPLY Positive Supply Current Symbol Condition PW >50% output swing ∆tPD from 10 ns to 200 ps < ±50 ps IVCC Min Typ Max Unit 5 200 Gbps ps ±10 ps @ +5.0 V 10 13 18 mA Negative Supply Current IVEE @ −5.2 V 60 70 80 mA Positive Supply Voltage Negative Supply Voltage Power Dissipation Power Dissipation Power Supply Sensitivity—VCC VCC VEE Dual Dual Dual, without load Dual, with load 4.75 −4.96 370 5.25 −5.45 490 PSSVCC 5.0 −5.2 435 550 67 V V mW mW dB Power Supply Sensitivity—VEE PSSVEE 83 NOTE: Under no circumstances should the input voltages exceed the supply voltages. Rev. 0 | Page 4 of 16 dB ADCMP565 ABSOLUTE MAXIMUM RATINGS THERMAL CONSIDERATIONS Table 2. ADCMP565 Absolute Maximum Ratings Supply Voltages Input Voltages Output Temperature Parameter Positive Supply Voltage (VCC to GND) Negative Supply Voltage (VEE to GND) Ground Voltage Differential Input Common-Mode Voltage Differential Input Voltage Input Voltage, Latch Controls Output Current Operating Temperature, Ambient Operating Temperature, Junction Storage Temperature Range Rating −0.5 V to +6.0 V −6.0 V to +0.5 V The ADCMP565 20-lead PLCC package option has a θJA (junction-to-ambient thermal resistance) of 89.4°C/W in still air. −0.5 V to +0.5 V −3.0 V to +4.0 V −7.0 V to +7.0 V VEE to 0.5 V 30 mA −40°C to +85°C 125°C −55°C to +125°C Stress above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Rev. 0 | Page 5 of 16 ADCMP565 QA QA NC QB QB PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 3 2 1 20 19 GND 4 18 GND PIN 1 IDENTIFIER 17 LEB LEA 5 NC 6 ADCMP565 TOP VIEW (Not to Scale) LEA 7 9 10 11 12 13 –INA +INA NC +INB –INB VEE 8 16 NC 15 LEB 14 VCC NC = NO CONNECT 02820-0-002 Figure 2. ADCMP565 Pin Configuration Table 3. ADCMP565 Pin Descriptions Pin No. 1 2 Mnemonic NC QA 3 QA 4 5 GND LEA 6 7 NC LEA 8 9 VEE −INA 10 +INA 11 12 NC +INB 13 −INB 14 15 VCC LEB 16 17 NC LEB Function No Connect. Leave pin unconnected. One of two complementary outputs for Channel A. QA will be at logic high if the analog voltage at the noninverting input is greater than the analog voltage at the inverting input (provided the comparator is in the compare mode). See the LEA description (Pin 5) for more information. One of two complementary outputs for Channel A. QA will be at logic low if the analog voltage at the noninverting input is greater than the analog voltage at the inverting input (provided the comparator is in the compare mode). See the LEA description (Pin 5) for more information. Analog Ground One of two complementary inputs for Channel A Latch Enable. In the compare mode (logic high), the output will track changes at the input of the comparator. In the latch mode (logic low), the output will reflect the input state just prior to the comparator’s being placed in the latch mode. LEA must be driven in conjunction with LEA. No Connect. Leave pin unconnected or attach to GND (internally connected to GND). One of two complementary inputs for Channel A Latch Enable. In the compare mode (logic low), the output will track changes at the input of the comparator. In the latch mode (logic high), the output will reflect the input state just prior to the comparator’s being placed in the latch mode. LEA must be driven in conjunction with LEA. Negative Supply Terminal Inverting analog input of the differential input stage for Channel A. The inverting A input must be driven in conjunction with the noninverting A input. Noninverting analog input of the differential input stage for Channel A. The noninverting A input must be driven in conjunction with the inverting A input. No Connect. Leave pin unconnected. Noninverting analog input of the differential input stage for Channel B. The noninverting B input must be driven in conjunction with the inverting B input. Inverting analog input of the differential input stage for Channel B. The inverting B input must be driven in conjunction with the noninverting B input. Positive Supply Terminal One of two complementary inputs for Channel B Latch Enable. In the compare mode (logic low), the output will track changes at the input of the comparator. In the latch mode (logic high), the output will reflect the input state just prior to the comparator’s being placed in the latch mode. LEB must be driven in conjunction with LEB. No Connect. Leave pin unconnected or attach to GND (internally connected to GND). One of two complementary inputs for Channel B Latch Enable. In the compare mode (logic high), the output will track changes at the input of the comparator. In the latch mode (logic low), the output will reflect the input state just prior to the comparator’s being placed in the latch mode. LEB must be driven in conjunction with LEB. Rev. 0 | Page 6 of 16 ADCMP565 Pin No. 18 19 Mnemonic GND QB 20 QB Function Analog Ground One of two complementary outputs for Channel B. QB will be at logic low if the analog voltage at the noninverting input is greater than the analog voltage at the inverting input (provided the comparator is in the compare mode). See the LEB description (Pin 17) for more information. One of two complementary outputs for Channel B. QB will be at logic high if the analog voltage at the noninverting input is greater than the analog voltage at the inverting input (provided the comparator is in the compare mode). See the LEB description (Pin 17) for more information. Rev. 0 | Page 7 of 16 ADCMP565 TIMING INFORMATION LATCH ENABLE 50% LATCH ENABLE tS tPL tH DIFFERENTIAL INPUT VOLTAGE VIN VREF ± VOS VOD tPDL tPLOH Q OUTPUT 50% tF tPDH 50% Q OUTPUT tPLOL tR 02820-0-003 Figure 3. System Timing Diagram The timing diagram in Figure 3 shows the ADCMP565 compare and latch features. Table 4 describes the terms in the diagram. Symbol tH Timing Minimum hold time tPL Minimum latch enable pulse width Minimum setup time Table 4. Timing Descriptions Symbol tPDH Timing Input to output high delay tPDL Input to output low delay tPLOH Latch enable to output high delay tPLOL Latch enable to output low delay Description Propagation delay measured from the time the input signal crosses the reference (± the input offset voltage) to the 50% point of an output low-to-high transition Propagation delay measured from the time the input signal crosses the reference (± the input offset voltage) to the 50% point of an output high-to-low transition Propagation delay measured from the 50% point of the Latch Enable signal low-to-high transition to the 50% point of an output lowto-high transition Propagation delay measured from the 50% point of the Latch Enable signal low-to-high transition to the 50% point of an output highto-low transition tS tR Output rise time tF Output fall time VOD Voltage overdrive Rev. 0 | Page 8 of 16 Description Minimum time after the negative transition of the Latch Enable signal that the input signal must remain unchanged to be acquired and held at the outputs Minimum time that the Latch Enable signal must be high to acquire an input signal change Minimum time before the negative transition of the Latch Enable signal that an input signal change must be present to be acquired and held at the outputs Amount of time required to transition from a low to a high output as measured at the 20% and 80% points Amount of time required to transition from a high to a low output as measured at the 20% and 80% points Difference between the differential input and reference input voltages ADCMP565 APPLICATION INFORMATION The ADCMP565 comparators are very high speed devices. Consequently, high speed design techniques must be employed to achieve the best performance. The most critical aspect of any ADCMP565 design is the use of a low impedance ground plane. A ground plane, as part of a multilayer board, is recommended for proper high speed performance. Using a continuous conductive plane over the surface of the circuit board can create this, allowing breaks in the plane only for necessary signal paths. The ground plane provides a low inductance ground, eliminating any potential differences at different ground points throughout the circuit board caused by ground bounce. A proper ground plane also minimizes the effects of stray capacitance on the circuit board. It is also important to provide bypass capacitors for the power supply in a high speed application. A 1 µF electrolytic bypass capacitor should be placed within 0.5 inches of each power supply pin to ground. These capacitors will reduce any potential voltage ripples from the power supply. In addition, a 10 nF ceramic capacitor should be placed as close as possible from the power supply pins on the ADCMP565 to ground. These capacitors act as a charge reservoir for the device during high frequency switching. The LATCH ENABLE input is active low (latched). If the latching function is not used, the LATCH ENABLE input should be grounded (ground is an ECL logic high), and the complementary input, LATCH ENABLE, should be tied to −2.0 V. This will disable the latching function. Occasionally, one of the two comparator stages within the ADCMP565 will not be used. The inputs of the unused comparator should not be allowed to float. The high internal gain may cause the output to oscillate (possibly affecting the comparator that is being used) unless the output is forced into a fixed state. This is easily accomplished by ensuring that the two inputs are at least one diode drop apart, while also appropriately connecting the LATCH ENABLE and LATCH ENABLE inputs as described above. The best performance is achieved with the use of proper ECL terminations. The open emitter outputs of the ADCMP565 are designed to be terminated through 50 Ω resistors to −2.0 V, or any other equivalent ECL termination. If a −2.0 V supply is not available, an 82 Ω resistor to ground and a 130 Ω resistor to −5.2 V provide a suitable equivalent. If high speed ECL signals must be routed more than a centimeter, microstrip or stripline techniques may be required to ensure proper transition times and prevent output ringing. CLOCK TIMING RECOVERY Comparators are often used in digital systems to recover clock timing signals. High speed square waves transmitted over a distance, even tens of centimeters, can become distorted due to stray capacitance and inductance. Poor layout or improper termination can also cause reflections on the transmission line, further distorting the signal waveform. A high speed comparator can be used to recover the distorted waveform while maintaining a minimum of delay. OPTIMIZING HIGH SPEED PERFORMANCE As with any high speed comparator amplifier, proper design and layout techniques should be used to ensure optimal performance from the ADCMP565. The performance limits of high speed circuitry can easily be a result of stray capacitance, improper ground impedance, or other layout issues. Minimizing resistance from source to the input is an important consideration in maximizing the high speed operation of the ADCMP565. Source resistance in combination with equivalent input capacitance could cause a lagged response at the input, thus delaying the output. The input capacitance of the ADCMP565 in combination with stray capacitance from an input pin to ground could result in several picofarads of equivalent capacitance. A combination of 3 kΩ source resistance and 5 pF of input capacitance yields a time constant of 15 ns, which is significantly slower than the sub 500 ps capability of the ADCMP565. Source impedances should be significantly less than 100 Ω for best performance. Sockets should be avoided due to stray capacitance and inductance. If proper high speed techniques are used, the ADCMP565 should be free from oscillation when the comparator input signal passes through the switching threshold. COMPARATOR PROPAGATION DELAY DISPERSION The ADCMP565 has been specifically designed to reduce propagation delay dispersion over an input overdrive range of 100 mV to 1 V. Propagation delay overdrive dispersion is the change in propagation delay that results from a change in the degree of overdrive (how far the switching point is exceeded by the input). The overall result is a higher degree of timing accuracy since the ADCMP565 is far less sensitive to input variations than most comparator designs. Propagation delay dispersion is a specification that is important in critical timing applications such as ATE, bench instruments, and nuclear instrumentation. Overdrive dispersion is defined Rev. 0 | Page 9 of 16 ADCMP565 as the variation in propagation delay as the input overdrive conditions are changed (Figure 4). For the ADCMP565, overdrive dispersion is typically 50 ps as the overdrive is changed from 100 mV to 1 V. This specification applies for both positive and negative overdrive since the ADCMP565 has equal delays for positive and negative going inputs. –VH 2 +VH 2 0V INPUT 1 The 50 ps propagation delay dispersion of the ADCMP565 offers considerable improvement of the 100 ps dispersion of other similar series comparators. 0 1.5V OVERDRIVE OUTPUT INPUT VOLTAGE 20mV OVERDRIVE 02820-0-005 VREF ± VOS Figure 5. Comparator Hysteresis Transfer Function DISPERSION 60 Q OUTPUT 50 02820-0-004 HYSTERESIS (mV) Figure 4. Propagation Delay Dispersion COMPARATOR HYSTERESIS The addition of hysteresis to a comparator is often useful in a noisy environment or where it is not desirable for the comparator to toggle between states when the input signal is at the switching threshold. The transfer function for a comparator with hysteresis is shown in Figure 5. If the input voltage approaches the threshold from the negative direction, the comparator will switch from a 0 to a 1 when the input crosses +VH/2. The new switching threshold becomes −VH/2. The comparator will remain in a 1 state until the threshold −VH/2 is crossed coming from the positive direction. In this manner, noise centered on 0 V input will not cause the comparator to switch states unless it exceeds the region bounded by ±VH/2. Positive feedback from the output to the input is often used to produce hysteresis in a comparator (Figure 9). The major problem with this approach is that the amount of hysteresis varies with the output logic levels, resulting in a hysteresis that is not symmetrical around zero. Another method to implement hysteresis is generated by introducing a differential voltage between the LATCH ENABLE and LATCH ENABLE inputs (Figure 10). Hysteresis generated in this manner is independent of output swing and is symmetrical around zero. The variation of hysteresis with input voltage is shown in Figure 6. 40 30 20 10 0 –20 –15 –10 –5 0 5 10 15 20 ∆ LATCH = LE – LEB (mV) 02820-0-006 Figure 6. Comparator Hysteresis Transfer Function Using Latch Enable Input MINIMUM INPUT SLEW RATE REQUIREMENT As for all high speed comparators, a minimum slew rate must be met to ensure that the device does not oscillate when the input crosses the threshold. This oscillation is due in part to the high input bandwidth of the comparator and the parasitics of the package. Analog Devices recommends a slew rate of 5 V/µs or faster to ensure a clean output transition. If slew rates less than 5 V/µs are used, then hysteresis should be added to reduce the oscillation. Rev. 0 | Page 10 of 16 ADCMP565 TYPICAL APPLICATION CIRCUITS VIN VIN ADCMP565 ADCMP565 OUTPUTS OUTPUTS VREF LATCH ENABLE INPUTS HYSTERESIS VOLTAGE –2.0V –2.0V 450Ω ALL RESISTORS 50Ω ALL RESISTORS 50Ω UNLESS OTHERWISE NOTED 02820-0-007 02820-0-010 Figure 7. High Speed Sampling Circuits Figure 10. Hysteresis Using Latch Enable Input +VREF ADCMP565 VIN OUTPUTS VIN ADCMP565 127Ω 30Ω 50Ω 30Ω 50Ω 127Ω –5.2V 02820-0-011 ADCMP565 –VREF LATCH ENABLE INPUTS Figure 11. How to Interface an ECL Output to an Instrument with a 50 Ω to Ground Input –2.0V ALL RESISTORS 50Ω 02820-0-008 Figure 8. High Speed Window Comparator VIN VREF ADCMP565 R1 OUTPUTS R2 –2.0V ALL RESISTORS 50Ω 02820-0-009 Figure 9. Hysteresis Using Positive Feedback Rev. 0 | Page 11 of 16 ADCMP565 TYPICAL PERFORMANCE CHARACTERISTICS (VCC = +5.0 V, VEE = −5.2 V, TA = 25°C, unless otherwise noted.) 25 25.0 24.5 INPUT BIAS CURRENT (µA) INPUT BIAS CURRENT (µA) 20 15 10 5 24.0 23.5 23.0 22.5 0 –2.5 0.5 3.5 –1.5 –0.5 1.5 2.5 NONINVERTING INPUT VOLTAGE (INVERTING VOLTAGE = 0.5V) 22.0 –40 –20 0 20 40 TEMPERATURE (°C) 60 80 02820-0-020 02820-0-021 Figure 15. Input Bias Current vs. Temperature Figure 12. Input Bias Current vs. Input Voltage 60 2.0 50 1.8 HYSTERESIS (mV) OFFSET VOLTAGE (mV) 1.9 1.7 1.6 1.5 40 30 20 1.4 10 1.3 1.2 –40 –20 0 20 40 TEMPERATURE (°C) 60 0 –20 80 –15 –10 –5 0 5 10 210 205 205 200 200 195 195 190 190 TIME (ps) TIME (ps) Figure 16. Hysteresis vs. ∆Latch 210 185 180 185 180 175 175 170 170 165 165 0 10 20 30 40 50 TEMPERATURE (°C) 60 70 20 02820-0-017 02820-0-022 Figure 13. Input Offset Voltage vs. Temperature 160 –40 –30 –20 –10 15 ∆ LATCH = LE – LEB (mV) 80 90 160 –40 –30 –20 –10 0 10 20 30 40 50 TEMPERATURE (°C) 02820-0-016 60 70 80 90 02820-0-019 Figure 14. Rise Time vs. Temperature Figure 17. Fall Time vs. Temperature Rev. 0 | Page 12 of 16 ADCMP565 304 315 303 PROPAGATION DELAY (ps) PROPAGATION DELAY (ps) 310 305 300 295 290 302 301 300 299 298 297 296 285 295 280 –40 –30 –20 –10 0 10 20 30 40 50 TEMPERATURE (°C) 60 70 80 294 90 –2 02820-0-015 02820-0-014 Figure 21. Propagation Delay vs. Common-Mode Voltage 35 0 30 –5 PROPOGATION DELAY ERROR (ps) PROPAGATION DELAY ERROR (ps) Figure 18. Propagation Delay vs. Temperature 25 20 15 10 5 0 0 0.2 0.4 0.6 0.8 1.0 OVERDRIVE VOLTAGE 1.2 1.4 1.6 –10 –15 –20 –25 –30 –35 –40 0.15 2.15 4.15 6.15 PULSEWIDTH (ns) 8.15 02820-0-013 02820-0-023 Figure 19. Propagation Delay Error vs. Overdrive Voltage Figure 22. Propagation Delay Error vs. Pulsewidth –0.8 RISE FALL OUTPUT RISE AND FALL (V) –1.0 –1.2 –1.4 –1.6 –1.8 –2.0 0.5 0.7 0.9 1.1 1.3 3 –1 0 1 2 INPUT COMMON-MODE VOLTAGE (V) 1.5 TIME (ns) 02820-0-018 Figure 20. Rise and Fall of Outputs vs. Time Rev. 0 | Page 13 of 16 ADCMP565 OUTLINE DIMENSIONS 0.180 (4.57) 0.165 (4.19) 0.048 (1.21) 0.042 (1.07) 3 0.048 (1.21) 0.042 (1.07) 0.056 (1.42) 0.042 (1.07) 19 18 4 TOP VIEW (PINS DOWN) 9 0.020 (0.50) R 0.021 (0.53) 0.013 (0.33) 0.050 (1.27) BSC 0.330 (8.38) 0.032 (0.81) 0.290 (7.37) 0.026 (0.66) 14 8 0.020 (0.50) R 0.20 (0.51) MIN BOTTOM VIEW (PINS UP) 13 0.356 (9.04) 0.350 (8.89) SQ 0.395 (10.02) SQ 0.385 (9.78) 0.025 (0.64) MIN 0.120 (3.04) 0.090 (2.29) COMPLIANT TO JEDEC STANDARDS MO-047AA CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN Figure 23. 20-Lead Plastic Leaded Chip Carrier [PLCC] (P-20) Dimensions shown in inches and (millimeters) ORDERING GUIDE Model ADCMP565BP Temperature Range −40°C to +85°C Package Description 20-Lead PLCC Rev. 0 | Page 14 of 16 Package Option P-20 ADCMP565 Notes Rev. 0 | Page 15 of 16 ADCMP565 Notes © 2003 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. C02820–0–10/03(0) Rev. 0 | Page 16 of 16