EL5281C EL5281C Dual 8ns High-Speed Comparator Features General Description • • • • • • • • The EL5281C comparator is designed for operation in single supply and dual supply applications with 5V to 12V between VS+ and VS-. For single supplies, the inputs can operate from 0.1V below ground for use in ground-sensing applications. 8ns Typ. Propagation Delay 5V to 12V Input Supply +2.7V to +5V Output Supply True-to-ground Input Rail-to-rail Outputs Active Low Latch Single Available (EL5181C) Quad Available (EL5481C & EL5482C) • Pin-compatible 4ns Family Available (EL5x85C, EL5287C & EL5486C) Applications • • • • • • Threshold Detection High Speed Sampling Circuits High Speed Triggers Line Receivers PWM Circuits High Speed V/F Converters The output side of the comparator can be supplied from a single supply of 2.7V to 5V. The rail-to-rail output swing enables direct connection of the comparator to both CMOS and TTL logic circuits. The latch input of the EL5281C can be used to hold the comparator output value by applying a low logic level to the pin. The EL5281C features two separate comparators. The EL5281C is available in the 14-pin SO package and is specified for operation over the full -40°C to +85°C temperature range. Also available are a single (EL5181C) and quad versions (EL5481C and EL5482C). Pin Configuration Ordering Information Package Tape & Reel Outline # EL5281CS Part No. 14-Pin SO - MDP0027 EL5281CS-T7 14-Pin SO 7” MDP0027 EL5281CS-T13 14-Pin SO 13” MDP0027 VS+ 1 INA+ 2 14 VSD + - INA- 3 13 OUTA 12 LATCHA NC 4 11 NC INB+ 5 10 LATCHB + INB- 6 - VS- 7 9 OUTB 8 GND Note: All information contained in this data sheet has been carefully checked and is believed to be accurate as of the date of publication; however, this data sheet cannot be a “controlled document”. Current revisions, if any, to these specifications are maintained at the factory and are available upon your request. We recommend checking the revision level before finalization of your design documentation. © 2001 Elantec Semiconductor, Inc. June 14, 2001 EL5281C 14-Pin SO EL5281C EL5281C Dual 8ns High-Speed Comparator Absolute Maximum Ratings (T A = 25°C) Absolute maximum ratings are those values beyond which the device could be permanently damaged. Absolute maximum ratings are stress ratings only and functional device operation is not implied. Analog Supply Voltage (VS+ to VS-) +12.6V Digital Supply Voltage (VSD to GND) +7V Differential Input Voltage [(VS-) -0.2V] to [(VS+) +0.2V] Common-mode Input Voltage Latch Input Voltage Storage Temperature Range Ambient Operating Temperature Operating Junction Temperature Power Dissipation [(VS-) -0.2V] to [(VS+) +0.2V] -0.2V to [(VSD ) +0.2V] -65°C to +150°C -40°C to +85°C 125°C See Curves Important Note: All parameters having Min/Max specifications are guaranteed. Typ values are for information purposes only. Unless otherwise noted, all tests are at the specified temperature and are pulsed tests, therefore: T J = TC = TA. Electrical Characteristics VS = ±5V, V SD = 5V, RL = 2.3kΩ, CL = 15pF, TA = 25°C, unless otherwise specified. Parameter Description Condition Min Typ Max Unit 1 4 mV -6 -3.5 Input VOS Input Offset Voltage IB Input Bias Current VCM = 0V, V O = 2.5V CIN Input Capacitance IOS Input Offset Current VCM Input Voltage Range CMRR Common-mode Rejection Ratio -5.1V < VCM < +2.75V VOH Output High Voltage VIN > 250mV VOL Output Low Voltage VIN > 250mV µA 5 VCM = 0V, V O = 2.5V -2.5 0.5 (VS-) - 0.1 65 pF 2.5 (VS+) - 2.25 90 µA V dB Output VSD - 0.6 VSD - 0.4 V GND + 0.25 GND + 0.5 V Dynamic Performance tpd+ Positive Going Delay Time VIN = 1VP-P, VOD = 50mV 8 12 ns tpd- Negative Going Delay Time VIN = 1VP-P, VOD = 50mV 8 12 ns Supply IS + Positive Analog Supply Current 7 8.2 mA IS - Negative Analog Supply Current 5 6.5 mA ISD Digital Supply Current Output high 4 5 mA Output low 0.75 1 mA PSRR Power Supply Rejection Ratio 60 80 dB Latch VLH Latch Input Voltage High VLL Latch Input Voltage Low 2.0 ILH Latch Input Current High VLH = 3.0V -30 -18 µA ILL Latch Input Current Low VLL = 0.3V -30 -24 µA td+ Latch Disable to High Delay 6 ns td- Latch Disable to Low Delay 6 ns ts Minimum Setup Time 2 ns th Minimum Hold Time 1 ns tpw(D) Minimum Latch Disable Pulse Width 10 ns 0.8 2 V V Typical Performance Curves Negative Supply Current vs Temperature Positive Supply Current vs Temperature 7.15 -4.4 7.1 -4.5 7.05 -4.6 -4.7 6.95 IS- (mA) IS+ (mA) 7 6.9 -4.8 -4.9 6.85 -5 6.8 -5.1 6.75 6.7 -50 -30 -10 10 30 50 70 -5.2 -50 90 -30 -10 Positive Supply Current vs Supply Voltage 7 5.5 VS-=-5V VSD=5V VIN=50mV TA=25°C 6 30 50 70 90 Negative Supply Current vs Negative Supply Voltage VS+=5V VSD=5V VIN=50mV TA=25°C 5 4.5 4 IS- (mA) IS+ (mA) 5 10 Temperature (°C) Temperature (°C) 3 4 2 3.5 1 0 0 1 2 3 4 5 6 3 7 0 1 2 VS+ (V) 3 4 5 6 7 50 70 90 VS- (V) Input Bias Current vs Temperature Offset Voltage vs Temperature 6 0.7 0.6 5 0.5 0.4 VOS (mV) IB (µA) 4 3 2 0.3 0.2 0.1 0 -0.1 1 -0.2 0 -50 -30 -10 10 30 50 70 -0.3 -50 90 Temperature (°C) -30 -10 10 30 Temperature (°C) 3 EL5281C EL5281C Dual 8ns High-Speed Comparator Dual 8ns High-Speed Comparator Typical Performance Curves Propagation Delay vs Overdrive 10 9 8.5 12 VS=±5V VSD=5V RL =2.2kΩ VIN =1V Step VOD=50mV 11 Tpd+ 8 Delay Time (ns) Delay Time (ns) Propagation Delay vs Load Capacitance VS=±5V VSD=5V VIN=1V Step RL=2.2kΩ 9.5 7.5 7 Tpd- 6.5 6 10 Tpd+ 9 Tpd- 8 7 5.5 5 0 100 200 300 400 500 6 0 600 20 40 60 VOD (mV) Propagation Delay vs Supply Voltage 100 120 Propagation Delay vs Overdrive 10 VSD=VS+ VIN=1V Step VOD=50mV RL=2.2kΩ 9 8.5 9.5 Tpd+ 9 8 Delay Time (ns) 9.5 Delay Time (ns) 80 CLOAD (pF) 10 Tpd+ 7.5 7 Tpd- 6.5 8.5 8 7.5 6.5 5.5 5 4 4.5 5 5.5 6 0 6 Tpd- VS=±5V VSD=5V VIN =3V Step RL =2.2kΩ 7 6 0.2 0.4 0.6 0.8 Propagation Delay vs Overdrive 10.5 10 VS=±5V VSD=5V RL=2.2kΩ VIN=5V Step 18 16 Tpd+ 9.5 9 Tpd- 8.5 14 7.5 6 1 1.5 1.6 1.8 2 2 2.5 4 0 3 VOD (V) VS=±5V VSD=5V RL =2.2kΩ VIN =1V Step VOD=50mV Tpd+ 10 8 0.5 1.4 12 8 7 0 1.2 Propagation Delay vs Source Resistance 20 Delay Time (ns) 11 1 VOD (V) ±VS (V) Delay Time (ns) EL5281C EL5281C Tpd - 0.2 0.4 0.6 0.8 1 Source Resistance (kΩ) 4 1.2 1.4 1.6 Typical Performance Curves Output Low Voltage vs Load Current Output High Voltage vs Load Current 0.31 4.75 VS=±5V VSD=5V VIN=50mV 0.27 TA=25°C 0.23 TA=-40°C 0.19 0.15 0 2 4 TA=-40°C 4.65 Output High Voltage (V) Output Low Voltage (V) 4.7 TA=85°C VS=±5V VSD=5V VIN =-50mV 6 8 4.6 TA=25°C 4.55 4.5 4.45 TA=85°C 4.4 4.35 4.3 10 0 2 Load Current (mA) 30 Digital Supply Current vs Input Switching Frequency 0.9 VS=±5V Power Dissipation (W) ISD (mA) 20 VSD=5V VSD=3V 10 SO 14 12 0° C/ W 0.6 0.5 0.4 0.3 0.2 5 0 8 833mW 0.7 10 6 Package Power Dissipation vs Ambient Temp. JEDEC JESD51-3 Low Effective Thermal Conductivity Test Board 0.8 25 15 4 Load Current (mA) 0.1 0 0 5 10 15 20 25 30 35 40 45 50 0 25 VIN=1VP-P FIN=30MHz VS=±5V VSD=5V 85 VIN =3VP-P FIN=30MHz VO VO VIN VIN 2V 75 100 Output with 30MHz Input VIN=3VP-P Output with 30MHz Input VIN=1VP-P 1V 50 Ambient Temperature (°C) Frequency (MHz) 2V 20ns 5 2V 20ns VS=±5V VSD=5V 125 EL5281C EL5281C Dual 8ns High-Speed Comparator EL5281C EL5281C Dual 8ns High-Speed Comparator Timing Diagram Compare Compare Latch Enable Input 1.4V Latch Latch Differential Input Voltage ts Latch th tpw(D) VIN VOS VOD tpd- td+ Comparator Output 2.4V Definition of Terms Terms Definition VOS Input Offset Voltage - Voltage applied between the two input terminals to obtain CMOS logic threshold at the output VIN Input Voltage Pulse Amplitude - Usually set to 1V for comparator specifications VOD Input Voltage Overdrive - Usually set to 50mV and in opposite polarity to VIN for comparator specifications tpd+ Input to Output High Delay - The propagation delay measured from the time the input signal crosses the input offset voltage to the CMOS logic threshold of an output low to high transition tpd- Input to Output Low Delay - The propagation delay measured from the time the input signal crosses the input offset voltage to the CMOS logic threshold of an output high to low transition td+ Latch Disable to Output High Delay - The propagation delay measured from the latch signal crossing the CMOS threshold in a low to high transition to the point of the output crossing CMOS threshold in a low to high transition td- Latch Disable to Output Low Delay - The propagation delay measured from the latch signal crossing the CMOS threshold in a low to high transition to the point of the output crossing CMOS threshold in a high to low transition ts Minimum Setup Time - The minimum time before the negative transition of the latch signal that an input signal change must be present in order to be acquired and held at the outputs th Minimum Hold Time - The minimum time after the negative transition of the latch signal that an input signal must remain unchanged in order to be acquired and held at the output tpw (D) Minimum Latch Disable Pulse Width - The minimum time that the latch signal must remain high in order to acquire and hold an input signal change 6 Pin Descriptions - EL5281C (14-Pin SO) Pin Number Pin Name 1 VS+ Positive supply current Function 2 INA+ Positive input, channel A Equivalent Circuit VS+ IN- IN+ VSCircuit 1 3 INA- 4, 11 NC Negative input, channel A (Reference Circuit 1) Not connected 5 INB+ Negative input, channel B (Reference Circuit 1) 6 INB- Positive input, channel B (Reference Circuit 1) 7 VS- Negative supply voltage 8 GND Ground 9 OUTB Output, channel B VSD V S+ OUT V SCircuit 2 10 LATCHB Latch input, channel B V S+ VSD LATCH VSCircuit 3 12 LATCHA 13 OUTA 14 VSD Latch input, channel A (Reference Circuit 3) Output, channel A (Reference Circuit 2) Digital supply voltage 7 EL5281C EL5281C Dual 8ns High-Speed Comparator EL5281C EL5281C Dual 8ns High-Speed Comparator Applications Information Power Supplies and Circuit Layout Input Slew Rate The EL5281C comparator operates with single and dual supply with 5V to 12V between VS+ and VS-. The output side of the comparator is supplied by a single supply from 2.7V to 5V. The rail-to-rail output swing enables direct connection of the comparator to both CMOS and TTL logic circuits. As with many high speed devices, the supplies must be well bypassed. Elantec recommends a 4.7µF tantalum in parallel with a 0.1µF ceramic. These should be placed as close as possible to the supply pins. Keep all leads short to reduce stray capacitance and lead inductance. This will also minimize unwanted parasitic feedback around the comparator. The device should be soldered directly to the PC board instead of using a socket. Use a PC board with a good, unbroken low inductance ground plane. Good ground plane construction techniques enhance stability of the comparator. Most high speed comparators oscillate when the voltage of one of the inputs is close to or equal to the voltage on the other input due to noise or undesirable feedback. For clean output waveform, the input must meet certain minimum slew rate requirements. In some applications, it may be helpful to apply some positive feedback (hysteresis) between the output and the positive input. The hysteresis effectively causes one comparator's input voltage to move quickly past the other, thus taking the input out of the region where oscillation occurs. For the EL5281C, the propagation delay increases when the input slew rate increases for low overdrive voltages. With high overdrive voltages, the propagation delay does not change much with the input slew rate. Latch Pin Dynamics The EL5281C contains a “transparent” latch for each channel. The latch pin is designed to be driven with either a TTL or CMOS output. When the latch is connected to a logic high level or left floating, the comparator is transparent and immediately responds to the changes at the input terminals. When the latch is switched to a logic low level, the comparator output remains latched to its value just before the latch’s highto-low transition. To guarantee data retention, the input signal must remain the same state at least 1ns (hold time) after the latch goes low and at least 2ns (setup time) before the latch goes low. When the latch goes high, the new data will appear at the output in approximately 6ns (latch propagation delay). Input Voltage Considerations The EL5281C input range is specified from 0.1V below V S - to 2.25V below VS +. The criterion for the input limit is that the output still responds correctly to a small differential input signal. The differential input stage is a pair of PNP transistors, therefore, the input bias current flows out of the device. When either input signal falls below the negative input voltage limit, the parasitic PN junction formed by the substrate and the base of the PNP will turn on, resulting in a significant increase of input bias current. If one of the inputs goes above the positive input voltage limit, the output will still maintain the correct logic level as long as the other input stays within the input range. However, the propagation delay will increase. When both inputs are outside the input voltage range, the output becomes unpredictable. Large differential voltages greater than the supply voltage should be avoided to prevent damages to the input stage. Inputs of unused channels should not be left floating. They should be driven to a known state. For example, one input can be tied to ground and the other input can be connected to some voltage reference (like ±100mV) to avoid oscillation in the output due to unwanted output to input feedback. Hysteresis Hysteresis can be added externally. The following two methods can be used to add hysteresis. Inverting comparator with hysteresis: VREF R3 R2 R1 8 + VIN - Check the current through R3 and make sure that it is much greater than the input bias current as follows: R3 adds a portion of the output to the threshold set by R 1 and R2. The calculation of the resistor values are as follows: 0.5VS D – VR E F I = --------------------------------------R3 Select the threshold voltage VTH and calculate R1 and R2. The current through R 1/R2 bias string must be many times greater than the input bias current of the comparator: The above two methods will generate hysteresis of up to a few hundred millivolts. Beyond that, the impedance of R3 is low enough to affect the bias string and adjustment of R 1 may be required. R1 VT H = VR E F × ------------------R1 + R2 Power Dissipation Let the hysteresis be V H, and calculate R 3: When switching at high speeds, the comparator's drive capability is limited by the rise in junction temperature caused by the internal power dissipation. For reliable operation, the junction temperature must be kept below TJMAX (125°C). VO × ( R 1 || R 2 ) R 3 = -------VH where: VO=V SD-0.8V (swing of the output) An approximate equation for the device power dissipation is as follows. Assume the power dissipation in the load is very small: Recalculate R 2 to maintain the same value of VTH: V T H VT H – 0.5VSD R 2 1 = ( VREF – V TH ) ÷ ----------+ ------------------------------------- R3 R1 P DISS = ( VS × I S + VSD × I S D ) × N Non inverting comparator with hysteresis: where: R3 VIN R1 VREF VS is the analog supply voltage from V S+ to VSIS is the analog quiescent supply current per comparator + - VSD is the digital supply voltage from VSD to ground ISD is the digital supply current per comparator R 3 adds a portion of the output to the positive input. Note that the current through R 3 should be much greater than the input bias current in order to minimize errors. The calculation of the resistor values as follows: N is the number of comparators in the package ISD strongly depends on the input switching frequency. Please refer to the performance curve to choose the input driving frequency. Having obtained the power dissipation, the maximum junction temperature can be determined as follows: Pick the value of R1. R1 should be small (less than 1kΩ) in order to minimize the propagation delay time. Choose the hysteresis VH and calculate R3: TJ M A X = T M A X + Θ J A × P D I S S R R 3 = ( V S D – 0.8 ) × --------1 V H where: TMAX is the maximum ambient temperature θJA is the thermal resistance of the package 9 EL5281C EL5281C Dual 8ns High-Speed Comparator EL5281C EL5281C Dual 8ns High-Speed Comparator Threshold Detector The inverting input is connected to a reference voltage and the non-inverting input is connected to the input. As the input passes the VREF threshold, the comparator's output changes state. The non-inverting and inverting inputs may be reversed. VIN VREF + - VOUT Crystal Oscillator A simple crystal oscillator using one comparator of an EL5281C is shown below. The resistors R1 and R2 set the bias point at the comparator's non-inverting input. Resistors R3, R4, and C1 set the inverting input node at an appropriate DC average voltage based on the output. The crystal's path provides resonant positive feedback and stable oscillation occurs. Although the EL5281C will give the correct logic output when an input is outside the common mode range, additional delays may occur when it is so operated. Therefore, the DC bias voltages at the inputs are set about 500mV below the center of the common mode range and the 200Ω resistor attenuates the feedback to the non-inverting input. The circuit will operate with most AT-cut crystal from 1MHz to 8MHz over a 2V to 7V supply range. The output duty cycle for this circuit is roughly 50% at 5V VCC, but it is affected by the tolerances of the resistors. The duty cycle can be adjusted by changing VCC value. 5V 200Ω R1 5kΩ R2 1.5kΩ 1MHz to 8MHz + - VOUT R3 C1 R4 0.01µF 2kΩ 2kΩ 10 EL5281C EL5281C Dual 8ns High-Speed Comparator General Disclaimer Specifications contained in this data sheet are in effect as of the publication date shown. Elantec, Inc. reserves the right to make changes in the circuitry or specifications contained herein at any time without notice. Elantec, Inc. assumes no responsibility for the use of any circuits described herein and makes no representations that they are free from patent infringement. WARNING - Life Support Policy Elantec, Inc. products are not authorized for and should not be used within Life Support Systems without the specific written consent of Elantec, Inc. Life Support systems are equipment intended to support or sustain life and whose failure to perform when properly used in accordance with instructions provided can be reasonably expected to result in significant personal injury or death. Users contemplating application of Elantec, Inc. Products in Life Support Systems are requested to contact Elantec, Inc. factory headquarters to establish suitable terms & conditions for these applications. Elantec, Inc.’s warranty is limited to replacement of defective components and does not cover injury to persons or property or other consequential damages. June 14, 2001 Elantec Semiconductor, Inc. 675 Trade Zone Blvd. Milpitas, CA 95035 Telephone: (408) 945-1323 (888) ELANTEC Fax: (408) 945-9305 European Office: +44-118-977-6020 Japan Technical Center: +81-45-682-5820 11 Printed in U.S.A.