® SiI 141B PanelLink Digital Receiver May 2001 General Description Features The SiI 141B uses PanelLink Digital technology to support displays ranging from VGA to High Refresh XGA (25-86 MHz), which is ideal for LCD desktop monitor applications. With a flexible single or dual pixel out interface and selectable output drive, the SiI 141B receiver supports up to true color panels (24 bit/pixel, 16.7M colors) in 1 pixel/clock mode (18 bit/pixel in 2 pixel/clock mode). PanelLink also features an inter-pair skew tolerance up to 1 full input clock cycle. The SiI 141B is pin for pin compatible with the SiI 141 but incorporates a number of enhancements. These include an improved jitter tolerant PLL design, new HSYNC filter and power down when the clock is inactive. All PanelLink products are designed on a scaleable CMOS architecture to support future performance requirements while maintaining the same logical interface. System designers can be assured that the interface will be fixed through a number of technology and performance generations. PanelLink Digital technology simplifies PC design by resolving many of the system level issues associated with high-speed digital design, providing the system designer with a digital interface solution that is quicker to market and lower in cost. • • • • • • • • Scaleable Bandwidth: 25-86 MHz (VGA to High Refresh XGA) Low Power: 3.3V core operation & power-down mode Automatic power down when clock is inactive High Skew Tolerance: 1 full input clock cycle (15ns at 65 MHz) Pin-compatible with SiI 101, SiI 141 Sync Detect: for Plug & Display “Hot Plugging” Cable Distance Support: over 5m with twisted-pair, fiber-optics ready Compliant with DVI 1.0 (DVI is backwards compatible with VESA® P&DTM and DFP) SiI 141B Pin Diagram 24-bit Input Data for 1-pixel/clock mode 8-bit Channel 1 Data 1-pixel/clock 8-bit Channel 2 Data 1-pixel/clock 8-bit Channel 0 Data 1-pixel/clock 18-bit Even Data for 2-pixel/clock mode Q19 VCC Q18 GND ODCK Q17 Q16 Q15 Q14 Q13 Q12 Q11 OVCC Q10 OGND Q9 Q8 Q7 Q6 Q5 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 6-bit Even Channel 0 Data 2-pixel/clock 6-bit Even Channel 1 Data 2-pixel/clock 6-bit Even Channel 2 Data 2-pixel/clock 20 Q4 19 Q3 Q21 43 18 Q2 Q22 44 17 Q1 Q23 45 16 Q0 OGND 46 15 OVCC Q24 47 14 VSYNC OVCC 48 13 OGND Q25 49 SiI141B 12 HSYNC VCC 50 GND Q26 51 80-Pin TQFP 11 10 CTL3 Q27 52 9 CTL2 Q28 53 8 CTL1 Q29 54 7 SCDT Q30 55 6 DFO Q31 56 5 PIXS Q32 57 4 OGND Q33 58 3 PDO Q34 59 2 PD Q35 60 1 RESERVED 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 RX1+ RX1- AVCC RX0+ RX0- AGND RXC- RXC+ HSYNC_DEJTR EXT_RES PVCC PGND ST OCK_INV 64 RX2+ AGND 63 AVCC 65 62 RX2- 61 VCC GND DIFFERENTIAL SIGNAL GENERAL PURPOSE CONTROL (Top View) CONTROL 41 42 6-bit Odd Channel 1 Data 2-pixel/clock DE Q20 6-bit Odd Channel 2 Data 2-pixel/clock 18-bit Odd Data for 2-pixel/clock mode 6-bit Odd Channel 0 Data 2-pixel/clock MISC. Subject to Change without Notice SiI 141B SiI-DS-0037-C Functional Block Diagram ST PIXS DFO OCK_INV PDO HSYNC_DEJTR Termination Control EXT_RES 8 RX2+ VCR RX2- DATA RECOVERY CH2 24/36 CLT3 Q[35:0/23:0] CLT2 ODCK DE2 DE HSYNC 8 RX1+ VCR RX1- DATA RECOVERY CH1 CLT1 INTERCHANNEL SYNC. DECODER PLL_SYNC PANEL INTERFACE LOGIC DE1 VSYNC SCDT 8 RX0+ VCR RX0- CLT1 VSYNC DATA RECOVERY CH0 CLT2 HSYNC CLT3 DE0 RXC+ VCR PLL RXC- Absolute Maximum Conditions Note: Permanent device damage may occur if absolute maximum conditions are exceeded. Functional operation should be restricted to the conditions described under Normal Operating Conditions. Symbol Parameter Min Typ Max Units VCC Supply Voltage 3.3V -0.3 4.0 V VI Input Voltage -0.3 VCC+ 0.3 V VO Output Voltage -0.3 VCC+ 0.3 V TA Ambient Temperature (with power applied) -25 105 °C TSTG Storage Temperature -65 150 °C Thermal Resistance (Junction to Ambient) 45 °C /W θJA Normal Operating Conditions Symbol VCC VCCN TA Parameter Supply Voltage Supply Voltage Noise Ambient Temperature (with power applied) Min 3.0 Typ 3.3 0 25 Max 3.6 100 70 Units V mVP-P °C DC Digital I/O Specifications Under normal operating conditions unless otherwise specified. Symbol Parameter Conditions Min Typ Max Units VIH High-level Input Voltage 2 V VIL Low-level Input Voltage 0.8 V VOH High-level Output Voltage 2.4 V VOL Low-level Output Voltage 0.4 V VCINL Input Clamp Voltage1 ICL = -18mA GND -0.8 V VCIPL Input Clamp Voltage1 ICL = 18mA IVCC + 0.8 V VCONL Output Clamp Voltage1 ICL = -18mA GND -0.8 V VCOPL Output Clamp Voltage1 ICL = 18mA OVCC + 0.8 V IIL Input Leakage Current -10 10 µA Note: 1 Guaranteed by design. Voltage undershoot or overshoot cannot exceed absolute maximum conditions for a pulse of greater than 3 ns or one third of the clock cycle. Silicon Image, Inc. 2 Subject to Change without Notice SiI 141B SiI-DS-0037-C DC Specifications Under normal operating conditions unless otherwise specified. Low drive strength values, when ST=0, are shown in brackets. Symbol Parameter Conditions Min Typ Max Units IOHD Output High Drive VOUT = 2.4 Data and Controls ST=1 5.0 10.3 17.6 mA ST=0 2.5 5.2 8.8 IOLD Output Low Drive VOUT = 0.4 Data and Controls ST=1 -5.5 -8.3 -11.2 mA ST=0 -2.8 -4.2 -5.6 IOHC ODCK High Drive VOUT = 2.4 ST=1 10.1 20.6 35.1 mA ST=0 5.0 10.3 17.6 IOLC ODCK Low Drive VOUT = 2.0 ST=1 -11.1 -16.7 -22.4 mA ST=0 -5.5 -8.3 -11.2 VID Differential Input Voltage 75 1000 mV Single Ended Amplitude IPDL Output leakage current to ground in 10 µA high impedance mode (PD, PDO = LOW) IPD Power-down Current1 50 100 µA ICLKI Power-down Current RXC± Inactive 4 7 mA IPDO Power-down-output Current 125 155 mA CLOAD = 10pF ICCR Receiver Supply Current ODCK=86MHz, 1-pixel/clock mode2 157 182 mA REXT_SWING = 510 Ω Typical Pattern3 CLOAD = 10pF 172 194 mA REXT_SWING = 510 Ω Worst Case Pattern4 Notes: 1 The transmitter must be in power-down mode, powered off, or disconnected for the current to be under this maximum. 2 For worst case I/O power consumption. 3 The Typical Pattern contains a gray scale area, checkerboard area, and text. 4 Black and white checkerboard pattern, each checker is one pixel wide. Silicon Image, Inc. 3 Subject to Change without Notice SiI 141B SiI-DS-0037-C AC Specifications Under normal operating conditions unless otherwise specified. Low drive strength values, when ST=0, are given below. Symbol Parameter Conditions Min Typ Max Units TDPS Intra-Pair (+ to -) Differential Input Skew 86 MHz 470 ps TCCS Channel to Channel Differential Input Skew 86 MHz 7 ns 65 MHz 465 ps Worst Case Differential Input Clock Jitter tolerance1,2 TIJIT 86 MHz 350 ps DLHT Low-to-High Transition Time: Data and Controls CL = 10pF; ST = 1 3.5 ns (43 MHz, 2-pixel/clock, PIXS=1) 4.5 ns CL = 5pF; ST = 0 Low-to-High Transition Time: Data and Controls CL = 10pF; ST = 1 3.5 ns (65 MHz, 1-pixel/clock, PIXS=0) 4.5 ns CL = 5pF; ST = 0 Low-to-High Transition Time: ODCK CL = 10pF; ST = 1 1.6 ns (43 MHz, 2-pixel/clock, PIXS=1) 2.1 ns CL = 5pF; ST = 0 CL = 10pF; ST = 1 1.6 ns Low-to-High Transition Time: ODCK (65 MHz, 1-pixel/clock, PIXS=0) CL = 5pF; ST = 0 2.1 ns DHLT CL = 10pF; ST = 1 3.0 ns High-to-Low Transition Time: Data and Controls (43 MHz, 2-pixel/clock, PIXS=1) 4.2 ns CL = 5pF; ST = 0 CL = 10pF; ST = 1 3.0 ns High-to-Low Transition Time: Data and Controls (65 MHz, 1-pixel/clock, PIXS=0) 4.2 ns CL = 5pF; ST = 0 CL = 10pF; ST = 1 1.5 ns High-to-Low Transition Time: ODCK (43 MHz, 1-pixel/clock, PIXS=0) 1.9 ns CL = 5pF; ST = 0 CL = 10pF; ST = 1 1.5 ns High-to-Low Transition Time: ODCK (65 MHz, 1-pixel/clock, PIXS=0) 1.9 ns CL = 5pF; ST = 0 Data, DE, VSYNC, HSYNC, and CTL[3:1] Setup Time to TSETUP CL = 10pF; ST = 1 3.6 ODCK falling edge (OCK_INV = 0) or to ODCK rising 3.0* ns edge (OCK_INV = 1) 18.4 ns CL = 5pF; ST = 0 *OCK_INV = 1 19.0* Data, DE, VSYNC, HSYNC, and CTL[3:1] Hold Time from CL = 10pF; ST = 1 THOLD 8.0 ns ODCK falling edge, (OCK_INV = 0) or from ODCK rising 8.4* edge (OCK_INV = 1) 24.0 ns CL = 5pF; ST = 0 *OCK_INV = 0 24.5* RCIP ODCK Cycle Time (1 pixel/clock) 11.6 40 ns FCIP ODCK Frequency (1 pixel/clock) 25 86 MHz RCIP ODCK Cycle Time (2 pixels/clock) 23.3 80 ns FCIP ODCK Frequency (2 pixels/clock) 12.5 43 MHz CL = 10pF, ST=1 5.0 RCIH ODCK High Time 4.4 ns 65 MHz, One Pixel / Clock, PIXS = 0 3 CL = 5pF, ST=0 9.0 ns 43 MHz, Two Pixel / Clock, PIXS = 1 3 CL = 10pF, ST=1 8.2 CL = 5pF, ST=0 CL = 10pF, ST=1 6 RCIL ODCK Low Time 5 ns 65 MHz, One Pixel / Clock, PIXS = 0 3 CL = 5pF, ST=0 9 ns 43 MHz, Two Pixel / Clock, PIXS = 1 3 CL = 10pF, ST=1 9 CL = 5pF, ST=0 THSC Link disabled (DE inactive) to SCDT low1 160 ms Link disabled (Tx power down) to SCDT low 5 200 250 ms TFSC Link enabled (DE active) to SCDT high6 Falling 40 DE edges TCLKPD Delay from RXC+/- Inactive to high impedance outputs RXC+/- = 25MHz 10 µs TCLKPU Delay from RXC+/- active to data active RXC+/- = 25MHz 100 µs TPDL Delay from PD/ PDO Low to high impedance outputs 8 ns 1 Notes: Jitter defined as per DVI 1.0 Specification, Section 4.6 Jitter Specification. 2 Jitter measured with Clock Recovery Unit as per DVI 1.0 Specification, Section 4.7 Electrical Measurement Procedures. 3 Output clock duty cycle is independent of the differential input clock duty cycle and the IDCK duty cycle. 4 The setup and hold timing for the data and controls relative to the ODCK rising edge (OCK_INV=1) is by design the same as the falling edge timing. 5 Measured when transmitter was powered down (see SiI/AN-0005 “PanelLink Basic Design /Application Guide,” Section 2.4). 6 Refer to the transmitter datasheet for minimum DE high and low time 7 Data is active (i.e. not tri-stated) but not valid yet. Data and controls are valid only when SCDT goes high. See TFSC and Figure 7. Silicon Image, Inc. 4 Subject to Change without Notice SiI 141B SiI-DS-0037-C Timing Diagrams 2.0 V SiI141B 2.0 V 10pF (5pF) 0.8 V 0.8 V DLHT DHLT Figure 1. Digital Output Transition Times RCIP RCIH 2.0 V 2.0 V 2.0 V 0.8 V 0.8 V RCIL Figure 2. Receiver Clock Cycle/High/Low Times RX0 VDIFF = 0V RX1 TCCS VDIFF = 0V RX2 Figure 3. Channel-to-Channel Skew Timing Output Timing ODCK_INV = 1 ODCK_INV = 0 TSETUP THOLD QE[23:0]/QO[23:0], DE, VSYNC, HSYNC, CTL[3:1] Figure 4. Output Data Setup/Hold Times to ODCK Silicon Image, Inc. 5 Subject to Change without Notice SiI 141B SiI-DS-0037-C PD TPDL Q[35:0], DE, VSYNC, HSYNC, CTL[3:1] Figure 5. Output Signals Disabled Timing from PD Active TCLKPD RXC ... ... Q[35:0], DE, VSYNC, HSYNC, CTL[3:1] Figure 6. Output Signals Disabled Timing from Clock Inactive TCLKPU + TFSC ... ... RXC SCDT Figure 7. Wake-up on Clock Detect THSC DE SCDT TFSC DE SCDT Figure 8. SCDT Timing from DE Inactive/Active Silicon Image, Inc. 6 Subject to Change without Notice SiI 141B SiI-DS-0037-C Output Pin Description Pin Name Q35 – Q0 Pin # See SiI 141B Pin Diagram Type Out ODCK 36 Out DE 41 Out HSYNC VSYNC CTL1 CTL2 CTL3 12 14 8 9 10 Out Out Out Out Out Description Output Data [35:0]. Output data is synchronized with output data clock (ODCK). When PIXS is low Q35-Q24 are low and Q23-Q0 output 24-bit/pixel data. When PIXS is high Q17-Q0 output the even numbered pixels (pixel 0, 2, 4, ... , etc.) and Q35-Q18 output the odd numbered pixels (pixel 1, 3, 5, ... , etc.). Refer to the TFT Signal Mapping (SiI/AN-0008) and DSTN Signal Mapping (SiI/AN-0007) application notes which tabulate the relationship between the input data to the transmitter and output data from the receiver. A low level on PD or PDO will put the output drivers into a high impedance (tri-state) mode. A weak internal pull-down device brings each output to ground. Output Data Clock. A low level on PD or PDO will put the output drivers into a high impedance (tri-state) mode. A weak internal pull-down device brings each output to ground. Output Data Enable. A low level on PD or PDO will put the output drivers into a high impedance (tri-state) mode. A weak internal pull-down device brings each output to ground. Horizontal Sync output control signal. Vertical Sync output control signal. General output control signal 1. This pin is not controlled by PDO. General output control signal 2 General output control signal 3. A low level on PD or PDO will put the output drivers into a high impedance (tri-state) mode. A weak internal pull-down device brings each output to ground. Configuration Pin Description Pin Name OCK_INV Pin # 80 Type In PIXS 5 In DF0 6 In HSYNC_DEJTR 75 In ST 79 In Description ODCK Polarity. A low level selects normal ODCK output, which enables data latching on the falling edge. A high level (3.3V) selects inverted ODCK output, which enables data latching on the rising edge. Both conditions are for color TFT panel support. For color 24-bit DSTN panel support, please refer to the DSTN Signal Mapping (SiI/AN-0008-A) application note. Pixel Select. A low level indicates that output data is one pixel (up to 24-bit) per clock and a high level (3.3V) indicates that output data is two pixels (up to 36-bit) per clock. Output Data Format. This pin controls clock and data output format. A low level indicates that ODCK runs continuously for color TFT panel support and a high level (3.3V) indicates that ODCK is stopped (LOW) for color 24-bit DSTN panel support when DE is low. Refer to the TFT Signal Mapping (SiI/AN0007-A) and DSTN Signal Mapping (SiI/AN-0008-A) application notes for a table on TFT or DSTN panel support. A low level enables the HSYNC de-jitter circuitry. A high level disables the de-jitter circuitry. If left unconnected, the circuitry defaults to disabled. Output Driver Strength. A low level indicates low drive. A high level indicates high drive. Power Management Pin Description Pin Name SCDT Pin # 7 Type Out PD 2 In PDO 3 In Silicon Image, Inc. Description SyncDetect. A high level is output when DE is toggling. A low level is output when DE is inactive. See page 9. Power Down (active low). A high level (3.3V) indicates normal operation and a low level indicates power down mode. During power down mode all internal circuitry is powered down and digital I/O are set the same as when PDO is asserted. (see PDO pin description). Power Down Output (active low). A high level indicates normal operation. A low level puts the output drivers only into a high impedance (tri-state) mode. A weak internal pull-down device brings each output to ground. There is an internal pull-up resistor on PDO that defaults the chip to normal operation if left unconnected. SCDT and CTL1 are not tri-stated by this pin. See explanation of clock detect on page 8-9. 7 Subject to Change without Notice SiI 141B SiI-DS-0037-C Differential Signal Data Pin Description Pin Name RX0+ RX0RX1+ RX1RX2+ RX2RXC+ RXCEXT_RES Pin # 70 71 67 68 64 65 74 73 76 Type Analog Description TMDS Low Voltage Differential Signal input data pairs. Analog TMDS Low Voltage Differential Signal input clock pair. Analog Impedance Matching Control. Resistor value should be ten times the characteristic impedance of the cable. In the common case of 50Ω transmission line, an external 530Ω resistor must be connected between AVCC and this pin. Reserved Pin Description Pin Name Pin # Type RSVD 1 Out Description This signal must be left unconnected. Power and Ground Pin Description Pin Name VCC GND OVCC OGND AVCC AGND PVCC PGND Pin # 39 50 61 11 37 62 15 28 48 4 13 26 46 63 69 66 72 77 78 Type Power Description Core VCC, must be set to 3.3V. Ground Digital GND. Power Output VCC, must be set to 3.3V. Ground Output GND. Power Analog VCC, must be set to 3.3V. Ground Analog GND. Power Ground PLL VCC, must be set to 3.3V. PLL GND. Application Information The SiI141B is pin for pin compatible with the SiI141 but includes two new features, HSYNC de-jitter and power down when the clock is inactive. HSYNC de-jitter enables the 141B to operate properly even when the HSYNC signal contains jitter. Pin 75 is used to enable or disable this capability (a reserved pin tied high on the SiI141). Tying this pin low enables the HSYNC de-jitter circuitry while tying it high disables the circuitry. The HSYNC de-jitter circuitry operates normally with most VESA standard timings. Some DOS mode resolutions do not have timings that are a multiple of eight (HSYNC and VSYNC total times and front and back porch times are multiples of eight pixel times). If they are not a multiple of eight, operation is not guaranteed and the HSYNC de-jitter circuitry should be turned off. When HSYNC dejitter is enabled, the circuitry will introduce anywhere from 0 to 7 CLK delays in the HSYNC signal relative to the output data. The SiI141B includes a new power saving feature, power down with clock detect circuit. The SiI141B will go into a low power mode when there is no video clock coming from the transmitter. In this mode the entire chip is powered down except the clock detect circuitry. During this mode digital I/O are set to a high impedance (tri-state) mode. A weak internal pull-down device brings each output to ground. The device power down and wake-up times are shown in Figures 6 and 7. The SiI141B also includes a sync detect feature for pin compatibility with SiI141. In both the SiI141 and SiI141B, SCDT goes low when DE is inactive. Silicon Image, Inc. 8 Subject to Change without Notice SiI 141B SiI-DS-0037-C In some application, SCDT is connected to the PDO pin to provide a power savings mode. In others, SCDT is connected to an external circuit to signal when an incoming video signal is available. These external devices may use an internal pull up which can cause problems. If SCDT is connected to an external circuit which has an internal pull up, then SCDT will not stay low when no video signal is present. The recommended circuit to keep SCDT low is shown Figure 9. For most applications, Silicon Image recommends a pull down resistor of 1.5 KΩ. However, conditions within every design may vary. Please use the calculations below to determine the proper pull-down resistor value. internal pull up SCDT(pin# 7) weak internal pull down R SiI141B pull down resister external chip Figure 9. Schematic for SCDT connected to external device with pull up The external pull down resistor value depends on the pull-up circuit in the external device and can be calculated with Equation [1] and [2] if the pull up is a passive circuit. If the pull up is an active circuit, please consult the manufacture of the other device. The calculation for the maximum resistor value is shown in the equation [1] below. In powered down mode, low power consumption is achieved by making the resistor value as large as possible. Equation [1] determines the maximum value of R while ensuring that SCDT stays lower than VIL of the external chip when SCDT goes into high impedance. The small current flowing into the SiI141B internal pull down resistor is ignored in equation [1]. Equation [1a] R × VCCMAX < VIL RPull −Up + R Equation [1b] × V ) (R R < Pull −Up IL (Vcc max − VIL ) Example : Pull-up resistor value is 10 KΩ, VIL of external chip is 0.8V, and maximum Vcc is 3.6V R < 2,857ohms = (10 KΩ x 0.8V) / (3.6V – 0.8V) The resistor value should be smaller than 2,857 KΩ. The calculation for the minimum resistor value is shown in the equation [2]. The minimum value is set so the SCDT voltage exceeds VIH of the external chip in normal operation. In equation [2], the small current flowing into the SiI141B internal pull-down resistor is ignored. Silicon Image, Inc. 9 Subject to Change without Notice SiI 141B Equation [2] V R > CC I OHDMIN or SiI-DS-0037-C V R > IH I OHDMIN Example : When ST(pin# 79) = 1,Vcc = 3.3V R > 660Ω = Vcc (or VIH of external chip) / Min IOHD = 3.3V / 5.0mA The resistor value should be larger than 660ohms When ST(pin# 79) = 0,Vcc = 3.3V R > 1,320Ω = Vcc (or VIH of external chip) / Min IOHD = 3.3V / 2.5mA The resistor value should be larger than 1,320ohms. These examples assume Vcc (or VIH) of 3.3V, with a lower VIH, the minimum pull down resistor value may be smaller. Silicon Image, Inc. 10 Subject to Change without Notice SiI 141B SiI-DS-0037-C 80-pin TQFP Package Dimensions Lead Length 1.00mm 80-pin Plastic TQFP Lead Width 0.22mm Package Height 1.15mm max. SiI141BCT80 LNNNNN.NLLL XXYY X.XX Footprint 14.00mm Device # Lot # Date Code # SiI Rev. # Body Size 12.00mm Lead Pitch 0.50mm Body Thickness 1.0mm Clearance 0.15mm max. Body Size 12.00mm Footprint 14.00mm Silicon Image, Inc. 11 Subject to Change without Notice SiI 141B SiI-DS-0037-C To obtain the most updated Application Notes and other useful information for your design application, please visit the Silicon Image web site at www.siimage.com, or contact your local Silicon Image sales office. Copyright Notice This manual is copyrighted by Silicon Image, Inc. Do not reproduce, transform to any other format, or send/transmit any part of this documentation without the express written permission of Silicon Image, Inc. Trademark Acknowledgment Silicon Image, the Silicon Image logo, PanelLink and the PanelLink Digital logo are trademarks or registered trademarks of Silicon Image, Inc. All other trademarks are the property of their respective holders. Disclaimer This document provides technical information for the user. Silicon Image, Inc. reserves the right to modify the information in this document as necessary. The customer should make sure that they have the most recent data sheet version. Silicon Image, Inc. holds no responsibility for any errors that may appear in this document. Customers should take appropriate action to ensure their use of the products does not infringe upon any patents. Silicon Image, Inc. respects valid patent rights of third parties and does not infringe upon or assist others to infringe upon such rights. Ordering Information Part Number: SiI141BCT80 Revision History Revision Date A 11/00 B 1/01 C 5/01 Comment Full release Added application information concerning HSYNC de-jitter and power down on clock Updated EXT_RES value for 50Ω transmission line. © 2001 Silicon Image, Inc. 5/01 SiI-DS-0037-C Silicon Image, Inc. 1060 E. Arques Ave Sunnyvale, CA 94086 USA Silicon Image, Inc. Tel: 408-616-4000 Fax: 408-830-9530 E-Mail: [email protected] Web: www.siimage.com www.panellink.com 12 Subject to Change without Notice