19-1780; Rev 0; 7/00 KIT ATION EVALU E L B A IL AVA Complete Dual-Band Quadrature Transmitters Features ♦ Dual-Band, Triple-Mode Operation ♦ +7dBm Output Power with -54dBc ACPR ♦ 100dB Power Control Range ♦ Supply Current Drops as Output Power Is Reduced ♦ Dual Synthesizer for IF and RF LO ♦ Dual On-Chip IF VCO ♦ QSPI/SPI/MICROWIRE-Compatible 3-Wire Bus ♦ Digitally Controlled Operational Modes ♦ +2.7V to +5.5V Operation ♦ Single Sideband Upconverter Eliminates SAW Filters Ordering Information PART TEMP. RANGE PIN-PACKAGE MAX2366EGM -40°C to +85°C 48 QFN-EP* MAX2367EGM MAX2368EGM -40°C to +85°C -40°C to +85°C 48 QFN-EP* 48 QFN-EP* *Exposed paddle IFCP VCC 37 38 39 40 RFPLL VCC RFCP VCC 41 42 43 GND LOL LOH 44 46 45 32 90 6 31 0 7 -45 8 30 -45 /2 9 29 28 0 10 Σ 11 27 90 /2 26 24 23 22 21 REF N.C. N.C. TANKH+ TANKHTANKL+ TANKLIFLO VCC SHDN II+ VCC Q+ Q- VGC VCC 20 25 19 12 CLK DI SPI and QSPI are trademarks of Motorola, Inc. 33 Σ 13 Selector Guide appears at end of data sheet. 34 MAX2366 4 18 Pin Configurations appear at end of data sheet. 35 3 IFOUTL+ IFOUTL- Wireless Local Loop (WLL) 5 36 IFPLL 17 High-Speed Digital Cordless Phones IDLE VCC TXGATE IFINL+ IFINLIFINH+ IFINHRBIAS RFPLL 2 16 High-Speed Data Modems 1 15 Wireless Local Area Networks (LANs) RFL RFH0 LOCK VCC CS IFOUTHIFOUTH+ Wireless Data Links (WAN/LAN) 14 Satellite Phones GND RFH1 GND Triple-Mode, Dual-Mode, or Single-Mode Mobile Phones 47 Applications 48 Functional Diagram MICROWIRE is a trademark of National Semiconductor Corp. ________________________________________________________________ Maxim Integrated Products 1 For price, delivery, and to place orders, please contact Maxim Distribution at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. MAX2366/MAX2367/MAX2368 General Description The MAX2366 dual-band, triple-mode complete transmitter for cellular phones represents the most integrated and architecturally advanced solution to date for this application. The device takes a differential I/Q baseband input and mixes it up to IF through a quadrature modulator and IF variable-gain amplifier (VGA). The signal is then routed to an external bandpass filter and upconverted to RF through an SSB mixer and RF VGA. The signal is further amplified with an on-board PA driver. Dual IF synthesizers, dual RF synthesizers, a local oscillator (LO) buffer, and a 3-wire programmable bus complete the basic functional blocks of this IC. The MAX2367 supports singleband, single-mode (PCS) operation. The MAX2368 supports single-band cellular dual-mode operation. The MAX2366 enables architectural flexibility because its two IF voltage-controlled oscillators (VCOs), two IF ports, two RF LO input ports, and three PA driver output ports allow the use of a single receive IF frequency and split-band PCS filters for optimum out-of-band noise performance. The PA drivers allow up to three RF SAW filters to be eliminated. Select a mode of operation by loading data on the SPI™/QSPI™/MICROWIRE™-compatible 3-wire serial bus. Charge-pump current, sideband rejection, IF/RF gain balancing, standby, and shutdown are also controlled with the serial interface. The MAX2366/MAX2367/MAX2368 come in a 48-pin QFN-EP package and are specified for the extended (-40°C to +85°C) temperature range. MAX2366/MAX2367/MAX2368 Complete Dual-Band Quadrature Transmitters ABSOLUTE MAXIMUM RATINGS VCC to GND ...........................................................-0.3V to +3.6V RFL, RFH0, RFH1................................................................+5.5V DI, CLK, CS, VGC, SHDN, TXGATE, IDLE, LOCK ...........................................-0.3V to (VCC + 0.3V) AC Input Pins (IFINL, IFINH, Q, I, TANKL, TANKH, REF, RFPLL, LOL, LOH)..........................................1.0V peak Digital Input Current (SHDN, TXGATE, IDLE, CLK, DI, CS) ................................................................±10mA Continuous Power Dissipation (TA = +70°C) 48-Pin QFN-EP (derate 27mW/°C above +70°C) ..............2.5W Operating Temperature Range ...........................-40°C to +85°C Junction Temperature ......................................................+150°C Storage Temperature Range .............................-65°C to +160°C Lead Temperature (soldering, 10s) .................................+300°C Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (MAX2366/7/8 test fixture: VCC = VBATT = +2.75V, SHDN = IDLE = TXGATE = +2.0V, VGC = +2.5V, RBIAS = 16kΩ, TA = -40°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C, and operating modes are defined in Table 6.) PARAMETER CONDITIONS MIN Operating Supply Voltage VGC = 0.5V PCS mode (Note 1) Operating Supply Current Cellular digital mode FM mode 92 UNITS 3.0 V 118 97 123 VGC = 2.5V 132 161 VGC = 0.5V 91 110 VGC = 2.0V 95 122 VGC = 2.5V 132 164 VGC = 0.5V 85 110 VGC = 2.0V 89 114 VGC = 2.5V 114 142 6.5 9.5 15 20 26 34 IDLE = 0.6V, cell idle TXGATE = 0.6V MAX VGC = 2.0V Addition for IFLO buffer RFPLL off mA 11 SHDN = 0.6V, sleep mode 0.5 Logic High (Note 7) Logic Low (Note 7) Logic Input Current (Note 7) VGC Input Current (Note 7) -10 VGC Input Resistance During Shutdown SHDN = 0.6V (Note 7) 225 Lock Indicator High 50kΩ pullup load (Note 7) Lock Indicator Low 50kΩ pullup load (Note 7) 2 TYP 2.7 20 2.0 µA V 0.6 -5 +5 +10 280 µA kΩ VCC - 0.4 _______________________________________________________________________________________ V µA V 0.4 V Complete Dual-Band Quadrature Transmitters (MAX2366/67/68 evaluation kit: 50Ω system, operating modes as defined in Table 6, input voltage at I and Q = 200mVRMS differential, common mode = VCC/2,300kHz quadrature CW tones, RF and IF synthesizers locked with passive lead-lag second-order loop filter, REF = 200mVp-p at 19.68MHz, VCC = SHDN = IDLE = CS = TXGATE = +2.75V, VBAT = +2.75V, IF output load = 400Ω, LOH, LOL input power = -7dBm, fLOL = 966MHz, fLOH = 1750MHz, IFINH = 125mVRMS at 130MHz, IS-95 CDMA modulation fRFH0 = fRFH1 = 1880MHz, fRFL = 836MHz, TA = +25°C, unless otherwise noted.) PARAMETER CONDITIONS MIN TYP MAX UNITS MODULATOR, QUADRATURE MODES (CDMA, PCS, FM_IQ) IF Frequency Range IF_BAND = 0 120–235 IF_BAND = 1 120–300 1.35 VCC/2 MHz VCC 1.25 I/Q Common-Mode Input Voltage VCC = 2.7V to 3.0V (Notes 2, 3, 7) IF Gain Control Range VGC = 0.5V to 2.5V, IFG = 100 IF Output Power at IFOUTL and IFOUTH, CDMA Mode VGC = 2.5V, IFG = 100, ACPR = -70dBc Gain Variation Over Temperature Relative to +25°C, TA = -40°C to +85°C (Note 4) -1 Carrier Suppression VGC = 2.5V, IFG = 100 30 49 dB Sideband Suppression VGC = 2.5V, IFG = 100 30 38 dB MODULATOR, FM MODE IF Gain Control Range VGC = 0.5V to 2.5V, IFG = 100 85 dB Output Power at IFOUTL 85 dB -10 dBm +1 VGC = 2.5V, IFG = 111, I/Q modulation -8.5 VGC = 2.5V, IFG = 111, direct VCO modulation -5.5 V dB dBm UPCONVERTER AND PREDRIVER IF Frequency Range RFL Frequency Range RFH Frequency Range LOL Frequency Range LOH Frequency Range RFPLL Frequency Range IF_BAND = 0 IF_BAND = 1 RFL port RFH0 and RFH1 ports 120–200 180–300 800–1000 1700–2000 800–1150 1400–2300 MHz MHz MHz MHz MHz Cellular frequency operation 1300 PCS frequency operation 2300 ACPR = -54dBc 7 FM mode 12 MHz Output Power, RFL Port VGC = 2.5V dBm Output Power, RFH1 Port VGC = 2.6V, ACPR = -54dBc 7.5 dBm Output Power, RFH0 Port VGC = 2.6V, ACPR = -54dBc 6.6 dBm Power Control Range VGC = 0.5V to 2.5V 30 dB Gain Variation Over Temperature Relative to +25°C, TA = -40°C to +85°C (Note 4) ±1 ±2 dB LO Leakage -17 dBm Image Signal -29 dBc _______________________________________________________________________________________ 3 MAX2366/MAX2367/MAX2368 ELECTRICAL CHARACTERISTICS MAX2366/MAX2367/MAX2368 Complete Dual-Band Quadrature Transmitters ELECTRICAL CHARACTERISTICS (continued) (MAX2366/67/68 evaluation kit: 50Ω system, operating modes as defined in Table 6, input voltage at I and Q = 200mVRMS differential, common mode = VCC/2,300kHz quadrature CW tones, RF and IF synthesizers locked with passive lead-lag second-order loop filter, REF = 200mVp-p at 19.68MHz, VCC = SHDN = IDLE = CS = TXGATE = +2.75V, VBAT = +2.75V, IF output load = 400Ω, LOH, LOL input power = -7dBm, fLOL = 966MHz, fLOH = 1750MHz, IFINH = 125mVRMS at 130MHz, IS-95 CDMA modulation fRFH0 = fRFH1 = 1880MHz, fRFL = 836MHz, TA = +25°C, unless otherwise noted.) PARAMETER CONDITIONS MIN TYP MAX UNITS IF_PLL Reference Frequency 5 30 MHz Frequency Reference Signal Level 0.1 0.6 Vp-p IF Main Divide Ratio 256 16384 2 2048 IF Reference Divide Ratio VCO Operating Range IF LO Output Power Charge-Pump Source/Sink Current VCO = 0 240–470 VCO = 1 240–600 BUF_EN = 1 MHz -6 dBm ICP = 00 (Note 7) 115 175 230 ICP = 01 (Note 7) 145 235 315 ICP = 10 (Note 7) 235 350 470 ICP = 11 (Note 7) 300 465 625 Turbolock Boost Current (Note 5, 7) 265 450 615 Charge-Pump Source/Sink Matching Locked, all values of ICP, over specified compliance range (Note 6) Charge-Pump High-Z Leakage RF_PLL RF Main Divide Ratio RF Reference Divide Ratio 5 Over specified compliance range (Note 6) Maximum Phase-Detector Comparison Frequency Charge-Pump Source/Sink Current 10 MHz RCP = 00 (Note 7) 100 165 225 RCP = 01 (Note 7) 135 230 310 RCP = 10 (Note 7) 210 340 460 RCP = 11 (Note 7) 270 450 630 (Note 5, 6) 245 435 630 Charge-Pump Source/Sink Matching Locked, all values of RCP, over specified compliance range (Note 6, 7) Charge-Pump High-Z Leakage Over specified compliance range (Note 6) Note 1: Note 2: Note 3: Note 4: Note 5: Note 6: Note 7: 4 nA 262144 8192 Turbolock Boost Current RFPLL Input Sensitivity µA % 10 4096 2 µA 5 µA % 10 160 µA nA mVp-p See Table 6 for register settings. ACPR is met over the specified VCM range. VCM must be supplied by the I/Q baseband source with ±6µA capability. Guaranteed by design and characterization. When enabled, turbolock is active during acquisition and injects boost current in addition to the normal charge-pump current. Charge Pump Compliance range is 0.5V to VCC - 0.5V. >25°C guaranteed by production test. <25°C guaranteed by design and characterization. _______________________________________________________________________________________ Complete Dual-Band Quadrature Transmitters OUTPUT POWER, ACPR ICC vs. VGC MAX2366/7/8-02 MAX2366/7/8-01 5 LOCK POUT (dBm), ACPR/ALTR (dBc) 4 3 2 1 VOLTS (1V/div) MAX2366/7/8-03 20 z0 = 200Ω CS 10 182 0 164 POUT -10 146 -20 128 -30 TIME (200µs/div) 110 ICC -40 92 ADJACENT -50 74 -60 56 -70 3: 330MHz, 1.58kΩ, 0.34pF 4: 780MHz, 1.21kΩ, 0.43pF 5: 1GHz, 0.94kΩ, 0.47pF EQUIVALENT PARALLEL R-C 1: 200MHz, 1.76kΩ, 0.26pF 2: 260MHz, 1.66kΩ, 0.31pF 200 CELLULAR CDMA, RFL 38 ALTERNATE 20 -80 1.5 1.7 1.9 2.1 2.3 2.5 2.7 VGC (V) OUTPUT POWER, ACPR, ICC vs. VGC 160 -20 140 -30 120 ICC 100 -40 ADJACENT -50 80 -60 60 -70 ALTERNATE -80 1.5 1.7 1.9 2.1 2.3 2.5 POUT -10 140 -30 100 ADJACENT -50 80 60 40 -70 40 20 -80 20 1.5 1.7 1.9 2.1 2.3 2.5 2.7 -90 -20 1.5 2.0 2.5 3.0 0 DESIRED -10 -20 -30 -60 -40 -50 SIDEBAND LO -60 -70 -80 -90 +25°C -110 -100 -120 1.0 1.0 SIDEBAND SUPPRESSION AND LO FEEDTHROUGH (IFOUTH) -100 0.5 0.5 IF OUTPUT POWER vs. VGC -80 0 0 VGC (V) -80 -100 010 011 POUT (dBm) -70 000 001 -120 MAX2366/7/8-08 MAX2366/7/8-07 -60 111 101 -100 -40 -50 110 -80 2.7V, 3.0V, 3.3V -40 -60 VGC (V) 0 +85°C 100 -40 ALTERNATE -60 POUT (dBm) IF POWER (dBm) 120 ICC -40 IF OUTPUT POWER vs. VGC -20 -30 -20 160 -20 2.7 -40°C 0 180 VGC (V) 0 -10 200 MAX2366/7/8-06 0 MAX2366/7/8-09 180 MAX2366/7/8-05 PCS CDMA, RFH1 POUT (dBm) POUT -10 10 ICC TOTAL (mA) POUT (dBm), ACPR/ALTR (dBc) 0 200 IF OUTPUT POWER vs. VGC AND IF DAC SETTING ICC TOTAL (mA) MAX2366/7/8-04 PCS CDMA, RFH0 POUT (dBm), ACPR/ALTR (dBc) 10 OUTPUT POWER, ACPR, ICC TOTAL vs. VGC 1.5 VGC (V) 2.0 2.5 3.0 0 0.5 1.0 1.5 VGC (V) 2.0 2.5 3.0 129.98 130.18 130.38 130.58 130.78 FREQUENCY (MHz) _______________________________________________________________________________________ 5 ICC (mA) TANK 1/S11 vs. FREQUENCY IF VCO VOLTAGE vs. TIME MAX2366/MAX2367/MAX2368 Typical Operating Characteristics (MAX2366EVKIT, VCC = +2.75V, TA = +25°C, unless otherwise noted.) Typical Operating Characteristics (continued) (MAX2366EVKIT, VCC = +2.75V, TA = +25°C, unless otherwise noted.) -2.0 -2.5 3.5 600 3.0 500 2.5 RESISTANCE 400 2.0 300 1.5 CAPACITANCE 200 1.0 0 0 0 5 10 15 20 25 30 35 40 45 50 500 5 400 4 200 2 CAPACITANCE 1 0 0 FREQUENCY (MHz) FREQUENCY (MHz) FREQUENCY (MHz) PHASE NOISE LOW-BAND OSCILLATOR vs. FREQUENCY OFFSET (130.38MHz) PHASE NOISE HIGH-BAND OSCILLATOR vs. FREQUENCY OFFSET (165MHz) -60 -100 -100 -20 -30 -110 -110 -120 -120 -130 -130 -70 -140 -140 -80 -150 -150 100k 10k 1M 10k 100k 1M FREQUENCY (Hz) RFH0 OUTPUT SPECTRUM RFHO CASCADE ACPR vs. POUT AND VBAT 0 -10 ACPR (dBc) LO -40 -50 DESIRED IMAGE -40 VCC = 2.75V -45 2.8V 3.0V 2.8V -50 2.7V -55 2.7V -55 -60 -60 -60 966.38 1166.38 1366.38 CASCADE ACPR vs. POUT AND VBAT 3.0V -50 -30 766.38 FREQUENCY (MHz) VCC = 2.75V -45 -20 IMAGE DESIRED 566.38 ACPR (dBc) MAX2366/7/8-16 -40 -60 10M FREQUENCY (Hz) 10 -50 -90 1k 10M MAX2366/7/8-17 1k LO -40 3.3V -65 -80 3.3V -65 3.6V -90 3.6V -70 -70 1350 1550 1750 1950 FREQUENCY (MHz) 2150 MAX2366/7/8-18 -90 -90 (dBc/Hz) -80 0 -10 AMPLITUDE (dBm) -70 -80 RFL OUTPUT SPECTRUM 10 MAX2366/7/8-15 -50 MAX2366/7/8-13 -70 AMPLITUDE (dBm) 3 100 120 140 160 180 200 220 240 260 280 300 -60 6 RESISTANCE 300 100 120 140 160 180 200 220 240 260 280 300 -50 -70 6 100 0.5 100 -3.0 PARALLEL RESISTANCE (Ω) -1.5 700 MAX2366/7/8-12 600 MAX2366/7/8-14 (dBc) -1.0 4.0 PARALLEL CAPACITANCE (pF) -0.5 MAX2366/7/8-11 800 PARALLEL RESISTANCE (Ω) MAX2366/7/8-10 0 IFINH DIFFERENTIAL PORT INPUT IMPEDANCE -10 -8 -6 -4 -2 0 2 POUT (dBm) 4 6 8 10 -10 -8 -6 -4 -2 0 2 POUT (dBm) _______________________________________________________________________________________ 4 6 8 10 PARALLEL CAPACITANCE (pF) IFOUTH DIFFERENTIAL PORT OUTPUT IMPEDANCE I/Q BASEBAND FREQUENCY RESPONSE (dBc/Hz) MAX2366/MAX2367/MAX2368 Complete Dual-Band Quadrature Transmitters Complete Dual-Band Quadrature Transmitters MAX2366/7/8-20 MAX2366/7/8-19 180 170 160 160 150 150 150 140 ICC (mA) 160 140 140 130 130 130 120 120 120 110 110 110 100 100 100 -40 -30 -20 -10 0 10 OUTPUT POWER (dBm) -60 -50 -40 -30 -20 -10 0 10 -60 -50 LOL PORT S11 BUFFERED LO OUTPUT -10 -20 -30 -20 -10 0 10 LOH PORT S11 MAX2366/7/8-22 0 -40 OUTPUT POWER (dBm) OUTPUT POWER (dBm) MAX2366/7/8-24 -50 MAX2366/7/8-23 -60 AMPLITUDE (dBm) 170 ICC (mA) ICC (mA) 170 ICC vs. RFH1 OUTPUT POWER (1880MHz) ICC vs. RFH0 OUTPUT POWER (1880MHz) 180 MAX2366/7/8-21 ICC vs. RFL OUTPUT POWER (836MHz) 180 -30 -40 -50 5 4 -60 3 4 321 -70 2 1 -80 -90 -100 129.18 129.78 130.38 130.98 FREQUENCY (MHz) 131.58 1: 2: 3: 4: 700MHz, 72Ω –j51Ω 966MHz, 60Ω –j46Ω 1.22MHz, 52Ω –j38Ω 1.5GHz, 40Ω –j25Ω 1600MHz TO 2500MHz 1: 1.6GHz, 40Ω –j25Ω 2: 1.75GHz, 36Ω –j22Ω 3: 1.88GHz, 34Ω –j18Ω 4: 2.01GHz, 32Ω –j15Ω 5: 2.5GHz, 29Ω –j0Ω _______________________________________________________________________________________ 7 MAX2366/MAX2367/MAX2368 Typical Operating Characteristics (continued) (MAX2366EVKIT, VCC = +2.75V, TA = +25°C, unless otherwise noted.) MAX2366/MAX2367/MAX2368 Complete Dual-Band Quadrature Transmitters Pin Description PIN MAX2366 MAX2360 NAME FUNCTION MAX2368 1 — 1 RFL Transmitter RF Output for Cellular Band (800MHz to 1000MHz)—for both FM and digital modes. This open-collector output requires a pullup inductor to the supply voltage, which may be part of the output matching network and may be connected directly to the battery. — 1, 8, 9, 18, 19, 30, 31, 34, 35, 44 2, 10, 11, 16, 17, 32–35 43, 47 N.C. No Connection. Make no connection to these pins. 2 2 — RFH0 Transmitter RF Output for PCS Band (1700MHz to 2000MHz). This opencollector output requires a pullup inductor to the supply voltage. The pullup inductor may be part of the output matching network and may be connected directly to the battery. 3 3 3 LOCK Open-Collector Output Indicating Lock Status of the IF and/or the RF PLLs. Requires a pullup resistor. Control using configuration register bit LD_MODE0, LD_MODE1. 4 4 4 VCC Power Supply 5 5 5 IDLE Digital Input. A logic low on IDLE shuts down everything except the RF PLL and associated registers. A small R-C lowpass filter may be used to prevent digital noise. 6 6 6 VCC Supply Pin for the Upconverter Stage. VCC must be bypassed to system ground as close to the pin as possible. The ground vias for the bypass capacitor should not be shared by any other branch. 7 7 7 TXGATE Digital Input. A logic low on TXGATE shuts down everything except the RF PLL, IF PLL, IF VCO, and serial bus and registers. This mode is used for gated transmission. 8, 9 IFINL+, IFINL- Differential Inputs to the RF Upconverter. These pins are internally biased to +1.5V. The input impedance for these ports is nominally 400Ω differential. The IF filter should be AC-coupled to these ports. Keep the differential lines as short as possible to minimize stray pickup and shunt capacitance. — IFINH+, IFINH- Differential Inputs to the RF Upconverter. These pins are internally biased to +1.5V. The input impedance for these ports is nominally 400Ω differential. The IF filter should be AC-coupled to these ports. Keep the differential lines as short as possible to minimize stray pickup and shunt capacitance. 8, 9 10, 11 8 MAX2367 — 10, 11 12 12 12 RBIAS 13, 14, 15 13, 14, 15 13, 14, 15 CLK, DI, CS Bias Resistor Pin. RBIAS is internally biased to a bandgap voltage of +1.18V. An external resistor or current source must be connected to this pin to set the bias current for the upconverters and PA driver stages. The nominal resistor value is 16kΩ. This value can be altered to optimize the linearity of the driver stage. Input Pins from the 3-Wire Serial Bus (SPI/QSPI/MICROWIRE compatible). An R-C filter on each of these pins may be used to reduce noise. _______________________________________________________________________________________ Complete Dual-Band Quadrature Transmitters PIN MAX2366 16, 17 MAX2367 16, 17 NAME FUNCTION IFOUTH-, IFOUTH+ Differential IF Outputs. These ports are active when the register bit IF_BAND is 1. They do not support FM mode. These pins must be inductively pulled up to VCC. A differential IF bandpass filter is connected between this port and IFINH+ or IFINH-. The pullup inductors can be part of the filter structure. The differential output impedance of this port is nominally 600Ω. The transmission lines from these pins should be short to minimize the pickup of spurious signals and noise. MAX2368 — 18, 19 — 18, 19 IFOUTL+, IFOUTL- Differential IF Outputs. These ports are active when the register bit IF_BAND is 0. These pins must be inductively pulled up to VCC. A differential IF bandpass filter is connected between this port and IFINL+ and IFINL-. The pullup inductors can be part of the filter structure. The differential output impedance of this port is nominally 600Ω. The transmission lines from these pins should be short to minimize the pickup of spurious signals and noise. 20 20 20 VGC RF and IF Variable-Gain Control Analog Input. VGC floats to +1.5V. Apply +0.5V to +2.6V to control the gain of the RF and IF stages. An RC filter on this pin may be used to reduce DAC noise or PDM clock spurs from this line. 21 21 21 VCC Supply Pin for the IF VGA. Bypass with a capacitor as close to the pin as possible. The bypass capacitor must not share its ground vias with any other branches. 22 22 22 VCC Supply for the I/Q Modulator. Bypass with capacitor as close to the pin as possible. The bypass capacitor must not share its ground vias with any other branches. 23, 24 23, 24 23, 24 Q+, Q- Differential Q-Channel Baseband Inputs to the Modulator. These pins go directly to the bases of a differential pair and require an external commonmode bias voltage. 25, 26 25, 26 25, 26 I+, I- Differential I-Channel Baseband Inputs to the Modulator. These pins go directly to the bases of a differential pair and require an external commonmode bias voltage. 27 27 27 SHDN Shutdown Input. A logic low on SHDN shuts down the entire IC. An R-C lowpass filter may be used to reduce digital noise. 28 28 28 VCC Supply Pin to the VCO Section. Bypass as close to the pin as possible. The bypass capacitor should not share its vias with any other branches. 29 29 29 IFLO NBuffered LO Output. Control the output buffer using register bit BUF_EN and the divide ratio using the register bit BUF_DIV. 30, 31 — 30, 31 TANKL-, TANKL+ Differential Tank Pins for the Low-Frequency IF VCO. These pins are internally biased to +1.6V. _______________________________________________________________________________________ 9 MAX2366/MAX2367/MAX2368 Pin Description (continued) MAX2366/MAX2367/MAX2368 Complete Dual-Band Quadrature Transmitters Pin Description (continued) PIN NAME FUNCTION — TANKH-, TANKH+ Differential Tank Pins for the High-Frequency IF VCO. These pins are internally biased to +1.6V. — — N.C. No Connection. Leave these pins floating. 36 36 36 REF Reference Frequency Input. REF is internally biased to VCC - 0.7V and must be AC-coupled to the reference source. This is a high-impedance port (25kΩ II 3pF). 37 37 37 VCC Supply for the IF Charge Pump. This supply can differ from the system VCC. Bypass as close to the pin as possible. The bypass capacitor must not share its vias with any other branches. MAX2366 MAX2367 MAX2368 32, 33 32, 33 34, 35 38 38 38 IFCP High-Impedance Output of the IF Charge Pump. Connect to the tune input of the IF VCOs through the IF PLL loop filter. Keep the line from IFCP to the tune input as short as possible to prevent spurious pickup, and connect the loop filter as close to the tune input as possible. 39 39 39 VCC Supply Pin for Digital Circuitry. Bypass as close to the pin as possible. The bypass capacitor must not share its vias with any other branch. 40 40 40 RFCP High-Impedance Output of the RF Charge Pump. Connect to the tune input of the RF VCOs through the RF PLL loop filter. Keep the line from this pin to the tune input as short as possible to prevent spurious pickup, and connect the loop filter as close to the tune input as possible. 41 41 41 VCC Supply for the RF Charge Pump. This supply can differ from the system VCC. Bypass as close to the pin as possible. The bypass capacitor must not share its vias with any other branches. 42 42 42 RFPLL 43 43 — LOH High-band RF LO Input Port. AC-couple to this port. 44 — 44 LOL Low-band RF LO Input Port. AC-couple to this port. 45, 46, 48 45, 46, 48 45, 46, 48 GND Ground. Connect to PC board ground plane. RF PLL Input. AC-couple this port to the RF VCO. 47 47 — RFH1 Transmitter RF Output for PCS Band (1700MHz to 2000MHz). This open-collector output requires a pullup inductor to the supply voltage. The pullup inductor may be part of the output matching network and may be connected directly to the battery. Exposed paddle Exposed paddle Exposed paddle GND DC and AC GND Return for the IC. Connect to PC board ground plane using multiple vias. 10 ______________________________________________________________________________________ Complete Dual-Band Quadrature Transmitters The MAX2366 complete quadrature transmitter accepts differential I/Q baseband inputs with external commonmode bias. A modulator upconverts this to IF frequency in the 120MHz to 300MHz range. A gain control voltage pin (VGC) controls the gain of both the IF and RF VGAs simultaneously to achieve best noise and linearity performance. The IF signal is brought off-chip for filtering, then fed to a single sideband upconverter followed by the RF VGA and PA driver. The RF upconverter requires an external VCO for operation. The IF PLL, RF PLL, and operating mode can be programmed by an SPI/QSPI/ MICROWIRE-compatible 3-wire interface. The following sections describe each block in the MAX2366 Functional Diagram. I/Q Modulator Differential in-phase (I) and quadrature-phase (Q) input pins are designed to be DC-coupled and biased with the baseband output from a digital-to-analog converter (DAC). I and Q inputs need a DC bias of VCC/2 and a current-drive capability of 6µA. Common-mode voltage will work within a 1.35V to (VCC - 1.25V) range. Typically, I and Q will be driven differentially with a 200mVRMS baseband signal. Optionally, I and Q may be programmed for 100mVRMS operation with the IQ_LEVEL bit in the configuration register. The IF VCO output is fed into a divide-by-two/quadrature generator block to derive quadrature components to drive the IQ modulator. The output of the modulator is fed into the VGA. IF VCOs There are two VCOs to support high IF and low IF applications. The VCOs oscillate at twice the desired IF frequency. Oscillation frequency is determined by external tank components (see Applications Information). Typical phase-noise performance for the tank is as shown in Table 1. The high-band and low-band VCOs can be selected independently of the IF port being used. Table 1. Typical VCO Phase Noise (IF = 130.38MHz) OFFSET (kHz) PHASE NOISE (dBc) 1 -80 12.5 30 120 -105 -111 -121 900 -128 IFLO Output Buffer IFLO provides a buffered LO output when BUF_EN is 1. The IFLO output frequency is equal to the VCO frequency when BUF_DIV is 0, and half the VCO frequency when BUF_DIV is 1. The output power is -6dBm. This output is intended for applications where the receiver IF is the same frequency as the transmit IF. IF/RF PLL The IF/RF PLL uses a charge-pump output to drive a loop filter. The loop filter will typically be a passive second-order lead lag filter. Outside the filter’s bandwidth, phase noise will be determined by the tank components. The two components that contribute most significantly to phase noise are the inductor and varactor. Use high-Q inductors and varactors to maximize equivalent parallel resistance. The IF_TURBO_CHARGE and the RF_TURBO_CHARGE bits in the CONFIG register can be set to 1 to enable turbo mode. Turbo mode provides maximum charge-pump current during frequency acquisition. Turbo mode is disabled after the second transition from phase lead to phase lag or from phase lag to phase lead. Turbo mode is also disabled after frequency acquisition is achieved. When turbo mode is disabled, charge-pump current will return to the programmed levels as set by ICP and RCP bits in the CONFIG register (Table 4). IF VGA The IF VGA allows varying an IF output level that is controlled by the VGs. The voltage range on VGC of +0.5V to +2.6V provides a gain-control range of 85dB. There are two differential IF output ports from the VGA. IFOUTL+/IFOUTL- are optimized for low IF operation (120MHz to 235MHz) for IFOUTH+/IFOUTH- support high IF operation (120MHz to 300MHz). IFOUTL ports support direct VCO FM modulation. The differential IF output port has an output impedance of 600Ω when pulled up to VCC through a choke. Single Sideband Mixer The RF transmit mixer uses a single sideband architecture to eliminate an off-chip RF filter. The single sideband mixer has IF input stages that correspond to IF output ports of the VGA. The mixer is followed by the RF VGA. The RF VGA is controlled by the same VGC pin as the IF VGA to provide optimum linearity and noise performance. The total power control range is >100dB. PA Driver The MAX2366 includes three power-amplifier (PA) drivers. Each is optimized for the desired operating frequency. RFL is optimized for cellular-band operation. ______________________________________________________________________________________ 11 MAX2366/MAX2367/MAX2368 Detailed Description MAX2366/MAX2367/MAX2368 Complete Dual-Band Quadrature Transmitters RFH0 and RFH1 are optimized for split-band PCS operation. The PA drivers have open-collector outputs and require pullup inductors. The pullup inductors can act as the shunt element in a shunt series match. The configuration register (CONFIG) sets the configuration for the RF/IF PLL and the baseband I/Q input levels. See Table 4 for a description of each bit. The test register is not needed for normal use. Programmable Registers Power Management Bias control is distributed among several functional sections and can be controlled to accommodate many different power-down modes as shown in Table 5. The shutdown control bit is of particular interest since it differs from the SHDN pin. When the shutdown control bit is active (SHDN_BIT = 0), the serial interface is left active so that the part can be turned on with the serial bus while all other functions remain shut off. In contrast, when the SHDN pin is low it shuts down everything. In either case, PLL programming and register information is lost. To retain the register information, use standby mode (STBY = 0). The MAX2366/MAX2367/MAX2368 include seven programmable registers consisting of four divide registers, a configuration register, an operational control register, and a test register. Each register consists of 24 bits. The 4 least significant bits (LSBs) are the register’s address. The 20 most significant bits (MSBs) are used for register data. All registers contain some “don't care” bits. These can be either a zero or a 1 and do not affect operation (Figure 1). Data is shifted in MSB first, followed by the 4-bit address. When CS is low, the clock is active and data is shifted with the rising edge of the clock. When CS transitions to high, the shift register is latched into the register selected by the contents of the address bits. Power-up defaults for the seven registers are shown in Table 2. The dividers and control registers are programmed from the SPI/QSPI/MICROWIRE-compatible serial port. The RFM register sets the main frequency divide ratio for the RF PLL. The RFR register sets the reference frequency divide ratio. The RF VCO frequency can be determined by the following: RF VCO frequency = fREF ✕ (RFM / RFR) IFM and IFR registers are similar: Signal Flow Control Table 6 shows an example of key registers for triplemode operation, assuming half-band PCS and IF frequencies of 130MHz/165MHz. Applications Information The MAX2366 is designed for use in dual-band, triplemode systems. It is recommended for triple-mode handsets (Figure 2). The MAX2367 is designed for use in CDMA PCS handsets or WLL single-mode 2.4GHz ISM systems (Figure 3). The MAX2368 is designed for use in dual-mode cellular systems (Figure 4). IF VCO frequency = fREF ✕ (IFM / IFR) where fREF is the external reference frequency. The operational control register (OPCTRL) controls the state of the MAX2366/MAX2367/MAX2368. See Table 3 for the function of each bit. 3-Wire Interface Figure 5 shows the 3-wire interface timing diagram. The 3-wire bus is SPI/QSPI/MICROWIRE compatible. Table 2. Register Power-Up Default States 12 REGISTER DEFAULT ADDRESS FUNCTION RFM 172087 dec 0000b RF M divider count RFR IFM IFR 1968 dec 6519 dec 0492 dec 0001b 0010b 0011b RF R divider count IF M divider count IF R divider count OPCTRL CONFIG TEST 892F hex D03F hex 0000 hex 0100b 0101b 0111b Operational control settings Configuration and setup control Test-mode control ______________________________________________________________________________________ Complete Dual-Band Quadrature Transmitters 24-BIT REGISTER MAX2366/MAX2367/MAX2368 MSB LSB DATA 20 BITS ADDRESS 4 BITS B19 B18 B17 B16 B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 A3 A2 A1 A0 RFM DIVIDE REGISTER RFR DIVIDE REGISTER IFM DIVIDE REGISTER IFR DIVIDE REGISTER CONTROL REGISTER CONFIGURATION REGISTER TEST REGISTER RFM DIVIDE RATIO (18) ADDRESS X X B17 B16 B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 X X X X X X X X X X X X B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 0 RFR DIVIDE RATIO (13) X B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 X X X X X X X B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 X X X X B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 X X X X B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 X X X X 0 X X X X X 1 0 1 0 0 1 1 1 0 0 ADDRESS 0 TEST BITS (8) X 0 ADDRESS 0 CONFIGURATION BITS (16) X 0 ADDRESS CONTROL BITS (16) X 0 ADDRESS 0 RFR DIVIDE RATIO (11) X 0 ADDRESS 0 IFM DIVIDE RATIO (14) X 0 B7 B6 B5 B4 B3 B2 B1 B0 1 0 1 ADDRESS 0 1 1 1 X = DON’T CARE Figure 1. Register Configuration Electromagnetic Compliance Considerations Two major concepts should be employed to produce a noise-free and EMC-compliant transmitter: minimize circular current-loop area to reduce H-field radiation and minimize voltage drops to reduce E-field radiation. To minimize the circular current-loop area, bypass as close to the part as possible and use the distributed capacitance of a ground plane. To minimize voltage drops, make VCC traces short and wide, and make RF traces short. The “don't care” bits in the registers should be zero in order to minimize electromagnetic radiation due to unnecessary bit banging. RC filtering can also be used to slow the clock edges on the 3-wire interface, reducing high-frequency spectral content. RC filtering also provides for transient protection against IEC802 testing by shunting high frequencies to ground, while the series resistance attenuates the transients for error-free operation. The same applies to the override pins (SHDN, TXGATE, IDLE). High-frequency bypass capacitors are required close to the pins with a dedicated via to ground. The 48-pin QFN-EP package provides minimal inductance ground by using an exposed paddle under the part. Provide at least five low-inductance vias under the paddle to ground to minimize ground inductance. Use a solid ground plane wherever possible. Any cutout in the ground plane may act as slot radiator and reduce its shield effectiveness. Keep the RF LO traces as short as possible to reduce LO radiation and susceptibility to interference. ______________________________________________________________________________________ 13 MAX2366/MAX2367/MAX2368 Complete Dual-Band Quadrature Transmitters Table 3. Operation Control Register (OPCTRL) BIT NAME POWER-UP STATE BIT LOCATION (0 = LSB) LO_SEL 1 15 1 selects LOL input port; 0 selects LOH port. RCP_MAX 0 14 1 keeps RF turbo-mode current active even when frequency acquisition is achieved. This bit has no effect when RF_TURBO_CHARGE = 0. This mode is used when high operating RF charge-pump current is needed. ICP_MAX 0 13 1 keeps IF turbo-mode current active even when frequency acquisition is achieved. This bit has no effect when IF_TURBO_CHARGE = 0. This mode is used when high operating IF charge-pump current is needed. FUNCTION Sets operating mode according to the following: 00 = FM mode 01 = Cellular digital mode; RFL is selected 10 = PCSHIGH mode; RFH1 is selected 11 = PCSLOW mode; RFH0 is selected MODE 01 12, 11 IF_BAND 0 10 1 selects IFINH and IFOUTH; 0 selects IFINL and IFOUTL. For FM mode (MODE = 00), set IF_BAND to 0. VCO 0 9 1 selects high-band IF VCO; 0 selects low-band IF VCO. IFG 100 8, 7, 6 3-bit IF gain control. Alters IF gain by approximately 2dB per LSB (0 to 14dB). Provides a means for adjusting balance between RF and IF gain for optimized linearity. SIDE_BAND 1 5 When this register is 1, the upper sideband is selected (LO below RF). When this register is 0, the lower sideband is selected (LO above RF). BUF_EN 0 4 0 turns IFLO buffer off; 1 turns IFLO buffer on. MOD_TYPE 1 3 0 selects direct VCO modulation. (IF VCO is externally modulated and the I/Q modulator is bypassed); 1 selects quadrature modulation. STBY 1 2 0 shuts down everything except registers and serial interface. TXSTBY 1 1 0 shuts down modulator and upconverter, leaving PLLs locked and registers active. This is the programmable equivalent to the TXGATE pin. SHDN_BIT 1 0 0 shuts down everything except serial interface, and also resets all registers to power-up state. 14 ______________________________________________________________________________________ Complete Dual-Band Quadrature Transmitters BIT NAME POWER-UP STATE BIT LOCATION (0 = LSB) FUNCTION IF_PLL_SHDN 1 15 0 shuts down the IF PLL. This mode is used with an external IF VCO and IF PLL. RF_PLL_ SHDN 1 14 0 shuts down the RF PLL. This mode is used with an external RF PLL. RESERVED 0 13 Must be set to 0 for normal operation. IQ_LEVEL 1 12 1 selects 200mVRMS input mode; 0 selects 100mVRMS input mode. BUF_DIV 0 11 1 selects ÷2 on IFLO port; 0 bypasses the divider. VCO_BYPASS 0 10 1 bypasses IF VCO and enables a buffered input for external VCO use. 9, 8 A 2-bit register sets the IF charge-pump current as follows: 00 = 175µA 01 = 235µA 10 = 350µA 11 = 465µA A 2-bit register sets the RF charge-pump current as follows: 00 = 165µA 01 = 230µA 10 = 340µA 11 = 450µA ICP 00 RCP 00 7, 6 IF_PD_POL 1 5 IF phase-detector polarity; 1 selects positive polarity (increasing tuning voltage on the VCO produces increasing frequency); 0 selects negative polarity (increasing tuning voltage on the VCO produces decreasing frequency). RF_PD_POL 1 4 RF phase-detector polarity; 1 selects positive polarity (increasing tuning voltage on the VCO produces increasing frequency); 0 selects negative polarity (increasing voltage on the VCO produces decreasing frequency). IF_TURBO_ CHARGE 1 3 1 activates turbocharge feature, providing an additional 450µA of IF chargepump current during frequency acquisition. RF_TURBO_ CHARGE 1 2 1 activates turbocharge feature, providing an additional 435µA of RF chargepump current during frequency acquisition. LD_MODE 11 1, 0 Determines output mode for LOCK detector pin as follows: 00 = test mode, LD_MODE cannot be 00 for normal operation 01 = IF PLL lock detector 10 = RF PLL lock detector 11 = logical AND of IF PLL and RF PLL lock detectors ______________________________________________________________________________________ 15 MAX2366/MAX2367/MAX2368 Table 4. Configuration Register (CONFIG) X TXGATE Pin For punctured TX mode X X RF PLL SHDN For external RF PLL use IF PLL SHDN For external IF PLL use TX STBY X TX is OFF, but IF and RF LOs stay locked X X REG STBY Shuts down, but preserves registers X X X REG SHDN Serial bus is still active X X X CONFIG REG X IF PLL REGS RF PLL REGS X X IF PLL RF PLL X X IF VCO SERIAL BUS X IDLE is low in RX mode SHDN Pin COMMENTS IF LO BUFF MODULATOR Ultra-low shutdown current IDLE Pin POWER-DOWN MODE OPCTRL REG UPCONVERTER Table 5. Power-Down Modes X X X X X X X X X X X X X X X X X X X X X X X = Off Table 6. Register and Control Pin States for Key Operating Modes CONFIG REGISTER MODE DESCRIPTION IF BAND VCO MOD TYPE STBY TXSTBY SHDN_BIT IF PLL SHDN RF PLL SHDN IDLE TXGATE SHDN PCS High PCS upper half-band, RFH1 selected 0 10 1 1 1 1 1 1 1 1 H H H PCS Low PCS lower half-band, RFH0 selected 0 11 1 1 1 1 1 1 1 1 H H H RFL selected 1 01 0 0 1 1 1 1 1 1 H H H Direct VCO modulation, RFL selected 1 00 0 0 0 1 1 1 1 1 H H H PCS Idle Listen for pages RX ON, TX OFF 0 1X X X X 1 X 1 X 1 L H H Cellular Idle Listen for pages RX ON, TX OFF 1 0X X X X 1 X 1 X 1 L H H Gated transmission, PCS 0 1X 1 1 1 1 X 1 1 1 H L H Cellular Digital FM PCS TXGATE Cellular TXGATE Sleep Gated transmission, cellular digital 1 01 0 0 1 1 X 1 1 1 H L H Everything off X XX X X X X X X X X X X L X = Don’t care 16 CONTROL PINS MODE OPCTRL REGISTER LO SEL MAX2366/MAX2367/MAX2368 Complete Dual-Band Quadrature Transmitters ______________________________________________________________________________________ X ______________________________________________________________________________________ 1000pF VREG 51k CELL PA CELL RX PCS PA 130MHz TXGATE IDLE LOCK CELL DUPLEXER DIPLEXER PCS DUPLEXER VREG 3pF 3.3pF 5nH 165MHz 100pF 836MHz 1880MHz VCC VCC 48 13 CLK 12 RBIAS 11 10 9 8 7 6 5 4 3 2 1 22nH 33pF 8.7µH VBAT 16k VBAT 14 DI 47 VBAT 45 15 CS 46 90 0 16 Σ 45 17 -45 44 100pF 19 42 RF PPL 41 3300pF VGC 20 Σ 100pF 0 MAX2366 33pF 50Ω PCS VCO 3 WIRE 18 43 33pF 33pF CELL VCO 21 39 10k 22 100pF VREG 23 24 TANK L /2 100pF 37 TANK H 38 IF PPL VCC /2 VCC 90 40 100pF 0.033µF 25 26 27 28 29 IFLO 30 31 32 33 34 N.C. 35 N.C. 36 0.033µF DAC DAC 39nH 22nH Q I SHDN 18pF 2.4pF 18pF 12pF 4.3pF 12pF 19.68MHz TCXO 3300pF VREG 100pF 10k 10k 10k 10k 10k 0.033µF MAX2366/MAX2367/MAX2368 PCS Rx 1960MHz DAC VREG Complete Dual-Band Quadrature Transmitters Figure 2. MAX2366 Typical Application Circuit 17 1000pF VREG 47pF 51k PCS PA 130MHz TXGATE IDLE LOCK PCS DUPLEXER 100pF 1880MHz 7 6 5 4 3 2 VCC VCC 16k 12 RBIAS 11 10 N.C. 9 22nH 13 CLK 48 33pF 1 N.C. N.C. 8 VREG 3.3pF 5nH VBAT 14 DI 47 VBAT 45 15 CS 46 90 0 16 Σ 45 17 -45 44 N.C. 33pF PCS VCO Figure 3. MAX2367 Typical Application Circuit ______________________________________________________________________________________ N.C. N.C. 3 WIRE 19 42 18 43 33pF RF PLL 41 3300pF VGC 20 Σ 100pF 0 MAX2367 100pF 21 39 10k 22 38 /2 100pF 24 25 26 27 28 29 IFLO 30 N.C. 31 N.C. 32 33 34 N.C. 35 N.C. 36 0.033µF 100pF 37 VCC TANK VREG 23 IF PLL VCC /2 VCC 90 40 100pF 0.033µF 18 DAC PCS Rx 1960MHz DAC DAC 39nH VREG Q I SHDN 18pF 2.4pF 18pF 19.68MHz TCXO 3300pF VREG 100pF 10k 10k 10k 0.033µF MAX2366/MAX2367/MAX2368 Complete Dual-Band Quadrature Transmitters ______________________________________________________________________________________ 1000pF VREG 47pF 51k CELL PA 130MHz TXGATE IDLE LOCK CELL DUPLEXER 836MHz 100pF 9 8 7 6 5 16k 48 13 CLK 12 RBIAS N.C. 11 VCC 4 VCC 3 N.C. 2 1 N.C. 10 VREG 3pF 8.7nH VBAT 14 DI 47 N.C. 45 15 CS 46 90 N.C. N.C. -45 17 0 44 16 Σ 45 33pF 3 WIRE 18 43 N.C. 33pF 19 42 3300pF VGC 20 Σ 100pF 0 MAX2368 RF PLL 41 21 22 37 100pF VREG 23 /2 24 TANK L 38 IF PLL 10k 39 /2 VCC 90 40 100pF 0.033µF 0.033µF 25 26 27 28 29 IFLO 30 31 32 N.C. 33 N.C. 34 N.C. 35 N.C. 36 100pF DAC DAC 39nH VREG Q I SHDN 18pF 2.4pF 18pF 19.68MHz TCXO 3300pF VREG 100pF 10k 10k 10k 0.033µF MAX2366/MAX2367/MAX2368 CELL Rx 880MHz 100pF DAC PCS VCO Complete Dual-Band Quadrature Transmitters Figure 4. MAX2368 Typical Application Circuit 19 MAX2366/MAX2367/MAX2368 Complete Dual-Band Quadrature Transmitters DI B19 (MSB) B18 B0 A3 A1 tCS > 50ns tCH > 10ns tCWH > 50ns tES > 50ns tCWL > 50ns tEW > 50ns A0 (LSB) CLK tCWL tCS tCH tCWH tEW tES CS Figure 5. 3-Wire Interface Diagram IF Tank Design The low-band tank (TANKL+, TANKL-) and high-band tank (TANKH+, TANKH-) are fully differential. The external tank components are shown in Figure 6. The frequency of oscillation is determined by the following equation: 1 fOSC = 2π (CINT + CCENT + CVAR + CPAR ) L CC MAX2366 MAX2367 MAX2368 CD CCENT L CPAR CINT -Rn CD CVAR = CD × CC 2 (CD + CC ) CC CINT = Internal capacitance of TANK port CD = Capacitance of varactor CVAR = Equivalent variable tuning capacitance CPAR = Parasitic capacitance due to PC board pads and traces CCENT = External capacitor for centering oscillation frequency CC = External coupling capacitor to the varactor Internal to the IC, the charge pump will have a leakage of less than 10nA. This is equivalent to a 300MΩ shunt resistor. The charge-pump output must see an extremely high DC resistance of greater than 300MΩ. This will minimize charge-pump spurs at the comparison frequency. Make sure there is no solder flux under the varactor or loop filter. Layout Issues The MAX2366/MAX2367/MAX2368 EV kit can be used as a starting point for layout. For best performance, take into consideration power-supply issues, as well as the RF, LO, and IF layout. 20 Figure 6. Tank Port Oscillator Power-Supply Layout To minimize coupling between different sections of the IC, the ideal power-supply layout is a star configuration, which has a large decoupling capacitor at a central VCC node. The VCC traces branch out from this node, each going to a separate VCC node in the MAX2366/ MAX2367/MAX2368 circuit. At the end of each trace is a bypass capacitor with impedance to ground less than 1Ω at the frequency of interest. This arrangement provides local decoupling at each VCC pin. Use at least one via per bypass capacitor for a low-inductance ground connection. Matching Network Layout The layout of a matching network can be very sensitive to parasitic circuit elements. To minimize parasitic inductance, keep all traces short and place components as close to the IC as possible. To minimize parasitic capacitance, a cutout in the ground plane (and ______________________________________________________________________________________ Complete Dual-Band Quadrature Transmitters Tank Layout Keep the traces coming out of the tank short to reduce series inductance and shunt capacitance. Keep the inductor pads and coupling capacitor pads small to minimize stray shunt capacitance. Selector Guide PART MAX2366 IF RANGE (MHz) RF LO RANGE (MHz) RF RANGE (MHz) 120 to 235 800 to 1150 800 to 1000 120 to 300 1400 to 2300 1700 to 2000 MAX2367 120 to 300 1400 to 2300 1700 to 2000 MAX2368 120 to 235 800 to 1150 800 to 1000 ______________________________________________________________________________________ 21 MAX2366/MAX2367/MAX2368 any other planes) below the matching network components can be used. On the high-impedance ports (e.g., IF inputs and outputs), keep traces short to minimize shunt capacitance. Pin Configurations (continued) MAX2366 30 37 38 39 40 41 42 43 44 45 32 TXGATE N.C. N.C. IFINH+ IFINHRBIAS 7 6 31 MAX2367 30 8 29 9 28 10 27 11 26 12 25 13 24 23 22 5 CLK DI CS IFOUTHIFOUTH+ N.C. N.C. VGC VCC VCC VCC Q+ Q- IFOUTHIFOUTH+ IFOUTL+ IFOUTLVGC 21 25 20 12 19 26 18 11 17 27 16 10 15 28 14 29 9 13 8 IDLE VCC N.C. TANK H+ TANK HN.C. N.C. IFLO VCC SHDN II+ 24 7 TANK L+ TANK LIFLO VCC SHDN II+ 23 TXGATE IFINL+ IFINLIFINH+ IFINHRBIAS 33 22 31 34 4 REF N.C. VCC Q+ Q- 32 6 3 N.C. TANK H+ TANK H- 21 5 35 20 IDLE VCC 36 2 19 33 1 18 34 4 N.C. RFH0 LOCK VCC 17 3 VCC REF N.C. 16 35 15 36 2 46 GND RFH1 GND GND N.C. LOH RFPLL VCC RFCP VCC IFCP VCC 1 47 48 RFL RFH0 LOCK 14 IFCP VCC 37 38 39 40 41 42 LOL LOH RFPLL VCC RFCP VCC 43 44 45 46 GND RFH1 GND GND 47 48 TOP VIEW CLK DI CS QFN-EP 37 38 39 40 41 42 43 44 45 46 RFL N.C. LOCK VCC 1 36 2 35 3 34 4 33 IDLE VCC TXGATE IFINL+ IFINL- 5 32 N.C. N.C. RBIAS 6 31 MAX2368 7 30 REF N.C. N.C. N.C. N.C. TANK L+ TANK LIFLO 24 23 22 21 I+ 20 25 19 26 12 18 11 VCC SHDN I- 17 27 16 28 10 15 29 9 14 8 13 BOTTOM SIDE GND 47 48 GND N.C. GND GND LOL N.C. RFPLL VCC RFCP VCC IFCP VCC QFN-EP CLK DI CS N.C. N.C. IFOUTL+ IFOUTLVGC VCC VCC Q+ Q- MAX2366/MAX2367/MAX2368 Complete Dual-Band Quadrature Transmitters QFN-EP Package Information For the latest package outline information, go to www.maxim-ic.com/packages. Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 22 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 © 2000 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.